Interfacing I/O Devices to the

Processor,
Memory, and Operating System
Dr. E. Papanasam
SoC
 Contents
• Interfacing I/O Devices
• Characteristics of I/O systems
• Hardware/ Software Interface – Functions of
OS
• Three types of communication
 Interfacing I/O Devices
• A bus or network protocol defines how a word or block of data
should be communicated on a set of wires
• Tasks must be performed to actually cause data to be
transferred from a device and memory
– Transforming a user I/O request into a device command and
communicating with the device
– Transferring data to or from a memory
– What is the role of the operating system?
• Operating system
– Plays a major role in handling I/O
– Acting as the interface between the hardware and the
program that requests I/O
 Characteristics of I/O systems
• The responsibilities of the operating system arise from three
characteristics of I/O systems:
• 1.Sharing of the I/O system
– Multiple programs using the processor share the I/O system
• 2. Interrupt
– I/O systems use interrupts (externally generated exceptions)
to communicate information about I/O operation
– Because interrupts cause a transfer to kernel or supervisor
mode, they must be handled by the operating system (OS)
• 3. Complex low-level control
– Low level control of an I/O device is complex, because it
requires managing a set of concurrent events
 Hardware/ Software Interface
• Several different functions the OS must provide:
• Guarantees that a user’s program accesses only the portions of
an I/O device to which the user has rights
– Ex, OS must not allow a program to read or write a file on
disk if the owner of the file has not granted access to this
program
• Provides abstractions for accessing devices by supplying
routines that handle low-level device operations
• Handles the interrupts (generated by I/O devices), just as it
handles the exceptions (generated by a program)
• Provide equitable access to the shared I/O resources, as well as
schedule accesses to enhance system throughput
 Hardware/ Software Interface
• To perform these functions the OS must be able to
– Communicate with the I/O devices
– To prevent the user program from communicating with the I/O
devices directly
• Three types of communication are required
1. The OS must be able to give commands to the I/O devices
– operations like read and write, but also other operations to be
done on the device, such as a disk seek
2. The device must be able to notify the OS when the I/O device
has completed an operation or has encountered an error
– For Ex, when a disk completes a seek, it will notify the OS
3. Data must be transferred between memory and an I/O device
– For Ex, the block being read on a disk must be moved from
disk to memory.
 Giving Commands to I/O Devices
• To give a command to an I/O device, the processor able to
– address the device and
– to supply one or more command words
• Two methods are used to address the device:
– memory-mapped I/O and
– special I/O instructions

• Memory mapped I/O

– Portions of the address space are assigned to I/O devices
– The device uses the address to determine the type of
command
– In any event, the address encodes both the device identity
and the type of transmission between processor and device
 Memory mapped I/O
• Have common bus (address, data, and control) for I/O and
memory
• Single address space for memory locations and I/O devices
• Same set of instructions for memory and I/O
• Uses the same machine instructions to access both memory and
I/O devices
• A single read line and a single write line are needed on the bus

With 10 address lines, a combined total of

1024 memory locations and I/O addresses
can be supported, in any combination

Addressing capability of memory become

less because some part is occupied by the
I/O
 Special I/O instruction (Isolated I/O)
• Common bus (data and address) for I/O and memory
• Separate read and write control lines
• Separate address space
• The bus may be equipped with memory read and write plus
input and output command lines
• Now, the command line specifies whether the address refers to
a memory location or an I/O device

The full range of addresses may be

available for both

With 10 address lines, the system

may now support both 1024
memory locations and 1024 I/O
addresses
 Special I/O instruction
• Performing a read or write of data requires several separate I/O
operations
• The processor may have to interrogate the status of the device
between individual commands
– Ex. a simple printer has two I/O device registers - one for status
information and one for data to be printed
• The Status register contains
– a done bit, set by the printer when it has printed a character,
– an error bit, indicating the printer is jammed or out of paper
• Each byte of data to be printed is put into the Data register
• The processor must then wait until the printer sets the done bit
• The processor must also check the error bit to determine if a
problem has occurred
• Each of these operations requires a separate I/O device access
Communicating with the Processor
• The process of periodically checking status bits to see if it is
time for the next I/O operation is called polling
• Polling - simplest way for an I/O device to communicate with
the processor
• The I/O device simply puts the information in a Status register,
and the processor must come and get the information

• Disadvantage of polling - Waste a lot of processor time

• Processors are so much faster than I/O devices
• The processor may read the Status register many times only
to find that the device has not yet completed
 Interrupt-driven I/O
• I/O scheme that employs interrupts to indicate to the processor
that an I/O device needs attention
• I/O interrupt is just like the exceptions with two important
distinctions
• An I/O interrupt is asynchronous with respect to the instruction
execution.
– That is, the interrupt is not associated with any instruction
and does not prevent the instruction completion
– Our control unit need only check for a pending I/O interrupt
at the time it starts a new instruction
• Identity of the device generating the interrupt
• The interrupts represent devices that may have different
priorities and whose interrupt requests have different urgencies
associated with them
 Interrupt Priority Levels
• Both internally generated exceptions and external I/O interrupts
have priorities
• I/O interrupts have lower priority than internal exceptions
• Multiple I/O interrupt priorities
• High-speed devices associated with the higher priorities

• Status register determines who can interrupt the computer

• If the interrupt enable bit is 0, then none can interrupt
 Status Register
• Interrupt mask field
– Contains a bit for each of the six hardware and two software
interrupt levels
– A mask bit 1 allows interrupts at that level to interrupt the
processor
– A mask bit 0 disables interrupts at that level
– When an interrupt arrives, it sets its interrupt pending bit in
the Cause register, even if the mask bit is disabled
– When an interrupt is pending, it will interrupt the processor
when its mask bit is subsequently enabled
• User mode bit
– 0 if the processor is running in kernel mode
– 1 if it is running in user mode
 Status Register
• Exception level bit
– normally 0, but is set to 1 after an exception occurs
– When this bit is 1,
• interrupts are disabled and the
• EPC is not updated if another exception occurs
– Prevents an exception handler from being disturbed by an
interrupt or another exception
– Should be reset when the handler finishes

• Interrupt enable bit

– 1, interrupts are allowed
– 0, they are disabled
 Cause register
• Branch delay bit is 1
– if the last exception occurred in an instruction executed in
the delay slot of a branch
• Interrupt pending bits become 1 when an interrupt is raised at a
given hardware or software level
• Exception code register describes the cause of an exception

• Exceptions and interrupts cause a MIPS processor to jump to a

piece of code, at address 80000180hex (in the kernel, not user
address space), called an exception handler
 Cause register - Exception code
• This code examines the exception’s cause and jumps to an
appropriate point in the operating system
• The OS responds to an exception either by terminating the
process that caused the exception or by performing some action
 Handling an Interrupt
• Steps that must occur in handling an interrupt
• Logically AND the pending interrupt field and the interrupt mask
field to find the enabled interrupts
• Select the higher priority of these interrupts
• The software convention is that the leftmost is the highest
priority
• Save the interrupt mask field of the Status register
• Change the interrupt mask field to disable all interrupts of equal
or lower priority
• Save the processor state needed to handle the interrupt
• To allow higher-priority interrupts, set the interrupt enable bit of
the status register to 1
 Handling an Interrupt
• Call the appropriate interrupt routine
• Before restoring state, set the interrupt enable bit of the status
register to 0. This allows you to restore the interrupt mask field

• The IPL is an operating system invention

• Stored in the memory of the process,
• Every process is given an IPL
• At the lowest IPL, all interrupts are permitted
• At the highest IPL, all interrupts are blocked
• Raising and lowering the IPL involves changes to the interrupt
mask field of the Status register
 Working- I/O Module view point
• For input, the I/O module receives a READ command from the
processor
• The I/O module then proceeds to read data in from an associated
peripheral
• Once the data are in the module’s data register, the module
signals an interrupt to the processor over a control line
• The module then waits until its data are requested by the
processor
• When the request is made, the module places its data on the data
bus and is then ready for another I/O operation
 Working - Processor point of view
• The processor issues a READ command. It then goes off and does
something else
• At the end of each instruction cycle, the processor checks for
interrupts
• When the interrupt from the I/O module occurs, the processor
saves the context of the current program and processes the
interrupt
• The processor reads the word of data from the I/O module and
stores it in memory
• It then restores the context of the program it was working on (or
some other program) and resumes execution
 Direct Memory Access (DMA)
• Both programmed I/O and Interrupt-driven I/O requires active
intervention of CPU to transfer data between memory and an I/O
module
• Two inherent drawbacks
– The I/O transfer rate is limited by the speed with which the
processor can test and service a device
– The processor is tied up in managing an I/O transfer; a number of
instructions must be executed for each I/O transfer
• Programmed I/O, the processor is dedicated to the task of I/O and
can move data at a rather high rate, at the cost of doing nothing else
• Interrupt I/O frees up the processor to some extent at the expense
of the I/O transfer rate
• Nevertheless, both methods have an adverse impact on both
processor activity and I/O transfer rate
 DMA Functions
• When large volumes of data are to be moved, a more efficient
technique required is: direct memory access (DMA)
• DMA involves an additional module (Hardware) on the system bus
• The DMA module is capable of mimicking the processor i.e. taking
over control of the system from the processor

DMA need to do this to transfer

data to and from memory over the
system bus

For this purpose, the DMA module

must use the bus only when the
processor does not need it

cycle stealing - Force the processor

to suspend operation temporarily
 DMA Operation
• When the processor wishes to read or write a block of data, it issues a
command to the DMA module
• Information send to the DMA module are:
– Whether a read or write is requested
• via read or write control line between processor and DMA module
– The address of the I/O device involved - via data line
– The starting location in memory to read from or write to
• via the data lines and stored by the DMA module in its address register
– The number of words to be read or written
• via the data lines and stored in the data count register
• The processor then continues with other work
• It has delegated this I/O operation to the DMA module
• The DMA module transfers the entire block of data, one word at a time,
directly to or from memory, without going through the processor
• When transfer is complete, DMA module sends an interrupt signal to CPU
• Thus, the processor is involved only at the beginning and end of the transfer
 DMA Transfer - Cycle Stealing
• Figure shows in the instruction cycle where the CPU may be
suspended
• In each case, the CPU suspended just before it needs to use the
bus i.e. before an operand or data fetch or a data write
• DMA module then transfers one word and returns control to CPU
Not an interrupt; the CPU does
not save a context and do
something else
CPU pauses for one bus cycle
The overall effect is to cause
the processor to execute more
slowly
For a multiple-word I/O
transfer, DMA is far more
efficient than interrupt-driven
or programmed I/O. DMA and Interrupt Breakpoints during an Instruction Cycle
 DMA Configurations (1)

• Single Bus, Detached DMA controller

• Each transfer uses bus twice
– I/O to DMA then DMA to memory
• CPU is suspended twice
• Each transfer of word consume two bus cycles
 DMA Configurations (2)

• Single Bus, Integrated DMA controller

• There is a path between the DMA module and one or more
I/O modules that does not include the system bus
• Controller may support >1 device
• Each transfer uses bus once
– DMA to memory
• CPU is suspended once
 DMA Configurations (3)

• Separate I/O Bus

• Bus supports all DMA enabled devices
• Reduces the number of I/O interfaces in the DMA module to one
• Provides for an easily expandable configuration
• Each transfer uses bus once
– DMA to memory
• CPU is suspended once
 Transferring the Data between a
Device and Memory
• Polling and I/O interrupts—two methods of transfer of data
between I/O device and memory
• Both polling and interrupt-driven transfers put the burden of
moving data and managing the transfer on the processor

• Interrupt driven I/O, the OS simply works on other tasks while

data is being read from or written to the device
• When the OS recognizes an interrupt from the device, it reads
the status to check for errors
• If there are none, the OS can supply the next piece of data
 Transferring the Data between a
Device and Memory
• Interrupt-driven I/O relieves the processor from having to wait
for every I/O event
• Transferring data from or to a hard disk, the overhead could
still be intolerable
• Since it could consume a large fraction of the processor when
the disk was transferring

• Designers invented a mechanism for offloading the processor

• Device controller transfer data directly to or from the memory
without involving the processor
• This mechanism is called direct memory access (DMA)
• The interrupt mechanism is still used by the device to
communicate with the processor, but only on completion of
the I/O transfer or when an error occurs.
 Direct Memory Access
• A mechanism that provides a device controller with the ability
to transfer data directly to or from the memory without
involving the processor
• Implemented with a specialized controller that transfers data
between an I/O device and memory independent of the
processor
• The DMA controller becomes the master and directs the reads
or writes between itself and memory