Verdi Jumpstart

Xavier Mathes – Dec 2020

© 2017 Synopsys, Inc. 1

 Agenda

Unified Front End (UFE)

Dump FSDB

Verdi GUI

Trace Design in Verdi

Debug Design in Verdi

© 2017 Synopsys, Inc. 2

 Unified Front End
Generate and Import KDB

© 2017 Synopsys, Inc. 3

 Verdi3 Unified Debug Architecture
Debug continuity across domains & abstractions

Virtual Static & FPGA-based

Simulation Emulation
Prototyping Formal Prototyping
Native Native Native Native Native

Verdi3 Environment VC Apps

Unified GUI, Unified Databases

KDB FSDB VDB ?

Verdi3 Analysis Engines

Verdi3
Structural Behavior Temporal Auto Transaction Coverage
Core Analysis Analysis Analysis Tracing Analysis Analysis
Debug

UVM- Power- Protocol-

AMS HW/SW Coverage Formal
Aware Aware Aware
Debug Debug Debug Debug
Debug Debug Debug

© 2015 Synopsys, Inc. 4

 Overview
Traditional Flow vs. Unified Front End

• Traditional Compile Flow • UFE Compile Flow

– Compile design twice – bad performance – Compile once and generate all database
– One for simulation database, one for debug – Better performance
database – Simple Usage
– Inconsistent may exist between databases – Only add one option to simulator executable
– XLRM (Out-of-LRM)
– Consistent result between Verdi and simulator
– Different design top
Native Integration
VCS Design
Verdi Debug Database
VCS Simulation Debug Unified Compile Verdi Design
Database
Database
VCS Design
Database Verdi Design
Compile Compile Database
Debug Database
Simulate

Simulate Debug
Debug
© 2017 Synopsys, Inc. 5
 Compile Option

• Just add the –kdb option to VCS executables when running simulation

• Three steps flow:

– % vlogan/vhdlan/syscan –kdb
– Compile design and generate un-resolved KDB to ./work
– % vcs –kdb
– Generate elaborated KDB to ./simv.dadir
• Two steps flow:
– % vcs –kdb –debug_access+all
– Compile design and generate elaborated KDB to ./simv.dadir

© 2017 Synopsys, Inc. 6

 Run Time Usage Model
Load KDB to Verdi

• Interactive Mode (debug with simulator):

– Add –verdi option to simv executable:
– % simv –verdi

• Post-Processing Mode (After getting the FSDB):

– Simply load the FSDB (using -ssf), the KDB will be loaded automatically:
– % verdi –ssf my.fsdb
– If you have move the simv.dadir directory to somewhere else, use the –dbdir option to load it:
– % verdi –ssf my.fsdb –dbdir <path to>/simv.dadir

© 2017 Synopsys, Inc. 7

 Dump FSDB

Generate FSDB with VCS

FSDB Utilities

© 2017 Synopsys, Inc. 8

 Dump FSDB
Generate FSDB with VCS

© 2017 Synopsys, Inc. 9

 Natively Dump FSDB with VCS

• Add the –debug_access option in VCS to dump FSDB natively

– Note the design still need to contain dumping task ($fsdbDumpvars) or command (fsdbDumpvars)

• Usage:
– Set VERDI_HOME to the Verdi install directory
– % setenv VERDI_HOME <Verdi_install_directory>
– Add –debug_access option in vcs
– % vcs –debug_access test.v –lca –kdb –full64

• NOTE: The –P, –debug, -debug_all, and –debug_pp options should be removed since it
conflicts with the –debug_access option

© 2017 Synopsys, Inc. 10

 Extra Option to Dump Library and Cell
Using the –debug_region Option

• Apply debugging capabilities to the desired portion of a design (DUT, cell, testbench (TB),
standard package (OVM, UVM, VMM, and RAL), or encrypted instances (modules, programs,
packages, interfaces)).

• Usage:
-debug_access(+<option>)* -debug_region=(<option>)(+<option>)*

• Example: to dump FSDB contains libraries and cells

– % % vcs test.v –debug_access –debug_region=lib+cell –lca –full64

• Note:
– -debug_region works only for the capabilities specified by -debug_access option. It has no effect on
the capabilities specified in tab files or configuration files

© 2017 Synopsys, Inc. 11

 Flow to Dump FSDB
Add dumping tasks
into your design Import design into Verdi
Dumping (Automatically done when
loading FSDB)
Tasks Your Design

Novas PLI Run Simulator

Link Novas PLI with
simulator
(Adding –debug_access
to VCS)

Generate dumping
result in FSDB format FSDB file Import FSDB
into Verdi

© 2017 Synopsys, Inc. 12

 FSDB Utilities

© 2017 Synopsys, Inc. 13

 FSDB Utilities
Process FSDB Files in Batch
• vfast
– Convert VCD files to FSDB files
• fsdb2vcd
– Convert FSDB files to VCD files
• fsdbextract
– Extract signals, scopes, time periods from existing FSDB files without re-simulating
• fsdbmerge
– Merge several FSDB files into one
• fsdbreport
– Generates a report of value changes for specified signals
• Fsdbdebug
– Debug/extract FSDB files

© 2017 Synopsys, Inc. 14

 FSDB Dumping Tasks
Frequently Used Dumping Tasks
• $fsdbDumpfile - Specify FSDB file name, limit the FSDB file size
– Uses the sliding window scheme to keep the last signal values in the FSDB file and drops the old values if file size
exceeds the limitation.

• $fsdbDumpvars - Dump signal value changes of specified instances and depth

– Can also specify the FSDB file name; different FSDB file names can be specified in each fsdbDumpvars
command.

• $fsdbDumpon/ fsdbDumpoff - Turn on/off FSDB dumping

– Can specify FSDB file name to turn on/off specific FSDB file

• $fsdbAutoSwitchDumpfile - Limit FSDB file size and switch dumping to new FSDB file automatically.

NOTE: Refer to Appendix 2: Frequently Used Dumping Tasks section in the end of this slide, to get detail usage of
most frequently used system tasks

© 2017 Synopsys, Inc. 15

 Fsdb probing example
Hints
• Add the following code into ./verilog/src/system.v:
– initial $fsdbSuppress is a global setting (affect all FSDB files
– begin), and must be specified before $fsdbDumpvars
– Generate My.fsdb, includes
$fsdbSuppress(system.i_pram);
$fsdbDumpvars (withoutall signals
any under
option) will generate a
system.i_cpu.i_ALUB scope and its child scopes (depth=0)
– $fsdbDumpvars; novas.fsdb and includes all scope by default
– $fsdbDumpvars(0, system.i_cpu.i_ALUB, "+fsdbfile+My.fsdb");
– #5000 Turn off dumping between
– $fsdbDumpoff("+fsdbfile+My.fsdb"); 5000~7000ns for My.fsdb
– #2000
– $fsdbDumpon("+fsdbfile+My.fsdb");
– #5500 $finish; Continue dumping till 12500ns
– end

© 2017 Synopsys, Inc. 16

 nWave overview and features
Debug Waveforms

© 2017 Synopsys, Inc. 17

 Overview of Waveform View
View Waveforms in nWave

• In the main window, invoke Tools  New Waveform or click on the New Waveform icon
to open nWave frame
– The nWave frame is opened in the bottom frame of the main window
– Click the Be Window icon can make it to be a standalone window
Cursor Position Marker Position Delta Time Ruler – Zoomed Time

Signal
Cursor
Position
Signal Pane Waveform Pane
Ruler – Full Time
Value Pane
© 2017 Synopsys, Inc. 18
 Search Signal in Get Signal Form

• Press Ctrl+F to search signals in the Get Signal form

– Matched signals will be marked as different color

Ctrl+F to open the

Search field

Matched signals
will be highlighted

© 2017 Synopsys, Inc. 19

 Waveform Markers
Set Markers

• Use Waveform  Marker to name and place markers

• Multiple markers are supported, markers can be saved and restored
• Specify name, color, and line style for labels to differentiate markers
Jump to markers
from toolbar

DC marker label
to change/delete

Labels always visible at the

top of the waveform pane

© 2017 Synopsys, Inc. 20

 Waveform Markers
Marker Values

• In nWave, turn on Waveform  Show Marker Values  Absolute, Adjacent, Relative

options to display marker values
– Turn on the Different as Frequency option to convert to frequency
• Use Waveform  Set Reference Marker command to specify the reference marker
– Default reference marker will be Cursor time

Time range
Absolute time two
between
adjacent markers
Relative to
Reference Market

© 2017 Synopsys, Inc. 21

 Waveform Alias
Create Alias for Waveforms

• Use Waveform  Signal Value Radix  Edit Alias to create/update an alias file and apply
to a signal
– Apply color to any alias

• Create a copy of a signal and

use RMB in value column
to Remove Local Alias

© 2017 Synopsys, Inc. 22

 Change Radix

• Select multiple signals (by pressing the Ctrl key), click Right-mouse-button in Value Pane
and change the radix
– Previous version only allows users to change radix for one signal

© 2017 Synopsys, Inc. 23

 Debug Delta Cycles
View VHDL Delta Cycles

• VHDL delta cycles can now be dumped and displayed with correct delta cycle number
– Turn on the View  Expand Delta  Region Mode to display delta cycles
– Can be displayed with the Verilog regions together
Delta cycle
Cursor time
number

© 2017 Synopsys, Inc. 24

 Waveform Comparison
Conventional Issues and Verdi Approach

• Issues when comparing waveforms:

– The most frequent application is to compare the RTL dumping results and the gate level dumping
results
– There usually exists mismatches between RTL and gate level simulation results. However some
mismatches can be ignored due to acceptable tolerance, and some need to be debugged
– Users need to have a good method to set constraints when comparing design, and also need a good
method to debug real mismatches

• Verdi Approach:
– Multiple nWave can be opened with different simulation databases
– Ability to perform comparison between selected signals, displayed signals or groups
– Mismatch results can be viewed, displayed and searched in nWave over time

© 2017 Synopsys, Inc. 25

 Waveform Comparison
Compare Simulation Files – Gate vs. RTL
Comparison
Mismatches
• Open two waveform frames and arrange the
layout to view both
• Load a different simulation file in each frame
• Use Window  Sync Waveform View in
one or both frames
• Use commands under Tools  Waveform
Compare to compare selected signals, Gate FSDB
displayed
signals or groups
• Viewing Errors
– Use Left / Right arrow icons on the toolbar to
step through the mismatch errors
– Use Up/Down arrow icons on the toolbar to
search through different signals at a time
RTL FSDB

© 2017 Synopsys, Inc. 26

 Verdi GUI
Search for Information

© 2017 Synopsys, Inc. 27

 One Search
Type a String to Search Everything

• The One Search window will be on by default when Verdi is invoked

– In the bottom of Verdi main window
Configure Search
Settings Query

Search
Engines
Search
Query
Hyperlinks to
nTrace Source Search
View Engines

Hyperlinks to
SmartLog Viewer

Hyperlinks to
nTrace Source
Hyperlinks to View
nTrace Source
View

Hyperlinks to
PDF Viewer

Overview Result
© 2017 Synopsys, Inc. 28 Engine Specific Results
 One Search
Command Line Tool: onesearch

• Syntax: onesearch [<options>] <search query>

– % onesearch xbus transfer class

• Type onesearch --help to get detail usage

© 2017 Synopsys, Inc. 29
 Debug Design in Verdi – With Different Views
Debug Source Code

© 2017 Synopsys, Inc. 30

 View Signal Values on Source Code
Enable Active Annotation

• Use the File  Load Simulation Results command to load FSDB file
• Enable Source  Active Annotation (or hot key x) in nTrace
– Display simulation results on source
– Signal values/transitions are synchronized with cursor time
– Select signal(s) and go to next or previous transitions
– Any Change, Rising or Falling

Search
previous/next

Simulation value will

be attached

© 2017 Synopsys, Inc. 31

 Highlight Signals
Unify Highlight for the Whole Verdi

• Select signals in any window,

invoke RMB  Highlight
command
– The color will be applied to all
windows
– D&D more signals to the Highlight
form to change color

© 2017 Synopsys, Inc. 32

 Trace Design in Verdi
Static Trace and Active Trace

© 2017 Synopsys, Inc. 33

 Static Trace – Without Simulation Result
FSDB Not Loaded

• When to use: you want to get the static drivers from source code without simulation result

Select the signal, click

Trace Driver icon

Static Drivers

Traced results will be

Click any line will jump to
logged in Message Pane
corresponding source code

© 2017 Synopsys, Inc. 34

 Active Trace – With Simulation Result
FSDB Loaded

• When to use: you want to get the active (actual) driver by considering simulation values in
current time
Current simulation value
will be considered

Traced to Traced results will be

the actual logged in Message Pane
driver

Just double click

the transition

© 2017 Synopsys, Inc. 35

 Trace Design in Verdi
Automatic Trace – Temporal Flow View

© 2017 Synopsys, Inc. 36

 Using Temporal Flow View

• Automatic cause and effect tracing

– One command to trace to the root cause
– Easy visualization of behavior with time and structure

In1@660 In1@780
Addr@600 00002

2 CWR
0
1
0

Clk2@776

mem1
ACC
IDR aa aa

Clk3@600

Clk3@700

0 Clk3@800
TDB 34
ACC

Ou1@649
Ou2@790
Clk2@676

Clk3@700

600 676 700 776 800

© 2017 Synopsys, Inc. 37

 How to Use Temporal Flow View?
From Waveform

• One command to automatically trace to the root cause

– Select the transition in waveform pane, and click the toolbar icon
– Temporal Flow View will open and automatically perform:
– Trace This Value for current time if current value is known or
– Trace Active X for current time if the current value is unknown

Click icon to do Trace This

Value or Trace Active X

Click mouse on the transition

© 2017 Synopsys, Inc. 38

 Trace a Bad Value
If the Transition is a Value

• The propagated path will be unrolled by time axis

– For example, a bad value found in out[7:0] at 950ns but the root cause is in addr[7:0] at 800ns
– One click tracing will bring you to the root cause
– Clock cycles will be considered, efficient for debugging sequential designs
– Will trace value in active drivers with the same clock cycle

Time axis

The root The wrong

cause value

© 2017 Synopsys, Inc. 39

 Trace Methods in TFV
Introduction to Transition-Based Tracing

• Input signals that trigger the output transition are automatically traced
• Used to visualize the propagation of signal transitions throughout the design and over time
• Very useful for gate level debug
• distinguishes transition based tracing from cycle-based tracing in the Temporal Flow View

© 2017 Synopsys, Inc. 40

 Correlate TFV with Other Views
Automatically Display Source Code

• Toggle on the Show Source Code Automatically icon or the View  Show Source
Code Automatically option to view corresponding source code for a selected node

Toggle on the icon

then select an object
in TFV frame

© 2017 Synopsys, Inc. 41

 Correlate TFV with Other Views
Show Traced Signals in nWave
• To show traced signals in the waveform:
– In the Temporal Flow View, invoke Tools  Show All Traced Signals on nWave to add traced
results to nWave

© 2017 Synopsys, Inc. 42

 Correlate TFV with Other Views
Show Fan-In Signals in nSchema
• To view a signal’s fan-in in nSchema:
– Select the signal
– Use Tools  Show Fan-ins on nSchema  Active Only

© 2017 Synopsys, Inc. 43

 Trace Design in Verdi
Trace Forced Signals

© 2017 Synopsys, Inc. 44

 Trace Forced Signals
Dump Forced Signals

• Add the +fsdb+force simulation runtime option or the equivalent environment variable
FSDB_FORCE can be used to dump forced information into FSDB
– The option and environment variable is valid for VCS only
– VCS versions 2013.06-SP1 or higher is required

© 2017 Synopsys, Inc. 45

 Trace Forced Signals
Debug Forced Signals in nTrace

Active Trace will

trace to the In Active Annotation, the “^” sign
force/release will be added in front of the value
statement to indicate it’s a forced value

External Command represents the

driver comes from a
force/release/deposit command
through UCLI/PLI

Traced results will be shown in

Message frame, double clicking to
jump to the source code

© 2017 Synopsys, Inc. 46

 Trace Forced Signals
Debug Forced Signals in nWave

• The forced/deposited/released information will be displayed in nWave

– Up/Down triangle represents forced/released event
– Empty triangle represents deposit forced event
– Dash line represents the forced range (forced  released)
– Double clicking will trace to the forced statement in nTrace

Forced Released

Deposit forced

© 2017 Synopsys, Inc. 47

 Debug Design in Verdi – With Different Views
Debug Schematics

© 2017 Synopsys, Inc. 48

 Open nSchema
Open a Full Hierarchy Window – Default Schematic View
• Select an instance in the nTrace design browser and click the New Schematic icon
• Or, D&D an instance from the design browser or a Verilog module or VHDL architecture from the nTrace
source code frame to New Schematic icon
• Or, execute Tools  New Schematic  Current Scope in nTrace
– The nSchema frame opens in the right frame of the main window
– Click the Be Window icon can make it to be a standalone window

© 2017 Synopsys, Inc. 49

 Open nSchema
Different Schematic Window Types

• Full Hierarchical Window – Shows complete objects in specific scope. Default schematic
view
• Browser Window – Shows partial schematic in specific scope
• Flatten Window – Shows partial schematic in flatten view, schematics in the Flatten Window
cross all scopes

Full Hierarchical Window

Browser Window

Flatten
Window

© 2017 Synopsys, Inc. 50

 Open nState Frame
Bubble Diagram to Show Finite State Machine
• DC on the state symbol to open nState
– The nState frame appears as a new tab in
the same location as the nSchema frame

• Verdi automatically identifies FSM code for 1-process, 2-process, or 3-process with
conventional encoding of the state variables
• NOTE: Remember to enable FSM Recognition option on the RTL page under the
Schematics folder of the Preferences form (invoked with Tools  Preferences)
otherwise not all FSM will be extracted
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 Manipulate FSM View
View Actions & Find States

• View  State Action

• View  Transition Condition
• View  Transition Action
• FSM  Find State

© 2017 Synopsys, Inc. 52

 Manipulate FSM View
State Animation (1/2)

• Load simulation results

• Enable FSM  State Animation
• Use Previous State / Next State toolbar icons to step through the
states
• Use FSM  Edit Search Sequence to create a sequence of states
to search on

© 2017 Synopsys, Inc. 53

 Manipulate FSM View
State Animation (2/2)

State Sequence Animation

© 2017 Synopsys, Inc. 54

 Analyze State Machines
Analyze State Transitions

• Use FSM  Analysis Report to display analysis report

– Details of FSM interpretation
– State coverage report
– Transition coverage report
• Save to File to save the report

© 2017 Synopsys, Inc. 55