Tmax 2017.09 SG

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CUSTOMER EDUCATION SERVICES
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TetraMAX
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Workshop
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Student Guide
30-I-021-SSG-017
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Synopsys Customer Education Services

690 E. Middlefield Road
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Mountain View, California 94043

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Workshop Registration: http://training.synopsys.com

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www.synopsys.com
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For Internal Microchip Training Purposes Only

Copyright Notice and Proprietary Information
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of Synopsys, Inc., or as expressly provided by the license agreement.
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All technical data contained in this publication is subject to the export control laws of the United States of
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reader's responsibility to determine the applicable regulations and to comply with them.
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Disclaimer
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http://www.synopsys.com/Company/Pages/Trademarks.aspx.
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Synopsys, Inc.
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690 E. Middlefield Road

Mountain View, CA 94043
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www.synopsys.com
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Document Order Number: 30-I-021-SSG-017

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TetraMAX Student Guide

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Table of Contents
Unit i: Introduction & Overview

Facilities ............................................................................................................................ i-2
Workshop Overview ......................................................................................................... i-3
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Target Audience ................................................................................................................ i-4
Workshop Prerequisite Knowledge .................................................................................. i-5
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Introductions ..................................................................................................................... i-6
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Agenda .............................................................................................................................. i-7
Agenda .............................................................................................................................. i-8
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Agenda .............................................................................................................................. i-9
Icons Used in this Workshop .......................................................................................... i-10
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Unit 1: Introduction to Test and TetraMAX
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Agenda ............................................................................................................................. 1-1
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Unit Objectives ................................................................................................................ 1-2
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Manufacturing Test Programs.......................................................................................... 1-3
Stuck-At Fault Model ...................................................................................................... 1-4
Rules for Detecting a Stuck-At Fault ............................................................................... 1-5
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Combinational Logic: Stuck-At Testing .......................................................................... 1-6
Activate the SA0 Fault (1/4) ........................................................................................... 1-7
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Propagate Fault Effect (2/4) ............................................................................................ 1-8

Anatomy of a Test Pattern (3/4) ...................................................................................... 1-9
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Record the Test Pattern (4/4) ........................................................................................ 1-10

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Testing Sequential Designs ............................................................................................ 1-11

Scannable Equivalent Flip-Flop..................................................................................... 1-12
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The Full Scan Strategy ................................................................................................... 1-13

Scan Testing Protocol .................................................................................................... 1-14
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Test Patterns Overlap .................................................................................................... 1-15

TetraMAX Overview ..................................................................................................... 1-16
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TetraMAX Interfaces ..................................................................................................... 1-17

ATPG Flow in TetraMAX ............................................................................................. 1-18
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Launching TetraMAX .................................................................................................... 1-19

Example TetraMAX Script ........................................................................................... 1-20
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Tcl API Commands........................................................................................................ 1-21

Using Collections and Filters ......................................................................................... 1-22
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Retrieving Attributes Values.......................................................................................... 1-23

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Tcl API Example............................................................................................................ 1-24

TetraMAX On-Line Help (OLH)................................................................................... 1-25
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Getting Help - SolvNet Resources ................................................................................. 1-26

Unit Objectives Summary .............................................................................................. 1-27
Command Summary (Lecture, Lab) .............................................................................. 1-28
Synopsys 30-I-021-SSG-017 i TetraMAX Workshop

Table of Contents
Unit 2: Building ATPG Models

Agenda ............................................................................................................................. 2-1
Unit Objectives ................................................................................................................ 2-2
BUILD Mode in TetraMAX ............................................................................................ 2-3
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Reading the Library Files................................................................................................. 2-4
Cell Models Derived from Simulation Library ................................................................ 2-5
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ATPG Model Derivation.................................................................................................. 2-6
Expect Warnings if Library not “Validated” ................................................................... 2-7
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Duplicate Module Definitions.......................................................................................... 2-8
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Read Design Netlist ......................................................................................................... 2-9
Build the ATPG Design Model...................................................................................... 2-10
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Missing Modules Discovered During Build .................................................................. 2-11
How Many Modules Are Missing? ................................................................................ 2-12
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Read ATPG Memory Models, If Available ................................................................... 2-13
Define Black Boxes If No ATPG Model Exists ............................................................ 2-14
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Empty Boxes Versus Black Boxes ................................................................................ 2-15
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Mode is DRC…Ignore those Build Violations? ............................................................ 2-16
Investigate Each N and B Warning ................................................................................ 2-17
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Did All of the Cells Translate Properly?........................................................................ 2-18
Graphical Schematic Viewer (GSV) .............................................................................. 2-19
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Design View vs. Primitive View In GSV ...................................................................... 2-20
Prefer to Debug ATPG Models Graphically? ................................................................ 2-21
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Investigating Models Graphically .................................................................................. 2-22

What If ATPG Models Cannot Be Derived? ................................................................. 2-23
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ATPG Modeling Primitives: Partial List ....................................................................... 2-24

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ATPG Modeling Primitives: Examples ......................................................................... 2-25

Testability of Embedded Memory ................................................................................. 2-26
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Memory DFT Strategies ................................................................................................ 2-27

Black Box or Bypass Mode ........................................................................................... 2-28
TetraMAX Memory Model............................................................................................ 2-29
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Clock Stable and Load Stable ........................................................................................ 2-30

RAM/ROM Modeling.................................................................................................... 2-31
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RAM Modeling: Basic Example .................................................................................... 2-32

ROM Model: Basic Example ......................................................................................... 2-33
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Utility to Generate TetraMAX Memory Models ........................................................... 2-34

Want to Quickly Return to DRC Mode? ....................................................................... 2-35
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Unit 3: Running DRC

Agenda ............................................................................................................................. 3-1
Unit Objectives ................................................................................................................ 3-2
ATPG Flow in TetraMAX ............................................................................................... 3-3
Synopsys 30-I-021-SSG-017 ii TetraMAX Workshop

Table of Contents
Controlling ATPG: Agenda ............................................................................................. 3-4

How Does TetraMAX Perform Design Rule Checks (DRC)? ........................................ 3-5
Partial STIL Protocol File ................................................................................................ 3-6
Different Ways to Create a STIL Protocol File ............................................................... 3-7
Writing Out the STIL Protocol File ................................................................................. 3-8
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Using Quick STIL Commands......................................................................................... 3-9
Defining PI Constraints.................................................................................................. 3-10
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Defining PI Equivalences .............................................................................................. 3-11
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SPF: PI Constraints and PI Equivalences ...................................................................... 3-12
Defining Clocks ............................................................................................................. 3-13
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Defining Asynchronous Set/Reset ................................................................................. 3-14
SPF: Capture Procedures ............................................................................................... 3-15
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SPF: Defining Scan Chains & Scan Enable ................................................................... 3-16
SPF: Controlling Test Mode .......................................................................................... 3-17
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Where Does TetraMAX Get Timing Info? .................................................................... 3-18
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Default WaveformTable (_default_WFT) ..................................................................... 3-19
Pre-clock Measure vs. End-of-cycle Measure ............................................................... 3-20
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Pre-clock Measure ......................................................................................................... 3-21
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TetraMAX Design Rule Checks .................................................................................... 3-22
Performing Scan Design Rule Checks ........................................................................... 3-23
Results of Design Rule Checks ...................................................................................... 3-24
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Controlling ATPG: Agenda ........................................................................................... 3-25
Debugging DRC Violations ........................................................................................... 3-26
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Debugging an S1 Violation ............................................................................................ 3-27

Debug S1 Violations Graphically in the GSV ............................................................... 3-28
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Change Pindata to test_setup to Debug Initialization Issues ......................................... 3-29

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Stability Patterns ............................................................................................................ 3-30

Simulation Waveform Viewer (SWV)........................................................................... 3-31
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Using the SWV .............................................................................................................. 3-32

Supported Pindata Types with SWV ............................................................................. 3-33
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Want to Quickly Return to TEST Mode? ...................................................................... 3-34

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Fault Classes .................................................................................................................. 3-36

Scan Path Faults are Detected by Implication ............................................................... 3-37
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Faults Classifications Right After DRC ......................................................................... 3-38

PT - Possibly Detected Faults ........................................................................................ 3-39
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Unused FF Output Pins become UU Faults ................................................................... 3-40

Actual Tie-offs in Netlist Become UT Faults ................................................................ 3-41
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Undetectable Redundant (UR) Fault .............................................................................. 3-42

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Constraints Can Create AU Faults ................................................................................. 3-43

Fault Progression from NC to DS .................................................................................. 3-44
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Defining Nofaults........................................................................................................... 3-45

Creating a Fault List with Nofaults ................................................................................ 3-46
Fault Interface File Format ............................................................................................ 3-47
Equivalent Faults .......................................................................................................... 3-48
Fault Collapsing ............................................................................................................. 3-49
Synopsys 30-I-021-SSG-017 iii TetraMAX Workshop

Table of Contents
Fault List After Collapsing ........................................................................................... 3-50

Equivalent Faults in the Fault File ................................................................................ 3-51
Collapsed vs. Uncollapsed Faults .................................................................................. 3-52
Calculating Test and Fault Coverage ............................................................................. 3-53
How to Report Fault Coverage ...................................................................................... 3-54
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Adding Faults / Saving Faults ........................................................................................ 3-55
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Unit 4: Controlling ATPG
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Agenda ............................................................................................................................. 4-1
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Unit Objectives ................................................................................................................ 4-2
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Controlling ATPG: Agenda ............................................................................................. 4-4
Running ATPG ................................................................................................................ 4-5
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ATPG: Select TetraMAX Engine(s) ................................................................................ 4-6
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Results after Basic-Scan ATPG ....................................................................................... 4-7
AU: Untestable under Current ATPG Settings ................................................................ 4-8
ATPG: Basic-Scan versus Fast-Sequential ...................................................................... 4-9
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Loadable Nonscan Cells ................................................................................................ 4-10
Using Loadable Nonscan Cells ...................................................................................... 4-11
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Enabling Fast-Sequential ATPG .................................................................................... 4-12

How to Determine –capture_cycles ............................................................................... 4-13
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When Can Fast-Sequential ATPG Help? ....................................................................... 4-14

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Results after Fast-Sequential ATPG .............................................................................. 4-15

How to Enable Full-Sequential Engine.......................................................................... 4-16
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ATPG Guidelines ........................................................................................................... 4-17

Multicore Support in TetraMAX ................................................................................... 4-18
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Enabling Multicore Support ........................................................................................... 4-19

Multicore Script Examples ............................................................................................ 4-20
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Multicore run_atpg Output ............................................................................................ 4-21

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Post-ATPG: Reducing ND Faults .................................................................................. 4-23

Post-ATPG: Results with Higher Abort Limit............................................................... 4-24
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Post-ATPG: Final Abort Limit Results.......................................................................... 4-25

Low Coverage: Review PI Constraints .......................................................................... 4-26
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Low Coverage: Analyze the Clocks .............................................................................. 4-27

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Are All Expected Flops Scannable? .............................................................................. 4-28

DRC Rules Affecting Coverage..................................................................................... 4-29
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Hierarchical Test Coverage............................................................................................ 4-30

Isolate the Impact of the AU Faults ............................................................................... 4-31
Running Analysis of AU Faults ..................................................................................... 4-32
Report More Details of AU Faults ................................................................................. 4-33
Fault Analysis Source Points ......................................................................................... 4-34
Synopsys 30-I-021-SSG-017 iv TetraMAX Workshop

Table of Contents
Analyze a Particular AU Fault ....................................................................................... 4-35

Analyze a Particular AU Fault ....................................................................................... 4-36
Hierarchy Browser ......................................................................................................... 4-37
Tips for Improving Test Coverage ................................................................................. 4-38
Functional Pattern Fault Simulation .............................................................................. 4-39
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Want to Quickly Return Post-ATPG?............................................................................ 4-40
Interrupting a Long Process ........................................................................................... 4-41
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TetraMAX II .................................................................................................................. 4-43
Running TetraMAX II ................................................................................................... 4-44
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TetraMAX II Specific Command Options ..................................................................... 4-45
When is Threading Used With TetraMAX II ................................................................ 4-46
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TetraMAX II Messages: Ignored Settings ..................................................................... 4-47
TetraMAX II Simulation................................................................................................ 4-48
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Other Behavior Differences with TetraMAX II ............................................................. 4-49
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TetraMAX II Limitations ............................................................................................... 4-50
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Command Summary ..................................................................................................... 4-52
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Appendix ........................................................................................................................ 4-53
Test Point Analysis ........................................................................................................ 4-54
Options: analyze_test_points (1/3) ................................................................................ 4-55
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Test Point Analysis Flow ............................................................................................... 4-58

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Unit 5: Minimizing ATPG Patterns

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Agenda ............................................................................................................................. 5-1

Unit Objectives ................................................................................................................ 5-2
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Benefits of Compact Vector Sets ..................................................................................... 5-3

What is Dynamic Pattern Compression? ......................................................................... 5-4
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Controlling Dynamic Pattern Compression ..................................................................... 5-5

Minimum Detects ATPG Option ..................................................................................... 5-6
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Avoiding Patterns that Detect Too Few Faults ................................................................ 5-7

Using run_atpg -optimize_patterns .................................................................................. 5-8
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Dynamic Clock Grouping ................................................................................................ 5-9

Dynamic Clock Grouping: Parallel ................................................................................ 5-10
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Dynamic Clock Group: Disturbed ................................................................................. 5-11

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Analyze Clock Grouping and Disturbances ................................................................... 5-12

Clock Grouping for Each Pattern ................................................................................... 5-13
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Adding Fault Models Increases Test Cost ..................................................................... 5-14

How Compression Works .............................................................................................. 5-15
Test Compression Concepts ........................................................................................... 5-16
Test Cycle Savings ......................................................................................................... 5-17
Test Modes Created During Insertion ............................................................................ 5-18
Synopsys 30-I-021-SSG-017 v TetraMAX Workshop

Table of Contents
Passing Compression Information to TetraMAX .......................................................... 5-19

ATPG – Scan Compression Flow .................................................................................. 5-20
Explore Compression in TetraMAX .............................................................................. 5-21
Using analyze_compressors Example............................................................................ 5-22
DFTMAX Ultra and ATPG ........................................................................................... 5-23
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Updating DFTMAX Ultra Patterns ................................................................................ 5-24
DFTMAX Ultra Padding Patterns ................................................................................. 5-25
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Unit 6: Pattern Validation
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Agenda ............................................................................................................................. 6-1
Unit Objectives ................................................................................................................ 6-2
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ATPG Pattern Validation: Agenda .................................................................................. 6-4
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ASIC Vendor: Specific Considerations ........................................................................... 6-5
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Options for Writing Patterns ............................................................................................ 6-6
Unified STIL Flow vs. Dual STIL Flow .......................................................................... 6-7
General Guidelines for Saving Patterns ........................................................................... 6-8
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Scan Chain Test ............................................................................................................... 6-9
Set Chain Test Bit Sequence before ATPG ................................................................... 6-10
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DFTMAX Ultra Chain Test Patterns ............................................................................. 6-11

Splitting Up Large Pattern Sets...................................................................................... 6-12
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Generate Reports Now for Later Debugging ................................................................. 6-13

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ATPG Pattern Validation: Agenda ................................................................................ 6-14

The Challenge of Verifying Scan Designs..................................................................... 6-15
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Verilog Pattern Validation ............................................................................................. 6-16

What is MAX Testbench? .............................................................................................. 6-17
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Using MAX Testbench .................................................................................................. 6-18

Configuration File Overview ......................................................................................... 6-19
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Parallel vs. Serial Load During Simulation ................................................................... 6-20

Flexible Simulation: Serial Vs. Parallel ......................................................................... 6-21
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Serial Load Simulate Which Patterns? .......................................................................... 6-22

Selecting Serial Patterns by Capture Clock ................................................................... 6-23
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Write Only Those Selected Patterns .............................................................................. 6-24

Handling Split Patterns With MAX Testbench ............................................................. 6-25
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Runtime Programmability .............................................................................................. 6-26

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Runtime Programmability for Patterns .......................................................................... 6-27

Recommended Simulation Strategy ............................................................................... 6-28
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Verilog Simulation ......................................................................................................... 6-29

Recognize Common Mismatch Causes ......................................................................... 6-31
Begin Debugging the First Failure ................................................................................. 6-32
Failure Log Formats ....................................................................................................... 6-33
Synopsys 30-I-021-SSG-017 vi TetraMAX Workshop

Table of Contents
Regular Scan Mode Failure Log Formats ...................................................................... 6-34

Regular Scan Mode Failure Log Formats with Cell Names .......................................... 6-35
Compression Mode Failure Log Formats (Unified STIL Flow) .................................... 6-36
Compression Mode Failure Log Formats (Dual STIL Flow) ........................................ 6-37
Combined Pattern Validation (CPV) ............................................................................. 6-38
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Generating a PSD File ................................................................................................... 6-39
Compression Mode Failure Log Formats with PSD ...................................................... 6-40
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Post Process Fail Log to Show Failing Cell Names ..................................................... 6-41
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Flow to Post Process Fail Log and Show Failing Cell Names ...................................... 6-42
Useful Debugging Signals ............................................................................................. 6-43
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What is Parallel Testbench Doing? ................................................................................ 6-44
Simulation Waveforms .................................................................................................. 6-45
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Comparing Waves to TetraMAX ................................................................................... 6-46
Some Causes of Simulation Mismatches ....................................................................... 6-47
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Still Have Failures in Simulation or on ATE? ............................................................... 6-49
Masking Simulation Failures ......................................................................................... 6-50
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Defining Input or Output Masks .................................................................................... 6-51
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Scan Cell Constraints ..................................................................................................... 6-52
Non-Scan Cell Masks .................................................................................................... 6-53
Per-cycle Pattern Masking ............................................................................................. 6-54
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Fail Data File Support From Simulation ........................................................................ 6-55
Failure Data File Formats From Simulation .................................................................. 6-56
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DFTMAX Ultra chain masking ..................................................................................... 6-57

DFTMAX Ultra chain masking: Examples ................................................................... 6-58
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Unit 7: Fault Models and At-Speed Testing

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Agenda ............................................................................................................................. 7-1

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Unit Objective .................................................................................................................. 7-2

New Defect Types with New Technologies .................................................................... 7-3
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Sources of Test Escapes ................................................................................................... 7-4

Delay Testing Introduction: Agenda ................................................................................ 7-5
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Fault Models .................................................................................................................... 7-6

At-Speed Defect ............................................................................................................... 7-7
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Why Chips Fail “At-Speed”? ........................................................................................... 7-8

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Methodologies for At-Speed Defect Testing ................................................................... 7-9

Which Methodology Detects Most Defects? ................................................................. 7-10
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Transition Delay Fault Model ....................................................................................... 7-11

Detection Path : Does it Matter? ................................................................................... 7-12
Detecting a Small Delay Defect ..................................................................................... 7-13
How Are Delay Defects Distributed? ............................................................................ 7-14
TetraMAX Slack-Based Transition ATPG .................................................................... 7-15
Synopsys 30-I-021-SSG-017 vii TetraMAX Workshop

Table of Contents
Cell-Aware Test ............................................................................................................. 7-16

Slack-Based Cell-Aware Test ........................................................................................ 7-17
Z01X Cell-Aware Fault Simulation ............................................................................... 7-18
Path Delay Fault Model ................................................................................................. 7-19
Bridging Fault Models ................................................................................................... 7-20
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Delay Testing Introduction: Agenda .............................................................................. 7-21
At-Speed Fault Models .................................................................................................. 7-22
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Structured At-Speed Fault Testing................................................................................. 7-23
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At-Speed Launch Methods ............................................................................................ 7-24
Transition Launch Methods ........................................................................................... 7-25
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system_clock Launch (Default) ..................................................................................... 7-26
system_clock Launch: Example .................................................................................... 7-27
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system_clock Launch: Details ....................................................................................... 7-28
Additional Delay Test Cycles ........................................................................................ 7-29
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last_shift Launch ........................................................................................................... 7-30
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last_shift Launch: Example............................................................................................ 7-31
last_shift Launch: Details .............................................................................................. 7-32
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extra_shift Launch: Details ............................................................................................ 7-33
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Pipelined ScanEnable..................................................................................................... 7-34
Delay Testing Introduction: Agenda .............................................................................. 7-35
STIL Protocol File Timing............................................................................................. 7-36
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Allclock Capture Procedures ......................................................................................... 7-37
allclock_*{} Procedures Example ................................................................................. 7-38
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WFTs for External System Clock Launch ..................................................................... 7-39

WFTs for External Clock Last Shift Launch ................................................................. 7-40
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Preambles and Postambles ............................................................................................ 7-41

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Unit 8: At-Speed Constraints

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Agenda ............................................................................................................................. 8-1

Unit Objective ................................................................................................................. 8-2
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At-Speed Constraints ....................................................................................................... 8-3

At-Speed Constraints: Agenda ......................................................................................... 8-4
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Timing Exceptions ........................................................................................................... 8-5

Slow Ports ........................................................................................................................ 8-6
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Slow Cells ........................................................................................................................ 8-7

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At-Speed Constraints: Agenda ......................................................................................... 8-8

Timing Exceptions with an SDC file ............................................................................... 8-9
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Exception Types............................................................................................................. 8-10

Simulation of Timing Exception During ATPG ............................................................ 8-11
Reading SDC ................................................................................................................ 8-12
Supported SDC Clock Constructs .................................................................................. 8-13
Supported SDC Exceptions............................................................................................ 8-14
Synopsys 30-I-021-SSG-017 viii TetraMAX Workshop

Table of Contents
Controlling Clock Propagation ...................................................................................... 8-15

SDC Timing Exception Example .................................................................................. 8-16
Functional Mode Vs Test Mode ................................................................................... 8-17
Test Mode Timing.......................................................................................................... 8-18
Timing Violations in Test Mode .................................................................................... 8-19
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Timing Exceptions From Violations Flow .................................................................... 8-20
Fine Tuning the SDC Flow ............................................................................................ 8-21
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Report SDC Exceptions ................................................................................................. 8-22
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Identifying AU Faults Caused by SDC Timing Exceptions .......................................... 8-23
At-Speed Constraints: Agenda ....................................................................................... 8-24
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Scan Testing is Power-Hungry ...................................................................................... 8-25
Power Problems During Shift Mode .............................................................................. 8-26
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Low-Power (i.e. Adjacent) Fill ...................................................................................... 8-27
Shift Power Effort and Budget ....................................................................................... 8-28
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Power Problems During Capture Mode ......................................................................... 8-29
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Excessive Power During Scan Capture.......................................................................... 8-30
Capture Power with Standard ATPG ............................................................................. 8-31
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Capture Power with Power-Aware ATPG ..................................................................... 8-32
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Power-Aware ATPG Commands ................................................................................... 8-33
Clock Gating Report ...................................................................................................... 8-34
Power-Aware Pattern Reporting .................................................................................... 8-35
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Power-Aware ATPG Script Example ............................................................................ 8-36
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Unit 9: Transition Delay Testing

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Agenda ............................................................................................................................. 9-1

Unit Objective ................................................................................................................. 9-2
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Transition Delay: Agenda ................................................................................................ 9-3

Step-by-Step Transition ATPG ....................................................................................... 9-4
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Transition Delay ATPG Script ........................................................................................ 9-5

Adding Transition Delay Faults ...................................................................................... 9-6
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Optimized Transition Delay ATPG Engine ..................................................................... 9-7

Design Guidelines for Transition Testing ........................................................................ 9-8
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Requirements for Transition ATPG ................................................................................. 9-9

Transition Delay Flow Considerations .......................................................................... 9-10
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Inter-Clock Domain Paths.............................................................................................. 9-11

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Common Launch Capture ............................................................................................. 9-12

Transition Delay: Agenda .............................................................................................. 9-13
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Testing for Small Delay Defects .................................................................................... 9-14

Slack-Based ATPG Flow ............................................................................................... 9-15
Slack Data Generation : PrimeTime Flow ..................................................................... 9-16
Reading Slack Data ....................................................................................................... 9-17
Slack on Red Path .......................................................................................................... 9-18
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Table of Contents
Slack on Green Path ....................................................................................................... 9-19

Slack on Blue Path ......................................................................................................... 9-20
Lowest Slacks On Each Pin ........................................................................................... 9-21
Slack-Based ATPG Terminology .................................................................................. 9-22
Illustration of Tmgn Tdet and Delta ............................................................................. 9-23
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Test For Understanding (Ex. 1) ..................................................................................... 9-24
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Negative and Infinite Slack ............................................................................................ 9-27
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Setting Standard for Targeted Faults ............................................................................. 9-29
Minimizing Pattern Count Inflation ............................................................................... 9-30
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Setting max_tmgn – Default ∞ – Too Many ................................................................. 9-31
Setting a Reasonable max_tmgn .................................................................................... 9-32
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Setting Standard for Full Detection ............................................................................... 9-33
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Setting max_delta_per_fault .......................................................................................... 9-34
Partially Detected Faults : TP ....................................................................................... 9-35
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Fault Report with Slack Data ......................................................................................... 9-36
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Fault Report: report_faults –slack tmgn ........................................................................ 9-37
Fault Report: report_faults –slack tdet ........................................................................... 9-38
Fault Report: report_faults –slack delta ......................................................................... 9-39
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Metric: Delay Effectiveness ........................................................................................... 9-40
Slack-Based ATPG Flow ............................................................................................... 9-41
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Slack-Based Test Does a Better Job .............................................................................. 9-42

Improved Pattern Quality ............................................................................................... 9-43
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Persistent Fault Models .................................................................................................. 9-45

Persistent Fault Model Flow .......................................................................................... 9-46
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Direct Credit .................................................................................................................. 9-47

Combined Coverage with Persistent Fault Models ........................................................ 9-48
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Unit 10: On-Chip Clocking Support

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Agenda ........................................................................................................................... 10-1

Unit Objective ............................................................................................................... 10-2
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At-Speed Clocking ......................................................................................................... 10-3

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Issues Testing At-Speed with External Clocks .............................................................. 10-4

Requirements for Using Existing PLL Clocks............................................................... 10-5
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On Chip Clock (OCC) Controller .................................................................................. 10-6

Fundaments of OCC ...................................................................................................... 10-7
OCC IP Operation .......................................................................................................... 10-8
OCC Flows in ATPG ..................................................................................................... 10-9
DFT Compiler and TetraMAX OCC Flows ................................................................ 10-10
Synopsys 30-I-021-SSG-017 x TetraMAX Workshop

Table of Contents
TetraMAX Flow: SPF Available ............................................................................... 10-11

TetraMAX Flow: SPF Not Available ......................................................................... 10-12
OCC QUICK STIL Flow (1/2) ................................................................................... 10-13
OCC QUICK STIL Flow (2/2) .................................................................................... 10-14
Black Box Requirement for DRC ................................................................................ 10-15
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DRC Violations ............................................................................................................ 10-16
Reporting Internal and PLL Clocks ............................................................................ 10-17
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Asynchronous Reference Clocks ................................................................................. 10-18
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Reference Clock and Pattern Formats.......................................................................... 10-19
ATE Cycles During Scan Capture ............................................................................... 10-20
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Issue: Capture Window Too Small .............................................................................. 10-21
Solution: Increase the Number of ATE Cycles............................................................ 10-22
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Capture Cycles with OCC ............................................................................................ 10-23
PLL Clocks in Capture Cycle ...................................................................................... 10-24
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Clock Grouping with OCC .......................................................................................... 10-25
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Multiple OCC Controller Usage During ATPG .......................................................... 10-26
Report OCC Clocking .................................................................................................. 10-27
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Verification of On-Chip Clocking ............................................................................... 10-28
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Inter-Clock Domain Test with Synchronous OCC ...................................................... 10-29
Synchronous Multi-Frequency Clocks ........................................................................ 10-30
Internal Clocking Procedures (ICP) ............................................................................. 10-31
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SPF Example With ICP ............................................................................................... 10-32
ICP Setup and Commands ........................................................................................... 10-33
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ICP Reporting Examples.............................................................................................. 10-34

Clocking Procedures Pattern Grouping ....................................................................... 10-35
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Unit Objectives Summary ............................................................................................ 10-36

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Command Summary (Lecture, Lab) ............................................................................ 10-37

Appendix ...................................................................................................................... 10-38
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OCC Controller Waveforms ........................................................................................ 10-39

Avoid Unified ATE Clock ........................................................................................... 10-40
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Avoid Using Reference Clock as Shift Clock.............................................................. 10-41

Avoid Using Reference Clock for Capture or in test_setup ........................................ 10-42
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Clock Bits Must Hold State ......................................................................................... 10-43

Very Slow De-assertion of Scan Enable ...................................................................... 10-44
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Solution: Add load_unload Postamble* ...................................................................... 10-45

Very Slow Assertion of Scan Enable ........................................................................... 10-46
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Solution: Add load_unload preamble * ....................................................................... 10-47

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Unit 11: Path Delay Testing

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Agenda ........................................................................................................................... 11-1

Unit Objective ............................................................................................................... 11-2
Automated Links for At-Speed Tests ............................................................................ 11-3
Path Delay Flow ............................................................................................................. 11-4
Main write_delay_paths Options ................................................................................... 11-5
Synopsys 30-I-021-SSG-017 xi TetraMAX Workshop

Table of Contents
Path Delay Fault Models and ATPG Engines............................................................... 11-6

Path Delay ATPG : Setup Check ................................................................................... 11-7
Path Delay ATPG : Hold Check .................................................................................... 11-8
Hold Time Path Delay Flow Details .............................................................................. 11-9
ATPG Script Examples ................................................................................................ 11-10
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Path Delay Hold Time ATPG Script ........................................................................... 11-11
Managing Faults........................................................................................................... 11-12
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Path File ....................................................................................................................... 11-13
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Path Syntax ................................................................................................................. 11-14
Path Example ............................................................................................................... 11-15
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Untestable Paths ........................................................................................................... 11-16
On Path Vs. Off Path Inputs ........................................................................................ 11-17
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Hazards Can Impact Path Delay Tests ......................................................................... 11-18
Hazard-Free Path Delay Test Example ........................................................................ 11-19
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Robust Path Delay Test ................................................................................................ 11-20
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Robust Path Delay Test Example ................................................................................ 11-21
Non-Robust Path Delay Tests ...................................................................................... 11-22
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Non-Robust Path Delay Test Example ........................................................................ 11-23
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Summary of Path Delay Fault Detections .................................................................... 11-24
Characterization Tests .................................................................................................. 11-25
Fault Classification ...................................................................................................... 11-26
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Launch Cycle ............................................................................................................... 11-27
Simulating Hazards ...................................................................................................... 11-28
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Reconvergent Path ....................................................................................................... 11-29

Multi-Cycle Paths ........................................................................................................ 11-30
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Multi-Cycle ATPG Flow ............................................................................................. 11-31

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Analyze Fault ............................................................................................................... 11-32

Analysis Report ............................................................................................................ 11-33
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GSV Debug of Delay Path Violations ......................................................................... 11-34

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Unit 12: Diagnosis

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Agenda ........................................................................................................................... 12-1

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Unit Objectives .............................................................................................................. 12-2

Purpose of Failure Diagnosis ......................................................................................... 12-3
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Yield Enhancement Process ........................................................................................... 12-4

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High Level View ............................................................................................................ 12-5

Volume Diagnostics Flow.............................................................................................. 12-6
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TetraMAX Diagnosis ..................................................................................................... 12-7

TetraMAX Diagnosis Features ...................................................................................... 12-8
TetraMAX Diagnosis Flow............................................................................................ 12-9
Requirements For Diagnosis ........................................................................................ 12-10
Diagnosis Commands .................................................................................................. 12-11
Synopsys 30-I-021-SSG-017 xii TetraMAX Workshop

Table of Contents
Diagnosis Flow Using Binary Image ........................................................................... 12-12

Advantages of Binary Image File ............................................................................... 12-13
Secure Image ................................................................................................................ 12-14
Secure Image Commands ............................................................................................ 12-15
Sample Scripts With Secure Image.............................................................................. 12-16
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Tester Failure Data File ............................................................................................... 12-17
Pattern-based Failure Data Format .............................................................................. 12-18
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Cycle-based Failure Data Format ................................................................................ 12-19
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Checking Expected Data in Failure Data File.............................................................. 12-20
Truncated Failure Data File ......................................................................................... 12-21
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TetraMAX Diagnosis Engines ..................................................................................... 12-22
Functional Logic Diagnosis ......................................................................................... 12-23
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Chain Diagnosis Overview .......................................................................................... 12-24
Chain Diagnosis Principle............................................................................................ 12-25
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Chain Diagnosis Output ............................................................................................... 12-26
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Sample Output: Diagnosis Summary ........................................................................... 12-27
Sample Output: Fault Candidate .................................................................................. 12-28
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What is the Match Score? ............................................................................................ 12-29
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Computing the Match Score ........................................................................................ 12-30
Terminology: Explaining Patterns ............................................................................... 12-31
GSV Output ................................................................................................................. 12-32
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N-Detect: Better Precision ........................................................................................... 12-33
N-Detect Flow Example .............................................................................................. 12-34
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Physical Data Improves Diagnostics ........................................................................... 12-35

High-Capacity Physical Database ................................................................................ 12-36
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PHDS Creation in TetraMAX ...................................................................................... 12-37

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PHDS Data Access Process (DAP) Server Setup in TetraMAX ................................. 12-38
TetraMAX PHDS Usage.............................................................................................. 12-39
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Sample Output: Physical Diagnosis Summary ............................................................ 12-40

Physical Diagnosis: Subnets ........................................................................................ 12-41
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Physical Diagnosis: Bridge Extraction ........................................................................ 12-42

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Unit 13: Conclusion

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Agenda ........................................................................................................................... 13-1

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After Units 1-4, You Can Now ...................................................................................... 13-2

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After Unit 5-8, You Can Now........................................................................................ 13-3

After Units 9-12, You Can Now .................................................................................... 13-4
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On Demand Training ..................................................................................................... 13-5

Documentation on SolvNet ............................................................................................ 13-6
Reference Methodology Scripts ..................................................................................... 13-7
SolvNet: TetraMAX Reference Methodology ............................................................... 13-8
Course Evaluation .......................................................................................................... 13-9
Synopsys 30-I-021-SSG-017 xiii TetraMAX Workshop

Table of Contents
Thank You! .................................................................................................................. 13-10

Appendix ...................................................................................................................... 13-11
How to Download Lab Files (1/2) ............................................................................... 13-12
How to Download Lab Files (2/2) ............................................................................... 13-13
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Synopsys 30-I-021-SSG-017 xiv TetraMAX Workshop

TetraMAX
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2017.09
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© 2018 Synopsys, Inc. All Rights Reserved Synopsys 30-I-021-SSG-017
Synopsys 30-I-021-SSG-016
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Introduction & Overview ©2018 Synopsys, Inc. All Rights Reserved. i-1
TetraMAX Workshop For Internal Microchip Training Purposes Only
Facilities
Building Hours Meals
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Emergency EXIT Smoking
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Restrooms Recycling
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Please turn off or silence your cell phone
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Workshop Overview
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 This workshop will cover the entire ATPG flow
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 Includes the following steps:
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 Generate test patterns given a scan gate-level design created by DFT
Compiler or other tools
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 Debug DRC and Stuck-At coverage problems using the GUI
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 Save and validate test patterns in simulation
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 Generate and validate At-Speed patterns using OCC
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 Diagnose failures on the ATE
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Target Audience
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DFT and Test engineers who perform ATPG
for ASIC or SoC designs
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SoC System On a Chip

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DFT Design for Test

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RTL Register Transfer Level, for example, VHDL and

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Verilog
ATPG Automatic Test Pattern Generation
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P&R Place and Route, also known as layout

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Workshop Prerequisite Knowledge
 Knowledge of Design For Test, scan insertion flows, and/or ATPG is

helpful but not necessary for this workshop
 Basic design concepts and terms are assumed:
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 Verilog or VHDL
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 UNIX environment for lab work
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Introductions
 Name
 Company
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 Job Responsibilities
Relevant Experience
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
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 Main Goal(s) and Expectations for this Course
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Agenda
DAY
1
i Introduction
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1 Introduction to Test and TetraMAX
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2 Building ATPG Models
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3 Running DRC
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4 Controlling ATPG
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Agenda
DAY
2
5 Minimizing ATPG Patterns
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6 Pattern Validation
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7 Fault Models and At-Speed Testing
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8 At-Speed Constraints
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Agenda
DAY
3
9 Transition Delay Testing
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10 On-Chip Clocking (OCC)
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11 Path Delay Testing
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12 Diagnosis
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13 Conclusion
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Icons Used in this Workshop
Caution.
Recommendation
Non-intuitive tool behavior
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Question Avoid
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Lab Exercise Group Exercise
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Agenda
DAY
1
i Introduction
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3 Running DRC
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4 Controlling ATPG
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Introduction to Test and TetraMAX ©2018 Synopsys, Inc. All Rights Reserved. 1-1
Unit Objectives
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After completing this unit, you should be able to:
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 Understand the D-algorithm fault model
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 Enter commands to obtain the TetraMAX Stuck-At coverage for a
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full-scan design
 Obtain TetraMAX reference material from the command help, on-
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line manual pages or the User Guide
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Manufacturing Test Programs
STIL 1.0;




Test



Program

Packaged 

IC Chips
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Pass
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ATE
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Fail
 Packaged IC chips tested on ATE
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 Pass/fail testing proposition
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 Looks for chips with physical defects
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 Chip is discarded if test fails
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 Passing chips go to end user 1- 3
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Today, automatic test-pattern generation (ATPG) tools generate most test programs; thus, the logic
designer can be increasingly involved in test-program development.
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ATE: Automated Test Equipment

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Stuck-At Fault Model
Fault Model:
A logical model representing the effects of a physical defect
U0/A Stuck-At 1 Fault (SA1):
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SA1
Due to a defect, input pin A
A
of U0 acts as if stuck high,
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U0 Y
B independent of input signal
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Defect at Input
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U1/Y
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Stuck-At 0 Fault (SA0): A SA0
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Due to defect, output pin Y U1 Y
of U1 acts as if stuck low, B
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independent of the inputs
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Defect at Output
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The stuck-at fault (SAF) model is still the most prevalent fault model in use today.
Defects land at random locations on a wafer in a semiconductor processing plant.
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It can therefore be assumed that stuck-at faults can occur anywhere in the logic on a chip.
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Any pin on a CMOS gate or flip-flop can be the site of a potential SA0 or SA1 fault.
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Chip complexity prevents us from considering stuck-at faults at the transistor level.
Other fault models exist, but a key advantage of the stuck-at model is its simplicity.
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It significantly reduces the complexity of CPU-intensive ATPG algorithms.

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Technical Reference:
Timoc, Buehler, et al., Logical Models of Physical Failures [Proc. ITC (Oct.1983)], p.546
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Rules for Detecting a Stuck-At Fault
Internal Probing
of IC Not Possible!
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Rules of the Game:
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Tester access to the device-under-test (DUT)
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is only allowed through its primary I/O ports
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Primary port means an I/O port that is directly accessible to external ATE hardware.
This corresponds to a package pin on a chip that has already gone through packaging; thus the ATE
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can:
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Individually drive—or control—the DUT’s primary inputs (PIs).

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Individually strobe—or observe—the DUT’s primary outputs (POs).

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Combinational Logic: Stuck-At Testing
A
Network N 1
SA0
B U1
Primary
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Inputs Z
C
Primary
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D
Output
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If this SA0 fault is not present,
Else SA0 fault is present,
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then node can be driven to 1.
and U1/Y remains at 0.
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This if / else behavior can be exploited to
detect the fault using the D algorithm
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Technical Reference (D algorithm):
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J. P. Roth, Diagnosis of Automata Failures,

IBM Journal Res. & Dev., Vol. 10, No. 4,
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p. 278, July 1966

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Activate the SA0 Fault (1/4)
A
U3
Network N 1
1/0
0 B U1
Input
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Stimulus
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U2
D
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Fault-Free
D Algorithm:
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Faulty Value
1. Target a specific stuck-at fault.
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2. Drive fault site to opposite value. 1/ 0 Legend
(continued)
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Presented now is the classic algorithm for detecting almost any stuck-at fault.
This automated procedure, from IBM in the Sixties, is known as the D algorithm.
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It detects a stuck-at fault anywhere in combinational logic—yet requires no internal probing.

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Since the original 1966 paper, many spin-offs of the D algorithm have been published.
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Its fundamental concepts are still essential to understanding most ATPG tools.
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The D algorithm detects one stuck-at fault at a time, making it very CPU-intensive.
The D algorithm creates a discrepancy between the fault-free and the faulty values.
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The composite logic value 1/0 is often symbolized by D.

The D (for Discrepancy) gives the algorithm its name.
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Propagate Fault Effect (2/4)
1 A Observable
0/1 Discrepancy
1/0 U3
0 B U1
1/0
U4
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0 C 0
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U2
0 D
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Enabling Input
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D Algorithm:
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The 1/0 is inverted,
1. Target a specific stuck-at fault. but the discrepancy is
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2. Drive fault site to opposite value. still easy to measure
3. Propagate error to primary output.
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(continued)
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The ATE then strobes this primary output port at a specific time in the test program.
If the ATE sees the expected fault-free response, then the fault is assumed not present.
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The ATE continues to execute the rest of the test program, targeting other faults.
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If it sees the faulty response, the SA0 fault is assumed present, and a failure is logged.
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Justification:
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Activating a fault site, and propagating the fault effect, often require justification.
To justify a node means to force a 0 or 1 onto that node, from the primary inputs.
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In N 1, the OR gate output was justified to 0 by applying 0s to the ports C and D.

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Anatomy of a Test Pattern (3/4)
Test Pattern
(U1/Y SA0)
Input
Stimulus Expected
Response
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Vector {ALL = 1000 1;}
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Test Pattern:
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A sequence of one or more vectors that applies a stimulus
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and checks for an expected response to detect a target fault.
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The pattern is shown in STIL syntax as a single vector statement, requiring one cycle.
The alias ALL represents an ordered list of DUT ports, including all the PIs and POs.
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This test pattern only has one vector; in general, many vectors will be required.
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In this workshop, the term test pattern is used just as it is defined in the STIL spec.
A test pattern is a series of one or more vectors comprising a test for a target Stuck-At fault.
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In this workshop, a vector will always correspond to exactly one tester clock cycle.
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Record the Test Pattern (4/4)
STIL 1.0;
•
•
This pattern detects Pattern "N1_Burst" {
Vector {}
the fault U1/Y SA0 Vector {}
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Vector {}
Vector {} Test
Vector {ALL=1000 1;} Program
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Vector {} for N 1
Vector {}
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Vector {}
Vector {}
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}
D Algorithm:
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1. Target a specific stuck-at fault.
Classic
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2. Drive fault site to opposite value. “D”
3. Propagate error to primary output. Algorithm
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4. Record pattern; drop detected fault.
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The fourth step in the D algorithm is just bookkeeping. The successful test pattern is recorded in
memory, and the detected fault is dropped from the list of target faults.
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The algorithm is repeated for all the remaining faults, resulting in a test program.
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A test program is a series of test patterns that detects all possible faults in the DUT.
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Testing Sequential Designs
Can the D algorithm handle flip-flops?
Pre-Scan
Target
Design
Fault
Embedded
1 Network N 1
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1/0
0
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0
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0
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 Still need to activate the fault and propagate its effect
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 Require the same ability to control and observe that was available in the
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purely combination circuit
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 Replace each flop with a testable flip-flop
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 This replacement allows serial loading/unloading of bits
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Scannable Equivalent Flip-Flop
D 0
Scannable SI D Q Q/SO Multiplexed
1
Equivalent Flip-Flop
for Ordinary SE
Scan Style
D Flip-Flop CLK
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CLK
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D D Q D Q D Q D Q D Q SO
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SI SI SI SI SI SI
SE SE SE SE SE SE
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 The scan equivalent has a serial path from pin SI to SO
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 This path is enabled only during testing, by asserting SE
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 Scannable equivalent FF’s will be connected SO->SI to form a shift
register also known as a scan chain
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When a normal flip-flop is replaced with a testable flip-flop that is called scan replacement.
The testable flip-flop has two modes:
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Normal mode—where the ASIC is operating as it was functionally designed to operate.

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Test mode—where the ASIC is undergoing manufacturing test.

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When the ASIC is undergoing manufacturing test the flip-flips will be connected together just like a
shift register—this configuration is called a scan-chain.
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The scan-chain will be used to serially shift in test patterns to parts of the design which are not
directly accessible to the primary input ports.
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The compile –scan command in Design Compiler causes the normal flops to be scan-replaced
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during the synthesis process.

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The vast majority of ASICs use a multiplexed flip-flop as the scan-replacement for normal flip-
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flops.
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The Full Scan Strategy
Serially preload registers Then capture the fault
with the stimulus, 1000 effect (1/0) into this register
PI1
SI
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PI2 PO1
0 1/0
1/0 PO2
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SO
PI3
PI4 0
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0
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SE
CLK
Serially unload fault effect at SO
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A serial path is stitched through all the scan flops, enabling
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the ATE to preload registers and capture responses!
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A Full Scan design is one in which all of the flip-flops in the design have been scan replaced and
will be included in the scan-chain.
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This slide shows the results of stitching a scan-chain (see the red path, starting at the SI port and
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ending at the SO port).

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Notice there are three additional ports now: SI (Scan In), SO (Scan Out), and SE (Scan Enable).
The DFT Compiler command to stitch the scan chains is: insert_dft.
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Scan Testing Protocol

PI1
SI
Targeted
1 SA0 fault


PI2 PO1
0 1/ 0


1/ 0 
PO2
SO
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PI3 
 0 
PI4
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0
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SE
CLK
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C a p tu r e
S c a n S h ift S c a n S h ift
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SE
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CLK
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SI   0 0 0 1  N e x t T e s t P a tte r n
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SO R e s u lts F ro m P re v io u s T e s t P a tte r n  1      
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The theta symbol (“”) represents a don’t-care (0 or 1) on an input or output port. The port can be a
either a 0 or a 1 on the ATE. In either case, the value will not affect the ability to detect the
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currently targeted fault(s).

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Test Patterns Overlap
Capture Capture
Scan Shift
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... ...
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Pattern (n -1)
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Pattern n
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 The scan load for a given pattern overlaps the scan unload of the
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previous pattern
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Note:
The load of the first pattern does not overlap with an unload since there is was no previous pattern.
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Likewise, the unload of the last pattern does not overlap a load operation.
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TetraMAX Overview
Common Graphical User Interface
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Unified ATPG Engines
Graphical
Basic-Scan Fault
Debugging
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Fast-Sequential Simulator
Environment
Full-Sequential
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Stuck-At / Transition
Slack-Based Transition / Path Delay
Parallel Bridging & IDDQ Fault
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Processing Diagnosis
Scan Compression
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Power-Aware / Cell-Aware
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Innovative Library Support
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TetraMAX Interfaces
Test
DFT Compiler Procedure STIL
File
Verilog
VHDL
Verilog
EDIF
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IC Compiler Netlist Library PrimeTime
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SDC,
LEF/DEF Layout Data Slack Data
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EVCD
Functional
Tcl Script TetraMAX Patterns
WGL
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STIL
PHDS
Bridging Pairs
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Yield Explorer STIL Star-RCXT
Reports
Reports Test Patterns WGL
Vendor Specific
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ATPG Flow in TetraMAX
BUILD
Mode
Verilog sim Read Library Prepare Save
Library Modules ATPG Patterns
TEST
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Mode
Gate-level Read Run
Test Patterns
Netlist Netlist ATPG
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Build Review
ATPG Model Coverage Verify
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Patterns
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DRC
Mode Incremental
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STIL Test Check
ATPG
Protocol DFT Rules
(if needed)
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The diagram shown above illustrates the basic test pattern generation flow. The three operation
modes of TetraMAX are shown by different colors. During build mode the design and libraries are
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read in, and the ATPG model of the design is built. If the build step was successful, TetraMAX will
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automatically enter into DRC (design rules checking) mode. If DRC was successful, TetraMAX
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will enter Test mode. In Test mode, ATPG settings are adjusted, TetraMAX can start pattern
generation, run incremental ATPG (if required) and save the patterns to disk.
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Launching TetraMAX
 To launch TetraMAX
unix% tmax [<command_file>]
The command file is optional - TetraMAX uses Tcl as its command
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
interface language
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 TetraMAX support two execution modes: “GUI mode” (default) and
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“shell mode”
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unix% tmax –shell [<command_file>]
In GUI mode, setup a TetraMAX log with the set_messages command
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
set_messages –log tmax.log –replace
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 In shell mode, use the UNIX tee command to create a log
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unix% tmax –shell [<command_file>] | tee tmax.log
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TetraMAX also has a legacy command interface mode termed as “native mode”. To launch TetraMAX in “native
mode”:
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unix% tmax –notcl [<command_file>]

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Note: Command and filename completion is supported in Tcl GUI mode only
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Note: when in Tcl mode, command options that take more than one argument must be provided with a Tcl list. A
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Tcl list can be denoted by the Tcl “list” command or by curly brackets “{ ... }”. For example:
set_build –black_box {PLL CLKMUL}
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Or ...
set_build –black_box [list PLL CLKMUL]
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Note: you can control the general level of message reporting in the TetraMAX logfile with set_messages -
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level <expert | standard>. The default is standard level. With the level set to expert, more information
is displayed for many commands.
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Example TetraMAX Script
# Save TetraMAX transcript to log file
set_messages –log lab1.log –replace
# Reading libraries and design

read_netlist ../libs/libs_tmax.v.gz
read_netlist ../libs/rams.v
read_netlist ../design_data/orca_final.v
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# Run Build
run_build_model
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# Perform Scan Design Rules Check
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run_drc ../design_data/orca_final.spf
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# Setup and run ATPG
add_faults -all
# Run ATPG engine(s)
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run_atpg -auto
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# Review Test Coverage
report_summaries
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analyze_faults -class au
report_patterns -summary
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# Save Test Patterns
write_patterns all_pats.stil -format stil -replace 1- 20
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Note: The set_messages command can be used to specify a logfile for the TetraMAX run.
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In the command file, command names can be shortened as long as they remain “unique”. For
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example, read_netlist could be shortened to read_ne. However, it’s recommended to stick

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with the full command names for the sake of readability.

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In TetraMAX, at the command prompt, TetraMAX supports command completion by starting a

command and then hitting the TAB key.
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Tcl API Commands
 Tcl API (Application Programming Interface) commands are used to

access the TetraMAX data structures in Tcl Mode
 Each command returns a collection (not a Tcl list!) of objects with
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specific class type
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 Classes available are
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 Clock, ScanChains, Cell, Pin, Port, Modules, Instances, Timings, Settings, Faults,
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Patterns, Candidates
 Example commands: get_cells, get_pins, get_scan_chains,
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get_faults
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 The Tcl API can be used to automatic common tasks and/or produce
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custom reports
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Limitation:
Tcl API commands are disabled when reading a secure image file. It is not possible for the secure
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image writer to enable these command as secure

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To get Tcl API Introduction

Fundamental Concepts  An Introduction to the TetraMAX Tcl API
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To get to a list of Tcl API commands and links

Commands by Group  Tcl API Commands
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Using Collections and Filters
 There are several commands to manage collections of objects

TEST-T> help -verbose *collection*
Some examples are:
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
 foreach_in_collection
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 sizeof_collection
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 copy_collection
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 Some commands have filtering options to manipulate the collection of
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objects returned based on “attributes” – Examples:
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TEST-T> set collection_cand [get_candidates -filter "pinpath=~*Z*"]
TEST-T> set collection_cell [get_cells -filter {chain_name == ch1} \
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–filter {scan_position == 4}]
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TEST-T> set collection_cell [get_cells {[A-U]12} –regexp]
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Tcl documentation on SolvNet:
https://solvnet.synopsys.com/dow_retrieve/B-2011.09/tclug/tclug.html
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(See section “Working With Collections”)

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Retrieving Attributes Values
 List of attributes available per object class can be printed using the
list_attributes command:
list_attributes –class <CLASS_NAME>
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 For instance, the attributes for the ScanChains object class are:
TEST-T> list_attributes –class scanchain
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Attribute Name Object Type Properties Constraints
---------------------------------------------------------------------
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chain_name ScanChains string U
clock_names ScanChains string U
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group_name ScanChains string U
input_pin ScanChains string U
length ScanChains int U
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object_class ScanChains string U
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output_pin ScanChains string U
 To access a particular attribute, use the get_attribute Tcl command
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Example use of get_attribute – to query the ScanDataIn for a particular scanchain
class object:
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get_attribute $chain input_pin

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Where $chain contains a scanchain object returned by a get_scan_chains command.

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Tcl API Example
 Defining a Tcl procedure that returns the longest scan chain length
Declare the procedure
Create collection
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of all ScanChains
proc report_scan_chain_max {} {
set max_length 0
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foreach_in_collection chain [get_scan_chains -all] {
if { [get_attribute $chain length] > $max_length } {
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set max_length [get_attribute $chain length]
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}
}
return $max_length
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}
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Access the “length” attribute
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Return the chain length
of each ScanChain object
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TetraMAX On-Line Help (OLH)
 Command-line help and man

help –v read_netlist
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man S22
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 GUI On-Line Help Menu
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HELP  Table Of Contents  Violations  S22
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 Standalone OLH (will not check out a license):
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UNIX: tmax –man &
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Browser: OLH is HTML based and can be run from most
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standard web browsers
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SolvNet Article ID: 024551 – How to Set Up Browser-Based TetraMAX Online Help in
Windows
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SolvNet Article ID: 027105 – TetraMAX Help in CHM Format

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If TetraMAX can’t locate your browser for launching the OLH, you can provide a path with an
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UNIX environment variable. For example, specify the following environment variable to use
Firefox as your default browser for running Online Help:
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unix> setenv USER_HELP_BROWSER /usr/bin/firefox

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Getting Help - SolvNet Resources
Browse
Docs
Manage
Support Reference
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Methodology
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Training
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Resources
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Search
Docs/Articles
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Open a Support
Center Case
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Unit Objectives Summary
You should now be able to:

 Understand the D-algorithm fault model
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 Enter commands to obtain the TetraMAX Stuck-At
coverage for a full-scan design
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 Obtain TetraMAX reference material from the
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command help, on-line manual pages or the User
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Guide
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Command Summary (Lecture, Lab)
%tmax Invokes the TetraMAX graphical user interface (Tcl mode)

%tmax –shell lab.tcl Invokes the TetraMAX command line interface (Tcl mode)
add_faults -all Create a faultlist with all faults
help -v Terse command help
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man Detailed on-line manual pages
read_netlist lab_1.v Reads in libraries and design netlists
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report_settings Reports current (ATPG, DRC, etc.) settings
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report_summaries Reports current fault statistics
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reset_state Resets all non-AU faults to ND
run_build_model Builds ATPG model of design
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run_drc lab_1.spf Performs test design rule checks
run_atpg Runs ATPG with current settings
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run_atpg -auto Automatic mode of ATPG
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set_atpg –merge {high high} Enables ATPG dynamic compaction
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Agenda
DAY
1
i Introduction
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3 Running DRC
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4 Controlling ATPG
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Building ATPG Models ©2018 Synopsys, Inc. All Rights Reserved. 2-1
Unit Objectives
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 Describe 2 methods for dealing with missing modules
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 Debug a library modeling issue and develop a simple
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workaround using TetraMAX modeling primitives
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BUILD Mode in TetraMAX
BUILD
Mode
TEST
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Mode
Gate-level Read Run
Test Patterns
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Build Review
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Patterns
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DRC
Mode Incremental
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STIL Test Check
ATPG
Protocol DFT Rules
(If needed)
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The diagram illustrates the basic test pattern generation flow.
During build mode the design and libraries are read in, and the ATPG model of the design is built. If
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the build step was successful, TetraMAX will then enter DRC (design rules checking) mode.
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Reading the Library Files
 Use NETLIST button or read_netlist command:

BUILD-T> read_netlist mylibrary.v
Example:
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BUILD-T> read_netlist /libs/0.18u/*/??DFF*.v
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 In case of module duplication when reading in netlists, the default
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behavior is to keep the last module definition encountered
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Netlist type (Verilog, EDIF, VHDL) is automatically detected.
Netlist compression (none, GZIP, proprietary binary) is automatically detected.
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A single file may have one or more modules

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A single read command may use wildcards to match multiple files using the ‘?’ and ‘*’ characters
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Cell Models Derived from Simulation Library
TetraMAX Library Support
Synthesis Implementation
Library
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ATPG
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Simulation
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Library
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Simulation
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 TetraMAX directly reads structural Verilog libraries
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 Eliminates the need for a special set of ATPG libraries
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Structural Verilog libraries are gate-level simulation libraries that use Verilog gate-level modeling
primitives (and, or) and UDPs (User Defined Primitives).
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TetraMAX does not read in RTL or behavioral simulation libraries, except for memory modeling
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which used a limited behavioral-like syntax.

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ATPG Model Derivation
 ATPG models are created directly from the structural/functional portion

of simulation models supplied in Verilog (including UDPs)
 Verilog language compiler directives understood:
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 `define
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 ìfdef
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 ìfndef
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 ìnclude
 `celldefine
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 `suppress_faults
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 ènable_portfaults, etc.
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 Behavioral models are not understood by TetraMAX and lead to
modules being treated as black boxes
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TetraMAX reads Verilog simulation libraries. UDPs are an integral part of the Verilog language.
They are essential for describing particular library cells. The TetraMAX library reader therefore
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supports UDPs.
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TetraMAX does not support behavioral models, except for memories. A very limited behavioral
syntax is used to model memories for TetraMAX.
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Expect Warnings if Library not “Validated”
DRC warnings reported

during read_netlist
ng
command
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Get details on DRC
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warning messages
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A “validated” library is one that is compatible with TetraMAX (i.e. contains only structural
primitives and/or UDPs).
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Duplicate Module Definitions
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 By default, if a module definition already exists and a second module with the
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same name is read, this will replace the first definition: An N5 violation
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(severity warning) will be issued
 This behavior is adjusted with the set_netlist command or dialog box to
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change the redefined_module selection
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set_netlist –redefined_module <last | first>
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 To prevent module redefinition of any kind, set the N5 rule to severity error:
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set_rules n5 error
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By default, when DRC violation’s severity is set to “error”, TetraMAX will abort execution of the
run script when the first error is encountered. This default behavior can be changed with the
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following command:
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set_commands [abort | noabort | exit]

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Read Design Netlist
 Use NETLIST GUI button or read_netlist command:

BUILD-T> read_netlist my_asic.v
 The same read_netlist command is used to read both libraries and
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design netlist files
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 Designs may be described using forms of:
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 Verilog structural netlists
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 EDIF structural netlists
 VHDL structural netlists
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 Mixtures of the above -- note: beware of naming convention restrictions of each
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language
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 Netlists may be either flat or hierarchical
Netlists may exist as a single file or multiple files
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
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Build the ATPG Design Model
read_netlist libs/*.v; read_netlist my_asic.v
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ATPG Primitive
Model of my_asic
my_asic
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run_build_model my_asic
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my_asic
_DFF
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nand2
top = my_asic _XOR
FD1
_NOR
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EO1
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NR2
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The build process is used to choose the top-level module and to build the in-memory design image
necessary for the ATPG algorithm. The build process can also be done at any intermediate level.
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Missing Modules Discovered During Build
Default severity of a B5
DRC violation is “Error”
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By default the build process will abort when the first B5 violation is encountered. If there are
multiple B5 violations, only the first B5 violation will be reported.
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How Many Modules Are Missing?
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Use report_modules to
find all undefined designs
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Read ATPG Memory Models, If Available
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Read any libraries that
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were missed the first time
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Define Black Boxes If No ATPG Model Exists
Black boxes are defined

for modules that cannot
be modeled for ATPG
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If Build is successful,
TetraMAX moves to
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DRC mode
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Empty Boxes Versus Black Boxes
Black Box Empty Box
X Z
X Z
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X Z
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set_build -reset_boxes; # Clears black & empty box list
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set_build –black_box RAM32x8
set_build -empty_box BUS_SWITCH
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# Use Tcl list for multiple black box modules:
set_build –black_box [list RAM32x8 RAM64X8]
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# Report all black box modules:
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report_modules –black_box
Even when a black-box is declared, it’s best to also read an “empty
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
shell” (i.e., just port declarations) model so that TetraMAX does not
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An “empty box” is similar to a black box with the exception that its output pins are not driven (i.e.
TIEZ). These can be used to model a module with tristate-able outputs.
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Specify an empty box module only if its outputs are actually at Z state during test. The empty box
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can be helpful if multiple modules are connected to a bus, but the module outputs are all at Z state.
Using black boxes in this case would result in bus contention.
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Two additional types of ‘box’ models are supported:

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To make TetraMAX treat a module as a library cell, use the –design_box option. TetraMAX
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will then add faults to just the ports of this module, but not inside
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To maintain the port connections of a level of hierarchy, use the –portfault_box option.
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Mode is DRC…Ignore those Build Violations?
Even though the build

step was successful,
violations reported may
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need further investigation
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Investigate Each N and B Warning
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Check the “What’s Next” section in the TetraMAX On-Line Help man page for a DRC violation, to
learn more about what to do if that violation is encountered.
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Did All of the Cells Translate Properly?
 To quickly answer this question, use the report_modules –summary

command
 Look for unsupported behavioral and errors
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These indicate that an ATPG model may not be correct
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DRC-T> report_modules –summary
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Modules: #UNKNOWN_FORMAT=2 #STRUCT_VERILOG=654
(#unsupported_beh=97) #BEH_VERILOG=3 #COMB_UDP=42 #SEQ_UDP=334
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DRC-T> report_modules –errors
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Although TetraMAX attempts to translate vendor cell descriptions into ATPG gate equivalent
models, this automatic translation is not always successful. For example, it is quite common to
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experience “N” rule violations when reading libraries.

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In general, this topic is important for library developers, as they have to deliver certified libraries.
TetraMAX users should always look for library problems to make sure TetraMAX does not
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generate wrong patterns due to library issues. It is beneficial for TetraMAX users to have at least a
basic idea of how to debug library issues, just in case.
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The important question is: Did all of the cells translate properly? Use the -summary option of the
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report_modules command and look for any X detectors or Errors indicated, either of which
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will indicate an ATPG model that may not be suitable for use.
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To review specific modules on which errors were encountered use the -error option of
report_modules. Once a module which had an error or other problem such as N13 or N24 is
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identified, the connectivity information of the module can be reported as one way to reveal how the
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module was translated.

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The Verilog parser attempts to classify each module read as structural (STRUCT_VERILOG) or
behavioral (BEH_VERILOG). If it can’t tell, the module is classified as UNKNOWN_FORMAT.
Graphical Schematic Viewer (GSV)
Open/Close GSV
Toolbar
Buttons
Cell
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Name
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Primitive ID
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Net Fanout
Gate Info (RMB->”Display Gate Info”)
Point
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Items displayed in the GSV can be controlled via the command line as well. See the man pages of
the following commands for more information:
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add_display_gates
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remove_display_gates
report_display_gates
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Information about a particular primitive can be reported by the report_primitives command.

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Design View vs. Primitive View In GSV
Scan Flip-Flop in Design View (vendor cell fdmf1a3)
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Scan Flip-Flop in Primitive View (TetraMAX DFF and MUX)
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When determining the “design” level, by default, TetraMAX will look for `celldefine compile
directives when the library was read into TetraMAX.
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If `celldefine statements are not in the library, TetraMAX will set the design level at any module
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that only contains Verilog primitive or UDPs. Or if read_netlist –library is used, then
any module defined in that netlist will be considered a design level cell (i.e. a library cell).
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The “design” level can also be referred to as the “standard cell” level or the “leaf cell” level.
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The symbol for a gate primitive and primitive ID can sometimes be seen even in the “design view”.
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This is normally the case for simple gates such as buffers or inverters.
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Prefer to Debug ATPG Models Graphically?
The run_build_model
command can be run at any
level, not just the top-level
run_build_model PROBLEM_CELL
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Open GSV, SETUP = Primitive
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Show All
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Review Model Accuracy
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Perhaps the easiest technique for reviewing the derived ATPG model is to look at the model
graphically.
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Do this by:
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• Performing run_build_model on the specific module by name

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• Opening the GSV viewer and selecting SETUP = primitive

• Clicking on the SHOW button in the GSV toolbar, and from the pop-up menu, select ALL
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The resulting graphical schematic will present the ATPG model in terms of the tool’s ATPG
primitives.
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Review the functionality defined by the schematic to help determine if the translation was accurate.
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Investigating Models Graphically
 P_LATCH model had an N14 reported during read

 In the GSV it is easy to see the problems with
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this model:
 D and SB inputs are floating
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 DATA and SET pins are tied to 1
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 To see all N14 rule violations:
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report_violations n14
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N14 – “Illegal UDP” : The UDP contains an entry that is not allowed.
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What If ATPG Models Cannot Be Derived?
 Direct access to ATPG modeling primitives is available for “difficult”

models such as cells with only a behavioral model available
 Model functionality is described by connecting ATPG primitives via a
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structural netlist
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 Use the TETRAMAX define as a compiler directive in an Verilog
simulation library cell, e.g.:
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ìfdef TETRAMAX
<TetraMAX model>
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èlse
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<behavioral model>
èndif
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ATPG Modeling Primitives: Partial List
AND ( in1, ..., inN, out );
BUF ( in, out );  A sampling of ATPG modeling
BUS ( in1, ..., inN, out );
BUSK01 inout ; // bus keeper
primitives
 Most primitives take a variable
DFF ( set,rst, clk1,d1, [clkN,dN,]... , out );
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DLAT ( set,rst, clk1,d1, [clkN,dN,]... , out );
INV ( in, out ); number of inputs but always have a
single output
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MUX ( sel, d0, d1, out );
NAND ( in1, ..., inN, out );
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NOR ( in1, ..., inN, out );
 For a complete list, see the on-line
OR ( in1, ..., inN, out );
help topic of “ATPG modeling”
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SW ( control, in, out ); // switch
TIE0 ( [in1, ..., inN,] out );
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TIE1 ( [in1, ..., inN,] out );
TIEX ( [in1, ..., inN,] out );
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TIEZ ( [in1, ..., inN,] out );
TSD ( ena, in, out );
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WIRE ( in1, ..., inN, out );
XNOR ( in1, ..., inN, out );
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XOR ( in1, ..., inN, out );
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It may be necessary to create custom ATPG models.
This may be done by instantiating ATPG modeling primitives in a Verilog, EDIF, or VHDL netlist.
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ATPG Modeling Primitives: Examples
module SCAN_FLOP (SE, D, SDI, CLK, SET, RSTB, Q, QN, SDO);
input SE,D,SDI,CLK,SET,RSTB;
output Q,QN,SDO;
_MUX u1 (SE,D,SDI, din);  Verilog netlists referencing ATPG
_DFF u2 (SET, !RSTB, CLK, din, Q);
_BUF u3 (Q, SDO);
modeling primitives to define ATPG
models
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_INV u4 (Q, QN);
endmodule
module buskeep (X);  When used in Verilog, ATPG primitives
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inout X;
_BUSK01 X;
must have an underscore (“_”) prefix
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endmodule
module dual_latch (RB, G1,D1, G2,D2, QN);
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input RB, G1, D1, G2, D2;
output QN;
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_DLAT reg (1’b0,!RB,G1,D1,G2,D2, q);
_INV u2 (q, QN);
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endmodule
module grey_box (in1, in2, in3, out1, out2);
input in1, in2, in3;
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output out1, out2;
_TIEX u1 (in1, in2, in3, out1);
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_TIE0 u2 (out2);
2- 25
endmodule
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When used in a Verilog netlist, the primitive names must have an underscore prefix, as in “_AND”
When used in an EDIF netlist, the primitive names must have a “&_” prefix, as in “&_AND”.
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When used in a VHDL netlist, no prefix is needed. Be aware, that a component named “AND” will
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have precedence over a primitive named “AND”.

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Read in the custom ATPG primitives after the original library has been read.
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Use:
set_netlist –redefined_module last
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read_netlist mylib.v
read_netlist myprimitives.v
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Testability of Embedded Memory
More Silicon
SoC with for Memory
Embedded
Memory
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Deeply
uP Core
Embedded
Limited
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RAM Memory
Direct
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Access Cache
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Logic ROM
Very Dense
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Transistor
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Implementation
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Embedded (on-chip) memory blocks pose SOC test challenges!
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The growing use of embedded, distributed memory blocks on ICs creates testability issues:
Limited Direct Access:
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Testers can’t control or observe embedded memory blocks directly from the package pins.
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Deeply embedded memory (e.g., L1 cache inside a microprocessor core) is even harder to access
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for test.
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More Silicon for Memory:

Embedded memory has begun to take up more silicon area than the application logic.
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The probability of a physical defect landing on or near a memory array is thus higher.
An effective DFT strategy for memory blocks and the surrounding logic is thus crucial.
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Dense Transistor Implementation:

Vendor SRAM, DRAM, E2PROM and ROM blocks are implemented at the transistor level.
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Market forces drive vendors to fabricate memory arrays at the highest density possible.
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Gate-level single stuck-at fault models and related algorithms are inadequate at this density.
Memory testing must target multiple stuck-at and bridging faults at the transistor level.
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Memory DFT Strategies
 Testing RAM/ROM for internal faults

 The transistor-level fabric of a RAM/ROM can’t be tested by gate-level stuck-at fault
techniques
 Memory BIST (such as STAR Memory System - SMS) is typically used to test internal
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memory faults
 Shadow logic is combinational logic around a RAM/ROM cell
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 Testing RAM/ROM shadow logic in ATPG
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1. Applying a black box model:
If there’s no ATPG model for a RAM/ROM cell, it’s often modeled as a black box.
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2. Using a bypass mode for Basic-Scan ATPG:
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If the memory supports a bypass mode, it can be used to obtain some coverage on the shadow logic.
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3. Writing functional models for Sequential ATPG:
Testability of shadow logic can be maximized by replacing the black box RAM/ROM cell with a user
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supplied functional Verilog model. 2- 27
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Black Box or Bypass Mode
untestable via Basic-Scan ATPG
 Non-scan sequential cells, including testable via Basic-Scan ATPG
memories, can cause DFT blockages

A RAM
and test coverage issues especially if DO
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DI
the cell is modeled as a black box empty
shell
CS
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 Bypass Mode: OE
WE
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 Bypass the RAM so that some logic around
RAM can be tested with Basic-Scan ATPG
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TM
 Memory IP may support a bypass mode(s).
RAM
If not, a manual RTL fix needed to
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A DO
DI
implement the bypass mode
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empty
 Memory bypass modes may be CS shell
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OE
combinational (shown) or WE
sequential/synchronous
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TetraMAX Memory Model
 Using a TetraMAX model untestable via Fast-Sequential ATPG

 Enables Fast-Sequential ATPG to test
testable via Fast-Sequential ATPG
“through” the memory
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 Bring write control signal to top-level A RAM DO
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ports to: DI TMAX
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 Control writes during sequential cycles CS
Model
of RAM
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 Need to control the clock for synchronous OE
WE
memory or WE for a level-sensitive memory
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 Protect memory contents during scan shift mem_clk
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The example above is an asynchronous memory, therefore, the write control signal is a
WriteEnable (WE). For synchronous memories, the write control signal would be a WriteClock.
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In both cases, the write control signal will be defined as a “clock” at the top-level
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The write enable/clock doesn’t need to be controlled with a dedicated signal at the top-level. The
memory control/clock can be shared with a functional/scan clock.
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Clock Stable and Load Stable
 A memory is “clock stable” if its contents are stable when all clocks are
in their “off state”
 A memory must be clock stable to be usable by ATPG1
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 A memory is “load stable” if its contents are stable during scan shift
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 Often achieved by gating the WriteEnable or ChipSelect signal of the memory
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with ScanEnable
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 Allows ATPG to be more effective by using multiple loads to test faults around the
memory
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 Also has the benefit of reducing power during scan shift
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 To report the attributes of the memories:
report_memory –all -verbose
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TEST-T> report memory -all -verbose
#ports width address stable off
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type ID wrt/rd addr/data min/max clk/load val instance_type

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---- --- ------ --------- -------- -------- --- ---------

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RAM 146 1 1 10 8 0 1023 yes yes X ram1024x8

RAM 149 1 1 9 8 0 499 yes yes X ram512x8
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RAM 150 1 1 6 8 0 63 yes yes X ram64x8

ROM 147 0 1 4 16 0 15 yes yes X rom16x16
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ROM 148 0 1 5 16 2 31 yes yes X rom32x16

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1Clock stable is a requirement for the memory to be usable by Fast-Sequential ATPG. Full-
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sequential ATPG can also support clock unstable memories.

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RAM/ROM Modeling
 RAMs/ROMs are modeled using a limited Verilog behavioral description

 Memory modeling features supported include:
Multiple read or write ports
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
 Common or separate address bus
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 Common or separate data bus
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 Edge or level sensitive read/write controls
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 One qualifier on the write control
 Read off state can hold or return data to 0/1/X/Z
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 Asynchronous set and/or reset capability
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 Memory initialization files
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 A ROM is created by defining a RAM without a write port and is required
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to have an initialization file
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RAM Modeling: Basic Example
module MY_ATPG_RAM ( read, write, data_in,

data_out, read_addr, write_addr );  A basic example for a RAM
input read, write;
input [7:0] data_in; // 8 bit data width using limited syntax
input [3:0] read_addr; // 16 words
input [3:0] write_addr; // 16 words behavioral Verilog
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output [7:0] data_out; // 8 bit data width
reg [7:0] data_out; // output holding reg
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reg [7:0] memory [0:15]; // memory storage  The RAM in this example has
event WRITE_OP; // event for write-thru
level sensitive write and read
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// Write port
ports
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always @ (write or write_addr or data_in)
if (write) begin
memory[write_addr] = data_in;
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#0; ->WRITE_OP;
end
// Read port
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always @ (read or read_addr or WRITE_OP)
if (read) data_out = memory[read_addr];
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endmodule
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The port list may vary as more complicated RAMS or ROMS with multiple ports are defined, but
the template is essentially the same.
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Note that the ATPG modeling of RAMs requires that bussed ports be used.
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ROM Model: Basic Example
ROM_8x4.v:
ROM_8x4 module ROM_8x4(ADDR,SINE); Initialization File

input [2:0] ADDR; (Required for ROMs)
output [3:0] SINE;
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reg [3:0] SINE; ROM_8x4.dat:
ROM reg [3:0] ROM [0:7];
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//Sine Decimal
Submodule initial 0000 // 0.000
$readmemb("ROM_8x4.dat",
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0011 // 0.195
ROM ); 0110 // 0.383
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1001 // 0.555
always @( ADDR )
1011 // 0.707
if (ADDR <=7)
1110 // 0.831
SINE = ROM[ ADDR ]; 1111 // 0.924
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endmodule 1111 // 0.981
ch
File opened for reading by
Functional Verilog
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$readmemb system task
Per TetraMAX Template
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TetraMAX understands a wide variety of RAM/ROM modeling features.
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Modeling Limitations:
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TetraMAX accepts a limited Verilog behavioral syntax for modeling RAM or ROM blocks.
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The Verilog code shown above is based on a template copied from TetraMAX on-line help.
For example, the if statement is part of the required template code, and cannot be left out.
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Many types of memories are supported, including RAMs with multiple read/write ports, and
asynchronous set/reset inputs; common or separate address/data buses, with edge- or level-
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sensitive read/write enables; and memory “read-off” states, with Z outputs.

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For More Information:

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Access TetraMAX Help, under index entries RAM Modeling and ROM Modeling.
For examples of RAM/ROM data initialization, see Memory Initialization Files.
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See Appendix for more examples of Memory models in TetraMAX.

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Utility to Generate TetraMAX Memory Models
A Tcl based utility called

# Source the memgen.tcl script “memgen” can be used
source memgen.tcl to generate TetraMAX
memory models
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# Declare the Memory signals
set_memgen_signal -port a[9:0] -type MemoryAddress
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set_memgen_signal -port wclk -type WriteClock
set_memgen_signal -port rclk -type ReadClock
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set_memgen_signal -port din[7:0] -type WriteData
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set_memgen_signal -port dout[7:0] -type ReadData
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# Generate the memory model
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memgen -output mem.v
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SolvNet Article: TCL Script for Generating TetraMAX Memory Models
https://solvnet.synopsys.com/retrieve/018490.html
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Want to Quickly Return to DRC Mode?
 First session:
BUILD-T> read_netlist . . .
BUILD-T> run_build_model
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DRC-T> write_image pass1.image.gz \
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–compress gzip -replace
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 A later session:
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BUILD-T> read_image pass1.image.gz
DRC-T> # Ready to resume in DRC mode
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 Describe 2 methods for dealing with missing
modules
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 Debug a library modeling issue and develop a
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simple workaround using TetraMAX modeling
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primitives
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Begin Lab 2: Handling Designs & Libraries
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add_net_connections Alter the behavior of nets or other design aspects
set_scan_ability on non_scan_ff Treats a non-scan flop as a scan flip-flop
build –force Returns to BUILD mode
report_feedback_paths –all Reports all combinational feedback paths
report_modules -errors Detailed on-line manual pages
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report_modules -summary Reports summary statistics for modules
report_modules -undefined Reports all modules which are not defined
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report_violations n14 -all Reports all n14 violations
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set_atpg -merge Enables dynamic ATPG pattern compression
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set_build -black_box Specifies a module to be a black box
set_build -empty_box Specifies a module to be an empty box
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set_build -nodelete_unused_gates Keeps unused gates in the ATPG model
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set_build -reset_boxes Removes all black, empty, etc. box definitions
set_faults -fault_coverage Report fault coverage in addition to test coverage
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set_rules n5 error Raises severity of n5 violation to Error
write_netlist libs_tmax.v.gz Save all library modules in one file
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write_patterns Save ATPG patterns to disk
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This page was intentionally left blank.
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Agenda
DAY
1
i Introduction
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3 Running DRC
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4 Controlling ATPG
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Running DRC ©2018 Synopsys, Inc. All Rights Reserved. 3-1

Unit Objectives
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 List 3 methods of creating an SPF file
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 Describe 2 ways of defining timing in TetraMAX
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 Name 2 types of procedures used by ATPG
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 Name the 5 high level fault classes
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BUILD
Mode
TEST
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Mode
Gate-level Read Run
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Verify
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Patterns
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Build Review
ATPG Model Coverage
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DRC
Mode Incremental
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STIL Test Check
ATPG
Protocol DFT Rules
(if needed)
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3- 3
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In DRC mode, all information needed by the TetraMAX to configure the design for test is
specified. The STIL test protocol file (STIL = Standard Test Interface Language) is read in. If DRC
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was successful, TetraMAX enters TEST mode.

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Controlling ATPG: Agenda
DRC Setup
ng
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Debugging DRC Violations
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Managing Faults
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How Does TetraMAX Perform Design Rule Checks (DRC)?
 TetraMAX learns information about the design

read_netlist, run_build_model
TetraMAX will automatically perform the N and B rule checks
Questions that need to be answered for TetraMAX:
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
 What are the Scan Chain Pins?
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 How is scan mode enabled for the design?
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 What is the initialization sequence for the design?
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 What are the clocks?
 Which clocks are used for shift and capture?
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 What is the timing for all the device pins?
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 And more questions
 These answers are provided via a STIL Protocol File or by using
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TetraMAX Quick STIL commands
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The term “Quick STIL” refers to TetraMAX commands that define aspects of the Test protocol. If
TetraMAX commands are not used to define the Test protocol, then the Test protocol is defined by
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passing a STIL protocol File (SPF) to TetraMAX.

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Partial STIL Protocol File
STIL;
ScanStructures {
ScanChain "chain1" { ScanIn “SDI[1]”; ScanOut SDO[1]; }
ScanChain "chain2" { ScanIn “SDI[2]”; ScanOut SDO[2]; }
}
Procedures {
ng
“multiclock_capture" { W "_default_WFT_";
F { TEST_MODE = 1; }
V { "_pi"=\r 12 #; #: Placeholder for values
"_po"=\r 8 #; }
supplied later during ATPG
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}
"load_unload" {
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// clocks & resets off; enable scan
V { CLOCK = 0; RSTB = 1; SCAN_EN = 1; TEST_MODE = 1; }
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Shift {
V { _si=##; _so=##; CLOCK=P;} // pulse shift clock
}
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}
}
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MacroDefs {
"test_setup" {
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V {TEST_MODE = 1; CLOCK = 0; RSTB = 1;}
}
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} V: Vector Statement – one
ATE clock cycle 3- 6
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The simplest STIL Protocol File consists of the STIL header, a ScanStructures block, and a
Procedures block containing the load_unload procedure and Shift statement.
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The load_unload procedure defines test cycles to apply, which will enable the scan chain shift
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path. It also defines the ‘Shift’ statement and where within the load_unload it is applied.
The load_unload procedure should: place all clocks at their off states, enable scan chain
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shifting, and disable bidirectional port drivers (if possible).

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There is usually one top-level port such as “SCAN_EN” which will enable the shifting of scan
chains. The port should be set appropriately inside the load_unload procedure.
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The Shift statement defines how to shift the scan chains by one bit position. In the Shift statement,
the ‘#’ is a special placeholder which takes on a value from the scan input or scan output data
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vector. The example above is from a design with two scan chains so two #’s are used.
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The test_setup macro is optional but may be needed to initialize a particular design for test
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mode.
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Different Ways to Create a STIL Protocol File
 In order of increasing effort to create:

 Have DFT Compiler create the SPF
 Use Quick STIL commands or the TetraMAX GUI
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 Create the SPF manually
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 If an SPF is available, to run DRC:
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run_drc <spf_file>
Or ...
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set_drc <spf_file>
run_drc
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 If using Quick STIL commands only, to run DRC:
ch
run_drc
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If commands are used to define the Test protocol file but a test_setup initialization sequence is
required to enter scan mode, the test_setup sequence can be included in an SPF file and
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“appended” to the existing protocol with the following command:

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run_drc design.spf –append

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Where design.spf contains a MacroDefs (with test_setup) and/or Procedures section.

All other sections of the provided SPF will be ignored.
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Check the man page of the run_drc command for details on how TetraMAX handles potential
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conflicts when protocol information is provided with both TetraMAX command and an SPF.
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SolvNet Article: 900846 – TetraMAX and STIL

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Writing Out the STIL Protocol File
 In DRC or TEST modes, the SPF file can be written with the command:
write_drc_file <file> [-replace]
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 Protocol information provided via Quick STIL commands will be reflected
in protocol file written out with the write_drc_file command
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 Quick STIL commands that will increase the protocol information include:
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add_clocks
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add_pi_constraints
add_pi_equivalences
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add_scan_chains
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add_scan_enables
run_drc
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Remember, the preferred method is to have DFT Compiler to automatically create the STIL
protocol file.
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The default timing produced will be written to be compatible with single-cycle capture.
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Using Quick STIL Commands
add_pi_constraints
add_clocks add_scan_chains add_scan_enables
add_pi_equivalences
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write_drc_file
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Manual SPF Editing
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Other Adjust
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load_unload Shift test_setup
Procedures Timing
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run_drc
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Passing DRC
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The easiest way to generate the STIL protocol file (SPF) from scratch is to specify as much
information as possible, while in DRC mode. Then write out an initial SPF for further editing.
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The SPF contains:

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•Names of scan inputs and outputs

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•Which pins act as “clocks”

•Timing definitions for pins, clocks, and measures
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•Constrained ports and equivalence relationships

•Test setup sequence, the test_setup macro
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•Scan enable sequence, the load_unload procedure

•Scan shift sequence, the Shift procedure
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•Other design dependent procedures: master_observe, shadow_observe

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The more SPF related information that is known at the time of the write_drc_file command
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then the more information that can be written into the SPF template.
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Defining PI Constraints
 To hold a port constant during the entire test program, define a PI

(primary input) constraint:
add_pi_constraints 1 ASIC_TEST
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 To review the existing list of PI constraints use:
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report_pi_constraints
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 To review a list of input, output, inout, or all ports use:
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report_primitives [ -pis | -pos | -pios | -ports]
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Constraints can also be defined in the SPF file.
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Note: If a PI constraint is used along with an SPF, then the PI constraint is only applied to the
nt
capture procedures. Values in other procedures like load_unload are controlled by the states
rI
provided in the SPF.

Fo
Constraints of Z can only be defined for bidirectional or tri-stateable outputs.

se
If DRC checks are going to be run using an SPF file and an add_pi_constraints command is
used, the constraint is applied to the capture procedures only.
U
ed
If DRC checks are going to be run only using Quick STIL commands and an
add_pi_constraints command is run, the constraint is applied to the capture procedures and
ct
the load_unload (Shift) procedure.

tri
es
R

Defining PI Equivalences
 PI equivalences on ports:
add_pi_equivalences [list P1 P2 P3]
ng
add_pi_equivalences ENA_P -invert ENA_N
ni
Defining differential Clocks:
ai

add_clocks 0 CLKP –shift
Tr
add_clocks 1 CLKN -shift
ip
add_pi_equivalences CLKP –differential CLKN
ch
 To review the existing list of PI equivalences use:
ro
report_pi_equivalences
ic
3- 11
lM
na
This command is commonly used to define the relationship of differential inputs.
TetraMAX supports differential inputs for clocks and data ports.
er
However, special consideration is required for differential scan chain inputs.

nt
See TetraMAX Online Help for details.

rI
Fo
se
U
ed
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tri
es
R

SPF: PI Constraints and PI Equivalences
STIL;
“W” Statement
ScanStructures { Selects The
ScanChain "c1" { ScanIn SDI2; ScanOut SDO2; } WaveFormTable
ScanChain "c2" { ScanIn SDI1; ScanOut D1; }
} (WFT) Timing
“E” Statement For Procedures {
"load_unload" {
Pin Equivalences W "_default_WFT_";
ng
V { RESETB = 1; SCAN_ENABLE = 1; ASIC_TEST = 1;
CLKP = 0; CLKN = 1; }
Shift { W "_default_WFT_";
ni
V { _si=##; _so=##;
CLKP=P; CLKN=P; } }
“F” Statement For }
ai
“multiclock_capture" { W "_multiclock_capture_WFT_";
PI Constraints E CLKP \m CLKN; // \m reference WFCMap
E P1 P2 P3;
Tr
E ENA_P \m ENA_N; \m references a WFCMap
F {ASIC_TEST=1;} statement in the Signals section:
V { "_pi"=\r 12 #;
"_po"=\r 8 #; } “ENA_N" In { WFCMap { 0->1; 1->0; } }
ip
“\r <n>” Repeat the next }
}
character “n” times
ch
MacroDefs { “#” Placeholder for
test_setup { W "_default_WFT_";
V { ASIC_TEST=1; CLKP=0; CLKN=1; RESET=0; } } value provided by ATPG
}
ro
ic
3- 12
lM
na
PI Equivalences can be defined in the SPF file by use of the “Equivalent” statement or “E” for
short.
er
nt
To define a PI equivalence, every capture procedure, i.e. multiclock_capture, as well as

rI
the load_unload procedure must contain identical E statements in order to imply a PI

equivalence condition.
Fo
A PI constraint translates into a fixed port value during the application of the capture procedures of
se
the STIL protocol file.

U
A PI constraint is also placed on the defined pin during procedures such as the test_setup,
ed
load_unload, and Shift unless explicitly overridden using an assignment statement in the
procedure.
ct
tri
When long strings of assigned values are specified, the repeat syntax can shorten the strings:
\r<count> string_to_repeat<space>
es
R

Defining Clocks
 Defining clocks may be done manually using:

add_clocks <off_state> <port_name> -shift \
-timing <[list period leading trailing strobe]>
ng
Examples:
add_clocks 0 [list clk1 clk2] \
ni
–timing [list 100 45 55 40] –shift
ai
Tr
add_clocks 1 RSTB \
–timing [list 100 45 55 40]
ip
 The –shift option causes the clock to be pulsed in the load_unload
procedure during scan shift
ch
ro
ic
3- 13
lM
na
To check on the list of defined clocks defined either manually or by a STIL protocol file referenced
by a run_drc command use report_clocks.
er
nt
add_clocks . . . -timing {<period> <t1> <t2> <measure_time>}

rI
This option is used to define the test cycle period associated with the clock:
Fo
• t1 is the time of the leading edge of the clock, while

• t2 is the time of the trailing edge of the clock
se
The measure time specifies the time within the test cycle at which the design's output pins will be
U
measured.
ed
If measure_time < t1, then a pre-clock measure protocol is implied.

If measure_time > t2, then an end-of-cycle measure protocol is implied.
ct
tri
The default for timing is: period 100, t1=50, t2=70, measure_time=40.
es
R

Defining Asynchronous Set/Reset
 TetraMAX requires that all ports which affect the stored state of
sequential devices and require a pulsing action within the tester cycle,
be defined as “clocks”
ng
 TetraMAX clocks include:
ni
 Traditional clocks
ai
 Asynchronous set and reset controls of flip-flops and latches
Reset Line gated
Tr
 Read/write controls of RAMS with a ScanEnable
signal (TEST_SE)
ASIC_TEST
TEST_SE
Exception: resets that are used as both
D Q D Q
 F2 F3
...
ip
SE SE
synchronous and asynchronous should Reset
ch
Synchronizer
not be defined as clocks D Q D Q

SE
F0
SE
F1 Internal Reset Line
ro
 Use the following drc option: Inactive During Shift
ic
RSTn
set_drc –allow_unstable_set_reset
3- 14
lM
na
From the TetraMAX OLH for the set_drc command:
er
-allow_unstable_set_resets | -noallow_unstable_set_resets
nt
rI
Specifies whether DFF/DLAT devices with unstable sets or resets are considered DRC violations.
An unstable set/reset condition exists when the control net is internally generated. The default is to
Fo
consider an unstable set/reset a DRC violation. Using the -allow_unstable_set_resets

option allows the presence of internally generated set/resets and allows Fast-Sequential ATPG to
se
use these set/reset-unstable nonscan cells to further improve test coverage. This is especially useful
in at least two situations:
U
ed
1) when a primary input is used as both a synchronous and asynchronous set or reset, and
2) when the scan-enable line is used to gate internal set/reset lines during scan load.
ct
tri
In either case, for better test coverage, the scan-enable input and the primary input acting as both
asynchronous and synchronous reset should not be defined as clocks.
es
R

SPF: Capture Procedures
 Generic capture procedure
"multiclock_capture" { W “_multiclock_capture_WFT_";
F { “TEST_MODE"=1; }
V { "_pi"= \r169 #; "_po"= \r164 #; }}
ng
 Capture procedures for Delay fault patterns that use external clocks
with system_clock launch
ni
"allclock_launch" { W “_allclock__launch_WFT_";
ai
Tr
V { "_pi"= \r169 #; "_po"= \r164 #; }}
"allclock_capture" { W “_allclock_capture_WFT_";
F { “TEST_MODE”=1; }
ip
V { "_pi"= \r169 #; "_po"= \r164 #; }}
ch
"allclock_launch_capture" { W “_allclock_launch_capture_WFT_";
ro
V { "_pi"= \r169 #; "_po"= \r164 #; }}
ic
 The _pi signal group controls the clocks that pulse in each pattern 3- 15
lM
na
For a given capture procedure, the order of events is determined by the Waveform Table Timing
(WFT) referenced by the capture procedure.
er
nt
The “\r” syntax in the SPF means to repeat the next state character <n> times. I.e., “\r169 #”
rI
means to repeat the # state character 169 times. The # character is a placeholder for state values that
will be later provided by ATPG.
Fo
se
U
ed
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tri
es
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SPF: Defining Scan Chains & Scan Enable
 Quick STIL Syntax:

add_scan_chains chain1 SDI1 SDO1 add_scan_chains
reflected in
ng
add_scan_chains chain2 SDI2 SDO2 ScanStructures
add_scan_enables 1 SCAN_EN
ni
add_scan_enables Z BIDI
ai
ScanStructures {
Tr
ScanChain "chain1" { ScanIn SDI1; ScanOut SDO1; }
ScanChain ”chain2" { ScanIn SDI2; ScanOut SDO2; }
}
ip
Procedures { add_scan_enables
"load_unload" { reflected in
ch
V { CLOCK = 0; BIDI = Z; SCAN_EN = 1; } load_unload
Shift {
ro
V { _si=##; _so=##; CLOCK=P;} // pulse shift clock
}
ic
}
}
3- 16
lM
na
STIL keywords must be exactly entered as shown. Keywords on this slide include
ScanStructures, ScanChain, ScanIn and ScanOut.
er
nt
STIL keywords can easily be identified because they are not surrounded by double-quotes and they
rI
have mixed upper- and lower-case letters. For example: STIL will not recognize SCANIN, scanin,
or scanIN as the keyword ScanIn
Fo
The Shift statement defines how to shift the scan chains by one bit position. The ‘#’ is a special
se
placeholder which takes on a value from the scan input or scan output data vector during ATPG.
U
TetraMAX has some predefined signal groups such as “_si” for scan inputs and “_so” for scan
ed
outputs as a shorthand way to reference all scan input and output ports.
ct
When long strings of assigned values are specified, the repeat syntax can shorten the strings:
\r<count> string_to_repeat<space>
tri
For example, in a design with 16 scan chains, Shift statement might be defined as:
es
Shift {
V { _si=\r16 # ; _so=\r16 # ; CLOCK=P;} // pulse shift clock
R

SPF: Controlling Test Mode
 In the simple case, placing the design into ATPG test mode involves
holding a specific top-level port to a constant value:
 Define a PI constraint on the port
 Assign the port to its constrained value in the load_unload and capture procedures
ng
 More complex designs may require multiple pins and/or a specific
initialization sequence:
ni
ai
 Add the test_setup macro procedure to the SPF file
Tr
ASIC_TEST = 1 MacroDefs { STIL state
Status Bits
“test_setup” {
assignments
CONFIG are persistent
ip
V {CONF = 1; CONF_ENABLE = 1; CLK = P;}
V {CONF = 0; } // CLK=P again, CONF_ENABLE still 1
ch
101 1 0 1 V {CONF = 1; }
CONF
F1 F2 F3 V {CONF_ENABLE = 0; CLK = 0;}
ro
CONF_ENABLE 1 }
CLK off at end
}
ic
CLK
3- 17
lM
na
There is no Quick STIL equivalent for test_setup sequences. If Quick STIL commands are
used to define the Test protocol file but a test_setup initialization sequence is required to enter
er
scan mode, the test_setup sequence can be included in an SPF file and “appended” to the
nt
existing protocol with the following command:

rI
run_drc design.spf –append

Fo
Where design.spf contains a MacroDefs (with test_setup) and/or Procedures section.

se
All other sections of the provided SPF will be ignored.

U
Check the man page of the run_drc command for details on how TetraMAX handles potential
ed
conflicts when protocol information is provided with both TetraMAX command and an SPF.
ct
In this example design, ASIC_TEST is not a primary input; therefore, add_pi_constraints

tri
can’t be used alone. This is the case for pin-limited designs, where there is not an pi available for an
ASIC_TEST pin. Existing configuration logic is used here to generate an on-chip ASIC_TEST
es
signal. Bits serially clocked into flip-flops F1, F2, F3 are decoded to generate status signals.
Assume one serial bit pattern is unused in normal operation; then it can be used for test.
R
The penalty is that the configuration register must be initialized before scan shift.
Therefore, a custom initialization sequence must be added to the test protocol.

Where Does TetraMAX Get Timing Info?
 TetraMAX uses a cycle based simulator for DRC analysis

 The simulator does not have timing per-se, but events happen in a specific order
and are applied at specific times on the tester
ng
 The event order and timing come from the test protocol which can
come from several places
ni
 A SPF file written out from DFTC
ai
 Timing specified with Quick STIL commands
Tr
 Default timing in TetraMAX
Timing entered manually into the SPF
ip

ch
 What does TetraMAX do with the timing during?
 DRC: uses the timing values and event order for DRC checks
ro
 ATPG and Fault Sim: timing information is not used
ic
 Pattern Formatting: timing is associated with the output vectors 3- 18
lM
na
The timing in an existing SPF can be modified within TetraMAX by using read_drc and the
update_* commands in the following flow:
er
nt
read_drc <original_SPF_file>
rI
update_wft –wft <name> -period <d> -force <d> –strobe <d>

Fo
update_clock –wft <name> -clock <name> -pulse {<le> <te>}

se
update_scale –wft <name> -unit <ns|ps>

write_drc_file <new_SPF_file>
U
...
ed
run_drc <new_SPF_file>
ct
tri
Note: After specifying the timing modification commands, it is required that you use the
write_drc_file command to write out the modified data. It is also required that you specify
es
the run_drc command with this newly produced file in order to incorporate these changes.
R

Default WaveformTable (_default_WFT)
 Timing defined in DFTC or TetraMAX Quick STIL is saved as waveform

tables in the STIL file
Timing {
WaveformTable "_default_WFT_" {
Period '100ns';
ng
Waveforms {
"_default_In_Timing_" { 01ZN { '0ns' D/U/Z/N; } }
"_default_Clk0_Timing_" { P { '0ns' D; ‘45ns' U; ‘55ns' D; } }
ni
"_default_Out_Timing_" { X { '0ns' X; } }
"_default_Out_Timing_" { HTL { '0ns' X; '40ns' H/T/L; } }
ai
}
}
Tr
}
 STIL uses signal groups to save space
ip
SignalGroups {
ch
"_default_Clk1_Timing_" = '"prst_n"';
"_default_Clk0_Timing_" = '"sdr_clk" + "sys_clk"';
"_default_In_Timing_" = '"pframe_n" + ... "pad[0]"';
ro
"_default_Out_Timing_" = '"pframe_n" + ... "pad[0]"';
"_si" = '"pad[0]" + ... "pad[5]"' { ScanIn; };
ic
"_so" = '"sd_A[0]" + ... "sd_A[5]"' { ScanOut; };
}
3- 19
lM
na
Timing in the STIL protocol file comes from the following DFT-Compiler variables:
er
Variable Name Default Value

nt
test_default_period 100
rI
test_default_delay 0
test_default_bidir_delay 0
Fo
test_default_strobe 40
se
Clock edges are defined as follows:

set_dft_signal –view existing_dft –type ScanClock –timing {45 55}
U
ed
ct
tri
es
R

Pre-clock Measure vs. End-of-cycle Measure
 Two types of timing configurations used on testers

 Pre-clock Measure
Default timing used by TetraMAX and DFTC (recommended)
ng

Force PI’s or SI’s
ni
Measure PO’s M
ai
Pulse clocks
Tr
 End-of-cycle Measure
ip
Alternate timing sometimes used by older testers
ch

Force PI’s or SI’s
ro
Pulse clocks
Measure PO’s
ic
M
3- 20
lM
na
er
nt
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Fo
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Pre-clock Measure
 When the default pre-clock timing is used, the capture procedure can use
a single vector
"multiclock_capture" {
W “_multiclock_capture_WFT_";
ng
V {"_po" = \r168 #; "_pi" = \r179 #;}
}
ni
Single Vector Capture
ai
test_setup Load Capture Load/Unload Capture
Tr
Shift Shift Shift Shift Shift Shift
PI’s
ip
scan_se
ch
M M M M M M M M
Measure PO’s
ro
clk
ic
3- 21
lM
na
Note: a single vector capture procedure is required for At-Speed ATPG using external clocks
er
Measures (“M”) during Shift will detect faults captured by scan FF’s. The measure during the
nt
Capture procedure will detect faults that fanout to a PO.

rI
Fo
se
U
ed
ct
tri
es
R

TetraMAX Design Rule Checks
 Checked during read_netlist, run_build_model:

 N rules (netlist) and B rules (build)
 Checked during run_drc:
ng
 S rules (scan chain or shift)
ni
 C rules (clocks or capture)
ai
 Z rules (internal tristate buses and bidirectional pins)
Tr
 X rules (combinational feedback loops)
 V rules (vector statements in the SPF)
ip
 Other rule categories:
ch
 P rules (Path delay checks)
D rules (Pre-DFT violations)
ro

 R rules (Scan Compression violations)
ic
3- 22
lM
na
er
nt
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Fo
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U
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ct
tri
es
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Performing Scan Design Rule Checks
Run DRC Checks
ng
ni
ai
Tr
ip
Scan Chain Tracing
ch
ro
ic
3- 23
lM
na
scan design rule checking - This indicates the beginning of the scan design rule checking process.
reading test protocol file - Read the test protocol file and indicate the parsing of the file was successful with
er
no errors
nt
Bus/Wire contention ability checking - Summary the types of bus gates that are used in the circuit. This
includes the total number of bus gates, the number of bidirectional bus gates, the number of weak bus gates
rI
(only weak drivers), the number of pull bus gates (a mixture of strong and weak drivers), and the number of
Fo
bus gates which have a bus keeper.

simulating test protocol procedures - The simulation is used to determine state elements that have a
constant state behavior and those that attain a set value after the scan chain load.
se
scan chain operation checking - The results of the previous simulation are used to verify the operation of
the scan chains and identify the associated scan cells. As each scan chain is successfully verified, a message
U
is given indicating its completion with its name and length.

ed
clock rules checking - During this process many clock rules are checked and messages are given when
violations occur.
ct
nonscan rules checking - The objective of this checking is to determine the appropriate behavior for all non
scan state elements. This includes the nonscan DFFs, nonscan DLATs, and the transparent latch usage. The
tri
next message gives a summary of the calculated nonscan behaviors. DRC dependent learning - Using the
es
behaviors learned during DRC, analyses are performed to determine control ability, observe ability,
constraint effects, and blockages due to constraint effects for all gates in the circuit.
R
contention prevention rules checking – Rules and design behavior affecting contention.
DRC Summary Report - For each rule that had at least one violation, a summary message for that rule is
given indicating the number of times it was violated. The next message indicates the total number of rule
violations that occurred during the DRC process.

Results of Design Rule Checks
 If DRC passes, a DRC Summary

Report will be shown
 When running DRC, if a violation
ng
with a severity of Error is
ni
encountered, DRC fails and the
DRC run is aborted at that point
ai
Tr
ip
ch
ro
ic
3- 24
lM
na
Some DRC rules can be downgraded from an Error to a Warning with the set_rules
command. However, some rules like S1 cannot be downgraded.
er
nt
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Fo
se
U
ed
ct
tri
es
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DRC Setup
ng
ni
ai
Tr
ip
ch
Managing Faults
ro
ic
3- 25
lM
na
er
nt
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Fo
se
U
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ct
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es
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 Report violations with report_violations command

report_violations <vio_id|rule_id|rule_type|-all> \
[-instance <name | id>] [-max d]
ng
 Example: report all S-rule violations
ni
report_violations s
ai
 Debug violations with analyze_violation command
Tr
 Example: debug first S1 violation
analyze_violation s1-1
ip
GSV will display gates associated with the violation
ch

 Not all DRC violations support analysis with GSV
ro
ic
3- 26
lM
na
er
nt
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Fo
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Debugging an S1 Violation
 The S1 DRC uses the event sequence of the simulated shift procedure
 Each scan chain output is traced backwards through combinational and
sequential gates until the scan input is reached
ng
ni
Name of scan chain TetraMAX Gate ID Violation ID
ai
Tr
Error: Chain c1 blocked at DFF gate out_reg (8) after tracing 0 cells. (S1-1)
ip
Position in the scan chain (0
Scan cell
closest to ScanOut)
ch
 So “after tracing 0 cells” means that the violation occured at the
ro
last scan cell in the chain
ic
3- 27
lM
na
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nt
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Fo
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Debug S1 Violations Graphically in the GSV
Cannot trace symbolic value “S”

 At the reported scan cell through scan cell to its SI
watch out for:
 Clock signal pulsing?
ng
 ScanEnable active state?
ni
 Set/Reset inactive state?
ai
The reset pin (CDN) is
“X” during shift. Why? Trace path
Tr
ip
In this case, rst was not specified in the SPF file
ch
Define “rst” as clock (best solution):
add_clocks 1 {rst} -timing {100 50 80 40}
ro
ic
3- 28
lM
na
The shift character specified by “set_pindata –shift_character S” (default is “S”) is
used to distinguish valid scan data (SSS) from unconstrained nets (XXX) when viewing the “Shift”
er
pindata in the GSV.

nt
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Fo
se
U
ed
ct
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es
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Change Pindata to test_setup to Debug Initialization Issues
Test clock clk not propagated Scan chain blocked because
through multiplexer because of invalid clock signal
select signal is “X”
The default pindata when
analyzing an S1 violation is
shift (best for most situations).
ng
ni
Test mode register has lost its
ai
state after test_setup. Why? By default, the test_setup
pindata only shows the final
Tr
simulated state. To show the
entire test_setup sequence:
ip
set_drc –store_setup
set_pindata –test_setup
ch
ro
In the test_setup the test mode register is
ic
initialized correctly. But does it hold its state
during load_unload and capture? 3- 29
lM
na
Using set_drc –store-setup will increase run time and memory consumption during DRC.
You can control which bits are stored with set_pindata –setup_cycles {n1 n2}
er
Otherwise the GSV may be overcrowded and hard to see for long sequences.
nt
rI
Can also use report_primitives to display the test_setup pindata on the gate primitive
in the Transcript instead of using GSV
Fo
TEST-T> report_prim 55
flop1 (55) DFF (FD1S)
se
--- I () (TIE_0)
--- I () (TIE_0)
U
--- I (0101010) 21-

ed
--- I (XXXXXXX) 22-

--- O (XXXXXXX) 23-
ct
scan_behavior: MASTER(LE/-) chain=c1 cell_id=6 invert_data=NI obs=noproc

tri
set_reset_usage: set=no, reset=no, unstable_flag=no, set_dominance=none,

reset_dominance=none
es
R

Stability Patterns
 To further investigate why the initialized value did not hold its state in
load_unload and capture, look at the stability_patterns pindata
 To view the stability pattern, it also needs to have been stored during
ng
run_drc with the following command:
ni
set_drc –store_stability_patterns
ai
Tr
ip
ch
Required value of 1 loaded The 1 loaded during test_setup
ro
during test_setup is not maintained during capture
ic
Root cause in this case was a missing constraint
that was supposed to recirculate the data 3- 30
lM
na
There are two types of stability patterns
er
T/S/CCC (stability pattern with three sections)

nt
LLLLLS/CCC (stability pattern with two sections)

rI
1) The stability pattern with 3-sections is seen when there is no V statement in load_unload
Fo
before the Shift procedure. I.e., there is no pre-shift vector in load_unload procedure. Where:
se
T is the value on the pin after last cycle in test_setup procedure (you will only see 1 character
here, independent of the number of events in test_setup procedure)
U
S is the value on the pin in shift procedure (1 character only)

ed
CCC is the value on the pin in three different states in capture procedure (3 characters)
ct
2) You will see stability pattern with 2-sections when there are some vectors in the load_unload
tri
procedure prior to Shift. I.e., there are some pre-shift vectors. Where:
es
LLLLLS : here LLLL denote the events in pre-shift vectors (the number of L's depends upon the
number of events before Shift). And the last character in this first section is S, which is the value
R
after final shift.

CCC is the value on the pin in three different states in capture procedure (3 characters)

Simulation Waveform Viewer (SWV)
 Enables faster debugging of DRC test_setup issues
ng
ni
ai
Tr
ip
ch
ro
ic
3- 31
lM
na
TetraMAX’s waveform viewer helps designers quickly isolate and correct the causes of DFT
problems that tend to create project bottlenecks.
er
nt
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Fo
se
U
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tri
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Using the SWV
 GUI Enabling Commands
set_drc –store_setup // Must store the test_setup to view in GSV/SWV
set_pindata -test_setup // Pindata type is test_setup
 Add gates of interest in GSV  Select a net and add it to waveform
ng
ni
ai
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ip
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SWV commands:
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
add_waveform_signals <pin_pathname | gate_id | -all>
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remove_waveform_signals <pin_pathname | gate_id | -all> 3- 32
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Another way to limit the pindata characters displayed in the GSV is to use:
set_environment_viewer -max_pindata_length d
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Specifies the length of the simulation string centered around the current wave cursor reference
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point. When the value is set to 0, all available simulation pindata values are displayed. Note that the
pindata length count includes all "information" characters displayed between the waveform
Fo
characters. An ellipsis (…) is added to the annotation to signify that only a partial value is
displayed.
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When you use this with the waveform viewer moving the cursor in the waveform will move the
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selected pin range around the cursor

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Supported Pindata Types with SWV
 test_setup
 Debug an initialization sequence
 sequential_sim_data
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 Look at the results of a
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TetraMAX sequential
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simulation of pattern data
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 debug_sim_data
 View pattern simulation data an/d
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or VCD data from another simulator
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Want to Quickly Return to TEST Mode?
 First Session:
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DRC-T> run_drc DUT.spf
TEST-T> write_image pass1.image.gz \
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–compress gzip –replace –violations
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 A Later Session:
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TEST-T> # Ready to resume in TEST mode
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An image file can be password protected and it’s net name and instances can be “garbled” for extra
security. Furthermore, the user can control which commands can be executed when an image file is
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read. Image files are covered in more detail in the Diagnosis unit.
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DRC Setup
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Managing Faults
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Fault Classes
 DT – Detected: High Level

Fault Class
 DS - detected by simulation
 DI - detected by implication
 PT – Possibly Detected:
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 AP - ATPG untestable, possibly detected
Low-level
 NP - not analyzed, possibly detected
Fault Classes
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 UD – Undetectable:
UU - undetectable unused
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
 UO - undetectable unobservable
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 UT - undetectable tied
 UB - undetectable blocked
 UR - undetectable redundant
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 AU – ATPG Untestable:
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 AN - ATPG untestable, not-detected Use set_faults –summary verbose to see
Low-level fault classes in fault summary reports
 ND – Not Detected:
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 NC - not controlled
NO - not observed
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
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Fault sub classes that are related to loadable nonscan cells
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D2 - Detected clock fault with loadable nonscan cell faulty value of 0 and 1 (sub class of DT)
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P0 - Detected clock fault and loadable nonscan cell faulty value is 0 (sub class of PT)
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P1 - Detected clock fault and loadable nonscan cell faulty value is 1 (sub class of PT)
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Fault sub classes that are related to delay testing:

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DR - robustly detected delay fault (sub class of DT for path delay testing)
TP - Transition Partially-detected (sub class of DT for Slack-Based Transition
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testing)
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AX - ATPG untestable timing exceptions (sub class of AN indicating faults that are
untestable due to timing exceptions)
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Scan Path Faults are Detected by Implication
Chain test applies from SI The pattern expects

a 0011 pattern for all chains to observe the same
0011 pattern on SO
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DRC traces the scan chains through all the scan flops.
The faults on the scan clock, scan enable and scan path
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are “detected by implication” (DI) before ATPG
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Faults Classifications Right After DRC
TEST> add_faults –all
88326 faults were added to fault list.
TEST> report_summaries Complete fault list
Uncollapsed Stuck Fault Summary Report
----------------------------------------------- Must be faults on scan chains
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fault class code #faults
------------------------------ ---- ---------
Caused by design topology
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Detected DT 14666
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Possibly detected PT 0
Undetectable UD 44 PI/ATPG constraints,
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ATPG untestable AU 5383 Not 100% Full-Scan,
Not detected ND 68233 and/or need Seq ATPG
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-----------------------------------------------
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total faults 88326 Most faults start here
test coverage 16.61%
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-----------------------------------------------
Have not yet run ATPG
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Pattern Summary Report
#internal patterns 0 3- 38
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PT - Possibly Detected Faults
 A fault is classified as PT when the ATPG Example PT Fault

pattern that detects a fault results in the faulty D Q
machine simulating an X while the good SI
F1
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machine simulates a 1 or 0 SE
Cannot
predict
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 AP (ATPG untestable, Possibly 0
value of
1 F2/Q
detected): If this driver
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D1 U1 Therefore
is disabled to U0/E SA0
An analysis has proven that this fault cannot be test U0
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 is PT
detected under current ATPG settings (this does not D Q
SI 0/Z 0/X
rule out non-ATPG methods)
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F0 D Q
SE SI
F2
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 NP (Not analyzed, Possibly detected): And this 1/0
SE
enable pin
 An analysis to prove that the fault cannot be 0
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has a SA0
D0 U0
detected was not conclusive
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 One possible cause is that the abort limit is too low
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Credit may be given for possibly detected faults in the Test Coverage calculation.
The default credit is 50% and may be changed using set_faults -pt_credit 0, for
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example.
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Unused FF Output Pins become UU Faults
D D D
SI Q SI Q D Q SI Q
...0011 ...0011 ...0011 ...0011 ...0011
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SE SE SE
1111111 UU UU UU UO
CLK QN CLK QN EN QN CLK QN
F2 F3 LD F4
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UU
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CLK_1
CLK_2
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Given that all the QN pins are unconnected or unused
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
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 Both the stuck-at-0 and stuck-at-1 faults on the QN pins are classified
as UU
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 Unconnected/unused faults with fanout are UO faults
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The UO (undetectable unobservable) class is similar to the UU (Undetectable Unused) class, except
that the UO fault class specifically includes faults on unused gates with fanout (i.e., gates connected
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to other unused gates). Faults on unused gates without fanout are identified as UU faults.
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Actual Tie-offs in Netlist Become UT Faults
ASIC_TEST D Q D Q
F2 F3
SE SE
...
Reset
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Tied Pin has Synchronizer
a UT fault
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D Q D Q
0
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SE SE
F0 F1
1
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Internal Reset Line
RSTn Inactive During Scan
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The F0/D pin stuck-at-1 is classified as UT
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
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 It can never be controlled to 0 since it is tied off to 1
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Undetectable Redundant (UR) Fault
Redundant
U2 Gate U1
B
1/0
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A U1 U0 Y
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C
Undetectable
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U3 Stuck-At Fault
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 To avoid an output glitch, designer has added gate U1 but the added
gate does not alter the function Y, and is thus redundant
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 Since U1 has no effect, the stuck-at-0 fault is UR
The majority of UR faults are identified during run_atpg
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
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There are 4 UR faults in this small example. All are stuck-at-0 faults.
U1/Z
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U1/A
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U1/B
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U0/B
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Constraints Can Create AU Faults
ASIC_TEST is constrained to logic 1 during scan

testing which allows ATE control of the scan clocks.
However, this creates ATPG Untestable faults
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ASIC_TEST
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D Q D Q
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Clock F0 F1
Divider 0 SE SE
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1
CLK
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 Both stuck-at-0 and stuck-at-1 on the MUX D0 pin are AU
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 Stuck-at-1 for ASIC_TEST is not a tie-off, so it is an AU, not a UT
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Fault Progression from NC to DS
 NC (Not Controlled):
 The starting classification for most faults prior to ATPG
 A way in which to control the fault location to the value opposite the stuck-at value
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has not yet been found
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 NO (Not Observed):
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 Once ATPG controls the NC fault site, it becomes NO
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 The fault site could be controlled but a way to propagate the fault effect to an
observe point, either a scan cell or primary output, has not yet been found
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 Ideally, an “NO” fault will become a “DS” fault during ATPG
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A fault site that is always X is also classified as NC since it can never be controlled to a 1 or 0.
Faults can remain NC or NO after ATPG if they are very difficult to control or observe or the ATPG
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settings are not directing TetraMAX to work long enough.

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Defining Nofaults
 The addition of faults to the fault list can be inhibited by defining a set
of faults as “nofaults” prior to adding faults
 Nofaults can be defined with add_nofaults by:
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 Pin pathname
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 Primitive instance pathname
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 Hierarchical instance pathname
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 Module name
 Nofaults can also be defined by placing the fault locations in a Fault
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Interface File Format and reading the file:
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read_nofaults filename
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Creating a Fault List with Nofaults
 After successfully completing DFT rules checking, declare any
nofaults, then populate the fault list:
Example: Exclude faults in A2D converter and JTAG block
add_nofaults /ANALOG2DIGITAL
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12456 faults were added to nofault list.
add_nofaults /ORCA_JTAG_BSR_top_inst
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2434 faults were added to nofault list.
add_faults –all
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 When the fault list is populated with add_faults, the faults identified
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with add_nofaults will not be added to the fault list
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 TetraMAX supports a sampled or partial seeding of faults by using the
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-retain_sample option of the remove_faults command:
TEST-T> add_faults -all
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87098 faults were added to fault list.
TEST-T> remove_faults -retain 5
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Fault sampling finished: #faults reduced from 87098 to 4308
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The commands add_nofaults and add_faults have similar options. Specify nofaults first,
then add the faults.
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Fault Interface File Format
Type of Fault Site Pin Pathname
Fault Class Other Text - Comments
sa0 DI /CLK ; comments here

sa1 DI /CLK
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sa1 DI /RSTB
sa0 DS /RSTB
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sa1 AN /i22/mux2/A
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sa1 UT /i22/reg2/lat1/SB
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sa0 UR /i22/mux0/MUX2_UDP_1/A
sa0 UR /i22/mux0/A
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sa0 DS /i22/reg1/MX1/D
sa0 DS /i22/mux1/X
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sa0 DS /i22/mux1/MUX2_UDP_1/Q
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sa1 DI /i22/reg2/r/CK
sa0 AP /i22/out0/EN
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sa1 AP /i22/out0/EN
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Fault lists can be exported from and imported into TetraMAX.
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Column 1 - Type of fault site, {sa0, sa1, str, stf}

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Column 2 - Class of fault, “--” indicates the fault is equivalent to the last line before it which has
other than “--”
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Column 3 - Pin pathname to the fault site

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Other text - Treated as comments

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Equivalent Faults
Fanout-free net Network N 1

A
B U1
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U1/A SA1  U1/Y SA0 Z
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C
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D
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Equivalent Faults:
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A set of faults whose effects cannot be distinguished
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at the ATE are equivalent to one another. No test can
be created to tell them apart from one another.
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Intuitively, some faults in network N 1 would seem to be identical in their effects:
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Functional Equivalence:
Functionally equivalent faults in a network produce the same truth-table output.
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Two arbitrary faults are functionally equivalent if no test exists to tell them apart.
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Proving this is an NP-complete problem—as CPU-intensive as ATPG itself!

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 Fortunately, many functionally equivalent faults are also structurally equivalent.

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Structural Equivalence:
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 Structurally equivalent faults are intuitively equivalent based on local structure.

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 A trivial example is the two corresponding faults at the ends of a fanout-free net; thus,
an stuck-at-0 fault at port A is equivalent to the stuck-at-0 at the NAND input pin A.
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 Another equivalence is the stuck-at-1 at inverter pin U1/A and the stuck-at-0 at pin U1/Y.
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Conclusion:
This slide shows how ATPG begins traversing the logic, thinning out the faults.
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 Only one fault per equivalent fault set is retained—reducing test pattern count.

Fault Collapsing
Nf = 2 ( Ninputs + 1 )
Before
= 6 Collapsing
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Nf = ( Ninputs + 2 ) After
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= 4
Collapsing
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 The effect of a NAND input stuck-at-0 (SA0) is identical to the output
stuck-at-1 (SA1)
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 The fault set { A SA0, B SA0, Y SA1 } is thus an equivalent set
Only one of the equivalent faults needs to be included
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
Example: Y SA1
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This slide examines structurally equivalent faults for a typical logic gate, a NAND.
It demonstrates that ATPG need consider only four faults out of the original six.
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This is because a 0 input value to a NAND is controlling—it forces the output to 1.

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Intuitively, there exists no test that can distinguish an input stuck-at0 and the output stuck-at-1.
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On the slide, the two input stuck-at-0 faults (gold diamonds) have thus been eliminated.
A similar structural equivalence analysis can be applied to any other N-input gate.
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Fault List After Collapsing
A Network N 1
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Z
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D After collapsing, only
8 of 32 faults left
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Fault Collapsing:
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By testing for only one fault per equivalence set, the fault
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population is reduced (or collapsed) which means fewer patterns
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Thinning out all but one fault per equivalent fault set is called fault collapsing.
This slide reveals that, after collapsing, only 8 faults remain in N1 out of 32.
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Fault collapsing significantly reduces ATPG run time and test-pattern count.
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This is one of the techniques TetraMAX uses to efficiently generate test programs.
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TetraMAX ATPG uses a mixture of techniques to determine equivalent faults:

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Quickly identifies structurally equivalent faults, using local analysis.

Selectively tries to prove functional equivalence between critical faults; thus TetraMAX
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rapidly thins a large fault population to a relatively lean one.

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Equivalent Faults in the Fault File
sa1 DS A
sa1 -- u_nand/A
sa1 DS u_inv/Z
sa0 -- u_inv/A
sa0 -- B
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sa1 -- u_nand/B
sa0 DS u_nand/Z
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sa0 -- u_norz/A
sa0 DS Z
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sa0 -- u_norz/Z
sa1 -- u_norz/A Equivalent
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sa1 -- u_norz/B Faults
sa1 -- u_nand/Z
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sa0 -- u_nand/A
... .. ...
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 By default, faults equivalent to the previously listed fault code are
indicated by --
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This slide is a report derived from the fault list that TetraMAX maintains for a DUT.
The legend -- indicates that a fault is equivalent to the previous reported fault.
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On the slide, faults belonging to an equivalent set are highlighted in the same color.
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The fault code DS means that ATPG successfully generated a pattern for that fault.
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Code DS stands for detected by simulation.

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set_faults -equiv_code <code_name> | -noequiv_code

Selects the equivalence code to use when reporting uncollapsed faults. The default is to use a
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double dash "--". Use of -noequiv_code suppresses the use of this character string and uses instead
the fault class of the fault to which this fault is equivalent.
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Collapsed vs. Uncollapsed Faults
 The uncollapsed fault list contain faults on ALL faultable pins
 The collapsed fault list contains only “primary” faults (i.e. one fault per
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set of equivalent faults)
 TetraMAX processes the collapsed fault list during ATPG but keeps
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track of both the collapsed and uncollapsed faults
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 Test Coverage can be reported using either collapsed or uncollapsed
numbers
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set_faults -report [-collapsed | -uncollapsed ]
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 Fault lists can be saved to files and reported in either the collapsed or
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uncollapsed form
write_faults <file> -all [-collapsed | -uncollapsed]
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To improve performance, most ATPG tools identify all equivalent faults and use only a single
member of each fault equivalence class. For example, a stuck-at-0 fault on the input pin of a BUF
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gate is equivalent to the stuck-at-0 fault on the output pin of the same gate. The collapsed fault list
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would contain only one of those faults which is termed the "primary" fault. For a given set of
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equivalent faults, the choice of which one is the primary fault is controlled by the equivalency
analysis and is not predictable.
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Calculating Test and Fault Coverage
 Test Coverage is defined as the percentage of detected faults divided

by the ATPG detectable faults
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DT + (PT * posdet_credit)
Test Coverage =
all faults - (UD + (AU * au_credit))
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 Fault Coverage calculation also includes UD faults, which do not
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change the static behavior of the design
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DT + (PT * posdet_credit)
Fault Coverage =
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all faults
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posdet_credit = 50% by default
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au_credit = 0% by default
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To consider only hard detected faults, use :
set_faults -pt_credit 0
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There is also a set_faults option to give credit to AX faults:

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set_faults -ax_credit <d>

Where <d> defines the percentage of credit given to AX (ATPG Untestable Timing Exceptions)
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faults. The default is 0.

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The Test Coverage calculations can be further controlled by the –test_coverage_include

and –test_coverage_exclude options of the set_faults command. See the man page
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for details.
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How to Report Fault Coverage
BUILD-T> set_build –nodelete_unused_gates

. . .
TEST-T> set_faults –fault_coverage
TEST-T> report_summaries
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-----------------------------------------------
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------------------------------ ---- ---------
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Detected DT 82596
Reports Uncollapsed Possibly detected PT 24
Undetectable UD 279
Faults by Default
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ATPG untestable AU 5458
Not detected ND 145
-----------------------------------------------
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total faults 88502
fault coverage 93.34%
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-----------------------------------------------
-----------------------------------------------
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#internal patterns 784
#basic_scan patterns 784
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-----------------------------------------------
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By default, TetraMAX only outputs the test coverage percentage whose value does not change
based on “set_build –delete_unused_gates”.
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If “set_build –nodelete_unused_gates” is specified, the following warning is reported:

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Warning: Unused gate deletion affects fault coverage calculation (M245)

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Adding Faults / Saving Faults
 Fault sites locations of a given fault model can be added to the fault
list for all locations (-all), specific pin pathnames, specific instance
names, or module names
ng
add_faults <pin_path | inst_name | -module <name> | -all>
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 Faults can also be defined by placing the fault locations in a Fault
Interface File Format and reading the file:
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read_faults filename
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 Once faults are populated, save all faults or just specific classes:
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write_faults my_asic_all.flt –replace –all
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write_faults my_asic_au_nd.flt –replace –class {au nd}
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 Fault files for SoC designs can be huge:
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write_faults my_asic_all.flt.gz –all –compress gzip
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 List 3 methods of creating an SPF file
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 Describe 2 ways of defining timing in TetraMAX
Name 2 types of procedures used by ATPG
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
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 Name the 5 high level fault classes
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ip
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Begin Lab 3: Running DRC
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add_clocks Defines a clock, set/reset or RAM control

add_pi_constraints Defines a constrained value for a PI
ng
add_pi_equivalences Defines an equal/opposite relation for Pis
add_scan_chains Declares the scan PI/PO for a chain
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add_scan_enables Defines a constrained value for a PI to enable shift
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report_pi_constraints Reports currently defined PI with constraints
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report_primitives Reports all primary inputs, outputs, etc.
run_drc DUT.spf Performs design rule checks using a STIL file
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source commands.tcl Executes the commands store in a file
write_drc_file my.spf Creates on disk the test protocol in STIL format
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Agenda
DAY
1
i Introduction
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3 Running DRC
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4 Controlling ATPG
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Controlling ATPG ©2018 Synopsys, Inc. All Rights Reserved. 4-1

TetraMAX Workshop
Unit Objectives
ng
 Describe when and how to use -abort limit
 Describe when and how to use -capture_cycles
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 Debug Low Fault Coverage
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 Name some differences between TetraMAX and TetraMAX II
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TetraMAX Workshop
BUILD
Mode
TEST
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Mode
Gate-level Read Run
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Verify
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Patterns
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Build Review
ATPG Model Coverage
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DRC
Mode Incremental
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STIL Test Check
ATPG
Protocol DFT Rules
(if needed)
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TEST Mode is entered if DRC was successful. In TEST mode, the following operations are typical:
adjust settings for ATPG, start pattern generation, run an incremental ATPG if needed, and save the
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patterns to disk.
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TetraMAX Workshop
Running ATPG
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Post-ATPG Analysis
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TetraMAX II
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TetraMAX Workshop
Running ATPG
 The command to configure various run options for ATPG is set_atpg

 The set_atpg command includes dozens of command options – some
of the more commonly used ones are:
ng
-abort_limit, -capture_cycles, -num_processes,
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-num_threads, -parallel_strobe_data_file, -patterns,
-power_budget, -verbose
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 The command to run ATPG is run_atpg
 Best starting point for tradeoff of coverage, pattern count, and runtime
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run_atpg –auto_compression
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 Some other commonly used command options are:
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-nodisturb_clock_grouping, -only_chain_test,
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-only_chain_diagnosis, -optimize_patterns
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More info on the set_atpg command options mentioned above:
-abort_limit <n> - Specifies the maximum number of remade decisions before terminating a test
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generation effort during the Basic-Scan and Fast-Sequential ATPG algorithms.

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-capture_cycles <n> - Sets the Fast-Sequential ATPG algorithm effort level.

-num_processes <n>- Specifies the number of slave processes to be used for multicore ATPG.
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-num_threads <n> - Specifies the number of threads for multithreading with TetraMAX II.
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-parallel_strobe_data_file [psd_file] - Generates a parallel strobe data (PSD) file used for
debugging parallel simulation failures.
-patterns max_patterns - Specifies the termination of the ATPG effort when the pattern count
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equals or exceeds the specified value.

-power_budget <n> - Sets a power (switching) budget for the Power Aware ATPG feature.
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-verbose - Extra messages are displayed during the pattern merge operation.
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More info on the run_atpg command options mentioned above:

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-auto_compression - Selects an algorithm that automatically produces compact patterns and high test
coverage using minimal CPU time.
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-nodisturb_clock_grouping - Runs ATPG without disturb clock grouping.

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-only_chain_test - Specifies ATPG to generate chain test patterns only.

-only_chain_diagnosis - Specifies ATPG to generate only X-tolerant chain test and capture
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patterns.
-optimize_patterns - Selects an algorithm designed to produce a very compact pattern set with high
test coverage. The trade-off is that this optimization increases the run time by dynamically adjusting the
internal settings, such as abort limits, minimum detects, and merge limits during ATPG.

TetraMAX Workshop
ATPG: Select TetraMAX Engine(s)
 Basic-Scan: very fast, excellent coverage for full-scan

 Fast-Sequential: higher coverage for near-full-scan designs; good for
shadow logic around memories, limited non-scan
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 Full-Sequential: powerful engine supporting more complex designs
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TetraMAX’s integrated ATPG engines provide the highest Stuck-At test coverage. Synopsys recommends
starting with Basic-Scan (combinational) ATPG, followed by Fast-Sequential (up to 10 capture cycles) and
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then Full-Sequential (unlimited capture cycles) if necessary. Full-Sequential is a powerful algorithm, but it
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takes longer to run. Run it only on the undetected faults after doing Basic-Scan/Fast-Sequential ATPG. All
these ATPG algorithms are available in a single tool, with a single user-interface.
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Basic-Scan (combinational mode) for fast coverage:

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Good for “full-scan”/“near-full-scan” designs.

Requires control of clocks during scan and shift non-transparent latches, memories are
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black boxed.
Fast-Sequential for increasing coverage on designs and supports (i.e.: can deterministically propagate faults
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through) load unstable nonscan cells as long as they are stable (in capture cycle) when all clocks are in their
off-state:
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Good for designs with Shadow Logic around Embedded Memories.

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Note: Limit of 10 “capture cycles”.

Full-Sequential for increasing coverage on designs and fully supporting load unstable nonscan cells.
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Note: No limit to the number of “capture cycles”.

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TetraMAX Workshop
Results after Basic-Scan ATPG
TEST> run_atpg –auto
Most NDs are now DTs
. . .
because of ATPG
-----------------------------------------------
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------------------------------ ---- ---------
Detected DT 82669
Slight Increase in Number of
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Possibly detected PT 23 PTs, UDs and AUs after ATPG
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Undetectable UD 103
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Not detected ND 93
-----------------------------------------------
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Very Few NDs Remain
total faults 88326
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-----------------------------------------------
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Pattern Summary Report Have only run Basic-Scan ATPG
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-----------------------------------------------
#basic_scan patterns 191 4- 7
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TetraMAX Workshop
AU: Untestable under Current ATPG Settings
 The ATPG untestable (AU) fault class includes faults which can neither
be hard detected under the current ATPG conditions nor proved
redundant
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 When calculating test coverage, these faults are considered the same
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as untested faults because they have the potential to cause failures
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 Primary reasons for faults in this classification include:
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 Fault untestable due to a PI, ATPG, or cell constraint which is in effect
 Fault requires sequential patterns for detection
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 Fault untestable due to a masked cell or PO
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Faults around non-scan elements (non-scan flip-flops, latches, bus keepers, RAMs) are AU for
Basic-Scan ATPG
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AX is a sub-class of AU containing faults that are untestable due to timing exceptions.

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TetraMAX Workshop
ATPG: Basic-Scan versus Fast-Sequential
 Basic-Scan: full scan, single capture clock pulse

Faults Between
Scan Registers are
Detectable By
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Basic Scan ATPG
SI SO
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Scan Registers
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 Fast-Sequential: limited amount of non-scan (non-
scan flip-flops, latches, bus keepers, RAMs), multiple
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capture clock pulses possible
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Faults Around
If a Nonscan Register
Nonscan
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is “Loadable”, it can
Registers Require
be controlled with
Sequential ATPG
Basic-Scan as well
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SI Nonscan Registers SO
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Basic-Scan means that there is exactly one capture cycle, i. e. test cycle with active clock and scan
enable set to normal operation mode.
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Fast-Sequential means there may be from 2 to 10 capture cycles between scan load and unload. By
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supporting multiple capture cycles TetraMAX allows full testing of circuitry between non-scan
registers, which would be untestable using Basic-Scan ATPG.
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TetraMAX Workshop
Loadable Nonscan Cells
 Loadable nonscan cells are nonscan flip-flops or latches that capture

known values during the last shift cycle(s)
 ATPG can control a loadable nonscan cell up to a sequential depth of 1
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 Control of loadable nonscan cells is supported by the Basic-Scan and
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two-clock ATPG engines
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 The additional control allows the more efficient Basic-Scan ATPG
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engine to obtain higher Test Coverage
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 Logic and fault simulation can simulate these load values for depths up
to the length of the longest scan chain (max of 10)
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 Simulation of loadable nonscan cells is also supported during Fast-
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Sequential ATPG
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By control to a sequential depth of 1, this means that ATPG knows it can load a particular value
(0/1) in a nonscan cell that is one level of sequential depth away from a scan cell. This value loaded
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in the nonscan cell can be used by ATPG to create a pattern to test a targeted fault.
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By simulation of loadable nonscan cells, this mean that ATPG can simulate the last n (max of 10)
cycles of scan load to see if any additional nonscan cells will resolve to known values. This allows
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nonscan registers greater than one level of sequential depth away from a scan register to be loaded
with a known value. ATPG is not able to use these values when creating a pattern to target a fault.
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However, it can use these additional known values to pickup additional detections from an existing
pattern during fault simulation.
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Note: Full-Sequential ATPG does not support loadable nonscan cells.

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TetraMAX Workshop
Using Loadable Nonscan Cells
 To enable loadable nonscan cells support

set_drc -load_nonscan_cells
Need to also set the number of cycles to simulate when determining
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
nonscan cell load values
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set_simulation -shift_cycles <n>
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 Where 1 < n < 10 (and less than longest chain)
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 Reporting nonscan cells
report_nonscan_cells [ load | nonx_load ]
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 load: Loadable nonscan cells
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 nonx_load: Loadable nonscan cells which always have a non-X value (i.e.,
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0 or 1) during the random pattern based analysis performed during run_drc
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 Use analyze_nonscan_loading for analysis
4- 11
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New section printed during run_drc when set_drc –load_nonscan_cells is set:
Begin nonscan rules checking...
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Nonscan cell summary: #DFF=7 #DLAT=0 #RAM_outs=0 tla_usage_type=none

Nonscan behavior: #LE=7
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Load disturbs : #LE=7

Nonscan rules checking completed, CPU time=0.00 sec.
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------------------------------------------------------------------------------
Shift_pattern simulation setup completed: #shift_cycles=1, #shift_patterns=3
Shift simulation completed: #shifts=1, #nonscancells_loaded=160
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Nonscan load cell identification completed: #load_nonscan_cells=6
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Begin DRC dependent learning...

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TetraMAX Workshop
Enabling Fast-Sequential ATPG
 If AU faults remain after Basic-Scan ATPG, the Fast-Sequential engine

can help detect faults that require sequential clocking
 To enable Fast-Sequential ATPG, specify the number of
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capture_cycles:
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set_patterns –histogram_summary
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set_atpg -capture_cycles <d>
run_atpg -auto
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[Where <d> is an integer between 2 and 10]
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d = 0 (the default) disables Fast-Sequential ATPG pattern effort and results in Basic-Scan ATPG
patterns.
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d = 1 is invalid and not accepted.

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set_patterns –histogram_summary will enable printing of a histogram that list the

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number of patterns for each capture depth as well as the number of multi-load patterns.
-----------------------------------------------
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#fast_sequential patterns 47
# 2-cycle patterns 7
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# 2-load patterns 14
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# 3-load patterns 33
-----------------------------------------------
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The capture cycles option also determines the number of scan loads that are possible. To prevent
TetraMAX from generating patterns with multiple loads:
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set_atpg –single_load_per_pattern

TetraMAX Workshop
How to Determine –capture_cycles
 Use report_summaries sequential_depths to find the largest
sequential depth for the design
TEST-T> report_summaries sequential_depths
type depth gate_id
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------- ----- -------
Control 1 21569
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Observe 2 6866
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Detect 3 6859
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 The depths show the theoretical maximum depths
 This doesn’t mean that ATPG will be able to detect all faults with that level of
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depth if -capture_cycles is set to the same value as the Detect depth
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 Recommendation is to start at the Detect depth
Designs with RAM models, recommended start depth is 4
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
Incrementally increase depth to the point of diminishing returns given
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
coverage and runtime goals 4- 13
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Note: it’s not recommended to start with a large number of capture cycles for the initial Fast-
Sequential run. Start with a reasonable setting of capture cycles (2-4). Then in subsequent runs,
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increase the number of capture cycles incrementally as needed.

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TetraMAX Workshop
When Can Fast-Sequential ATPG Help?
Non-Scan Flops/Latches D Q D Q
TI TI
SE SE
CP CP
CLK
D Q
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D Q
Must be stable during capture CP G
when CLK is in its off-state
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Embedded
Memories
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Internal
SA0
Tristates
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Bus Complex
Keeper Internal
RAM R/W,
RAM
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Tristate Clock
Logic controls
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The Fast-Sequential algorithm supports (i.e. deterministically propagates faults through) load
unstable nonscan cells as long as they are stable (in capture cycle) when all clocks are in their off
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state.
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The Full-Sequential algorithm fully supports load unstable nonscan cells.

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Load stable cells can be used by Fast-Sequential by creating patterns with multiple loads. The first
load places a value in a non-scan cell. After the next load, the previously loaded value can be used
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during capture to detect faults.

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TetraMAX Workshop
Results after Fast-Sequential ATPG
Recall: After Basic Scan ATPG After Fast Sequential ATPG
TEST> run_atpg –auto Uncollapsed Stuck Fault Summary Report
. . . More DTs-------------------------------------------
because of
Fast-Sequential
Uncollapsed Stuck Fault Summary Report ATPG
------------------------------------------- -------------------------- ---- ---------
fault class code #faults Detected DT 87644
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-------------------------- ---- --------- Possibly detected PT 62
Detected DT 82669 Undetectable UD 129
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Possibly detected PT 23 ATPG untestable AU 176
Undetectable UD 103 Not detected ND 315
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ATPG untestable AU 5438 -------------------------------------------
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Not detected ND 93 total faults 88326
------------------------------------------- test coverage 99.41%
total faults 88326 -------------------------------------------
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test coverage 93.72% Pattern Summary Report
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------------------------------------------- -------------------------------------------
Pattern Summary Report #internal patterns 491
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------------------------------------------- #basic_scan patterns 195
#basic_scan patterns 191 #fast_sequential patterns 296
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Fast Sequential Patterns Added Very Few AUs Remain
4- 15
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Only the very-hard-to-detect faults remained after running both Basic-Scan and Fast-Sequential
ATPG.
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TetraMAX Workshop
How to Enable Full-Sequential Engine
 Enable Full-Sequential ATPG before the run_atpg command:

set_atpg -full_seq_atpg <other_opts>
run_atpg -auto
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 To run only the Full-Sequential ATPG engine:
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run_atpg –auto full_sequential_only
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 When Full-Sequential ATPG might help:
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 Clocks (ordinary clocks, resets/sets, memory writes) to nonscan elements not
controlled from Primary Inputs
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 Sequential Detect depth greater than 10
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Note: Full-Sequential ATPG is not compatible with some features and flows.
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TetraMAX Workshop
ATPG Guidelines
ATPG Methodology Tips:

 Always run the Basic-Scan engine first
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 If sequential ATPG is needed, try running the
Fast-Sequential engine next
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 Run the Full-Sequential ATPG engine last
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For all ATPG engines and fault models, use run_atpg –auto for the
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
best results
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 When run_atpg –auto is run, TetraMAX will cycle through all of the
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enabled ATPG engines
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 ATPG can utilize multiple processor cores to decrease runtime
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TetraMAX Workshop
Multicore Support in TetraMAX
 Utilizes multiple processor cores on the same machine

 TetraMAX launches multiple slave processes to parallelize ATPG work on a single
host
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 User can specify the number of processes to launch based on number of CPUs
and available memory on the machine
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Multicore supported for ATPG (run_atpg), fault simulation
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
(run_fault_sim) and pattern simulation (run_simulation)
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 One license supports up to 4 cores
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 Each additional license allows 4 more cores
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Writing dual-STIL flow parallel compressed patterns requires run_simulation functionality to
generate the internal data
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If you observe long write times for these patterns:

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set_simulation -num_processes <n>

write_patterns –parallel
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TetraMAX Workshop
Enabling Multicore Support
 Commands to enable TetraMAX multicore support

 Multicore ATPG:
set_atpg –num_processes <<n>|max>
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 Multicore simulation:
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set_simulation –num_processes <<n>|max>
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 Where <n> is a positive integer to specify number slave processes to be used for
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Multicore
 If max is specified TetraMAX computes the maximum number of processes available
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on the host based on number of CPUs
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 Command settings are persistent throughout the same
TetraMAX session
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Ensure the machine being used has as many available cores as <n> in set_atpg –
num_processes <n>
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If multicore is used on a machine that does not have sufficient cores (or memory) available, you are
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likely to see a slowdown!

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TetraMAX Workshop
Multicore Script Examples
Multicore ATPG Multicore Faultsim

set_messages -log tmax.log -rep set_messages -log tmax.log -replace
read_netlist Libs/*.v -delete read_netlist Libs/*.v -delete
read_netlist gates/top.v read_netlist gates/top.v
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run_build_model top_level run_build_model top_level
run_drc top_level.spf run_drc top_level.spf
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set_pattterns -external data.vcde \
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-strobe {rising CLK} \
–strobe {offset 50 ns}
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… …
add_faults –all add_faults –all
set_atpg –num_processes 4 set_simulation –num_processes 4
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… …
run_atpg -auto run_simulation
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run_fault_sim
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Master log file: tmax.log
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Slave log files: tmax.log.1, tmax.log.2, tmax.log.3 etc.
4- 20
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TetraMAX Workshop
Multicore run_atpg Output
set_messages –level expert

set_atpg –num_processes 2
run_atpg -auto
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Starting parallel ATPG with 2 processes.
…
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… Master Process Process id Wall Clock Time Shared + Private Pattern Memory
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Processes Summary Report
-----------------------------------------------------------------------------
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Process Patterns Time(s) Memory(MB)
----------- ----------- -------------- ---------------------------------
ID pid Internal CPU Wall Shared Private Total Pattern
ip
-----------------------------------------------------------------------------
0 7611 1231 0.53 35.00 67.78 30.54 98.32 5.27
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1 7612 626 35.68 35.00 64.87 22.31 87.18 0.00
2 7613 605 35.50 35.00 64.71 22.47 87.18 0.00
Total 1231 71.71 35.00 67.78 75.32 143.10 5.27
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-----------------------------------------------------------------------------
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Child Processes Total Memory
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Note: To see the process summary report expert level messaging must be enabled with: set_messages –
level expert
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TetraMAX Workshop
Running ATPG
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Post-ATPG Analysis
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TetraMAX II
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TetraMAX Workshop
Post-ATPG: Reducing ND Faults
 The abort limit controls how many times ATPG will re-attempt to detect
a fault (also called remade decisions)
 Raising this limit may reduce the number of ND faults – at the expense of
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longer run times and higher pattern counts
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 In the Basic-Scan and Fast-Sequential engines the abort limit is set with
the following command:
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set_atpg -abort <N> (default is 10)
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 In the Full-Sequential engine the primary control of ATPG effort is
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–full_seq_time which specifies the max time (in seconds) to spend
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per fault:
set_atpg –full_seq_time <N> (default is 10)
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4- 23
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What is a remade decision?
A decision is remade when a choice of stimulus to sensitize a fault control path or
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observation path fails to achieve the desired control/observe condition.

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Even though –full_seq_time is the primary control for Full-Sequential ATPG, there is also an
abort limit for Full-Sequential that can be set when –full_seq_time is set to zero. E.g.:
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set_atpg –full_seq_time 0
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set_atpg –full_seq_abort_limit <N>

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TetraMAX Workshop
Post-ATPG: Results with Higher Abort Limit
 Higher limit allows both Basic-Scan and Fast-Sequential ATPG to

generate more patterns and increase coverage
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TetraMAX Workshop
Post-ATPG: Final Abort Limit Results
 Warning: Higher abort limits can result in significantly longer runtime

 Abort limits of 100 to 1000 or more are considered high
Recommendation: Increase abort limit gradually and incrementally
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
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run_atpg –auto
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set_atpg –abort 100
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run_atpg –auto
set_atpg –abort 1000
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run_atpg -auto
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More information on experimental results seen with gradually increasing abort limit can be found in
this Tutorial from San Jose SNUG 2009:
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https://www.synopsys.com/news/pubs/snug/sanjose09/wc2_test_tutorial.pdf
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TetraMAX Workshop
Low Coverage: Review PI Constraints
TEST-T> report_pi_constraints
port_name constraint_value
---------- ----------------
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RTFM_CLK 0
THAT can’t be good
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TMU_MODE_0 0
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TMU_MODE_1 0 Circuit behind MODE is AU
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POW_RST_N 1
Missing RESET coverage
TAP_RST_N 1
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TMS 0
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Complex MODE
ABCD_CS0_N 0
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SCAN_EN 1
This isn’t good, either
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Audit the list of PI constraints. Make sure that only the required PI constraints are listed.
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TetraMAX Workshop
Low Coverage: Analyze the Clocks
TEST-T> report_clocks –verbose

scan connections nonscan connections
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clock_name off clock set reset clock set reset
-------------- --- ------------------ -------------------
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RTFM_CLK 0 18 0 0 0 0 0
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PIPE_STAT0 0 47511 0 0 851 0 0
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TRACE_SYNC 0 54844 0 0 2124 0 0
A08 0 0 0 0 6070 0 0
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RESET 1 0 500 2457 0 23 11
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Large # of Nonscan FF’s
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To perform “what if” analysis of the Test Coverage impact if non-scan FF’s were made scanable,
use the set_scan_ability command.
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TetraMAX Workshop
Are All Expected Flops Scannable?
TEST-T> report_nonscan_cells –summary
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Nonscan cell summary: #DFF=12855 #DLAT=3159
#RAM_outs=737 tla_usage_type=X_clock_tla
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Nonscan behavior: #CU=184 #C0=184 #C1=2138
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#TLA=1045 #LE=12453 #TE=1 #LS=9
#RAM_outs=737
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Load disturbs : #CU=184 #C0=0 #C1=0 #TLA=1045
#LE=5507 #TE=1 #LS=1 #RAM_outs=0
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TLA behavior: #no_clock=27, #hot_clock=1016,
#X_clock=2
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C0 (constant zero) - This is a nonscan cell that has been initialized to a 0 state from the test
setup procedure and will always retain that state in the presence of the current PI (primary input) constraints.
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C1 (constant one) - This is a nonscan cell that has been initialized to a 1 state from the test setup
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procedure and will always retain that state in the presence of the current PI constraints.
CU (clock unstable) - This is a nonscan cell that does not have clock-off stability and does not qualify to
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be a transparent latch (described below).

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L0 (load 0) - This is a nonscan cell that has been set to a 0 state at the end of the scan chain load, but is not
restricted to always retain the state.
L1 (load 1) - This is a nonscan cell that has been set to a 1 state at the end of the scan chain load, but is not
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restricted to always retain the state.

TLA (transparent latch) - This is a nonscan DLAT that is not stable when all clocks are off. This allows it
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the opportunity to behave as a transparent latch when one of its clock inputs is active while the other
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clock/set/reset inputs are inactive. The transparency condition must occur at the force_pi time of a pattern
when all clocks are off.
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LE (leading edge clock behavior) - This is a nonscan DFF that is stable when all clocks are off and the
clock-off state results in a 0 on its clock input lines. An LE cell captures data on the leading edge of a clock
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pulse.
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TE (trailing edge clock behavior) - This is a nonscan DFF that is stable when all clocks are off and the
clock-off state results in a 1 on its clock input lines. A TE cell captures data on the trailing edge of a clock
R
pulse.
LS (level sensitive behavior) - This is a nonscan DLAT that is stable when all clocks are off.

TetraMAX Workshop
DRC Rules Affecting Coverage
 Make sure to investigate the following rules because they can

adversely affect coverage
 C1, C2, C3, C4, C12, C15, C16, C19, C20, C21, C22, C23, C25, C26, C37,
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X1, and Z-rules for example
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 Example – C12 violation:
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By default, a C12 violation
will cause the captured
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value to be masked
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TetraMAX Workshop
Hierarchical Test Coverage
TEST-T> report_faults -all -level {3 256}
#faults testcov instance name (type)
------- ------- -----------------------
88102 93.60% / (top_module)
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86866 93.55% /I_ORCA_TOP (ORCA_TOP)
11734 100.00% /I_ORCA_TOP/I_SDRAM_WRITE_FIFO (SDRAM_WFIFO)
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11734 99.81% /I_ORCA_TOP/I_SDRAM_READ_FIFO (SDRAM_RFIFO)
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2116 99.24% /I_ORCA_TOP/I_SDRAM_IF (SDRAM_IF)
12788 58.14% /I_ORCA_TOP/I_RISC_CORE (RISC_CORE)
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12008 100.00% /I_ORCA_TOP/I_PCI_WRITE_FIFO (PCI_WFIFO)
11694 99.34% /I_ORCA_TOP/I_PCI_READ_FIFO (PCI_RFIFO)
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2344 100.00% /I_ORCA_TOP/I_PCI_CORE (PCI_CORE)
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1924 99.95% /I_ORCA_TOP/I_PARSER (PARSER)
19268 99.27% /I_ORCA_TOP/I_BLENDER (BLENDER)
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610 100.00% /I_ORCA_TOP/I_PCI_W_MUX (PCI_W_MUX)
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610 100.00% /I_ORCA_TOP/I_SD_W_MUX (SD_W_MUX)
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The -level option to the report faults command can be used to display test coverage on a
hierarchical basis.
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-level <d> <m>

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Generates a fault report for specified hierarchical levels. The d argument specifies the hierarchical
depth of the report and the m specifies a minimum number of faults required to display a given
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depth. For example, “-level 6 32” reports faults from the top level down for a total of six
levels, but shows only those hierarchical blocks that had 32 faults or more. When the -level and
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-all options are specified with an instance, the depth can be calculated based on the specified
instance.
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Note: The faults associated with top level inputs, outputs, and bidirectional ports are not considered
as "under" the top level of hierarchical and are not included in the counts of the hierarchical report.
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Those faults will be included in the top_module level.

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Isolate the Impact of the AU Faults
TEST-T> report_faults -class au -level {3 256}
------- ------- -----------------------
5427 93.60% / (top_module)
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TEST-T> report_faults -class au -level {4 256}
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------- ------- -----------------------
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5427 93.60% / (top_module)
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448 83.73% /I_ORCA_TOP/I_RISC_CORE/I_REG_FILE (REG_FILE_ram)
914 11.61% /I_ORCA_TOP/I_RISC_CORE/I_DATA_PATH (DATA_PATH)
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3705 0.05% /I_ORCA_TOP/I_RISC_CORE/I_ALU (ALU)
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By combining the -level option and -class option to the report faults command specific
classes of faults can be reported by hierarchy.
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This example shows the density of AU faults by hierarchy side-by-side with the test coverage by
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Running Analysis of AU Faults
TEST-T> analyze_faults -class au
Fault analysis summary: #analyzed=4190, #unexplained=369.
952 faults are untestable due to constrain values.
2465 faults are untestable due to constrain value blockage.
58 faults are connected to CLKPO.
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16 faults are connected to SHADOW.
17 faults are connected to TIEX.
Note: a fault may belong to
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6 faults are connected to TLA.
multiple analysis categories
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287 faults are connected to RAM_ADR.
2232 faults are connected to RAM_DATA.
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139 faults are connected to RAM_WRITE.
8 faults are connected to RAM_READ.
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89 faults are connected to CLOCK.
9 faults are connected to SET.
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11 faults are connected to RESET.
4 faults are connected to TS_ENABLE.
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244 faults are connected from CLOCK.
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1 faults are connected from TLA.
392 faults are connected from TIEX. 4- 32
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The analyze_faults command can produce a summary of faults assigned to that class and
possible reasons why the faults were placed in that class.
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The vast majority of AU faults are due to constrain values, constrain value blockages and
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connections to memory data paths.

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Report More Details of AU Faults
TEST-T> analyze_faults -class AU –verbose –max 10
sa1 AN I_CLOCK_GEN/I_PLL_SD/clk_4x
. . .
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sa1 AN I_CLOCK_GEN/U19/S
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sa0 AN I_CLOCK_GEN/U16/S0
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. . .
sa0 AN I_ORCA_TOP/I_BLENDER/latched_clk_en_reg/Q
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. . .
130 faults are connected from TIEX.
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sa1 AN I_CLOCK_GEN/U15/S
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sa1 AN I_CLOCK_GEN/U15/D0
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sa0 AN I_CLOCK_GEN/U15/D0
. . .
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The -verbose option of the analyze_faults command will produce a detailed report of
reasons why the faults were placed in that class.
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See the TetraMAX online Help FAQ on “Understanding Reported Data”, analyze_faults for
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more information.
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Fault Analysis Source Points
TEST-T> analyze_faults -class AN -source_points 5 0
14 faults are connected from TLA.
10 faults are connected from TIEX. Total of 122 points
Blockage Points - Total 122: explained AN faults
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------------------------------------------
o_dout[7] 14.04%
due to blockages
o_dout[6] 14.04%
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o_dout[5] 14.04%
o_dout[4] 14.04%
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o_dout[3] 14.04% Only 8 points met
o_dout[2] 14.04%
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o_dout[1] 14.04% threshold of 5% of
o_dout[0] 14.04% explained faults
Blockage Value Source Points - Total 1:
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------------------------------------------
i_test_se 20.48%
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Constraint Value Source Points - Total 6:
------------------------------------------
test_mode1 7.92%
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SNPS_PipeHead_test_si7_1 5.73%
SNPS_PipeHead_test_si2_1 5.02%
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TEST-T>
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-source_points min_percent max_points
Prints a list of blockage points, blockage value source points, and constraint value source points
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based on the order of their effect on explained faults. The parameters for this option control the
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length of the report. The min_percent parameter is the minimum percentage of explained faults for
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the point to be reported. The max_points parameter is the maximum number of points to list in each
category; 0 specifies that there is no limit. This option must be used with the -class option. The fault
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classes are supported: Undetectable (UD) and ATPG Untestable (AU), and any of their subclasses.
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Analyze a Particular AU Fault
AU Due to Constrained Values
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The –display option will
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show the fault analysis
results in the GSV
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Source of
constraint
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~01 means “can’t be controlled to a 0 or a 1”
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See the TetraMAX online Help FAQ “Understanding Schematic Data” for more information.
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analyze_faults –display drew the highlighted MUX and path back to test_mode PI.
The net connection diamond on the MUX D0 input can be clicked on to display the clk pin driven
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by the TIEX (TX) primitive.

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TIEX’s come from:

Black box modules
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Modules with undriven, unconnected outputs

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Analyze a Particular AU Fault
AU Due To Constrain Value Blockage
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Source of Blockage
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blockage point
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Note: pindata is set to “constrain_value”.
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See TetraMAX Online help “Understanding Schematic Data” for details:

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Examples:
a) X/-,X/-,X/- b) 0/-,0/B,0/- c) X/-,1/B,1/- d) X/-,~01/B,~01/B
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Example A "X/-,X/-,X/-" indicates no constraints and no blocks.

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Example B "0/-,0/B,0/-" indicates the pin is constrained to 0 due to tied logic, there is also a
constraint of 0 during combinational ATPG which contributes to a blockage. During sequential scan
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ATPG there is a constraint to 0 but no corresponding blockage.

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Example C "X/-,1/B,1/-" indicates a constraint to 1 for both combinational and sequential scan
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ATPG, but a blockage due to that constraint only for combinational ATPG.
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Hierarchy Browser
 Displays a design’s basic hierarchy

 Enables graphical analysis of coverage
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 Launched as a stand-alone window
Supplements the GSV by enabling
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
graphical analysis of test coverage and
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fault information while browsing the
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design’s hierarchy
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TetraMAX Workshop
Tips for Improving Test Coverage
 Without design changes

 Increase abort limit
 Enable Fast-Sequential and Full-Sequential ATPG
Create TetraMAX memory models
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
More effort
 See if some PI constraints can be eliminated
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 Example: PI constraint on an async reset will result in reduced coverage
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 With design changes
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 Fix DRC violations
 Many DRC violations have some impact on coverage
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 Add scan to non-scan cells
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 Use set_scan_ability for what-if analysis
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 Add test points
Analyze test points with run_testpoint_analysis
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
Use run_atpg –observe_file <file> for what-if analysis 4- 38


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TetraMAX can perform analysis of where might be good locations for test points to improve
coverage. Use the run_testpoint_analysis command. Refer to the appendix of this unit
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for more details.

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TetraMAX Workshop
Functional Pattern Fault Simulation
 Another potential method for improving Test Coverage is to fault

simulate functional patterns targeting faults not detected by ATPG
 Supported by TetraMAX or by Z01X (Synopsys fault simulation tool)
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 Features of Z01X:
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 Optimized concurrent fault simulator (150M+ primitives)
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 RTL & gate level fault simulation
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 Verilog (1995, 2001 & 2005) and SystemVerilog (partial) support
Stuck-At, Transition Delay, Bridge, IDDQ & transient (soft error) faults models
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
 STIL, WGL, VCD & Verilog testbench stimulus
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 Advanced fault classification (28 classes) & reporting
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 Import and export of ATPG fault lists
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Note: Z01X is a separate tool from TetraMAX and requires a separate license.
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Script Example for Functional Pattern fault simulation in TetraMAX:

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# Run ATPG first

run_build_model top_mod_name
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run_drc atpg_related.spf
set_faults –persistent_fault_models
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add_faults -all
run_atpg -auto
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write_patterns pat.bin -f binary -rep

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write_faults atpg.flt -all -rep

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# After ATPG, go back to DRC mode for fault sim flow

drc -force
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remove_pi_constraints -all
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remove_clocks -all
set_drc -nofile
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test
set_patterns -external –strobe_period {20 ns}... my_asic.evcd
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TetraMAX Workshop
Want to Quickly Return Post-ATPG?
 First Session:
DRC-T> run_drc DUT.spf
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TEST-T> add_faults –all
TEST-T> run_atpg -auto
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TEST-T> write_image pass1.image.gz \
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–compress gzip –replace -violations
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TEST-T> write_faults faults.all -all -replace
TEST-T> write_patterns pats.bin –format bin –replace
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 A Later Session:
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TEST-T> read_faults faults.all
TEST-T> set_patterns –external pats.bin
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An image file can be password protected and it’s net name and instances can be “garbled” for extra
security. Furthermore, the user can control which commands can be executed when an image file is
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read. Image files are covered in more detail in the Diagnosis unit.
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Interrupting a Long Process
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 When there is the need to abort the current command and any pending
output is not desired
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 The “Discard” button will only be visible in the GUI after a user interrupt
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is detected (by “Stop” button or “ESC” key)
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 When the original command output is discarded/flushed, the “Discard”
button will be hidden
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The Stop button will always be enabled and operational as long as the kernel is still processing the
current command.
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TetraMAX Workshop
Running ATPG
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Post-ATPG Analysis
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TetraMAX II
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TetraMAX Workshop
TetraMAX II
 TetraMAX II is the Synopsys next generation

ATPG tool that includes support for
multithreading DFTMAX
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PrimeTime
 Multithreading allows for more efficient TetraMAX II ATPG
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memory usage across multiple threads 10X Faster - 25% Fewer Patterns
when compared to “multi-processor” (3x
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StarRC
VCS
reduction on average) Pattern Silicon Fine-grain
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Generation Diagnosis Multithreading
More efficient memory usage allows more
HSPICE

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threads to be used by ATPG which will
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improve runtime (10x faster on average) Yield Explorer
Includes new ATPG algorithms to reduce
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
pessimism and decrease pattern count (25%
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pattern reduction on average) 4- 43
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Running TetraMAX II requires an additional add-on license
There are separate licensing options to support 8 threads per license or 20 threads per license
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TetraMAX Workshop
Running TetraMAX II
 New exec in $SYNOPSYS/bin/

tmax2
When TetraMAX II is launched, the default setting will use 8 threads
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
 report_settings atpg shows num_threads=8
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 report_settings simulation shows num_threads=8
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 Threaded ATPG can not be used after invoking tmax
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 Non-threaded ATPG can be used after invoking tmax2
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 Just set_atpg –num_threads 0 and set_simulation –num_threads 0
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TetraMAX Workshop
TetraMAX II Specific Command Options
 Two new command options for TetraMAX II

set_atpg –num_threads <N>
set_simulation –num_threads <N>
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 Always set both to same number
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 Default is 8
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 Set to 0 to disable threading
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 Multicore options have no effect when N > 0
 These are used if execution switches to non-threaded ATPG or simulation
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set_atpg –num_processes <P>
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set_simulation –num_processes <P>
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TetraMAX Workshop
When is Threading Used With TetraMAX II
 Commands using threading

run_atpg
run_simulation
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run_fault_sim
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run_diagnosis (good-machine simulation portion only)
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report_power (simulation portion only)
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write_patterns (dual STIL/parallel patterns for simulation)
 All other commands behave identically whether threading is used or not
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Messages when first command using threading is run
Parallel simulation data created for 16 threads
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#TLA_input_gates=2312 #levels=1 CPU_time=0.00 sec.

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Parallel simulation data created for 16 threads

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#internal_gates=1876366 #levels=6 CPU_time=1.02 sec.

Message when run_atpg starts using threads
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ATPG will be performed on 16 threads using words of size 64

#collapsed_faults=3100/5730.
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Note: When chain test is enabled, this is not printed until after chain test generation
Message when run_simulation or run_fault_sim starts using threads
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Simulation will be performed on 16 threads using words of size

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64.
Fault simulation will be performed on 16 threads using words of
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size 64.
To confirm: search for the word threads
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TetraMAX Workshop
TetraMAX II Messages: Ignored Settings
 The TetraMAX II ATPG doesn’t make use of all set_atpg settings

 Settings ignored by threaded ATPG are flagged by M724 messages
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 The M733 message will confirm that threaded ATPG is being used
Example
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
TEST-T> run_atpg -auto
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The following settings are ignored for threaded ATPG. (M724)
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set_atpg -decision random
set_atpg -lete_fastseq
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set_atpg -fast_min_detects_per_pattern 17 40
Starting threaded ATPG with 8 threads. (M733)
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 See the “TetraMAX II Command Option Support” section of the OLH for
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details
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TetraMAX Workshop
TetraMAX II Simulation
 TetraMAX generates patterns that can be simulated or fault simulated

with TetraMAX II
 TetraMAX II threaded simulation is better at resolving to non-X values
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 TetraMAX II threaded ATPG patterns should not be simulated
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(run_simulation) or fault simulated (run_fault_sim) with non-
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threaded simulation
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 Non-threaded run_simulation may give got=X mismatches
 run_fault_sim may lead to Possibly Detected (NP) credit for Detected (DS) faults
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TetraMAX Workshop
Other Behavior Differences with TetraMAX II
 TetraMAX II generates the chain test using non-threaded ATPG
 TetraMAX II ATPG (run_atpg –auto) does not generate Parallel Strobe
Data (PSD) file
Use run_simulation to generate PSD file after final pattern set
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
 TetraMAX adds a dummy cycle to system-clock launch transition
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patterns allow slow primary inputs to settle
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 Can be disabled by set_delay –noextra_force
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 TetraMAX II never adds a dummy cycle for slow primary inputs
Instead use write_patterns –use_delay_capture_start N
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
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 TetraMAX II may generate 2-cycle patterns for Stuck-At faults by default
 This can happen even with set_atpg –capture_cycles 0
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 To prevent 2-cycle pattern generation in TetraMAX II
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set_atpg –noextra_cycle 4- 49
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TetraMAX Workshop
TetraMAX II Limitations
 TetraMAX II has some feature limitations

 In most cases, when there is a limitation, ATPG will automatically revert
to a non-threaded run and will flag with M729 messages
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 The M733 message will confirm the switch to non-threaded - Example
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run_atpg -auto
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Warning: The following setting requires single-process/multi-core ATPG. (M729)
set_delay -launch_cycle last_shift
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Warning: Feature "fault model" requires single-process/multi-core ATPG. (M729)
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Starting single-process ATPG. (M733)
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 If num_processes > 0 the M733 message reflects that as well
Starting parallel ATPG with 4 processes. (M733)
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TetraMAX Workshop

 Describe when and how to use -abort limit
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 Describe when and how to use -capture_cycles
Debug Low Fault Coverage
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
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 Name some differences between TetraMAX and
TetraMAX II
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Begin Lab 4: Controlling ATPG
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TetraMAX Workshop
Command Summary
add_faults -all Create faults on every location not "nofaulted"
add_nofaults Exclude certain faults from the fault list
analyze_faults -class AU Attempt to explain why AU faults are AUs
analyze_faults -display Analyze a fault through the GSV
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remove_faults -retain 5 Remove 95% of the faults from the fault list
report_faults -all -level {3 256} Report fault statistics hierarchically
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report_faults –class AU -lev {3 256} Report only AU faults hierarchically
run_atpg basic_scan_only Run only the Basic-Scan ATPG engine
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run_atpg fast_sequential_only Run only the Fast-Sequential ATPG engine
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run_atpg full_sequential_only Run only the Full-Sequential ATPG engine
set_atpg -abort 100 Increase Basic and Fast-Sequential ATPG effort
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set_atpg -capture_cycles 4 Enable Fast-Sequential ATPG with a depth of 4
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set_atpg -coverage 98 Stop ATPG if test coverage reaches 98%
set_atpg -full_seq_atpg Enable the Full-Sequential Engine
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set_atpg -full_seq_abort_limit 100 Give Full-Sequential ATPG more time for NDs
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set_atpg -patterns 1000 Limit the total number of ATPG patterns to 1,000
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TetraMAX Workshop
Appendix
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Test Point Analysis
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TetraMAX Workshop
Test Point Analysis
 TetraMAX can analyze the design and suggest possible locations for
Test Points
 The analysis can be focused on adding Test Points to improve
ng
Testability, reduce pattern count, or target specific fault classes
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 The TetraMAX command that performs the Test Point analysis is
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analyze_test_points
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analyze_test_points -target <testability | pattern_reduction | fault_class>
-test_points_file <file_name>
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[-max_control_points <n>] [-max_observe_points <n>]
[-num_observe_points_per_scan_cell <n>]
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[-class <list_of_fault_classes)]
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[-exclude <list_of_instance_names>] [-replace]
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Note: the analyze_test_points command requires a DFTMAX license
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TetraMAX Workshop
Options: analyze_test_points (1/3)
 -target <testability | pattern_reduction | fault_class>

 testability
 Improves Test Coverage with control and observe points
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 Uses random patterns for iterative static analysis
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 Does not require prior ATPG
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 pattern_reduction
Targets reduced pattern size with observe points
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
 Uses SCOAP numbers for static analysis
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 Does not require prior ATPG
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 fault_class
 Improves Test Coverage with observe points for fault classes
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 Uses fault cone topology for dynamic analysis
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 Requires initial ATPG for analysis of fault cones
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SCOAP: Sandia Controllability and Observabilty Analysis Program
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TetraMAX Workshop
 -test_points_file <file_name>
 Specifies the name of the output file containing the list of test points
-max_control_points <number>
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
 Specifies the maximum number of control points selected in the design (default is
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1000)
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 -max_observe_points <number>
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 Specifies the maximum number of observe points selected in the design (default
is 1000)
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 -num_observe_points_per_scan_cell <number>
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 Number of observe points XOR’ed to a scan cell or PO (default is 8)
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Note: -max_control_points only support with –target testability
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TetraMAX Workshop
 -class:
 Default is to analyze all undetected faults
 User can choose to target specific fault sub-classes
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 Detected (DS, DI, TP, DR)
 Possibly detected (AP, NP)
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 Undetectable (UU, UO, UT, UB, UR)
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 ATPG untestable (AN, AX)
 Not detected (NC, NO)
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 Can specify multiple sub-classes, i.e. –class {NO AN}
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 -exclude <list_of_instances>
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 Instances to avoid placing a test point
 TCL syntax: –exclude {inst_xx inst_yy}
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 -replace
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 Replaces an existing output file
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Major fault classes not supported for –class:
DT, PT, UD, AU, ND
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Note: -class only supported when –target fault_class is used

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Note: -exclude only supported when –target fault_class is used

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Test Point Analysis Flow
 Run analysis after ATPG, otherwise there will be a huge number of

ND faults resulting in very long run-times
 Rerun ATPG with the test point file to get an estimate of the
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resulting coverage
run_build_model
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run_drc
add_faults –all
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run_atpg –auto
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analyze_test_points <options>
run_atpg –auto –observe_file <test_point_file>
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 Fine tune the test point list as needed by running analysis before
going to DFT Compiler for insertion
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 The test point file is sourced in DFT Compiler prior to insert_dft
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Actual TMAX test point file:
set_test_point { CHIP_CORE_1/DM_1/dm_inface_1/U706/Z } -type observe
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User modified for DFT Compiler:

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set_test_point_element { CHIP_CORE_1/DM_1/dm_inface_1/U706/Z } -type observe -clock TEST_CLOCK

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If –clock option not used, a new clock pin name tpclk would be inserted
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Limitations:
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• Only observe test points are currently supported

• run_testpoint_analysis will run on LSSD designs but DFT Compiler doesn’t support
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automated test point insertion on LSSD designs

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Agenda
DAY
2
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Minimizing ATPG Patterns ©2018 Synopsys, Inc. All Rights Reserved. 5-1
TetraMAX Workshop
Unit Objectives
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 List 3 methods for reducing test program size
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 Describe example design topologies which create parallel or
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disturbed dynamic clock grouping
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 Run ATPG on DFTMAX compressed designs
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TetraMAX Workshop
Benefits of Compact Vector Sets
Cost (¢) Manufacture

0.01
0.0001
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Test
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0.00001
1991 1994 1997 2000 2003 2006 2009 2012
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Year
cost = $ $ $ $
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10001010111000101
cost = $
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10001010111000101

00001000101011101
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11111000101011101 11111000101011101
10001010101011101
11001100101011101
vs. 10001010101011101
11001100101011101
10111000101011101 10111000101011101
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01110100101011101 01110100101011101
11001100101011101 11001100101011101
11001100101011101 ...
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11001100101011101
...
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Most ASIC Vendors charge for “extra” tester time and/or vector set sizes.
The larger the vector sets, the longer the tester time, and the more expensive the ASIC Production
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tests will be.

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TetraMAX Workshop
What is Dynamic Pattern Compression?
Conceptual View of ATPG with Dynamic Pattern Compression
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Original Merged
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1 1 0 0 - - 1 1 0 0 1 0 1
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2 0 - 1 1 - - 0 - 1 1 - -
3 - 0 0 - 0 1
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4 1 - 0 1 0 -
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5 1 - 0 - 1 - 1 1 0 - 1 0
6 - 1 0 - 1 0
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0/1: Care Bits
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“-”: Don’t Care
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Note that the example above is only a partial description of how TetraMAX merges patterns.
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Pattern merging - also known as dynamic pattern compression - is being performed during ATPG.
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Pattern merging takes advantage of don’t-care values. Dynamic pattern merging is controlled with
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the setting of the set_atpg -merge command option prior to generating patterns.
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Be aware that ATPG runtime may increase when the merging defaults are increased during
run_atpg -auto. Using a high merge effort is only recommended for generating final test
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patterns, and only if it is really necessary.

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When merge is on, for each new fault detected an attempt is made to modify an existing pattern to
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also detect this fault and still detect previous faults. If successful, no new pattern is needed. If not
successful another fault is tried until the merge effort limit is reached. Once the limit is reached a
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new pattern is added for the fault detection that could not be merged with existing patterns.
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TetraMAX Workshop
Controlling Dynamic Pattern Compression
 A default -merge setting of {high high} is used by Basic-Scan and Fast-

Sequential ATPG during run_atpg –auto
 There is individual control for each of the ATPG engines:
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 Basic-Scan & Fast-Sequential
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set_atpg -merge <low|medium|high|<d>> [<low|medium|high|<d>>]
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 Full-Sequential
set_atpg –full_seq_merge <low|medium|high|<d>>
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 Use set_atpg -verbose reporting to get details of how effective merge
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settings are on your design
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 If the #failed_merges continually hits the limit, try raising limits (gradually); the
tradeoff is increased run time
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The arguments indicate how much effort to spend doing merging. The default is off (0), which
means no merging is performed. Unless a value for this option is specified or the run_atpg -
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auto command is being used, no merging will occur and there is no verbose output to report.
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The first value sets normal ATPG secondary test generation merge effort The second value sets the
merge effort for multiple fault sensitization, which occurs when –auto is used. The labels low,
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medium, and high are accepted for both, as well as an integer value. The first group of labels have
corresponding numeric values of low=20, medium=100, and high=500. The second group of labels
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have corresponding numeric values of low=200, medium=1000, and high=5000.

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Integer values <d> can also be specified for the merge effort:
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set_atpg -merge {1250 2000}

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TetraMAX Workshop
Minimum Detects ATPG Option
 To avoid creating patterns that fail to detect a minimum number of

collapsed faults
 Only works when –merge option is also enabled
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 Separate option for each ATPG engine:
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set_atpg -basic_min_detects_per_pattern <d1> [d2]
set_atpg -fast_min_detects_per_pattern <d1> [d2]
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set_atpg -full_min_detects_per_pattern <d1> [d2]
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Where:
<d1> = Minimum num of faults detected/pattern
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[d2] = Number of consecutive rejected patterns (optional)
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Examples:
set_atpg –basic_min_detects_per_pattern [list 5 10]
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set_atpg –fast_min_detects_per_pattern {10 20}
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This option may be set at any time prior to running ATPG; the default is 0 (not used). The second d
parameter specifies to terminate Basic-Scan ATPG when the number of consecutive rejected
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patterns due to failure to achieve minimum detections reaches the value specified. The default value
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for this parameter is 40.

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-basic_min_detects: Basic-Scan ATPG

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-fast_min_detects: Fast-Sequential ATPG

-full_min_detects: Full-Sequential ATPG
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Avoiding Patterns that Detect Too Few Faults

-----------------------------------------------
-----------------------------------------------
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#fast_sequential patterns 248
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-----------------------------------------------
reset_state
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set_atpg –basic_min_det 10 –fast_min_det 10
run_atpg - auto
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test coverage 98.21% -1.04% drop in
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----------------------------------------------- test coverage
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-----------------------------------------------
In about 1/3rd the
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#basic_scan patterns 101 number of Basic
#fast_sequential patterns 62 and Fast Seq
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patterns! 5- 7
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For more information on the commands that control minimum detects per patterns reference:
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SolvNet Article: 000939 – Using TetraMAX’s Minimum Detects per Pattern Options To
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Reduce Vector Count

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Using run_atpg -optimize_patterns
 Produces a very compact set of patterns with high test coverage with a
single run_atpg command
 TetraMAX dynamically adjusts the internal algorithms to generate a
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compact pattern set
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 All manually specified set_atpg settings, such as abort limits,
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minimum detects, and merge limits are ignored during this operation
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 The -optimize_patterns option is useful for a final TetraMAX ATPG
run where the goal is to optimize the pattern count at the expense of
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added run-time
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 Only supports Basic-Scan and Two-Clock optimized ATPG engines
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Note the following limitations when using the -optimize_patterns option:
• Multiple run_atpg commands are supported, but pattern optimization can only be specified
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once.
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• A learned recipe is not saved.

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• Fast-Sequential and Full-Sequential ATPG modes are not supported.

• Be aware that unlike the run_atpg -auto_compression command, specifying set_atpg -
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capture_cycle number will not enable Fast-Sequential ATPG during the pattern optimization
process. To run Fast-Sequential top-off ATPG, it must be done as an extra step. For example:
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run_atpg –optimize_patterns
set_atpg –capture 4
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run_atpg -auto fast_sequential

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• Only Stuck-At and Transition fault models are supported.

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TetraMAX Workshop
Dynamic Clock Grouping
 The clocks pulsed for a given vector are selected dynamically during
pattern generation:
 Maximizing the fault detection
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 Minimizing the pattern count
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 Dynamic clocking schemes:
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 Parallel
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 Disturbed
 Clock grouping allows multiple clock domains to be pulsed in
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simultaneously during the capture window
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 Dynamic clock grouping is enabled by default
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It is possible to pulse several clocks in the same vector, thus observing more logic and reducing the
need for additional patterns. Given two clocks independent from one another (when one clock is
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pulsed, no logic driven by the other clock is affected), then two patterns would be required to
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exercise the logic in the two clock domains. However, since the clocks are independent, they could
be safely pulsed together, thereby saving one test pattern.
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Dynamic Clock Grouping: Parallel
No data paths between the
Clock CLK1 and CLK2 clock domains
Domain
1 skew
CLK1
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CLK1
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Clock
Domain CLK2
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2
CLK2
t t
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B A
 Parallel clock pairs are clocks that can be pulsed in the same tester cycle
without any sequential effects
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set_drc -clock –dynamic (Enabled by default)
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 More flexible and gives better results than static clock grouping
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 TetraMAX decides on a pattern-by-pattern basis whether to pulse a clock
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With dynamic clock grouping enabled during DRC and clock domains CLK1 and CLK2 identified
as parallel, Basic-Scan ATPG can pulse CLK1 and CLK2 simultaneously during the same capture
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cycle.
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Skew is the difference between the capture clock edges of flip-flops from two different clock
domains. The test protocol timing or add_clocks command defines clock edges.
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Skew does not matter when clock domains share no paths. Skew DOES matter when the clock
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domains do share paths. TetraMAX uses the setting for skew defined by the following command
set_drc –skew <d> (default is 1)
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When the design has two state elements, A and B, with the output of A connected to the input of B,
and each element is clocked by a different clock, and those clocks have nearly identical timing, then
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the two clocks have a parallel grouping relationship only if the capture edge of clock B occurs at or
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before the capture edge of clock A minus the skew value. Otherwise, the clocks are ungrouped, or
have a disturbed grouping.
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To disable parallel clock grouping:

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set_drc –clock -any
For static parallel clock grouping

To group some clocks manually, use the add pi equivalences command. Once a static clock group
is defined, any clock belonging to that group cannot be pulsed alone.
TetraMAX Workshop
Dynamic Clock Group: Disturbed
Data paths between the CLK1 and CLK2
clock domains going in both directions
skew
CLK1
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CLK2
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t t
B A
 Disturbed clocks pairs are clocks that can be pulsed in the same tester
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cycle with a limited amount of sequential effects
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set_drc [-disturb_clock_grouping | -nodisturb_clock_grouping]
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 Disturbed cells are masked during ATPG. Disturbed clock grouping results
in fewer patterns but can leave some faults undetected due to masks
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 To recover coverage loss due to masks, run ATPG again without disturb clock grouping
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run_atpg –nodisturb_clock_grouping
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With clock grouping disabled, Basic-Scan ATPG must pulse CLK1 and CLK2 in separate capture
cycles with a load_unload in between the two patterns.
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With dynamic clock grouping enabled and clock domains CLK1 and CLK2 identified as
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disturbed, Basic- Scan ATPG can pulse CLK2 and CLK1 in the same capture cycle masking
cells disturbed by sequential behavior.
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Dynamic and disturbed clock grouping is supported for the Basic-Scan and Fast-Sequential engines
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only.
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Pattern generation does not consider masked cells:

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•Masks enforced during simulation

•Target fault can become undetected, no vector will be further attempted to detect this fault
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•Performing a separate ATPG run without disturb clock grouping may be able to detect
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those faults that were left undetected due to masks

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Analyze Clock Grouping and Disturbances
TEST-T> report_clocks –matrix
id# clock_name type 0 1 2 3
--- ---------------- ---- --- --- --- ---
0 pclk CW --- -D- -D- ---
1 sys_clk CW -D- --- -D- ---
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2 sdr_clk CW -P- -P- --- -D-
3 prst_n SR --- --- -D- ---
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------------------------------------------------
clock 1 clock 2
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id# #masks #cells id# #masks #cells masked gates
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--- ------ ------ --- ------ ------ --------------
0 25 1074 1 25 722 29284 ...
0 5 1074 2 7 1132 29392 ...
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1 38 722 2 47 1132 31063 ...
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2 99 1132 3 78 1301 31062 ...
Clock ID 1 (sys_clk) has 722 flops of which 38 are disturbed when
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
grouped with Clock ID 2 (sdr_clk)
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 sdr_clk has 1132 flops of which sys_clk disturbs 47 5- 12
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Note that report_clocks –matrix is supported only in TEST mode.
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-matrix
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Displays the dynamic clock pair group ability in table form where each row indicates the potential
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grouping relationship of a candidate clock with each of the other candidate clocks.
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The type indicates the current clock type. The clock type may be any combination of C (flip-flops),
W (RAM write control), S (set), or R (reset).
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If two clock have a parallel relationship, then there will be a “P” in the second character of the
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matrix, i.e., “-P-”.

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If there is a disturb relation between two clocks, then “-D-” is seen in the matrix. These are disturb
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clock pairs.
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Dashes “---” in the matrix means that the pair of clocks did not meet the criteria for a disturb
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relationship.
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TetraMAX Workshop
Clock Grouping for Each Pattern
TEST-T> report_patterns –all –type

Patn Pattern Cycle Load Observe Clocks
num type count count proc used
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----- ------------ ----- ----- ------- ------
0 basic_scan 1/0 1 - -
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. . .
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33 basic_scan 1/1 1 - pclk,sdr_clk
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34 basic_scan 1/1 1 - pclk,sys_clk,sdr_clk
35 basic_scan 1/1 1 - sys_clk,sdr_clk
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36 basic_scan 1/1 1 - sys_clk
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38 basic_scan 1/1 1 - sys_clk,sdr_clk
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Patn num:
Indicates the pattern number. Pattern numbers start with zero.
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Pattern type:
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Indicates the type of pattern. Basic-Scan is a combinational pattern using one scan
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load, one capture clock (optional), and one scan unload. Fast-Sequential can use up to 10 scan loads
and 10 captures. Basic_scan(COM) indicates a "Clock On Measure" is being performed. A clock is
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being held on and the primary outputs are being measured during the clocks on time. A type of
sequential is also possible when the pattern source is external functional patterns.
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Cycle count:
The cycle count reports two numbers: N1/N2. The N1 is the number of capture
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procedures, or in other words the number of force/measure pairs. This corresponds to the number of
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tester cycles that will be used by the pattern. The N2 is the number of these capture procedures that
contain a clock pulse. Since not every force/measure pair needs to be accompanied by a clock
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pulse, N2 will always be less than or equal to N1.

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Load count:
Indicates the number of scan loads used by the pattern.
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Observe proc:
If a master observe or shadow observe procedure is used, the type is indicated here.
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Clocks used:
Indicates the active clock used by the pattern. If more than one clock is listed the
order matches the order used by the pattern.
TetraMAX Workshop
Adding Fault Models Increases Test Cost
Tester Memory Limit

Above 130nm SA
Stuck-At (SA)
~4-6X Test Time & Test Data
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130nm & Below Transition Delay Test Bridging
(High Cost) SA BridgingTest
Test
Slack-Based Delay Test
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130nm & Below
With Compression
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(Low Cost)
Tester Cycles
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Test budget fixed, yet
must not compromise on product quality
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Test Pattern Compression Needed!
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With legacy process nodes, designers generally use Stuck-At tests and some Transition Delay
testing up to the memory limits of their tester.
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At smaller process nodes, Transition delay, Slack-Based Transition Delay, and Bridging tests
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become critical. The Transition Delay tests can replace some of our stuck-at tests, but tester
memory is usually far exceeded.
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By adding compression, we can maintain the quality of our tests and avoid any cost of upgrading
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our tester configuration

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How Compression Works
 Traditional scan chains are split into shorter chains

 Shorter chains require less time to load and less data to be loaded on
tester
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Traditional Scan Scan Compression
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…
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One Scan chain for each Multiple Scan chains share
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scan-in/scan-out pin same scan-in/scan-out pins
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Test Compression Concepts
 Test Application Time Reduction (TATR)

 Used to reduce tester execution cost
Regular Scan Patterns x Regular Chain Length
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TATR =
Compressed Patterns x Compressed Chain Length
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 Test Data Volume Reduction (TDVR)
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 Used to ensure test program resides within tester memory
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 Avoids time-consuming reloads
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 Used if adding more patterns to increase test quality
Regular Scan Patterns x Regular Pin Data
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TDVR =
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Compressed Patterns x Compressed Pin Data
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DFTMAX TATR:
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TATR =
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DFTMAX Patterns x DFTMAX Chain Length

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DFTMAX Ultra TATR:

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TATR =
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Ultra Patterns x (Lengthinternal + Lengthcontrol + 1)

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Test Cycle Savings
1000 100 40 internal chains

flops flops
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4 chains 4 chains
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Test Application Time = Patterns x ScanLength
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Example: Example:
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 2,000 patterns  2,400 patterns
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 1,000 cycles to load a pattern  100 cycles to load a pattern
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= > 2000 * 1000 = 2,000,000 cycles = > 2400 * 100 = 240,000 cycles
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TATR = 2000000 / 240000 = 8.33 X
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How does this compression work?
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We know from scan that Test Application Time is equal to the number of patterns times the length
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of the longest scan chain. With DFTMAX, we are shrinking the length of that longest chain.
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For scan, Test Data Volume is proportional to the longest chain times the number of pins we use to
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push the data through. Of course we then multiply by the number of patterns, but lets say that for
Adaptive Scan, the pattern count is the same. Again, since the scan chain length is shorter in
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Adaptive Scan, but the pin count is identical, we get a lower Test Data Volume.
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Test Modes Created During Insertion
 Internal Scan Mode

 Re-configures the chip to look like traditional scan
dc_shell> write_test_protocol –out internalscan.spf \
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-test_mode Internal_scan
 Short compression chains are reconfigured into longer scan
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chains
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 Also called:
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 Reconfigured/regular/uncompressed scan mode
 Scan Compression Mode
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 Uses the shorter chains directly
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dc_shell> write_test_protocol –out scancompression.spf \
-test_mode ScanCompression_mode
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 Also called:
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Passing Compression Information to TetraMAX
 All the information TetraMAX needs to know about the compression

architecture is in the compression mode protocol file (SPF)
 The protocol is generated by DFT Compiler during DFT insertion, and
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can be written out as follows:
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write_test_protocol -out scancompress.spf \
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-test_mode ScanCompression_mode
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 The ATPG flow in TetraMAX for DFTMAX is the same as for regular scan
 Both DFTMAX and regular scan designs use the same fault diagnosis
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flow in TetraMAX
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ATPG – Scan Compression Flow
 Simply read in the DFTMAX scan netlist and run_drc with the
ScanCompression_mode STIL protocol file:
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read_netlist libs/tmax_libs/*.v
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read_netlist design_w_compression.v
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run_build top
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run_drc scancompress.spf
add_faults –all
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run_atpg –auto
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write_patterns pat_compression.stil -format stil
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Explore Compression in TetraMAX
 Use analyze_compressors to do ‘what-if’ analysis of different

compression architectures
analyze_compressors
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-num_chains <d>
-num_inputs <d>
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-num_scanouts <d>
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[-xtolerance <default | high>
[-nodiag]
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[-verbose]
Run on any standard scan design after passing DRC
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
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 Runs only Scan Compression mode ATPG
 Reports coverage, pattern count, and an estimate of compression and
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compressor area
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SolvNet Article: 017408 – Performing 'What If' Analysis for Inserting Adaptive Scan
Compression Logic
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-nodiag
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Specify this option to disable the requirement to generate a compressor with high precision
diagnosis. By default, the analyze compressors command generates a compressor with failure
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diagnosis; this requires a specific number of scan outputs for a given number of chains.
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Note: analyze_compressors does not support DFTMAX Ultra compression

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TetraMAX Workshop
Using analyze_compressors Example
Example:
run_build_model
run_drc SCAN.spf
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analyze_compressors –num_chains 96 \
-num_inputs 8 –num_scanouts 8
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Check pattern count and coverage
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
 Compare with scan mode pattern count and coverage
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-----------------------------------------------
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------------------------------ ---- ---------

Detected DT 73803
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Undetectable UD 3218
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Not detected ND 491
-----------------------------------------------
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total faults 78482

-----------------------------------------------
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-----------------------------------------------
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-----------------------------------------------
CPU Usage Summary Report
-----------------------------------------------
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Total CPU time 2.91

-----------------------------------------------
Warning: Internal pattern set is now deleted. (M133)
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Data reduction per pattern: 11.43X

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Cycle reduction per pattern: 18.34X

Compressors area overhead per internal chain: 9.2 equivalent two-input NAND
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gates
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TetraMAX Workshop
DFTMAX Ultra and ATPG
 TetraMAX supports both the regular DFTMAX

compression architecture as well as DFTMAX
Ultra
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DECOMPRESSOR
 DFTMAX Ultra is the latest scan compression
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architecture from Synopsys
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 The ATPG flow for regular DFTMAX and
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DFTMAX Ultra is the same
 There are some ATPG features that are unique
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to DFTMAX Ultra COMPRESSOR
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Some current limitations of DFTMAX Ultra in TetraMAX:
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- Full-Sequential ATPG is not supported (Path Delay must use Fast-Sequential)

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- The analyze_compressors command is not supported

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- The run_justification command is not supported

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Updating DFTMAX Ultra Patterns
 Use the command update_streaming_patterns to manipulate

DFTMAX Ultra ATPG patterns
 Controlling the peak and average power during shifting
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 Use -load_scan_in option
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 Increase the maximum shift length of patterns to allow top-level pattern set
merging
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 Use -max_shift option
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 Optimizing padding patterns
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 Use -remove_padding_patterns option
Add virtual pipeline stages to account for pipelines to be added at a higher level
ch

 Use -virtual_head_pipelines and -virtual_tail_pipelines options
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 Removing and reordering patterns
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 Use -remove and -insert options
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Note: virtual pipelines can also be accounted for when the patterns are originally generated by
ATPG by using the following command options:
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set_drc -virtual_head_pipelines <n>

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set_drc -virtual_tail_pipelines <n>

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VCS simulations of scan patterns will pass only if the correct number of pipelines are in the netlist.
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DFTMAX Ultra Padding Patterns
 DFTMAX Ultra inserts padding patterns as follows:

 Basic-Scan/2-Clock ATPG: after every 32 patterns
 Fast-Sequential ATPG: after every pattern
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 Padding patterns are automatically removed during write_patterns
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 Manual removal of padding patterns with update_streaming_patterns
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P0P1 P2.........P 32P33P34 P35......... P 65P 66……Plast
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update_streaming_patterns –remove_padding_patterns
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P0P1 P2.........P 32P33P34 P35......... P 65P 66…… Plast
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TetraMAX Workshop

 List 3 methods for reducing test program size
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 Describe example design topologies which create
parallel or disturbed dynamic clock grouping
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 Run ATPG on DFTMAX compressed designs
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Begin Lab 5: Minimizing ATPG Patterns
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TetraMAX Workshop
report_clocks -matrix Examine clock grouping opportunities

reset_state Removes generates patterns and resets fault list
set_atpg -basic_min_detects 50 Constrain minimum faults detected per Basic pattern
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set_atpg -fast_min_detects 10 Constrain minimum faults detected per Fast pattern
set_atpg -full_min_detects 5
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Constrain minimum faults detected per Full pattern
set_atpg -full_seq_merge value Enable Full-Sequential ATPG pattern compression
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set_atpg -merge [list high med] Enable Basic-Scan ATPG pattern compression
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set_atpg -merge [list high low] Enable Fast-Sequential ATPG pattern compression
set_drc -disturb_clock_grouping Allow disturbed clock grouping with Basic patterns
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set_drc -clock -dynamic Enable DRC to analyze clock grouping
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analyze_compressors Perform “what if” analysis on compression setups
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TetraMAX Workshop
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TetraMAX Workshop
Agenda
DAY
2
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Pattern Validation ©2018 Synopsys, Inc. All Rights Reserved. 6-1

TetraMAX Workshop
Unit Objectives

Explain the benefits of saving patterns in binary format
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
 Describe the minimal set of ATPG patterns that should be
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simulated with serial load_unload
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 Use two ways to translate a STIL pattern to a Verilog
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testbench with MAX Testbench
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 Describe 2 reasons why you might use the ATPG masking
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commands
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TetraMAX Workshop
BUILD
Mode
TEST
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Mode
Gate-level Read Run
Test Patterns
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Build Review
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Patterns
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DRC
Mode Incremental
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STIL Test Check
ATPG
Protocol DFT Rules
(If needed)
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TetraMAX Workshop
ATPG Pattern Validation: Agenda
Writing Patterns
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Pattern Validation
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Simulation Debug
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Dealing With ATE Failures
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TetraMAX Workshop
ASIC Vendor: Specific Considerations
 ASIC Vendor restrictions on patterns may require some non-default

settings during pattern generation or pattern writing to meet ASIC
Vendor requirements
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 Check with your vendor:
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 Documentation
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 Help desk
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 Check with Synopsys
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 Documentation
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 SolvNet
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TetraMAX Workshop
Options for Writing Patterns
 There are many options for saving
patterns:
 Pattern Source - normally this is the internal
pattern buffer but if external patterns have been
read, they can be written from the external buffer
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 Pattern Range - provides the ability to specify the
starting or stopping range to write (pattern
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numbering starts at zero)
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write_patterns <file> [-replace] [-first <d>] [-last <d>] [-split [n]]
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[-internal | -external] [-serial | -parallel [d]] [-compress <gzip|binary>]
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[-nocompaction] [–use_delay_capture_start <d>] [-use_delay_capture_end <d>]
[-format <binary | stil | wgl | wgl_flat ...>] [-unified_stil_flow]
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[-exclude <setup|repeat_setup|patterns|chain_test|atpg_patterns|all>] ...
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Available Formats:
STIL, WGL, WGL_Flat, STIL/99, TDL91, FTDL, TSTL2, Binary
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Split options creates multiple pattern files of “d” patterns each.

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TetraMAX Workshop
Unified STIL Flow vs. Dual STIL Flow
 Unified STIL Flow (USF) uses single STIL pattern for all targets
 Failing cell identification with parallel compressed simulations requires PSD
 Dual STIL Flow uses separate STIL patterns for serial/parallel
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 Can be used to get failing cell information of parallel compressed simulation but only
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if N-shifts is not required – only serial STIL pattern is appropriate for the ATE
Dual STIL Flow
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Unified STIL Flow (Default)
Different STIL Generate 1 STIL
TMAX TMAX
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One STIL file, constructs for Scan (serial) or 2,
supports all design types, Compression depending on
simulation modes, and the ATE
Serial STIL limited
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STIL Parallel STIL
limited to Par STIL Ser STIL to serial sim for
Scan Compression
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parallel sim for
MAXTB Scan MAXTB MAXTB
Compression Be sure to send
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TB Ser TB the right STIL to
Par TB
Parallel N-shift not the ATE
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VCS ATE supported for Scan
VCS ATE
Compression 6- 7
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To support failing cell identification with USF and parallel simulation of compressed patterns
requires a Parallel Strobe Data (PSD) file. We cover creating/using a PSD file later in this Unit.
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Note: Dual STIL Flow serial and parallel patterns are identical for un-compressed (regular scan)
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TetraMAX Workshop
General Guidelines for Saving Patterns
 Save patterns in binary format so they can be translated later

to different formats:
run_atpg . . .
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write_patterns –format binary . . .
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write_image run_img.gz . . .
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 Save patterns in appropriate format for simulation and for
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translation to ATE (USF by default):
write_patterns pats.stil –format stil -replace
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write_patterns pats.wgl –format wgl –replace
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Dual STIL patterns are written by specifying –nounified_stil_flow and –serial or –
parallel. For example:
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# Write Dual STIL parallel patterns

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write_patterns pats_par.stil –format stil –nounified_stil_flow –parallel

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# Write Dual STIL serial patterns

write_patterns pats_ser.stil –format stil –nounified_stil_flow –serial
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Note: If the pattern file name already exists, the –replace option will overwrite the existing file
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with the new pattern.

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TetraMAX Workshop
Scan Chain Test
 Do all your patterns fail on the ATE or mismatch in your simulator?

 If not all, do you have so many
failures on the ATE or so many
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mismatches in the simulator that
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you do not know where to begin?
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 Was Static Timing Analysis performed on your scan design in scan shift
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mode?
 Were best-case back-annotated delays or parasitics used to check for
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hold time problems?
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 Were worst-case delays used to check the shift speed?
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 Need to validate that scan shifting works!
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TetraMAX Workshop
Set Chain Test Bit Sequence before ATPG
set_atpg -chain_test <off|0011|0101|1000|0111|<string>>

off = do not generate
0011 = repeating pattern of 0011... DEFAULT
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0101 = repeating pattern of 01..
1000 = leading bit 1, rest 0, i.e. 1000000...000
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0111 = leading bit 0, rest 1's, i.e. 01111.…111
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string = user defined sequence of 1's and 0's with a
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final character of "C" to repeat last digit as
a constant or "R" to repeat the sequence, For example:
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– 011001R -> 011001 011001 011001...
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– 011001C -> 011001 111111 111111...
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run_atpg –auto ...
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write_patterns chain_test.stil –format stil –last 0
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TetraMAX generates a user-controllable chain test as Pattern 0 during ATPG for regular scan
designs.
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The default chain test pattern, 0011, results in a 50% toggle rate during scan shift.
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TetraMAX automatically generates additional chain test patterns for DFTMAX X-tolerant designs
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with R10 violations

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To enable/disable
set_atpg [–augmented_chain_test|-noaugmented_chain_test]
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For compressed designs with multiple chain tests, run_atpg –chain_test_only can be
used:
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run_atpg –chain_test_only
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write_patterns chain_tests.stil –format stil -replace

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TetraMAX Workshop
DFTMAX Ultra Chain Test Patterns
 DFTMAX Ultra chain test patterns generated by default

 To disable: set_atpg –streaming_xtol_chain_test off
Tests all internal chains plus codecs
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 Patterns test all faults marked DI in fault list
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 Required to distinguish failures in DFT logic from regular failures
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 Pattern count roughly equal to compression ratio
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 1 pattern per internal chain if 1 scan-out port is used
Divide this by N if N scan-out ports are used
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
All codecs tested simultaneously
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
 Total pattern count determined by codec requiring most patterns
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TetraMAX Workshop
Splitting Up Large Pattern Sets
 Large pattern sets can be “split” into multiple STIL patterns

write_patterns pat.stil –format stil –split <n> [-exclude repeat_setup]
 Patterns will be split into groups of n patterns
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 Patterns will be named pat_0.stil, pat_1.stil, etc.
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 Each pattern file will contain a test_setup section unless excluded
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 If –exclude repeat_setup is used, the first split pattern (pat_0.stil) will
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contain a test_setup but all other split patterns will not
 Only the first split pattern file contains the chain test patterns
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TetraMAX Workshop
Generate Reports Now for Later Debugging
Simulation miscompares on pattern N…

 Which ATPG engine generated pattern N?
report_patterns –all –type
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Scan unload miscompare on chain c4 position 10…
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 What is the corresponding design flip-flop?
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report_scan_cells –all
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 Obtain a list of any shadow cells:
report_scan_cells -shadow
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Shadow cells can effect the results of parallel Verilog simulation of scan patterns. The shadow cells
need to be accounted for by either adding serial shifts after parallel load (N-shift) or by disabling
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the use of shadows by ATPG (set_drc –noshadows).

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TetraMAX Workshop
Writing Patterns
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Pattern Validation
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Simulation Debug
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TetraMAX Workshop
The Challenge of Verifying Scan Designs
Scan paths not in RTL; cannot use Formal Verification on scan paths
Pre Scan
design
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Formality DFT Compiler
DFTMAX
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Optimized STIL
scan design Procedures
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PrimeTime DSMTest
DSMTest TetraMAX IDDQ
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Verify scan path timing
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DSMTest Stuck-At IDDQ Test
Vectors Test Vectors Vectors
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MAX Testbench IDDQ-PLI
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Verify scan pattern functionality VCS 6- 15
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TetraMAX Workshop
Verilog Pattern Validation
 It is critical to simulate the ATPG

patterns to validate their
STIL Test Data
correctness
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 The method for simulating ATPG
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patterns from TetraMAX is called
MAX Testbench
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 MAX Testbench uses STIL as the
source for creation of the Verilog
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testbench Design Under Test
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 The Test Pattern Validation User’s
Guide contains details on APTG
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pattern validation and using MAX
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Testbench 6- 16
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TetraMAX Workshop
What is MAX Testbench?
101011101 TetraMAX
111010000 STIL
011011011 Patterns
Stimulus/response
TetraMAX
Testbench
MAX Testbench
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write_testbench Module test; DUT
or stil2verilog
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Instance of DUT Model
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Stimulus/response
Data File Verilog
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Netlist/library
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 MAX Testbench converts STIL patterns into a Verilog simulation
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testbench using write_testbench or stil2verilog
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 The Verilog testbench applies test stimulus to the DUT and checks
the responses against the expected data specified in the data file
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TetraMAX Workshop
Using MAX Testbench
 Translate a STIL pattern to a Verilog testbench from within TetraMAX

write_testbench -input <stil_filename>
-output <testbench_name>
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[-replace]
[-config_file config_filename]
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[-parameters {list_of_parameters}]
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 Or use stil2verilog utility from UNIX
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UNIX% stil2verilog <stil_filename> <testbench_name>
[-config_file <file>] [options]
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Two output files are generated
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
 Verilog testbench file: <testbench_name>.v
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 Data file: <testbench_name>.dat
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-config_file config_filename
Specifies the name of a configuration file that contains a list of customized options to the MAX
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Testbench command line

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-parameters {list_of_parameters}
Enables you to specify additional stil2verilog options to the MAX Testbench command line
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stil2verilog <pattern_file> <tbench_file> [options]

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-config_file <TB_config_file>
-first <d> -last <d>
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-generate_config <config_file_template>
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-help [<msg_code>]
-log <log_file>
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-parallel [nshift] -serial -ser_only

-replace –report -run_mode go-nogo | diagnosis
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-sdf_file <sdf_file_name> -shell

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-sim_script vcs | mti | nc | xl

-split_in {1.stil, 2.stil…} <testbench_name>
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-split_out <pat_int> <stil_file> <testbench_name>

-tb_format v95 | v01 | sv
-tb_module <module_name>
-verbose -version
-v_file <design_file_names> -v_lib <library_file_names>

TetraMAX Workshop
Configuration File Overview
 The testbench can be configured with:

 Command line options
 Configuration file
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 A template of the configuration file can be created by
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write_testbench_config or stil2verilog:
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TEST-T> write_testbench_config
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UNIX% stil2verilog -generate_config <config_name>
 The configuration file contains two types of configuration information:
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 Variables affecting the testbench definition
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 Variables affecting the simulator script generation
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The write_testbench_config command is an alias of the following command:
write_testbench -parameters {-generate_config stil2verilog.config} -rep
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# Example configuration file variables. “#” is a comment

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# cfg_patterns_report_interval: Specifies interval of messages

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#set cfg_patterns_report_interval 5
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# cfg_message_verbosity_level: control for trace options

#set cfg_message_verbosity_level 0
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# cfg_evcd_file evcd_file: generates an extended-VCD of the run

#set cfg_evcd_file "evcd_file"
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# cfg_diag_file: generates a failures log file for diagnostics

#set cfg_diag_file "diag_file“
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TetraMAX Workshop
Parallel vs. Serial Load During Simulation
 Parallel/Serial - specifies how the scan chain load/unload should be

formatted during simulation:
 Serial - scan chain load/unload is not flattened but left intact and patterns
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contain test cycles that shift data into the scan chains
Parallel - scan chain load/unload is flattened and scan cells are broadside
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
loaded
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 N-Shifts <d> - parallel load followed by “d” serial shifts
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 A single STIL pattern set can support both parallel and serial load
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during scan pattern simulation (default is parallel load)
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 The simulation load method can be changed when STIL patterns are
translated with write_testbench / stil2verilog or at simulation
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run-time
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TetraMAX Workshop
Flexible Simulation: Serial Vs. Parallel
Note: we are not specifying serial

 Example: in TetraMAX save STIL pattern set or parallel simulation at this point
write_patterns pats.stil –format stil -replace
Default simulation is parallel with a pre-computed number of N-shifts
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
 Number of N-shifts is based on shadow cells and settings for loadable nonscan
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cells
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 MAX Testbench can specify serial vs. parallel when translating the STIL
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to a Verilog testbench - Example:
write_testbench –in pats.stil –out pat_xtb –parameters {-serial}
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 Can also be changed in the VCS compile script:
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+define+tmax_parallel=N Parallel with N serial shifts
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+define+tmax_serial=M First M patterns serial, remaining patterns parallel
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Parallel Options:
None or 0: all parallel patterns
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N: all parallel patterns with last N bits serially loaded

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Serial Options:
None or 0: all serial patterns
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M: First M patterns serial, remaining patterns parallel

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TetraMAX Workshop
Serial Load Simulate Which Patterns?
 Typically, it is not feasible to serial-load simulate all

the patterns
 It’s advisable to at least serial-load simulate the
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chain test pattern(s)
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 Beyond chain test, it’s at user discretion – one
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strategy would be to identify a selection of patterns
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so that each capture clock is serially simulated at
least once
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 Use report_patterns –all –type to document
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the capture clocks used for each pattern
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Note: simulating each capture clock at least is example method that could be used to determine
which patterns to simulate with serial load. At a minimum, the chain test pattern should be
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simulated with serial load. Beyond that, it’s up to user discretion regarding which patterns to
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TetraMAX Workshop
Selecting Serial Patterns by Capture Clock
TEST-T> report_patterns –all –type > pattern.rpt
Patn Pattern Cycle Load Observe Clocks
num type count count proc used
----- --------------- ----- ----- ------- -----------------------
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1 basic_scan 1/1 1 - sdr_clk,sys_clk,pclk
3 basic_scan 1/1 1 - sdr_clk,prst_n
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Patterns of
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Interest 6 basic_scan 1/1 1 - sdr_clk,sys_clk,pclk
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8 basic_scan 1/1 1 - sys_clk,pclk
9 basic_scan 1/1 1 - prst_n
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TEST-T> report_clocks
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clock_name off usage

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---------------- --- --------------------------

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test_pci_clk 0 master shift

test_sys_clk 0 master shift nonscan_DLAT
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test_sdram_clk 0 PO master shift

test_sys2x_clk 0 master shift nonscan_DFF
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prst_n 1 PO master reset

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TetraMAX Workshop
Write Only Those Selected Patterns
unix% cp pattern.rpt serial_select.rpt

The -reorder option looks only
unix% vi serial_select.rpt at the first column of the file
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TEST-T> write_patterns select_pats.stil –format stil \
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-reorder serial_select.rpt –serial
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 DFTMAX compressed patterns cannot be reordered but a range of
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patterns can be written
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TEST-T> write_patterns range_pats.stil –format stil \
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-first 0 -last 3 –serial
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Adaptive Scan patterns cannot be “reordered” with the –reorder option. See the following
SolvNet article for a workaround flow:
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SolvNet Article: 020892 – How to Combine Adaptive Scan Pattern Files

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FYI, by default the first pattern is pattern 0, so it’s not required to specify that option in the above
example. The option was included to demonstrate how a range of pattern can be written.
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TetraMAX Workshop
Handling Split Patterns With MAX Testbench
 To use previously split STIL patterns for MAX Testbench simulation:

write_testbench -input {-split_in \{pat_0.stil pat_1.stil foo_2.stil\}} \
-output pat_xtb -replace
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 Separate “partitions” are created when the testbench is created
 Each split pattern set is a partition and will have its own data file (i.e.,
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pat_xtb_0.dat)
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 By default, all partitions are simulated in order
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 A specific partition can be simulated by specifying simv
+tmax_part=<partition#>
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 Alternately, a single large STIL pattern file can be split out into multiple
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partitions by MAX Testbench for simulation
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write_testbench -input pat.stil –output pat_xtb –replace \
–parameters {-split_out <n>}
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 Partition handling is the same as mentioned above 6- 25
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TetraMAX Workshop
Runtime Programmability
 The goal of runtime programmability is to facilitate reusing a compiled

simulation executable (simv) for multiple validation runs
 Useful for designs that take a long time to compile with VCS
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 Two types of runtime programmability
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 Basic programmability (changing serial vs. parallel simulation, etc.)
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 Pattern programmability (different pattern sets reuse the same simv)
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 Basic programmability involves specifying runtime options with simv
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simv +<runtime_option>
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 The available runtime options are: tmax_msg, tmax_rpt, tmax_serial,
tmax_parallel, tmax_n_pattern_sim, tmax_test_data_file
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+tmax_msg=N Control for a pre-specified set of trace options
+tmax_rpt=N Specifies the interval of the progress message
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+tmax_serial=N Forces the serial simulation of the first N patterns for a testbench written by
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MAX Testbench with only the -parallel option. This option then starts the parallel simulation of the
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remaining patterns using the parallel parameters specified when the testbench was written. If N=0
or not specified, then all patterns will be serial simulated.
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+tmax_parallel=N Forces the parallel-load simulation of all scan data, with N bits extracted and
serially simulated. This option overrides the behavior of a testbench written by MAX Testbench
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with the -serial option and overrides the value of N of a testbench written by MAX Testbench with
the -parallel option. If N is not specified, it is processed as zero (meaning all bits are parallel-
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tmax_n_pattern_sim=N Specifies the number of patterns to simulate.

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TetraMAX Workshop
Runtime Programmability for Patterns
 A special “generic” testbench is created

 Subsequent testbenches can be generated to only produce the required
pattern data that will be used by the generic testbench
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 Pattern can be changed at runtime without having to recompile simv
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run_atpg -auto
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write_patterns pats_1.stil –format stil
write_testbench –input pats_1.stil –output xtb_1 -parameter {–generic_testbench}
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run_atpg -auto
write_patterns pats_2.stil –format stil
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write_testbench –input pats_2.stil –output xtb_2 -parameter {–patterns_only}
write_patterns -first 5 –last 10 pats_3.stil –format stil
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write_testbench –input pats_3.stil –output xtb_3 -parameter {–patterns_only}
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%> ./simv
%> ./simv +tmax_test_data_file=“xtb_2.dat"
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%> ./simv +tmax_test_data_file=“xtb_3.dat"
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TetraMAX Workshop
Recommended Simulation Strategy
 Before post-route SDF is available, run zero-delay or unit-delay

simulations
 Simulate all patterns with the parallel-load testbench
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 Validate the ATPG patterns as early as possible in the overall design
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flow in order to stay out of the critical path
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 With post-route SDF timing annotated simulate:
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 ALL patterns with the parallel-load testbench
 As many patterns as possible with the serial-load testbench (how many depends
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on simulation runtime and/or ASIC vendor requirements)
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 At a minimum, the chain test pattern should be serially simulated
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SIMULATION DELAY SWITCHES

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Zero delay:
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Use +nospecify +zero_delay_mode +tetramax

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Having problems? Try unit delay or typical timing

Unit delay:
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Unit cell delays, what about interconnect delays

Having problems? Try typical timing
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Typical delay:
Typical cell delays, what about interconnect delays
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Having problems? Try fully annotated timing

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TetraMAX Workshop
Verilog Simulation
 Any Verilog simulator can be used to simulate the testbench generated

by MAX Testbench
vcs -R -l xtb_verilog.log +delay_mode_zero +tetramax \
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parallel_xtb.v -v ../lib/class.v ../dftc/result/timer.v
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 Check the simulation log for mismatches
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#############################################################################
MAX TB Version I-2017.09-SP2
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Test Protocol File generated from original file "test.stil"
STIL file version: 1.0
Enhanced Runtime Version: use <sim_exec> +tmax_help for available runtime options
#############################################################################
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XTB: Starting parallel simulation of 375 patterns
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XTB: Using 0 serial shifts
XTB: Begin parallel scan load for pattern 0 (T=200.00 ns, V=3)
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...
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XTB: Simulation of 375 patterns completed with 0 errors (time: 225400.00 ns, cycles: 2254)
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TetraMAX Workshop
Writing Patterns
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Pattern Validation
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Simulation Debug
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TetraMAX Workshop
Recognize Common Mismatch Causes
Expected vs. Actual States:

 Actual all X’s
Initialization issues
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
 Loss of internal state - glitches, transient events, X on clock
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 Differences with Z’s
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 Tristate enable lines (set_buses –external_z x)
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 1/0 or 0/1 mismatches
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 Timing problems
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 Strobe positioning
 Extra/missing clocks, glitches, transients
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 Bad Memory model (have the memory models been validated?!)
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 DRC violations (for example C1, C5, or C39) 6- 31
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The first piece of data to analyze is the expected state, specified in the test data, and the actual state
present from the simulation run.
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Are all the actual states an “X” value? This can indicate initialization issues, or the loss of the
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internal design state during operation, caused by glitches or transient events. If an “X” is found in
the simulation, start tracing that “X” backwards in both the design and in simulation time - where
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did that X come from?

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Are the mismatches on bi-directional signals, and do the differences involve actual or expected “Z”
values? In this type of situation, review the state of the tristate enable lines.
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Are the mismatches “hard errors” - for instance, an expected “1” but an actual “0” or vice-versa?
This could be caused by timing problems in the design, or strobe positioning, or extra or missing
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clocks, glitches, or transients in the design that are causing the wrong state to appear too soon or too
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late compared to what the expected state was.

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TetraMAX Workshop
Begin Debugging the First Failure
 Subsequent failures may be caused by cascade effects

 The very first error is the best place to start examining failures
Errors in scan patterns are bounded by the TetraMAX “Pattern”, which is:
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
 The previous load_unload Shift that loads the scan-in state
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 One or more capture cycles
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 The current load_unload Shift that unloads the new scan-out state
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 Example failure log
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>>> Error during scan pattern 8 (detected from parallel unload of pattern 7)
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>>> At T=3340.00 ns, V=34, exp=0, got=1, chain 1, pin test_so1, scan cell 25
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Because Basic-Scan patterns, starting with a scan load and ending with a scan unload, are self-
contained units, failures in one scan pattern do not typically propagate - unless the failure is
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indicative of a design or timing fault that persists throughout the patterns (or the patterns have
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sequential behavior).
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Do not take “first” literally as the first printed mismatch - all mismatches that happen at the same
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time step (or even at different times but in the same STIL Vector) - are all a consequence of the
problem that was functionally detected at this point. Any error generated in the first failing Vector is
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a good starting point.

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TetraMAX Workshop
Failure Log Formats
 For a given simulation mismatch, an initial goal for debug is to

determine the scan cell(s) that captured the wrong values
 The format of the simulation failure log varies depending on several
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factors including:
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 Parallel vs. serial simulation
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 Uncompressed vs. compressed mode
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 Unified STIL Flow vs. Dual STIL Flow
 MAX Testbench runtime defines
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 MAX Testbench configuration file options
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TetraMAX Workshop
Regular Scan Mode Failure Log Formats
 With “regular scan” (uncompressed) mode simulations, the failing cell

information is available for both parallel and serial simulations
 Parallel simulation:
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>>> Error during scan pattern 9 (detected from parallel unload of pattern 8) Cell names can be
determined by cross-
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referencing with
 Serial simulation: report_scan_cells
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XTB: Begin serial scan load for pattern 0 (T=200.00 ns, V=3)
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>>> Error during scan pattern 4 (detected from unload of pattern 3)
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TetraMAX Workshop
Regular Scan Mode Failure Log Formats with Cell Names
 To see the cell names in the fail log, the MAX Testbench can be created
using the following configuration variable:
set cfg_parallel_stil_report_cell_name 1
ng
Cell Names
 Parallel simulation:
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>>> At T=1540.00 ns, V=16, exp=1, got=0, chain 15, pin test_so15, scan cell 33, cell name q1_reg_0_
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 Serial simulation:
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XTB: Starting serial simulation of 288 patterns
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TetraMAX Workshop
Compression Mode Failure Log Formats (Unified STIL Flow)
 With compression mode simulations, the ability to report the failing

cells is more complicated due to the compressor
 Parallel simulation (with USF)
ng
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...
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>>> At T=13940.00 ns, V=140, exp=1, got=0, pin test_so3, shift cycle 4 ScanOut port and
shift cycle reported.
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>>> At T=13940.00 ns, V=140, exp=1, got=0, pin test_so4, shift cycle 6
>>> Error during scan pattern 34 (detected from parallel unload of pattern 33) Can use diagnosis to
>>> At T=13940.00 ns, V=140, exp=1, got=0, pin test_so13, shift cycle 4 determine failing cell.
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 Serial simulation
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XTB: Starting serial simulation of 514 patterns
...
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TetraMAX Workshop
Compression Mode Failure Log Formats (Dual STIL Flow)
 With compression mode and Dual STIL Flow, failing cells are reported
XTB: Using 0 serial shifts Note that N-shift is
not supported with
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...
XTB: Begin parallel scan load for pattern 30 (T=9200.00 ns, V=93) the Dual STIL Flow
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>>> At T=10540.00 ns, V=106, exp=1, got=0, chain 242, scan cell 1
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 With set cfg_parallel_stil_report_cell_name 1 in config file:
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...
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>>> At T=10540.00 ns, V=106, exp=1, got=0, chain 242, scan cell 1, cell name q1_reg_0_
Reporting of serial simulations with Dual STIL Flow is the same as for USF
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
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TetraMAX Workshop
Combined Pattern Validation (CPV)
 To report failing cells with parallel

simulation of compression mode USF TetraMAX run_atpg *.psd file
ATPG Parallel
patterns requires additional information Strobe Data
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write_patterns
 TetraMAX can create a Parallel Strobe STIL (USF)
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Data (PSD) file to provide that additional
write_testbench
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information to MAX Testbench
MAX
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 The PSD file is a binary file that contains Testbench
additional internal parallel strobe data
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tb.v tb.dat tb_psd.dat
 The PSD file can be created by
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TetraMAX either during pattern
generation (run_atpg) or during
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VCS
simulation (run_simulation)
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Note: CPV limitations:
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• The Full-Sequential mode is not supported.

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• The set_patterns and run_simulation commands are not supported for multiple contiguous runs
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(see “Creating a PSD File”). Also, update and masking flows are not supported, including pattern
restore from binary and new pattern write flows, multiple pattern read back, and single merged
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pattern write.
• When the set_atpg –parallel_strobe_data command is used with DFTMAX Ultra compression,
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the PSD file is invalidated by a subsequent update_streaming_patterns –

remove_padding_patterns command. Only the run_simulation flow should be used with
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DFTMAX Ultra compression.

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• The -first, -last, -sorted, -reorder, and -type options of the write_patterns command are not
supported.
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• The -sorted, -reorder, and -type options of the write_testbench and stil2verilog commands are not
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supported.
• The -last option of the run_simulation command is not supported.
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TetraMAX Workshop
Generating a PSD File
 Enable the generation of a PSD file during run_atpg:

set_atpg –parallel_strobe_data_file <PSDfile> -replace
run_atpg -auto
ng
 PSD file can be (re)generated during simulation with:
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run_sim -parallel_strobe_data_file <PSDfile> -replace
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 TetraMAX II does not support generating a PSD file during run_atpg
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 If enabled, a Warning message will be issued
 A PSD file will still be created but it will be unusable
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 Use run_sim to create the PSD file with TetraMAX II
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 In DFTMAX Ultra flows, the PSD file should be created by run_sim after
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the patterns have been generated by ATPG and the padding patterns
have been removed
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To create the PSD file with DFTMAX Ultra compression in a single session:
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1. Run ATPG in TetraMAX ATPG.

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run_atpg -auto
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2. Use the update_streaming_patterns command to clean up the padding patterns.

update_streaming_patterns -remove_padding_patterns
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3. Write the unified STIL patterns.

write_patterns out.stil -format stil -unified -replace
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4. Delete all current internal and external patterns

set_patterns -delete
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5. Specify a set of externally generated patterns.

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set_patterns -external out.stil

6. Create the PSD file.
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run_simulation -parallel_strobe_data_file comp.psd -replace

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7. Write the final set of patterns that match the PSD file.
write_patterns pat_u.stil -for stil -repl -unified_stil_flow -ext
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8. Run MAX Testbench.

write_testbench -input pat_u.stil -out maxtb -replace \
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TetraMAX Workshop
Compression Mode Failure Log Formats with PSD
Confirms that the
PSD file is used
 Parallel sim with PSD and cell names (USF)
XTB: Enabling Enhanced Debug Mode. Using mode 1 (conditional parallel strobe). Note that N-shift is
supported with USF
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...
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Still reports the
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>>>
XTB:
At T=13940.00 ns, V=140, exp=1, got=0, pin test_so13, shift cycle 4
searching corresponding parallel strobe failures...
failures seen at the
>>> At T=13940.00 ns, V=140, exp=1, got=0, chain 242, scan cell 1, cell name q1_reg_0_ ScanOut pins
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New section of the failure log
To have the cell name reported, you
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shows the “internal” parallel
strobe failures that led to the still need to use a configuration file
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failures seen on the ScanOuts when generating the MAX Testbench
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TetraMAX Workshop
Post Process Fail Log to Show Failing Cell Names
 Avoids the overhead during compilation (and simulation) using the

previous solution (cfg_parallel_stil_report_cell_name)
 Useful for large designs that require a lot of memory
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 If a W-048 message is seen when creating the MAX Testbench, the
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overhead required to report the failing cell names via the configuration
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file may be significant
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 Candidate to use the post processing flow
 Uses stil2verilog to post-process a failure log and identify failing
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cell names
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stil2verilog pats.stil -failing_cell_report sim.log –log new_sim.log
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W-048: Failing scan cell name display feature may have an impact on simulator performance.
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The failing scan cell name display functionality increases the Verilog testbench size and the
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memory usage. On large designs, this feature can impact the simulator performance.
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TetraMAX Workshop
Flow to Post Process Fail Log and Show Failing Cell Names
Configuration file
not used or disabled
Configuration File
cfg_parallel_stil_report_cell_name 0
Verilog Simulation Log
Pattern, Time, Vector number,
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Scan chain name, Cell ID No cell
PSD File STIL File
names
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MAX Testbench stil2verilog
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stil2verilog –failing_cell_report
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Log with Verilog
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Enhanced Simulation Log
W-048 Testbench Pattern, Time, Vector number,
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Scan chain name, Cell ID, Cell
Scan cell instance name names
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added
VCS
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TetraMAX Workshop
Useful Debugging Signals
 A waveform viewer can view useful signals to help debug mismatches:

 Cycle number (v_count or v_count_per_pat)
 Current Pattern number (cur_pat)
STIL statement currently executed (cur_StmtName)
ng

 Cells with miscompares
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 Clocks/Resets
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 ScanEnable
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...
"pattern 3":
Call "load_unload" {
"test_so1"=HLHLHHLLHLLLLLLLLLL; "test_so2"=HLHLH…; "test_so3"=HLHL…;
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"test_so4"=LLLLLLLLLLLLLLLLLLL; "test_so5"=HHHHL…; "test_so6"=LLLL…;
"test_si5"=0011111011000011101; "test_si1"=00011…; "test_si2"=0110…;
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"test_si3"=1111111011000010111; "test_si4"=01111…; "test_si6"=0000…; }
Call "allclock_launch" {
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"_pi"=1P101011001000111; }
Call "allclock_capture" {
"_pi"=0P001011000011111; "_po"=LLLLLHHLHHHLLLH…; }
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...
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TetraMAX has a command called write_simtrace that can be used to monitor certain signals
during Verilog simulation for debug purposes. See the write_simtrace man page for details.
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TetraMAX Workshop
What is Parallel Testbench Doing?
 Load of scan flops not performed by full scan shift

 Load stimulus is applied/forced at scan_flop.SI port
 Shift clock pulsed to load flop then force is released
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 Reduces long shift cycle to single cycle for load
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 Strobe of scan_flop.Q done in same load cycle
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 Capture cycles applied by normal means
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 Shift load/unload can be extended by using N-shift
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+define+tmax_parallel=N
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 Where N is > 0
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TetraMAX Workshop
Simulation Waveforms
 Sometimes the only way to debug a simulation issue is to view the waves
Time when scan cell is forced
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Time when scan cell is released
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Time where scan cells
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are strobed/measured
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1st pulse to do parallel
load, 2nd pulse for N-shift
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Additional cycles for
load_unload and capture
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TetraMAX Workshop
Comparing Waves to TetraMAX
 To debug the root cause of a

simulation mismatch, the value
seen during simulation can be
ng
compared to the value expected by
TetraMAX
ni
To show the simulated values for a
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
specific pattern in the GSV
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analyze_simulation_data –fast <n>
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 The GSV will show that pattern’s
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values for the capture procedure(s)
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 Trace backwards in the GSV and in
Waves to find the cause
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Another option to show simulated values in the GSV is:
set_pindata –good_sim_results <n>
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In many cases the cause of the mismatch is a scan cell that was loaded with the wrong value.
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TetraMAX Workshop
Some Causes of Simulation Mismatches
 Some common causes of parallel simulation mismatches

 Difference between TetraMAX model and simulation model
 Shadow cells may not loaded with expected 1/0 due to missing N-shift(s)
ng
 DRC violations: C5, C12, S18, S29, etc.
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 Watch for warnings issue during ATPG and/or when patterns are written in TetraMAX
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 If the chain test is failing, then there’s an issue with the parallel load itself
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 Timing issue and/or missing TetraMAX SDC exception with SDF At-Speed
simulation
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 Clock edge for falling edge flops too late in period
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 Conflicting forces elsewhere in the simulation environment
Some common causes of serial simulation mismatches
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
 Issue with compression mode logic
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 Pipelined scan data not behaving as TetraMAX expects 6- 47
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TetraMAX Workshop
Writing Patterns
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Pattern Validation
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Simulation Debug
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TetraMAX Workshop
Still Have Failures in Simulation or on ATE?
 ATPG pattern testbench simulates with mismatches

 ATE test program runs, but all DUTs produce failures
ng
 Even with clean STA and simulation with no simulation
mismatches, actual DUTs can still fail on ATE
ni
 If the same ATE timing and post-route SDF is used in both STA and
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simulation, and STA reports no violations, simulation mismatches can
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still occur due to:
Simulation mode (zero, unit, typical) issues
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
ATPG results predicted based on 0-delay environment
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
 Simulation model may not match ATPG model
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 The project schedule is tight:
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How will you debug the simulation mismatches or ATE failures? 6- 49
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TetraMAX Workshop
Masking Simulation Failures
 Not Making Any Progress in Debugging?

 Will the project manager or customer relax the schedule so you can perform more
debugging?
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 If the mismatches and failures are localized and not widespread, one
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option is to use PI/PO Masks, Cell Constraints, or Capture Masks
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 Reduce simulation mismatches
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 Reduce ATE false negatives
 Perform the masking in TetraMAX rather than ATE
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 Determine reduction in test coverage
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TetraMAX Workshop
Defining Input or Output Masks
 Input masks are accomplished by defining a PI constraint of X on an

input:
add_pi_constraints x <port_name>
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 An output mask is used to prevent the ATPG algorithm from observing
ni
faults through a specific output port
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add_po_masks <port_name> | -all
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 Faults can no longer be controlled from masked inputs or observed
from masked outputs (therefore coverage will drop)
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Useful if you have a reduced-pin count revision to a full pin count chip and need to determine the
fault coverage (reduction).
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Power and Ground (VDD/VSS) pins would typically not be masked but totally excluded from the
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design. Remove VDD/VSS top-level pins using the “add_net_connections –delete”

command.
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To review existing PI masks use: report_pi_constraints

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To delete use: remove_pi_constraints [ port | -all ]

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TetraMAX knows how to handles CLKPOs; do not mask them.

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If you discover after simulation or on the ATE that an output has glitches or is difficult to strobe at
ct
the correct time, consider masking it out.

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This command is also useful to determine the fault coverage (reduction) of a reduced-pin count
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revision to a full pin count chip.

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To review existing PO masks use: report_po_masks

To delete use: remove_po_masks [ port | -all ]

TetraMAX Workshop
Scan Cell Constraints
 TetraMAX supports constraining what is to be loaded into a specific

scan cell (0, 1, X)
add_cell_constraints <0|1|X> <chain|inst> \
ng
[-position {<cell_pos1|sci> [cell_pos2]>}|-all>>]
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 Other settings provide for scan cell masking
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 OX - scan cell will always “Observe X” regardless of captured value (note: OX =
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“oh X”)
 XX - scan cell will always be loaded with X and observed as X
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 To control the value loaded and mask unload
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 0X – scan cell will be loaded with a 0 and observe an X
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 1X – scan cell will be loaded with a 1 and observe an X
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Cell constraints can be specified in several ways:
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1. instance name
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add_cell_constraints OX reg2/r/D
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2. By chain_name & position

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add_cell_constraints xx c34 –position 6

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3. An entire chain (must also use add_po_masks on scan-output port)

add cell constraint OX CHAIN_1 -all
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add_po_masks chain_1_SDO
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4. Specify a range of flops to be loaded to all 1’s

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add_cell_constraints 1 CHAIN_2 –position {23 29}

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TetraMAX Workshop
Non-Scan Cell Masks
 Scan or non-scan elements can be masked with the

add_capture_masks command
 Simulates an X when the specified cell is clocked
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 Is similar to but has slightly different behavior than
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add_cell_constraints OX
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Example:
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add_capture_masks /PROBLEM/NONSCAN/FLOP
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 To prevent a loadable non-scan cell from being loaded but still allow the
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cell to capture
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add_capture_masks nonscan/cell –load_only
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Example report_capture_masks output
Only when add_capture_masks –load_only has been used
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gate_id type lo instance_name

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------- ---- -- ----------------------------

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45 DFF -- s1
58 DFF LO n0and
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LO indicates a load-only mask, and -- indicates a normal mask

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Refer to following SolvNet Articles:

000612 – Creating Test Patterns with Timing Violations in the Scan Chain
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901030 – Difference Between the add cell const OX and the add capture mask Commands
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TetraMAX Workshop
Per-cycle Pattern Masking
 Goal: replace L’s and H’s with X’s in scan patterns to mask specific
measures that mismatch on tester
 Use –resolve_differences <mask_file> option of set_patterns
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to update external patterns
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set_patterns –external <patterns_file> \
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–resolve_differences <masks_file>
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 When the external patterns are read, TetraMAX will report the total
number of X measures added
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set_patterns -external pat.stil –resolve_differences mask.txt
End parsing STIL file pat.stil with 0 errors.
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End reading 200 patterns, CPU_time = 33.40 sec, Memory = 5MB
6 X measures were added in the external patterns.
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write_patterns mask_pats.stil –format stil –external -replace
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To determine the Test Coverage difference after masking:
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add_faults –all
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# Read UD faults – run_fault_sim can’t identify redundant

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faults
read_faults ud.flt –retain_code
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run_fault_sim
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Per-cycle pattern masking limitations:

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• Failures in cycle-based format with cycle offset can not be automatically read
• Full-Sequential patterns could have multiple load-unloads with measures on the scanout in each
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unload. Only the failures for the first unload can be masked
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TetraMAX Workshop
Fail Data File Support From Simulation
 By default, the simulation failures are formatted to be human-readable

and not ready to be used for TetraMAX masking flows or diagnosis
>>> Error during scan pattern 20 (detected during unload of pattern 19)
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>>> At T=10195.00 ns, V=102, exp=0, got=1, chain 1, pin pc[11] , scan cell 0
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 To format failure messages for per-cycle pattern masking or diagnosis,
MAX Testbench can be configured to store the failures in a fail data file
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Use –run_mode diagnosis option at stil2verilog execution time
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 Initializes file name for collection of the failures for the diagnostics to diag.txt
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 Set the variable cfg_diag_file in the config file with the name of the file
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set cfg_diag_file <file_name>
 Specify failures file using the tmax_diag_file and tmax_diag define options
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at simulation execution
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% vcs ... +define+tmax_diag_file=\”<file_name>\”
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For MAX Testbench, the tmax_diag define controls the format of the fail data file.
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+tmax_diag=<N>
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Configures the miscompares in pattern-based (N=1) or cycle-based (N=2) format.

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Note: fail data files can also be created on the ATE

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TetraMAX Workshop
Failure Data File Formats From Simulation
 Serial simulation
 Pattern-based failure file with output port name
5 test_so4 10 (exp=1, got=0)
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 File can be used for per-cycle pattern masking or diagnosis
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 Parallel simulation
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 Pattern-based failure file with chain name
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3 chain2 7 (exp=0, got=1)
File can be used for per-cycle pattern masking or diagnosis
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
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Note: If a pattern-based failure file with chain name is used with a DFTMAX design the following
command is required:
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set_diagnosis -dftmax_chain_format
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Note: there is also a cycle based fail data format that is covered in the Diagnosis unit:
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Cycle-based:
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C <output_name> <cycle> [expected_data]

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TetraMAX Workshop
DFTMAX Ultra chain masking
 Mask specific internal scan chains during ATPG or apply masks to

modify existing patterns:
add_chain_masks
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 Chain masking applied at compressor inputs
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 Done by adjusting values scanned into decompressor cache
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 Masked chains loaded with normal scan-in values
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 Not consistent with any type of chain defect
Result is reduction in number of mismatches
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
Large mismatch count can be hard to debug with high compression
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
 Small mismatch count allows user to concentrate on individual causes of
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mismatches
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add_chain_masks main options:
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-name { <string_value> ... } Specify chain (or list of chains) to be masked

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-do_not_mask { <string_value> ... } Specify chains to never be masked

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Takes precedence over conflicting –name or

–compressor specifications
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-compressor { <string_value> ... } Specify compressors for which all chains will be masked
-filename <string_value> Specify file containing chains to be masked
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-percent <int_value> Percentage of external patterns to be masked

-external Mask the patterns in the external pattern buffer
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Otherwise specification applies to new patterns

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-reset Delete all previous add_chain_masks specifications

-diagnosis Masks the external patterns for diagnosis
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-diagnosis_pattern_count Specifies the pattern count for masking each chain

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when using the -diagnosis option. The default value is 50

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The following example masks all chains in the abc.txt file and chains 12, 45, and 67:
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add_chain_masks -filename abc.txt -name {12 45 67}

TetraMAX Workshop
DFTMAX Ultra chain masking: Examples
 Chain masking for new ATPG patterns

run_drc …
# User wants ch1 and ch2 to be masked
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add_chain_masks –name {ch1 ch2}
# add_chain_masks has specified constraints on ATPG,
# so nothing actually happens until run_atpg
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run_atpg -auto
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# Write the masked pattern set
write_patterns ..
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 Chain masking for an existing pattern set
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set_patterns –external …
# User wants to mask ch1 and ch2 of the external pattern set
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add_chain_masks –name {ch1 ch2} –external
# add_chain_masks has resimulated the patterns,
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# so they are ready to write out immediately
# Write the masked pattern set
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write_patterns .. –external
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Limitations of DFTMAX Ultra chain masking:
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• Chains not within the DFTMAX Ultra codecs (e.g. OCC chains) cannot be masked by this
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command
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• Coverage will be lower due to loss of observation on masked scan chains

• Chain selection based on trial and error
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• No multicore simulation support for masking of patterns in external pattern buffer

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TetraMAX Workshop

 Explain the benefits of saving patterns in binary format
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 Describe the minimal set of ATPG patterns that should
be simulated with serial load_unload
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 Use two ways to translate a STIL pattern to a Verilog
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testbench with MAX Testbench
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 Describe 2 reasons why you might use the ATPG
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masking commands
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Begin Lab 6: Pattern Validation
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TetraMAX Workshop
report_patterns -all -type Obtain report of patterns and their type

set_atpg -chain_test Specifies bit sequence to load during chain test
write_patterns –format binary Write patterns in binary format
write_patterns –format wgl Write patterns in WGL format for translation to ATE
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write_patterns –format stil Write patterns in STIL format for translation to ATE
write_patterns -last 0 Writes the chain test, pattern 0
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write_patterns -sorted Writes patterns ordered by complexity
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report_scan_cells –all Reports all scan cells
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report_scan_cells -shadow Reports only the shadow gates of scan cells
add_pi_constraints X <port> Apply an input mask to a port
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add_cell_constraints <0|1|XX| Control value loaded and/or mask the value
OX|0X|1X> –chain <name> <pos> unloaded from a scan cell
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add_po_masks <port> Apply an output mask to a port
add_capture_masks <instance> Mask values captured on a non-scan or scan cell
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set_patterns –resolve_diff <f> Apply per-cycle pattern masking
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TetraMAX Workshop
Agenda
DAY
2
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Fault Models and At-Speed Testing ©2018 Synopsys, Inc. All Rights Reserved. 7-1
TetraMAX Workshop
Unit Objective
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 List several fault models supported by TetraMAX
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 Describe At-Speed defects
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 Describe two popular fault models for At-Speed testing
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 Describe three different way to launch an At-Speed transition
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for delay testing
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 Modify the default STIL Protocol File (SPF) written out from
DFT Compiler to support At-Speed ATPG
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In this unit you will see an overview of At-Speed defects and their causes. You will also learn why
it is important to include At-Speed ATPG tests as part of your overall manufacturing test flow.
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TetraMAX Workshop
New Defect Types with New Technologies
 Rapidly changing technology moving down to smaller process

geometries
 Increasing performance requirements to reach GHz in the applications
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 Many defects will pass Stuck-At testing and defective parts are sent
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back to silicon provider
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 Additional IDDQ patterns are not enough, IDDQ current is too high in
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Deep Submicron technology
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 Test cost should not increase
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~50% of defects at < 0.18µ
not covered by Stuck-At
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TetraMAX Workshop
Sources of Test Escapes
 Nigh and Gattiker list 7 types of test-escapes
 Timing-related defects  Environmental failures
 Resistive contacts/vias,  Soft errors
 Resistive bridges,  Untested faults
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 resistive opens  <100% coverage
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 gate oxide shorts
 Faults unmodeled by Stuck-At
improper implants
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
 “stuck opens” causing sequential
Silicide breaks behavior
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
 Reliability failures  net-to-net bridging defects
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 Circuit / process sensitivities
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 Many of the defects can be detected with DFT techniques
Timing-related defects • Unmodeled faults
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
 Untested faults
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Nigh & Gattiker (IBM), Test Method Evaluation Experiments & Data 7- 4
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Note: a “test escape” is a device that passes every test applied on the ATE but still has undetected
defects that could cause functional issues and/or a customer return
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TetraMAX Workshop
Delay Testing Introduction: Agenda
Fault Models
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At-Speed Launch Methods
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SPF Timing For External Clock
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Delay Testing
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TetraMAX Workshop
Fault Models
 TetraMAX supports several fault models

 High defect coverage for established and emerging nodes
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1 0
D Q
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D Q
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 0 0
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Slack-Based
Stuck-At Slack-Based Hold-Time Static Bridging IDDQ
1
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
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1 1 0
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Transition Cell-Aware Path Delay Dynamic Bridging IDDQ-Bridging
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TetraMAX Workshop
At-Speed Defect
 Manufacturing defect that prevents the device from operating At-Speed

 Under static or slow conditions it operates as expected
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 In the presence of a defect, the output does not transition within the
stipulated time
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 Critical timing paths are particularly susceptible to At-Speed defects, but
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other paths as well can have a defect which can lead to failure of the chip
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 If not detected, At-Speed defects will increase the number of test escapes
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Normal Transition Slow Transition
High
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Low
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At-Speed strobe Stuck-At strobe
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Studies have shown if scan-based At-Speed tests are removed from the test program, the escape rate
goes up nearly 3%
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TetraMAX Workshop
Why Chips Fail “At-Speed”?
Point defects Distributed defects
 Metal scratches  Mask alignment

 Ion implants
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 Dark/missing vias
 Poly cracks  Oxide thickness
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 Metal/poly bridges  Metal widths
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 Metal thickness
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Metal short Open via FinFET opens Lithography defect
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Think of “point defects” like circuit nodal defects affecting a gate, for example.
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Distributed defects affect a bigger part of a circuit. These might be magnified across a long circuit
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path.
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TetraMAX Workshop
Methodologies for At-Speed Defect Testing
 At-Speed Functional Patterns

 Manual effort to create
 Unpredictable coverage
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 Costly high speed, high bandwidth ATE required
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 Scan based ATPG patterns
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 Automated using DFT structures
 Predictable with high coverage
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 Less expensive ATE needed
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 Complementary to Stuck-At Methodology
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TetraMAX Workshop
Which Methodology Detects Most Defects?
Slow At-Speed
0 8 Functional
Functional 0
0 5
0 22
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190
4 6
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2
Stuck-At 0 At-Speed
24 Scan
Scan
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 Venn diagram from HP ITC paper:
A single fault model does not catch all failures
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
Stuck-At scan missed 20% of the failures
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
 At-Speed scan caught 97% of the failures
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Maxwell (HP), et al, ITC ’96, IDDQ and AC Scan: The War Against Unmodelled Defects
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Many faults fail only At-Speed testing.
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TetraMAX Workshop
Transition Delay Fault Model
 Defect delay is confined to a single gate pin

 Test pattern applies the transition on the fault site
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 Path to apply the transition or to capture its effect is selected by the
tool
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 May not be the longest path (more on this later)
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 Same fault sites and classes as stuck-at ATPG
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Many possible paths for detection Transition Delay Fault
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Defect causes DUT to fail At-speed
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Time you strobe the output is constant (red arrow) and the size of the defect (hashed red pulse) is
constant.
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With 3 different length paths coming in, the amount of the delay added from the defect is the same,
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but you can sensitize it from different paths (I.e. the arrival time of the transition is changing).
(This example shows three paths.)
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Will measure a 0 in the good circuit and a 1 if there’s delay. The larger the delay, the easier it is to
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detect.
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In this example, the short path will cause you to actually measure 0 and miss detecting fault. For a
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small defect, it’s important to use a longer path.

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This is generally the opposite behavior of ATPG, which tries to use less effort to generate a vector
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and is one of the limitations of the transition delay model (in general).
To accommodate for this limitation, you should also use the path delay model to detect defects that
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are distributed along the path. The ATPG algorithm is given the path to test, and it doesn’t have a
choice to use less effort. Targeting a specific path requires a powerful (full-sequential) ATPG
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algorithm.
In general, for any given transition, there may be multiple paths coming into/out of gate – need to
enhance w/Path Delay testing. Note: this paths can come directly from Prime Time.
TetraMAX Workshop
Detection Path : Does it Matter?
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 Consider fault b0 slow-to-rise (STR) on a 4 bit adder
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 Can be detected at S0,S1,S2,S3 or C4
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Detection at S0
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
 Minimum effort for ATPG
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 Maximum Slack on the path
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 Detection at C4
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 Maximum effort for ATPG
Minimum Slack on the path
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
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TetraMAX Workshop
Detecting a Small Delay Defect
C D Q
1
1 B
A TA-B
Δt
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Small Delay Observe test

A
point
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Defect
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B Small delay defect not detected through path A-B
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TA-B
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C Much better chance to detect through path A-B-C
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TA-B-C
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Capture
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To illustrate, let’s see what happens when there’s a small delay defect on node A…
• Standard transition delay ATPG will most likely target this fault along the shortest path, path A-B.
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• Because the slack is so large relative to the defect delay, there’s enough time for the transition and
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so the small delay defect is not detected.

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• However, Slack-Based ATPG will target the fault along the longest path, path A-B-C.
• This time, the slack is less than the defect delay, so there’s not enough time for the transition and
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there’s a much better chance to detect the fault through this path.
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This is the way Slack-Based ATPG works….

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TetraMAX Workshop
How Are Delay Defects Distributed?
9
Delay Defect Distribution
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Tighter timing needed

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to cover these
Number of Devices
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6
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4 Cycle
Time Covered by transition
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3
testing
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2
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0
4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46
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Additional Delay (ns)
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Source: IBM for 0.45um technology
P. Nigh and A. Gattiker, “Test Method Evaluation Experiments &
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Data,” ITC, Oct. 2000.
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TetraMAX Workshop
TetraMAX Slack-Based Transition ATPG
SDC,
 One-pass flow SDF,
Exceptions
Parasitics
 Slack-based ATPG for small delay
defects
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PrimeTime
 Standard transition delay ATPG for
larger delay defects
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Pin Slacks
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Uses PrimeTime
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
 Industry’s de-facto sign-off timing TetraMAX
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engine Slack-Based ATPG
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 No design or DFT changes required Transition and
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Small Delay Reports,
Defect Patterns Histograms
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TetraMAX Workshop
Cell-Aware Test
 Increases defect coverage, especially Example of a Complex Cell

for complex cells
 Enhances diagnostics accuracy
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Traditional test
targets inter-cell
 Supports flexible ATPG flows faults on pins
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 Cell- or instance-based
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 Inter-cell + intra-cell patterns
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 Stuck-at and transition delay
Traditional test might
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not cover defects like
this inside the cell
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Unlike standard ATPG, cell-aware ATPG explicitly target faults inside cells (intra-cell faults).
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• It complements existing inter-cell fault models, so it can be thought of as yet another way to
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increase defect coverage and lower DPPM. It can be applied to any design to increase defect
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coverage—especially if it has complex cells—and enhance diagnostics accuracy.

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• The cell-aware ATPG flows are highly flexible. For example, you can use cell-aware ATPG on
specific cells or instances in a design.
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• One possible flow is to first run TetraMAX ATPG using inter-cell models. Then, after fault-
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simulating those patterns using intra-cell models, perform incremental ATPG using intra-cell
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models.
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• You can use it for both stuck-at and transition delay testing.
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TetraMAX Workshop
Slack-Based Cell-Aware Test
 Combines the best of both
Detect Faults Inside Cells Detect Faults on Longest Paths
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VDD
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TetraMAX Workshop
Z01X Cell-Aware Fault Simulation
 Z01X is a separate Synopsys fault Z01X Cell-Aware Flow

simulation tool
 Can boost defect coverage with PrimeTime Timing
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Slacks
functional patterns
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 Z01X fault simulates functional TetraMAX II ATPG
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patterns to measure cell-aware fault Cell Test
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coverage Models
 Also measures coverage of other fault Z01X Fault Simulation
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types
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 Reuses cell-aware fault models and Coverage Reports
fault list from TetraMAX
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Reports aggregate fault coverage
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
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TetraMAX Workshop
Path Delay Fault Model
 Transition launched at the start of a specified path

 Transition must be able to propagate along the path
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 The entire specified path is considered as the Path Delay “fault”
Huge number of possible circuit paths
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
Specific Paths extracted from STA
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
Cumulative effect of
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all defects along path
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Test along a
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0 1 0
specific path
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TetraMAX Workshop
Bridging Fault Models
 Static Bridging Aggressor

 Bridge fault is static in nature
 Aggressor node will override the value on the 1 0
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victim node 1
1
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 Stuck-At fault Model used for victim with aggressor
forced to 1/0
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0
Dynamic Bridging 0
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
0 1
 Bridge fault is dynamic in nature
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 Victim node too slow for the rated clock speed
Victim
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because of aggressor node effects
 Transition Fault Model used for victim with
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aggressor forced to 1/0
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Fault Models
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Delay Testing
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TetraMAX Workshop
At-Speed Fault Models
 Transition Delay
 Standard Transition Delay (targets medium to large delay defects)
 Slack-Based Transition Delay (targets small delay defects)
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 Path Delay
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 Setup Time Fault
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 Hold Time Fault
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 Dynamic Bridging
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 Faults are targeted as STR and STF
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 STR --- Slow to Rise
 STF --- Slow to Fall
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The Transition Delay fault model models the behavior of defects that cause individual nets or gates
to Transition too slowly. The defects are assumed large enough so that an incorrect value is sampled
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at any flip-flop.
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Transition Delay faults target point defects that can cause an At-Speed failure. Examples of point
defects include a bad metal contact, or a partially defective gate oxide. Transition delay tests can
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provide good At-Speed coverage of gates that are not on a critical path. Path Delay faults may
catch some point defects, but specifically target systematic defects.
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Transition Delay Testing

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faults are associated with a library cell

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each node has a slow-to-rise/slow-to-fall site

targets point defects
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Path Delay Testing

faults are associated with a path
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targeted paths typically include “critical” paths

targets process-oriented defects
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TetraMAX Workshop
Structured At-Speed Fault Testing
 At-Speed Test Pattern

 Uses existing scan chains
 Scan load a known circuit state (V1) to prepare for launching a transition at the
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target fault site
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 Scan shifting can be done at a slower speed
Pulse clock to launch Transition (V2)
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
Second pulse captures effect of Transition
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
 At-Speed cycle time between clocks
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V1 V2
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CLK
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The principle of detecting a delay fault consists in applying a Transition to the fault site and, after a
specific time (your At-Speed, functional, clock period), measuring the effect of that Transition in
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the design.
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In this timing diagram, TetraMAX will first put the design in a known state using the V1 vector.
Then it will apply the Transition at the fault site; this is achieved using the V2 vector. (V2 vector
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initiates the Transition at the head of the path.)

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After one period of an At-Speed clock, TetraMAX will measure the effect of the Transition on the
design. This effect must correctly propagate to a PO or a scan flop in order to not have a delay
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problem in your design.

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Note that the only “critical” time is the time between V2 and the capture clock edge (symbolized by
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the green arrow). All other operations can be done using the classical test clock, which typically has
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a slower period.
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The tester will use two time sets (i.e. Waveform Tables in TetraMAX) and it changes the timesets
on the fly. (Note: Inexpensive testers can have poor accuracy, and the placement of the pulse is
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TetraMAX Workshop
 Transition Delay – launch method controlled by:

set_delay –launch last_shift|system_clock|extra_shift|any
 last_shift
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 Uses the last clock pulse of load_unload as the launch
system_clock
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
Uses system clock pulses for launch (default)
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
 extra_shift
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 Launch the transition with a fast OCC shift pulse after the slow shift
any
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
Allows any of the methods to be used for launching the fault
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
 Path Delay – No direct control over the launch method
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 Fast-Sequential Path Delay: always uses system_clock launch
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 Full-Sequential Path Delay: can avoid last_shift launch by constraining ScanEnable
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Fast-Sequential Path Delay: always uses system_clock launch
Full-Sequential Path Delay: constrain ScanEnable to it’s inactive state during capture to avoid
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last_shift launch (add_pi_constraint 0 test_se)

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TetraMAX Workshop
Transition Launch Methods
system_clock Launch (default) last_shift Launch
SE inactive SE active inactive

At-Speed testing time At-Speed testing time
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CLK CLK
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launch capture launch capture
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extra_shift Launch
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SE active inactive
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active inactive
Internal Pipelined SE
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At-Speed testing time
CLK
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Slow Shift Last Slow Shift launch capture
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The system_clock launch is easier to use because it does not require SE switch between
launch and capture.
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By default, the system_clock launch mode uses a two-clock ATPG engine. (This is similar to
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the basic_scan engine but with capture_cycles =2)

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If you can use last_shift launch, you definitely can use system_clock Launch.
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TetraMAX Workshop
system_clock Launch (Default)
set_delay -launch_cycle system_clock

 PI's are changed at the beginning of each capture cycle
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Capture Transition
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Launch Transition
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Vector Shift Shift Shift Capture Capture Shift Shift Shift
Load_unload Load_unload
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Apply PI's for Launch Apply PI's for Capture
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set_delay –launch_cycle system_clock
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A selection of system_clock results in a capture clock procedure being used to launch the
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Transition and a second capture clock procedure is used to observe it.

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Use of system_clock will enable you to also generate Fast-Sequential patterns with the -
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capture_cycle option of the set_atpg command.

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TetraMAX Workshop
system_clock Launch: Example
ATPG controls load and capture
SI STR fault
values to SO
launch a transition
Scan Chain
X Don’t Care
X A A A
X X X
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1 B X B B
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1 0 1 1 X 1
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D D D
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1 C X C C
X 0 1
0 1 X
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After Nth shift V2 vector SE=0
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V1 vector SE=0 Capture clock
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SE = 1 Launch clock
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This example shows a STR fault at the output of the AND gate. (To test a STR fault on this pin, the
tool must use a two pattern sequence which will change the value from a ‘0’ to a ‘1’).
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For system_clock, launching the ‘0’ to ‘1’ Transition (launch) at the fault location happens by the
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launch clock after the Scan Enable has gone low.

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On the last shift, the inputs of the AND gate are ‘1’ and ‘0’, which means that the output is ‘0’. The
initial state on the output of AND gate has been achieved. The next step is to launch the fault.
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Take a note on the functional pins of flops “B and C” driving the AND gate; both are at value ‘1’.
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Pulsing the clock driving these flops, causes the output of the AND gate to ‘1’ and initiates the
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launch of the fault.

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Immediately after the launch, the capture clock is pulsed, which captures the Transition on the
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functional pin of D flop.

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The launch and the capture happens with Scan Enable inactive.
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TetraMAX Workshop
system_clock Launch: Details
 Patterns generated primarily using a dedicated (two clock) algorithm

 Generation is fast and efficient in terms of coverage, runtime and pattern count
 Fast-Sequential or Full-Sequential ATPG can also be used
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 If set_atpg –capture <n> is set where n>2, then a Fast-Sequential pass is
performed
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The ScanEnable timing does not affect the capture operation, it is
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
constrained to its inactive state
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 At-Speed timing for external clocks can be defined by the user in
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special WaveFormTable (WFTs) in the SPF
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 Most commonly used At-Speed launch method
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Note: run_atpg –optimize_patterns supports the two-clock ATPG engine
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Additional Delay Test Cycles
 Setup Cycles
 Precede launch cycle
 Get V1 values to non-scan devices
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 Propagation Cycles
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 Follow At-Speed capture cycle
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 Get fault effect to an observation point
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 These are slow cycles and their WFT is the same as what is defined in
the _multiclock_capture_WFT
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With On-Chip Clocking the additional cycles are fast pulses
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
SE
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Shift Cycles Setup Cycles L C Propagation Cycles
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CLK
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For Fast and Full sequential ATPG, there can be additional cycles that may be needed to set up the
fault detection.
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For example, extra clock cycles are needed to pass values through a non-scan element or when
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detecting faults around the shadow of the memory (i.e. when propagating values through the
memory.)
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Once the capture clock arrives, additional cycles may also be needed to propagate the fault to a scan
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flop or to the output.

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These extra cycles use the WFTs that are defined for their capture in the SPF file.
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TetraMAX Workshop
last_shift Launch

 PI’s are changed at the beginning of the capture cycle
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Capture Transition
Launch Transition
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SE
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CLK
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Shift Shift Shift Shift Capture Shift Shift Shift Shift Shift Capture Shift Shift
Load_unload Load_unload
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Apply PI's for Launch Apply PI's for capture
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For the Transition fault model, this specifies how the Transition is launched. A selection of
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last_shift results in the Transition being launched on the last shift clock of the scan chain
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load. A capture clock procedure is then used to observe the Transition.

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TetraMAX Workshop
last_shift Launch: Example
ATPG controls load values
SI STR fault
to launchSO
a transitionSI SO
Scan Chain
X Don’t Care
X A A A
X
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1 X
X B
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B B
1 0 1 1 X 1
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D D D
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X C C C
X 0 1
0 1 X
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N - 1 shift Nth shift Capture Mode
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V1 vector V2 vector SE = 0
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SE = 1 SE = 1 Capture clock
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Launch clock
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This example shows a STR fault at the output of the AND gate. (To test a STR fault on this pin, the
tool must use a two pattern sequence which will change the value from a ‘0’ to a ‘1’).
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This AND gate is in between some flops. These flops (A,B,C,D) are part of a scan chain, shown as
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dotted blue line.

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The ‘0’ to ‘1’ Transition (launch) at the fault location has to happen on the last shift.
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On the N-1 shift, the values on the input of the AND gate are ‘1’ and ‘0’. This gives the V1 vector.
The output is now low. At this time notice the value of flop “A”. Since it creates the Transition, it
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has a value of ‘1’.

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On the Nth shift, the output of the AND gate changes to ‘1’ - that is the fault has been launched.
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After the launch the SE goes low. Scan chains are no longer present. The capture clock comes in the
first tester cycle and captures the Transition on the functional pin of flop D.
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If a ‘0’ is captured at flop D, then there is a fault - otherwise there is not.

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TetraMAX Workshop
last_shift Launch: Details
 Patterns are generated using Basic-Scan ATPG engine

 Generation is fast and efficient in terms of coverage, runtime and pattern count
The STA should ensure that the Scan Enable is fast enough to not affect
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
the capture operation
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 Pipelining ScanEnable can help
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 Critical timing for the ScanEnable requires special tester control
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 Not a commonly used launch method
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TetraMAX Workshop
extra_shift Launch: Details
 Set the launch cycle before run_drc

 Different clock matrix checking for the launch cycle
 Only launching clock needs the extra shift
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 Better coverage
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 Patterns are generated using two_clock algorithm
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 Fast and full sequential ATPG can be used
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 Requires pipelined ScanEnable
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 Separate for each clock domain and edge
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 Can be added by insert_dft
 Both OCC controller and clock chain need non-pipelined ScanEnable
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TetraMAX Workshop
Pipelined ScanEnable
D Q D Q D Q D Q
SI QB SI QB SI QB SI QB
SE SE SE SE
 Launch on shift clock requires the >CK >CK >CK >CK
ScanEnable to transition from 1 to 0

At-Speed SE
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D Q PipelineSE
 Scan enable net has a high load QB
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>CK
 Due to high load, it is sometimes not
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LOSPipelineEnable
possible to meet timing
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 Pipelined ScanEnable can be used LOSPipelineEnable
with launch on last_shift or
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Clock
extra_shift
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SE
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PipelineSE
PI data
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Scan In
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Pipelining scan enable allows a full cycle for the internal scan enable to propagate to the scan
registers. Without pipelining, you have less that a cycle for the external scan enable to propagate
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and also the added input delay from the pad to account for.
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At-Speed Faults
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At-Speed Launch Modes
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Delay Testing
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TetraMAX Workshop
STIL Protocol File Timing
 DFT Compiler generates the SPF with only a single timing setup
 Multiple WaveFormTables (WFT’s) all with the same timing
The default SPF timing provided works ‘as-is’ for Stuck-At, Static
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
Bridging, IDDQ, and OCC-based At-Speed testing
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 Only need to modify the WFT’s timing when external clocks are used for
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At-Speed testing
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 The same protocol file can be used for both Stuck-At and At-Speed
ATPG
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To generate a SPF from TetraMAX that included all_clock_* procedures:
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set_faults –model transition

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write_drc_file <file name>

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TetraMAX Workshop
Allclock Capture Procedures
 Only system_clock launch patterns with external clocks use allclock_*

capture procedures
 Note: patterns that only pulse OCC clocks use the multiclock_capture
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procedure
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 allclock_launch {}: applied to tagged launch operations in
launch/capture contexts only
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 allclock_capture {}: applied to tagged capture operations in
launch/capture contexts only
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 allclock_launch_capture {}: applied to tagged launch-capture
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operations only (single-cycle At-Speed tests)
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The all_clock_* capture procedures are referred to a “tagged” procedures. A tagged procedure
is one that is called by TetraMAX for a specific purpose.
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TetraMAX Workshop
allclock_*{} Procedures Example
"allclock_capture" { "allclock_launch_capture" {
W "_allclock_capture_WFT_"; W "_allclock_launch_capture_WFT_";
F { F {
"i_scan_block_sel[0]" = 1; "i_scan_block_sel[0]" = 1;
"i_scan_block_sel[1]" = 1; "i_scan_block_sel[1]" = 1;
"i_scan_compress_mode" = 0; "i_scan_compress_mode" = 0;
"i_scan_testmode" = 1; "i_scan_testmode" = 1;
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} }
V { V {
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"_po" = \r168 #; "_po" = \r168 #;
"_pi" = \r179 #; "_pi" = \r179 #;
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} }
} }
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"allclock_launch" {
W "_allclock_launch_WFT_";
F {
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...
}
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V {
"_po" = \r168 #;
"_pi" = \r179 #;
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}
}
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TetraMAX Workshop
WFTs for External System Clock Launch
WaveformTable "_allclock_launch_WFT_" {
Period ’40ns’;
65 ns Waveforms {
15 ns "CLK1" { P { ’0ns’ D; ’5ns’ U; ’10ns’ D; } }
40 40 "CLK2" { P { ’0ns’ D; ’30ns’ U; ’35ns’ D; } }
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"_default_In_Timing_"{01ZN {’0ns’ D/U/Z/N; } }
"_default_Out_Timing_"{X {’0ns’ X; } }
5 10 30 35
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"_default_Out_Timing_" { HLT { ’0ns’ X; ’4ns’ H/L/T; } }
CLK1 }
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}
30 35 5 10 WaveformTable "_allclock_capture_WFT_" {
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Period ’40ns’;
CLK2
_allclock_launch_WFT_ _allclock_capture_WFT_ Waveforms {
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"CLK1" { P { ’0ns’ D; ’30ns’ U; ’35ns’ D; } }
"CLK2" { P { ’0ns’ D; ’5ns’ U; ’10ns’ D; } }
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"_default_In_Timing_"{01ZN {’0ns’ D/U/Z/N; } }
"_default_Out_Timing_"{X {’0ns’ X; } }
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CLK1 has an effective cycle time of 65ns "_default_Out_Timing_" { HLT { ’0ns’ X; ’4ns’ H/L/T; } }
CLK2 has an effective cycle time of 15ns
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}
}
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The WFT period does not need to be At-Speed
• Just need to ensure that there’s an At-Speed relationship between the launch and capture pulses
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• WaveFormTable timing is changed in consecutive cycles

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• Launch pulse can be at the beginning or end of the cycle

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• Capture pulse can at the beginning or end of the cycle

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Ensure that the strobe timing is before the clock

• The strobe timing must be earlier in the cycle than the active edge of all the external clocks
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WFTs for External Clock Last Shift Launch
Timing { Timing {
WaveformTable "_default_WFT_" { Original Modified
WaveformTable "_default_WFT_" {
Period '100ns'; Timing Period '100ns'; Timing
Waveforms { Waveforms {
"all_inputs" {01Z {'0ns' D/U/Z;}} "all_inputs" {01Z {'0ns' D/U/Z;}}
"all_outputs" {X {'0ns' X;}} "all_outputs" {X {'0ns' X;}}
"all_outputs" {HLT {'0ns' X; '40ns' HLT;}} "all_outputs" {HLT {'0ns' X; '40ns' HLT;}}
"pci_Clk" {P {'0ns' D; ‘45ns' U; ‘55ns' D;}} "pci_Clk" {P {'0ns' D; '90ns' U; '95ns' D;}}
} }
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} }
WaveformTable "_multiclock_capture_WFT_" { WaveformTable "_multiclock_capture_WFT_" {
Period ‘100ns'; Period ‘100ns';
Waveforms { Waveforms {
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"all_inputs" {01Z {'0ns' D/U/Z;}} "all_inputs" {01Z {'0ns' D/U/Z;}}
"all_outputs" {X {'0ns' X;}} "all_outputs" {X {'0ns' X;}}
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"all_outputs" {HLT {'0ns' X; '40ns' HLT;}} "all_outputs" {HLT {'0ns' X; '8ns' HLT;}}
"pci_Clk" {P {'0ns' D; ‘45ns' U; ‘55ns' D;}} "pci_Clk" {P {'0ns' D; '10ns' U; '15ns' D;}}
} }
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} }
}
}
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_default_WFT_ _multiclock_capture_WFT_ _default_WFT_
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20ns
pci_Clk = 20ns
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90 95 90 95 10 15 90 95
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100 ns 100 ns 100 ns 7- 40
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The delta between rising edges of clock in the Shift WFT and the capture WFT should be equal to
the period of the system clock
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TetraMAX Workshop
Preambles and Postambles
 Defining load_unload procedure

 Uses the slow timing waveform
 Avoid Postamble if using last_shift launch
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"load_unload" {
W "_default_WFT_";
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// preamble vectors
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Shift {
V { "BPCICLK"=P; “pci_CLk"=P; "Test_mode"=1;
"nReset"=1; test_sei"=0; "_so"=###; "_si"=###; }
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}
// postamble vectors
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}
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Preamble and postamble vectors are often seen in scan-through-TAP designs.
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TetraMAX Workshop

 List several fault models supported by TetraMAX
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 Describe At-Speed defects
Describe two popular fault models for At-Speed
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
testing
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Describe three different way to launch an At-Speed
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
transition for delay testing
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 Modify the default STIL Protocol File (SPF) written
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out from DFT Compiler to support At-Speed ATPG
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TetraMAX Workshop
set_delay -launch_cycle Launch delay fault transitions on the last scan shift
last_shift
set_delay -launch_cycle Launch delay fault transitions during capture
system_clock
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set_delay -launch_cycle Launch delay fault transitions with an OCC shift
extra_shift
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set_delay -launch_cycle any Launch delay fault transitions with any method
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multiclock_capture { } Capture procedure used for Stuck-At ATPG and
delay testing with OCC clocks
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allclock_capture { } Capture procedure for capturing an At-Speed
transition with system_clock launch patterns
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allclcok_launch { } Capture procedure for launching an At-Speed
transition with system_clock launch patterns
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allclock_launch_capture { } Capture procedure for single cycle At-Speed
testing with system_clock launch patterns
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Agenda
DAY
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At-Speed Constraints ©2018 Synopsys, Inc. All Rights Reserved. 8-1

TetraMAX Workshop
Unit Objective
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 List sources of timing exceptions
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 Read SDC from PrimeTime to import timing exceptions
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in TetraMAX
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 Handle the slow ports and Bidi’s of your designs
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 Use Power-Aware ATPG to reduce switching activity
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during At-Speed testing
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TetraMAX Workshop
At-Speed Constraints
 Running a design at its functional rated speed in scan mode creates

issues that need to be considered by ATPG – such as:
 Some paths cannot meet timing in a single At-Speed cycle
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 Excessive switching activity during At-Speed scan testing may cause power
issues
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 Paths that cannot meet timing can be accounted for with Timing
Exceptions (i.e. design constraints)
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 Excessive switching activity during At-Speed scan testing can be
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controlled using Power-Aware ATPG
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TetraMAX Workshop
At-Speed Constraints: Agenda
Timing Exceptions
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Using SDC In ATPG
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Power-Aware ATPG
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TetraMAX Workshop
Timing Exceptions
 Design attributes that impact the generation of valid At-Speed patterns:

 Slow ports (inputs, outputs and bidirectionals)
 False and multi-cycle paths
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 Inter-clock domain paths
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 If Timing Exceptions are not defined, At-Speed patterns may fail SDF-
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based simulation and/or on the ATE because of timing issues
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 Timing Exceptions affect the test coverage
They cause X’s in the design during ATPG due to masking
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
 Verify each timing exception is really needed
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 More of an impact for Scan Compression architectures (especially if high x-
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tolerance mode is not used)
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TetraMAX Workshop
Slow Ports
 Slow Inputs: PI’s cannot switch at functional clock speed

set_delay –nopi_changes
Slow Outputs: PO’s cannot be strobed at functional clock speed
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
set_delay –nopo_measure
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 Bidirectional loopback test can fail
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add_slow_bidis
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 Output of the BUS primitive goes to X when BIDI is in
output mode
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Combo
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Logic
X Disables the path in red when
BUS
FLOP
propagating a Transition along
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Combo the path in green
Logic
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BIDI
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Using “set_delay –nopi_changes” introduces one dead cycle between the last shift and the launch
clock for system_clock launch patterns.
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Refer to the following SolvNet Article for more details:

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Unclocked cycle in transition ATPG patterns

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TetraMAX Workshop
Slow Cells
 Cells that drive multi-cycle or false paths can be called “slow cells”
 Specified with the add_slow_cells command
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 Can be set on scan or non-scan elements
A transition launched from these cells will be simulated as an X
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
add_slow_cells <instance_path>
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For Basic-Scan ATPG, the output is masked if there is a transition on the last-shift cycle. For Fast-
Sequential or Full-Sequential ATPG, the output is masked if there is a transition on any ATPG clock
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TetraMAX Workshop
Timing Exceptions
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Using SDC in ATPG
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Power-Aware ATPG
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TetraMAX Workshop
Timing Exceptions with an SDC file
 Multi-cycle and false paths are identified in the Synopsys Design

Constraints (SDC) file from Design Compiler or PrimeTime
 To read an SDC file into TetraMAX:
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read_sdc <file_name>
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 By reading the SDC, TetraMAX can apply the same timing exceptions
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during ATPG
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 By default, timing exceptions from the SDC are only honored during At-
Speed testing
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 Timing exceptions can be honored during Stuck-At testing with the
following command:
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set_simulation –timing_exceptions_for_stuck_at
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The set_sdc command can be used to control how the timing exceptions are interpreted by
TetraMAX.
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The report_sdc command can be used to report the timing exceptions that were read by
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TetraMAX Workshop
Exception Types
 TetraMAX supports both Setup and Hold exceptions

 Use command set_sdc to control which type of exceptions are
honored
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set_sdc [-setup|-nosetup] [-hold|-nohold]
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 If both –setup and -hold exceptions are enabled
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 If there is no type specified in the SDC, both exceptions are applied
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set_false_path –to iq_reg/D
Otherwise only specified exception is applied
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
set_false_path –to iq_reg/D -setup
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TetraMAX Workshop
Simulation of Timing Exception During ATPG
FF1 FF2
D Q D Q
SI QB
SI QB
SE
SE
>CK
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>CK
set_false_path-to FF2/D
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CK
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D
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Q (normal)
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Q (-setup)
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Q (-hold)
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Q (both)
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TetraMAX Workshop
Reading SDC
 All legal SDC commands can be read by read_sdc

 Does not support non-SDC commands (i.e. regular PrimeTime Tcl commands)
Reading an SDC is supported only in Tcl mode
ng

 Some TetraMAX Tcl API commands are also valid SDC commands: get_clocks,
ni
get_pins, etc.
ai
 SDC commands affecting Clocks (Propagation)
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 create_clock, create_generated_clock, set_case_analysis
SDC commands affecting ATPG
ip

set_false_path, set_multicycle_path, set_disable_timing,
ch

set_case_analysis, set_clock_group
ro
 Other SDC timing constraint commands are ignored
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 set_clock_uncertainty, set_output_delay
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Note: SDC commands are NOT shell commands
- If the SDC file was read in PT with read_sdc, then the file should only contain SDC
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commands
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- If the SDC file was “sourced” in PT, then the SDC file may also contain regular PT Tcl
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commands that will not be allowed by TetraMAX

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TetraMAX Workshop
Supported SDC Clock Constructs
create_generated_clock
set_clock_groups –multiply_by … –source
–async {CLKA}
CLKA
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CLKB OCC
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PLL
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RAM
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create_clock
-name CLK
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–period 100
ch
–waveform {45 55}
CLK
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In summary:
create_clock defines the clock period and timing for all clock sources.
er
nt
set_clock_group defines relationship between different clocks. Used to specify clock groups
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that are mutually exclusive or asynchronous with each other in a design so that the paths between
these clocks are not considered during timing analysis or at speed testing. Options such as –
Fo
asynchronous or –exclusive will, in effect, create false_path information between different the
clock domains.
se
create_generated_clock can be used to create internally generated clocks based upon other
U
master clocks.
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TetraMAX Workshop
Supported SDC Exceptions
set_multicycle_path
CLKA (across a path)
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CLKB OCC
set_false_path
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PLL
-from …
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-to … RAM
(across a path)
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set_case_analysis 1
ch
test_mode
set_disable_timing
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(across a single arc)
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set_false_paths defines paths which are not timed or tested.
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set_case_analysis can be used to drive a signal to a constant state such as test_mode.

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Similar to set_dft_signal –type constant.

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set_disable_timing does what the name implies. It will disable a timing arc.
Fo
set_multicycle_path defines a path which propagates data in, typically, more than one clock
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cycle. The idea is that data through this path will likely be unknown until X-many cycles have
gone by. It is typically an X-generator.
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TetraMAX Workshop
Controlling Clock Propagation
set_sdc –environment none|sdc_case_analysis|tmax_drc
create_clock in SDC
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add_clocks in TetraMAX or SPF
ni
ai
Tr
 Clocks can be defined in the SDC file, in TetraMAX (SPF or add_clocks
ip
command), or both
ch
 With the default setting of none, both “Functional Clock” and “Test
ro
Clock” will be considered to propagate through the mux so SDC
ic
exceptions that refer to either clock will be honored
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Note:
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With a setting of set_sdc –environment sdc_case_analysis, only clocks that

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propagate based on the set_case_analysis commands in the SDC will be honored. In the
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above example, only SDC exceptions that refer to the “Functional Clock” would be honored by
TetraMAX, since that’s the only clock that is able to propagate through the mux based on the
Fo
set_case_analysis command.
se
Likewise, with a setting of set_sdc –environment tmax_drc, only clocks that propagate
based on the TetraMAX PI constraints will be honored. In the above example, only SDC exceptions
U
that refer to the “Test Clock” would be honored by TetraMAX, since that’s the only clock that is
able to propagate through the mux based on the add_pi_constraint command.
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TetraMAX Workshop
SDC Timing Exception Example
 SDC generated for functional mode might have:

set_false_path –from [get_clocks functional_clock_1] \
-to [get_clocks functional_clock_2]
ng
 Neither of these clocks are used for scan shift or capture, so they are
ni
not TetraMAX clocks
ai
 This exception will be honored in TetraMAX by specifying:
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set_sdc –environment sdc_case_analysis | none
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TetraMAX Workshop
Functional Mode Vs Test Mode
 Focus of SDCs are often for functional or mission-mode timing

 In other words, the normal “in system” environment in which the chip will be
running
ng
 For manufacturing testing, the environment can be very different
ni
 Synchronization – everything fits into a tester cycle
ai
 Operational speeds – scan shifting and static defect detection is slower that
functional speed
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 Test head effects – input drives/slew and output loads/strobes are very different to
ip
the application environment
ch
 Controlled environment – testers work at set temperatures and voltage supply
levels
ro
This is therefore a completely different STA environment!
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SolvNet article ID: 019765 - TetraMAX at-speed timing exceptions for a complex clocking flow
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TetraMAX Workshop
Test Mode Timing
 Must run full chip Static Timing Analysis (STA) in scan test mode (ATPG
mode)
 STA should be configured to match the environment on the ATE (timing
ng
and loads)
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 All the Test-Modes and Test-Operations should be verified:
ai
 Scan Shift (used for both Stuck-At and At-Speed testing)
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 Stuck-At Capture (slow speed capture)
 At-Speed Capture
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Design must pass full-chip STA in Test mode (ATPG mode) with sign-off
ch

accuracy
ro
ic
8- 18
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When we begin the discussions about at-speed test generation, we need the designer to consider the
operating environment of the tester. There may be new constraints to deal with in this environment.
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Test Mode Timing handle

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Functional Timing Mode can lead to missing constraints

Broken scan chains
Fo
Missing timing exceptions

Unconstrained test logic – OCC, Scan Compression etc.
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Functional Timing Mode can lead to over-constraints

Timing Exceptions are used for Synthesis
U
Some Timing Exceptions may be removed

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New violating paths appear only in Test Mode

Misalignment of Timing Exceptions and timing constraints
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Testable paths becomes untestable

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Un-testable paths could be testable

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There needs to be some way to simplify and automate this process

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TetraMAX Workshop
Timing Violations in Test Mode
 SDC is usually developed for Mission Mode

 Functional timing can be very different from ATPG timing
 Often set_case_analysis can prevent STA timing of many paths used by
ng
ATPG
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 Result: Too many STA timing exceptions that create X’s in ATPG, but real ATPG
timing violations are missed
ai
Possible solution: Generate new SDC based on violations found by STA
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
using ATPG timing
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ch
TetraMAX at-speed timing exceptions for a complex clocking flow
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Timing Exceptions From Violations Flow
TetraMAX
source tmax2pt.tcl
run_drc at_speed.spf
1. In TetraMAX: source write_timing_constraints capture.tcl \
tmax2pt.tcl -mode capture \
-wft _allclock_launch_WFT_ \
ng
write_timing_constraints \
–mode capture -wft _allclock_capture_WFT_
capture.tcl
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2. In PrimeTime:
PrimeTime
ai
a) Use timing from source pt2tmax.tcl
Tr
tmax2pt.tcl output source capture.tcl
write_exceptions_from_violations \
b) Source pt2tmax.tcl -output exceptions.sdc
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write_exceptions_from_violations
ch
TetraMAX exceptions.sdc
3. TetraMAX: Read new SDC set_sdc -environment tmax_drc
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from pt2tmax using read_sdc exceptions.sdc
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set_sdc –environment tmax_drc …
8- 20
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1. In TetraMAX
a) Run run_drc
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b) Run tmax2pt.tcl procedure

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write_timing_constraints –mode capture

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2. In PrimeTime
a) Use timing from write_timing_constraints output script
Fo
b) Run pt2tmax.tcl procedure write_exceptions_from_violations

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3. Re-run TetraMAX
a) Use set_sdc –environment tmax_drc
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b) Read new SDC from write_exceptions_from_violations (but not

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functional SDC and not SDC from write_timing_constraints)

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Fine Tuning the SDC Flow
 To disable a group of exceptions

set_sdc [-nocase_paths –nofalse_paths \
-nodisable_paths -nomulticycle_paths …]
ng
 Prepend the specified instance path to all instances in the SDC file
ni
set_sdc –instance <instance_path>
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 For more verbosity during read_sdc
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set_sdc –verbose
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 To control the length of multi-cycle paths
ch
set_delay –multicycle_length <d>
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TetraMAX Workshop
Report SDC Exceptions
 Report SDC Constraints

report_sdc # Report SDC objects
-clocks # Report clocks
ng
-to_cells # Report to cells
-groups # Report clock groups
-case_analysis # Report case analysis
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-false_paths # Report false paths
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-multicycle_paths # Report multi-cycle paths
-case_paths # Report case analysis paths
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-disable_paths # Report disable timing paths
-all_paths # Report all paths
ip
 This command may be used to report on how the SDC timing
ch
exceptions were interpreted by TetraMAX and for debug
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TetraMAX Workshop
Identifying AU Faults Caused by SDC Timing Exceptions
 SDC timing exceptions identify paths that are not expected to meet
single cycle timing and will be masked in TetraMAX
 These masks will cause some faults to be untestable (AU)
ng
 The following command can be used to identify faults that are AU due
ni
to SDC timing exceptions
ai
set_atpg –timing_exception_au_analysis
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 The AU faults identified are only reported separately when the
set_faults -summary verbose command has been set. They will
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appear in the fault summary report under the AX subclass of faults
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TetraMAX Workshop
Timing Exceptions
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Using SDC in ATPG
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Power-Aware ATPG
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TetraMAX Workshop
Scan Testing is Power-Hungry
Up to 10X Peak Levels of Normal Operating Mode
Switching Activity
70%
Power spikes can
affect at-speed tests
60%
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50%
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40%
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30%
20%
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ch
10%
0%
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0 50 100 150 200 250
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Pattern Number
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This is a plot of flop switching activity vs. pattern number during scan testing. Notice the peaks;
they can produce up to 10 times the peak power in a device compared with its normal operating
er
mode.
nt
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Exceeding the power limits of a design can lead to yield loss and slows test program ramp-up
because too much power consumption can damage devices or cause false failures. It can also be
Fo
very difficult and time-consuming to trace these problems back to excessive power consumption.
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Today’s nanometer designs are more susceptible to power problems during test because these power
spikes can affect the outcome of at-speed tests.
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Power Problems During Shift Mode
 Excessive peak power

 IR-drop delays prevent scan data
ng
from shifting at target frequency
Excessive average power
ni

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 Hot spots damage device or
drive it out-of-spec
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 Ad hoc “solution”
ip
Reduce scan shift frequency
ch

Functional
Test
(adds more tester time)
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Too much power consumption affects test in different ways depending on whether a device is
shifting in the patterns or capturing the responses.
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During shift mode, excessive peak power can produce IR-drop delays that prevent scan data from
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shifting at the target frequency. That’s what we’re seeing in the red region of this graph of peak IR-
drop in a device.
Fo
Also during shift mode, excessive average power can create hot spots that damage a device or drive
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it out-of-spec.
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Both these problems could be addressed by reducing the scan shift frequency on the tester, but this
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adds more tester time and increases tester execution cost.

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TetraMAX Workshop
Low-Power (i.e. Adjacent) Fill
 Enable low-power fill during scan shift

set_atpg –fill adjacent
ng
ADJACENT-FILL 0 0 0 0 1 1 1 transition
RANDOM-FILL 0 1 0 0 1 0
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CARE BITS 0 · · 0 1 · 4 transitions
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SCAN_IN
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CLK
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Up to 50% Reduction in Average Test Power
ch
 Generate chain tests with limited switching activity
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set_atpg -quiet_chain_test | -noquiet_chain_test
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8- 27
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Typically, only a small fraction of the bits in a pattern are actually needed to detect target faults.
These are called “care bits.”
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nt
We see that random-filling the other bits causes a lot of switching…

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But low-power fill replicates care bits as far as possible down the scan chain, and this results in
Fo
much less switching and up to a 50% reduction in average test power during shift mode.
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There is a command to control the “effort” level when attempting to reduce shift power:
U
set_atpg -shift_power_effort <low | medium | high | number>

ed
This option enables you to reduce switching activity. The arguments specify a relative level of
effort for reducing switching activity. You can use the number argument to specify a number
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between 1 and 100. The lower the specified number, the more effort will be applied to reducing
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switching activity. The low argument corresponds to a setting of 50, the medium argument
corresponds to a setting of 30, and the high argument corresponds to a setting of 10.
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TetraMAX Workshop
Shift Power Effort and Budget
 To enable ATPG to reduce the average shift power

set_atpg -shift_power_effort <off|low|medium|high|d>
ng
 To specify a shift power budget
set_atpg –shift_power_budget <d>
ni
 Where d is the maximum percentage of scan cells that switch during shift
ai
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 To reject patterns that exceed the max shift budget, both
switches must be used
ip
set_atpg –shift_power_budget 50
ch
set_atpg –shift_power_effort high
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 If high effort is not used, patterns that exceed the budget will be kept if
ATPG can’t detect a fault without exceeding the budget
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-shift_power_effort <off | low | medium | high | d >
Specifies a relative level of effort for reducing switching activity. You can use the d argument to
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specify a number between 1 and 100. The lower the specified number, the more effort is applied to
nt
reducing switching activity. The low argument corresponds to a setting of 50, the medium argument
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corresponds to a setting of 30, and the high argument corresponds to a setting of 10. The default is
the off argument, which disables the -shift_power_effort option.
Fo
The -shift_power_effort settings do not result in an exact reduction of switching activity.

In some cases, there might not be a discernible difference in switching activity reduction, even
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though different levels are specified.

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-shift_power_budget number
ed
Sets a budget for TetraMAX ATPG to reject patterns that exceed the specified maximum percentage
of scan cells switching in a shift cycle. This option must be used with the -
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shift_power_effort option, and works only with basic scan, fast-sequential, and two-clock
transition ATPG. Set the -shift_power_budget option to 0 to turn it off, as shown in the
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following example:
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set_atpg shift_power_budget 0
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TetraMAX Workshop
Power Problems During Capture Mode
L C
CLK
 Low-power fill doesn’t limit
switching during capture
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 Excessive peak power
ng
 IR-drop delays cause “good”
V1 V2
devices to fail at-speed tests
ni
ai
Ad hoc “solutions”
80%
70%

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60%  Over-design power rails
(increases die cost)
Switching Activity
50%
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40%
30%
ch
20%
10%
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0%
0 50 100 150 200 250
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Pattern Number
8- 29
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Power problems during capture mode tend to be more difficult to debug and fix. They’re caused by
these peaks in switching activity that occur going from shift mode to capture mode when there are a
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large number of logic state transitions.

nt
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If the switching peaks are large enough, the IR-drop delays cause “good” devices to fail at-speed
tests.
Fo
The problem could be addressed by over-designing the power rails, but this increases die size and
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die cost. DFT techniques could be used to limit switching during capture mode, but they’re
cumbersome and require a lot of manual intervention.
U
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A better approach is to use power-aware ATPG to automatically reduce switching during capture
mode.
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TetraMAX Workshop
Excessive Power During Scan Capture
 Standard ATPG will attempt to target as many faults as possible

 May cause a large number Flip-Flop’s (FF) to toggle
 May exceed the design power intent or limits
ng
 May cause IR drop and unintended ATE failures, or worse, product damage
ni
 Power-Aware ATPG Uses clock-gating structures to limit switching
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 Analyzes the fanout of clock gating structures and other clock sources during
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DRC
 Uses a power budget directive for ATPG to reduce maximum number of switching
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scanable FF’s
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 Actual FF switching activity can be reported after ATPG
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TetraMAX Workshop
Capture Power with Standard ATPG
Standard ATPG
60%
Flop Switching Activity During Capture

50%
Budget reflects peak
switching activity of
ng
40% mission mode operation
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30%
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Switching
Budget
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20%
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10%
ch
0%
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0 500 1000 1500 2000 2500 3000 3500 4000 4500 5000 5500
Pattern Count
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8- 31
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This is a standard ATPG run. Each of these red dots represents the percentage of total scan flops in
the design that switch during capture mode for each pattern, and we’re including all the patterns in
er
an ATPG run.
nt
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Now let’s say we have a switching budget, about 25% in this example, that reflects the peak
switching activity of mission mode operation.
Fo
It’s apparent that standard ATPG generates a large number of patterns that exceed the switching
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budget.
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But power-aware ATPG tries to observe this budget every time it generates a test pattern….
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TetraMAX Workshop
Capture Power with Power-Aware ATPG
Standard ATPG Power-Aware ATPG
60%
Flop Switching Activity During Capture

50%
Budget reflects peak
switching activity of
ng
40% mission mode operation
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30%
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Switching
Budget
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20%
Trades off more
ip
patterns for lower
10%
switching activity
ch
0%
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0 500 1000 1500 2000 2500 3000 3500 4000 4500 5000 5500
Pattern Count

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Avoids Yield Loss from False Test Failures
8- 32
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There’s always a tradeoff between switching activity and pattern count, but the designer now has
control over it.
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TetraMAX’s power analysis summary provides the “minimum level for peak power budgeting.”
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It’s the flop fan-out of the largest independently-controlled clock domain in the design, expressed as
a percentage of total scan flops.
Fo
For more info on Synopsys Power-Aware Test solutions, see the following flash recording on
se
SolvNet:
SolvNet Article: 023940 – Complete Power-aware Test Solution
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TetraMAX Workshop
Power-Aware ATPG Commands
 Enable Power-Aware ATPG and set a budget

set_atpg –power_budget <n>
Set an effort level for Power-Aware ATPG
ng

set_atpg –power_effort <high | low>
ni
 Allow testing of asynchronous sets/resets with
ai
Power-Aware on regular scan designs
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set_atpg -power_aware_asyncs | -nopower_aware_asyncs
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 Report clock gating analysis done during run_drc
ch
report_clocks –gating
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 Report the switching activity per pattern after ATPG
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report_power –per_pattern -percentage
8- 33
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There are several other options for the report_power command:
er
report_power
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[-shift] [-capture]
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[-average] [-peak]
[-per_clock_domain]
Fo
[-per_pattern] [-per_cycle]
[-first_pattern d] [-last_pattern d]
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[-max d] [-percentage] [-csv filename]

[-module name]
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TetraMAX Workshop
Clock Gating Report
 report_clocks –gating -verbose

 Performs an analysis based upon DRC and reports the clock gating latches
associated with each clock domain
ng
 If DRC finds CG-cells transparent, then those CG cells are not reported
ni
run_drc
…
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Begin clock-gating analysis...
585 ATPG controllable clock-gating cells were found
Tr
…
report_clocks –gating -verbose
Clock name: clk (75)
ip
Number of cells directly controlled by the clock: 896 (6.65%)
Number of cells controlled by the clock through a clock-gating cell: 12562 (93.18%)
ch
Number of cells directly controlled by the clock + largest clock-gating domain:
1025 (7.60%)
Clock-Gating Latch topt4/regs/cgc6/latch (1287508) drives 12 (0.1%) scan cells
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…
Minimum Recommended Low-Power ATPG Budget: 7.60% (1025)
Estimated minimum. Don’t
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TetraMAX Workshop
Power-Aware Pattern Reporting
 TetraMAX “power (switching) analysis” command is report_power
TEST-T> report_power –percent [many available options]
ng
-------------------------------------------------------------
Power Analysis Summary
-------------------------------------------------------------
ni
Number of Scan Cells 134813
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Number of Patterns 0-2908
Cycles Per Load 2366
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Average Shift Switching 2440.84 1.81%
Average Capture Switching 5882.63 4.36%
ip
Peak Shift Switching 7190 5.33% (pattern: 2 cycle: 1)
Peak Capture Switching 10792 8.01% (pattern: 2669)
ch
To make report_power run faster, use set_atpg –calculate_power
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
before run_atpg
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8- 35
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TetraMAX Workshop
Power-Aware ATPG Script Example
read_netlist …
run_build_model
…
ng
run_drc
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report_clocks –gating [-verbose]
ai
…
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set_atpg –power_budget N
ip
set_atpg –calculate_power
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run_atpg –auto
report_power -per_pattern -percentage
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report_clocks [-gating] [-verbose]
Performs an analysis based upon DRC’s and reports the clock gating latches associated with
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each clock domain

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set_atpg [-power_budget <n>]

• Must be set prior to run_atpg
Fo
• Minimize power usage during capture cycles. It requires an integer argument identifying
the maximum percent of scancells associated with clocks which may be pulsed for a
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given cycle.
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set_atpg -calculate_power | nocalculate_power

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Improves the runtime performance of the report_power command by enabling the

ATPG process to internally calculate the switching activity of the scan flip-flops.
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report_power
[-shift] [-capture] [-average] [-peak]
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[-per_pattern] [-per_cycle] [-first_pattern <d>]

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[-last_pattern <d>] [-max <d>]

[-percentage] [-csv <filename>]
[-module <name>]
Used after patterns are generated.

TetraMAX Workshop

 List sources of timing exceptions
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 Read SDC from PrimeTime to import timing
exceptions in TetraMAX
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 Handle the slow ports and Bidi’s of your designs
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 Use Power-Aware ATPG to reduce switching
activity during At-Speed testing
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Begin Lab 8: Power-Aware ATPG
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TetraMAX Workshop
set_sdc [-setup|-nosetup] Enable or disable setup timing exceptions in SDC
set_sdc [-hold|-nohold] Enable or disable hold timing exceptions in SDC
set_sdc –environment none Use neither tmax or case analysis for clock prop
set_sdc –environment tmax_drc Use tmax DRC env for clock propagation
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set_sdc –environment Use SDC case analysis for clock propagation
sdc_case_analysis
set_sdc –instance <inst_path> Prepend inst_path to all paths in the SDC
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set_sdc -verbose Verbose reporting when SDC is read
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read_sdc <sdc_file> Read SDC exceptions into tmax
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report_sdc Report the results after SDC has been read
set_delay -nopi_changes Specify that PI’s cannot change At-Speed
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set_delay –nopo_measures Specify that PO’s cannot be measured At-Speed
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add_slow_cells <instance> Mask transitions launched from a slow cell
add_slow_bidis <port | -all> Mask the bidirectional loopback path
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set_atpg –power_budget <n> Set a switching activity budget
report_power –per_pattern Report the switching activity for each pattern
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Agenda
DAY
3
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Tr
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12 Diagnosis
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13 Conclusion
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Transition Delay Testing ©2018 Synopsys, Inc. All Rights Reserved. 9-1
TetraMAX Workshop
Unit Objective
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Run ATPG for the Transition fault model
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
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 Describe guidelines and flow considerations for Transition
ATPG
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 Describe small delay defects
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 Use PrimeTime to generate necessary files for Slack-Based
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ATPG
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Transition Delay: Agenda
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Slack-Based Testing
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Slack-Based ATPG
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Persistent Fault Models
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Step-by-Step Transition ATPG
 DRC
1. Read the SDC file (read_sdc …)
Define the delay options (set_delay …)
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2.
3. Constrain the resets and the Scan Enable if not constrained in the SPF
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4. Set SPF file to use (set_drc <SPF file>)
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5. Run Design Rule Check (run_drc)
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 ATPG
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1. Specify the target fault model (set_faults –model transition …)
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2. Run ATPG (run_atpg –auto)
Write pattern in desired format (write_patterns …)
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3.
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Transition Delay ATPG Script
 Basic Transition Delay script

read_netlist lib.v –lib
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read_netlist test.v
run_build_model –model top
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read_sdc test_mode.sdc
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set_delay –launch_cycle <last_shift|system_clock|extra_shift|any>
add_pi_constraints 0 scan_en
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set_drc test.spf
run_drc
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run_atpg –auto
write_patterns pats.stil –format stil
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exit
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TetraMAX Workshop
Adding Transition Delay Faults
 Add all possible Transition faults

add_faults –all
 To add a specific Transition fault to the design
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add_faults <pin_pathname> -slow <r|f|rf>
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 Reading a Fault List File
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read_faults <fault file>
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 By default, TetraMAX does not add faults on the Clocks and Scan Enables
for Transition ATPG
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 To add faults on the clocks and scan enable
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add_faults –clocks
add_faults -scan_enable
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 It is not recommended to add faults on clocks and scan enable for Transition
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ATPG 9- 6
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To consider a slow-to-rise (str) and slow-to-fall (stf) delay faults as equivalent:
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set_delay –slow_equivalence
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Transition pattern generation where the slow-to-rise fault for a particular node is considered
equivalent to the slow-to-fall fault for the same node. Once one fault is detected by simulation
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(DS), then the other is considered detected by implication (DI). Reduces run time and pattern count
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Optimized Transition Delay ATPG Engine
set_delay –two_clock_transition_optimization
 Two-clock optimized patterns (on by default)
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 Following conditions must be satisfied for optimization
Fault model must be Transition fault
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
Transition type must be system_clock launch
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
Merging must be turned on (this is automatically enabled with run_atpg –auto)
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
 Basic Scan ATPG must not be disabled
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TetraMAX Workshop
Design Guidelines for Transition Testing
 Keep multiple clocks domains independent

 Do not use a single test-mode clock otherwise delay testing is limited to slowest
clock domain and complex masking needed
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 Disable asynchronous resets
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 Provide ability to hold resets at their inactive state
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 Usually these are multi-cycle (slow) signals
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 Optionally disable test points
 ATPG may miss delay defects on longer functional paths (if not using Slack-
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Based ATPG)
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 Test points may also not be designed to launch/capture At-Speed
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Requirements for Transition ATPG
 Ability to generate At-Speed clock pulses

 Tester must be capable of delivering At-Speed pulses - - or
 Use an existing on-chip PLL to generate At-Speed clock pulses from an on-chip
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clock controller (OCC)
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 Must run full chip Static Timing Analysis (STA)
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 Recommended that the STA environment be configured to match timing on tester
and the pass full-chip STA in Test mode (ATPG mode)
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 Automated by tmax2pt.tcl
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 Transition ATPG should include multi-cycle and false path timing
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exceptions
 Use read_sdc command to read SDC from PrimeTime
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TetraMAX Workshop
Transition Delay Flow Considerations
 Transition Delay patterns also detect Stuck-At faults

 Persistent Fault model flow can be used to give direct credit to the overlapping
faults (see Appendix)
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 Transition patterns may detect Stuck-At faults other than the direct
credited Transition faults
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For cumulative coverage, fault simulation of transition patterns against the Stuck-
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
At fault model is recommended
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 Some Stuck-At faults won’t be detected by any Transition Delay pattern,
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so additional patterns will be required to top-off the Stuck-At coverage
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 Some transition faults not detectable by system-clock launch can be
detected by last-shift launch
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 However, many of those faults are functional false paths and could be considered
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to be untestable delay faults 1 9- 10
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1J. Rearick, “Too Much Delay Fault Coverage Is A Bad Thing”, Proceedings International Test
Conference, pp. 624-633, Oct 2001
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Inter-Clock Domain Paths
 Clock skew issue between different clock domains

 No STA performed for these paths if domain crossings are declared as false
paths
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 To disable test generation on inter-clock domain paths (system clock
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launch)
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 set_delay -common_launch_capture_clock
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 The faults will only be detected using the same clock for launch and capture
 Faults that cannot be launched and captured by the same clock will not be
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detected
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 To allow multiple clocks to be pulsed together
set_delay –allow_multiple_common_clocks
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
 Default with common_launch_capture_clock
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Common Launch Capture
Both clocks are

tested. Cross
CK1 path values are
CK1
masked
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X
Non targeted 1 0
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clock domains
held constant
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CK2 CK2
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CK1
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CK2
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Fast Slow
Capture Shift
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TetraMAX is capable of testing multiple clock domains at once, as seen on the left, by using
set_delay -common_launch_capture_clock . This will cause TetraMAX to only test
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register to register paths in the same clock domain. Any paths that go between clock domains
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(which could cause race conditions) will get masked out, as indicated by the X on the left.
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To get higher coverage, TetraMAX will run additional passes where the cross clock paths will have
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static values there, as on the right. This allows for improved coverage on the CK1 domain, as
shown on the right side of the figure.
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Slack-Based Testing
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Slack-Based ATPG
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TetraMAX Workshop
Testing for Small Delay Defects
 Slack-Based ATPG and Fault Simulation

 Target faults on long paths where the slack available is less than a specified limit
Leverage PrimeTime for accuracy
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
 More accurate slack calculations than an SDF approach
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 Considers “Clock Reconvergence Pessimism Removal”
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 Provide user settings for trade-offs
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 Control which faults are to be targeted in test generation based on the slack
margin available
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 Define how close to the longest path a detected fault must be to be considered
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detected adequately
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 Trade off ATPG effort to test longer paths against runtime, coverage, and pattern
count
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SNPS has a sign-off STA engine that is widely used in the industry and extremely accurate.
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Rather than build our own timing engine inside of TetraMAX, we’re going to leverage PrimeTime.
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Solution is based on slack numbers from PT and not SDF.

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The tool provide the user with tradeoffs to allow them to generate an optimal set of test benches.
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1) Control the faults which have to be targeted using the Slack-Based ATPG
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algorithm.
2) Relax the constraint for ATPG to detect the fault on the longest path.
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Tradeoff 1 & 2 against coverage, pattern count and CPU time.

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Slack-Based ATPG Flow
SDC,
SDF,
Exceptions
Parasitics
PrimeTime
ng
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Pin Slacks
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TetraMAX
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Slack-Based ATPG
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Transition and Slack- Reports,
Based ATPG Patterns Histograms
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This shows a flow for Slack-Based ATPG. TetraMAX will read pin slacks from PrimeTime prior to
ATPG. These pin slacks represent the full accuracy of PrimeTime, including CRPR. In this flow,
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Slack-Based ATPG is being used to measure how good existing transition fault patterns are at
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detecting small delay defects, and then to “top off” those patterns to improve coverage of small
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delay defects. In summary, Slack-Based ATPG is a way to improve transition fault testing.
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Slack Data Generation : PrimeTime Flow
 Set-up Test Mode timing report_global_slack > my_slacks.dat

constraints in STA: Max_Rise Max_Fall Min_Rise Min_Fall Point
read_sdc at_speed_constraints.sdc -------------------------------------------
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* * * * TOP/Z
 Timings and constraints to match 13.72 13.41 1.20 1.46 U114/A1
tester environment 12.44 11.93 1.35 1.74 U114/A2
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12.44 11.93 1.20 1.46 U114/Z
Report the worst case rise and
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 13.72 13.41 1.20 1.46 U106/A1
12.44 11.93 1.35 1.74 U106/A2
fall slack available on every
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12.44 11.93 1.20 1.46 U106/Z
node for Slack-Based ATPG 13.72 13.41 1.20 1.46 U126/A1
12.44 11.93 1.35 1.74 U126/A2
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12.44 11.93 1.20 1.46 U129/Z
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From the global slack file, only the 1st, 2nd and last column is used by TetraMAX.
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Reading Slack Data
 Read slack data

read_timing <file-name> –delete
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 The –delete option removes current slack data and replaces with the
data in the file (default just adds data in file to current data)
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 Hierarchical Slack Data is not supported
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 Manually add the additional hierarchy to the slack data
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 Slack data can be read at any time after run_build_model and prior to
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ATPG or fault simulation
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 Automatically turns on Slack-Based ATPG
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Turns on/off use of slack for ATPG:
set_delay < –slackdata_for_atpg | –noslackdata_for_atpg >
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Turns on/off use of slack for fault simulation:

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set_delay < –slackdata_for_faultsim | –noslackdata_for_faultsim >

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Slack on Red Path
Slack =1/1
Slack =1/1
For each Flop:
Tcq = 0.5ns Tsetup = 0.5ns
Slack =1/1
For each two input Gate:
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Slack =1/1
T2pind = 2.0ns
Slack =1/1
Slack =1/1 For each single Input Gate:
T1pind = 1.0ns
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Slack =1/1
Slack =1/1 Clock Frequency:
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Slack =1/1 Clk Period = 12.0ns
Slack =1/1 Rise Transition = Fall Transition
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Slack =1/1
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Slack =1/1 Slack available on the node
Slack =1/1
for Rise / Fall Transition
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Slack on Green Path
Slack =8/8
Slack =8/8
Slack =8/8 Slack =8/8
For each Flop:
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Slack =8/8
Slack =8/8 T2pind = 2.0ns
For each single Input Gate:
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T1pind = 1.0ns
Clock Frequency:
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Clk Period = 12.0ns
Rise Transition = Fall Transition
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Slack on Blue Path
For each Flop:

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Slack =4/4 T2pind = 2.0ns
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Slack =4/4 Slack =4/4 T1pind = 1.0ns
Clock Frequency:
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Slack =4/4 Clk Period = 12.0ns
Rise Transition = Fall Transition
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Slack =4/4
Slack =4/4
Slack =4/4
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Slack =4/4
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Slack =4/4
Slack =4/4
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Lowest Slacks On Each Pin
Slack =1/1
Slack =1/1 Slack =8/8 Slack =8/8
 The lowest slack values for

Slack =1/1
Slack =1/1
Slack =8/8 each pin is what is reported
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Slack =1/1 Slack =1/1 by the
report_global_slacks
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command
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Slack =1/1
Slack =4/4
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Slack =1/1

Slack =1/1
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Slack =1/1
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Slack =4/4
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Slack-Based ATPG Terminology
 Timing Margin : Tmgn

 Slack of the longest path on which the fault may be detected
 The smallest defect size which can make the device fail
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 Slack values read with read_timing
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Note: PrimeTime does not know if it’s even possible to launch and capture a
transition fault along its longest path
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 Detection Margin: Tdet
 The slack of path on which the fault is detected
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 This may not be the longest path
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 Delta
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 The difference between tmgn and tdet ( tdet – tmgn )
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 Ideally the delta would be 0 which means the detection was along the longest path
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TetraMAX Workshop
Illustration of Tmgn Tdet and Delta
Slack = 4
16
t mgn = 1 ns
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t det = 3ns
Slack = 3
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18 Slack = 2
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Slack = 1
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

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tmgn tdet
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Probability of Defect: The chances of physical defect present in the chip after manufacturing.
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For a given fault : Any defect size less than its Tmgn does not create a problem. This fault does not
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affects the function of the chip and hence can be ignored. (area from 0 to Tmgn)
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Any defect size bigger that Tdet is supposed to be captured by the regular Transition ATPG.
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(area from Tdet to infinity)

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If the defect size is between Tmgn and Tdet, those defects get escaped during regular Transition
Test. This is the range of defect magnitude that is to be targeted by Slack-Based ATPG.
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Test For Understanding (Ex. 1)
1/1
1/1
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1/1
For each Flop: 1/1
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T2pind = 2.0ns 1/1
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T1pind = 1.0ns
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Clock Frequency:
Clk Period = 10.0ns
1/1
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Rise Tr. = Fall Tr.
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Tmgn = ________
Tdet = ________
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Delta = ________
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Answer: Tmgn = 1, Tdet = 1, Delta = 0
TetraMAX Workshop
1/1 4/4
1/1 4/4
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1/1
For each Flop:
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3/3
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T2pind = 2.0ns
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T1pind = 1.0ns
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Clock Frequency:
Clk Period = 10.0ns
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Rise Tr. = Fall Tr.
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1’b0
Tmgn = ________
Tdet = ________
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4/4
4/4
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For each Flop:
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1’b0
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For each two input Gate: 3/3
T2pind = 2.0ns
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T1pind = 1.0ns
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Clock Frequency:
Clk Period = 10.0ns
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Rise Tr. = Fall Tr. 3/3
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Tmgn = ________
1’b0
Tdet = ________
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Delta = ________
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Negative and Infinite Slack
 Negative Slack
 Path segment with a timing violation
 Indication that PrimeTime and TetraMAX timing exception setups might be different
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 Presumably, the PrimeTime functional mode setup was “clean” (i.e., no negative slacks)
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 If the PrimeTime setup for Scan mode has negative slacks, then those paths will not
meet single cycle timing on the ATE (and in simulation)
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 Inconsistency in timing exceptions may result in bad patterns
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 Use set_delay -negative_slack_checks to identify negative slack values
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 Infinite Slack
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 Fault not testable
 Use set_delay -infinite_slack_checks to identify infinite slack values
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-negative_slack_checks | -nonegative_slack_checks
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Enables or disables negative slack check during read timing file, slack-based transition fault test
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generation, or fault simulation. During slack-based transition fault test generation or fault
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simulation, warning message M752 is printed if this check is enabled. The default is -
nonegative_slack_checks.
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-infinite_slack_checks | -noinfinite_slack_checks
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Enables or disables infinite slack check during read timing file, slack-based transition fault test
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generation, or fault simulation. During read timing file, warning message M751 is printed if this
check is enabled. During slack-based transition fault test generation or fault simulation, warning
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message M753 is printed if this check is enabled. The default is –noinfinite_slack_checks.

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Slack-Based Testing
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Slack-Based ATPG
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TetraMAX Workshop
Setting Standard for Targeted Faults
 Control the number of Faults for Slack Based ATPG

set_delay –max_tmgn <float|fault%>
Default is Infinity
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
 Faults with tmgn less than max_tmgn or fault% of total faults will be
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targeted using Slack-Based ATPG
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 Value of max_tmgn is reported when ATPG starts
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TEST-T> run_atpg –auto
The max tmgn for small delay defect faults has been set to 6.04
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 Remaining faults targeted as standard transition faults
 The fault targeting process occurs automatically
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This parameter is for the Test Generator and making tradeoffs
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If you specify set_delay -max_tmgn 50%, you are setting the max_tmgn to include 50% of all the
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faults with the smallest tmgn faults as Slack-Based ATPG targets. A message is printed that informs
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you of the absolute value of the max_tmgn according to the percentage.

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This implementation is based on following assumptions:

1. All faults are considered, not just the active faults. This is to maintain the same fault base in case
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of multiple ATPG runs. Otherwise the set of Slack-Based ATPG faults is a moving target.
2. The max_tmgn is adjusted according to the percentage you specify. As a result, it may not be
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possible to have the exact percentage of faults sampled. For example, if 1/2 of the faults have
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tmgn=1, and 1/2 of faults have tmgn=infinite, an 80% setting is essentially the same as 100% since
it will internally set the max_tmgn to infinite.
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3. The number of faults can be counted either as collapsed or uncollapsed, which is controlled by
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the command report faults -collapsed | uncollapsed.

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For multicore runs, you need to look at the slave logs to find the absolute value of max_tmgn.
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TetraMAX Workshop
Minimizing Pattern Count Inflation
 Slack Based ATPG will generate more patterns than standard

transition ATPG
 Selecting paths with minimum slack restricts choice and ability to merge patterns
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 Use of the following can help to minimize pattern count increase:
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 Set a realistic target fault list (max_tmgn)
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 Faults that already have a large timing slack can be targeted with transition ATPG
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 Define minimum detection per pattern limits during slack based ATPG, e.g.:
set_atpg –basic_min_detect 10 –fast_min_detect 10
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Note: During the pattern generation, run_atpg –optimize_patterns can also be used to
reduce the number of Slack-Based patterns that use the two-clock ATPG engine.
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Setting max_tmgn – Default ∞ – Too Many
50000
40000 Fault Universe Targeted

= by Slack-Based ATPG
Endpoints
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30000
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20000
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10000 
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0
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Slack
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 Default max_tmgn setting is infinity – targets too many faults for Slack-
Based testing
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Setting a Reasonable max_tmgn
Fault Universe Targeted by
50000 = Slack-Based ATPG
40000
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Endpoints
30000
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20000
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0.2
10000
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0
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Slack
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 A setting of 0.2 or 20% covers a reasonable percentage of faults for
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Slack-Based testing
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In the TetraMAX reference methodology scripts, a setting of set_delay -max_tmgn 20% is
used as good starting point. Ultimately, it’s up to the user to determine a reasonable setting for –
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max_tmgn.
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Setting Standard for Full Detection
 Control the maximum delta for full detection

set_delay –max_delta_per_fault <float | tmgn%>
Delta = 0 means fault was detected on the path with minimum slack (the
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
longest path)
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 If delta for a detected fault is less than or equal to
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–max_delta_per_fault, the fault is DS; otherwise it is TP (transition
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partially detected)
 The default is 0
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TP = Transition Partially detected (it’s a sub-category of DT). A TP fault will continue to remain
active in the fault list.
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TetraMAX Workshop
Setting max_delta_per_fault
Targeted Transition
Delay Fault
SET
D Q D
SET
Q
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Q
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CLR
CLR Q
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SET
D Q
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CLR Q
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Detected path slack = 0.5 = TP  DS
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(if max_delta_per_fault > 0.2)
Minimum slack path = 0.3 (longest) = DS
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TetraMAX Workshop
Partially Detected Faults : TP
 Faults categorized as a TP fault

 If delta > max_delta_per_fault for slack-based ATPG faults
 All faults targeted by standard Transition ATPG
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 Verbose fault report shows the TP faults
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set_faults –summary verbose
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 report_faults –summary
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------------------------------ ---- ---------
Detected DT 22079
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detected_by_simulation DS (14630)
detected_by_implication DI (3856)
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transition-partially_detected TP (3593)
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Undetectable UD 284
Not detected ND 7989
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TetraMAX Workshop
Fault Report with Slack Data
 When reporting faults (report_faults) with slack data present, the

report will include the tmgn and delta of each detected fault
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tmgn delta
str DS mem2/na1_10/u57/B 3.74 0.00
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stf DS a2901/g0/g75/g7/B 5.27 0.00
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stf DS mem2/na1_10/u55/Z 3.14 0.06
str DS mem2/na1_10/u58/Z 3.12 0.15
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stf DS mem2/na1_10/u58/Z 2.94 0.28
str DS a2901/g0/g75/g7/Z 3.12 0.00
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stf DS a2901/g0/g75/g7/Z 2.94 0.00
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str DS a2901/g0/g40/g7/LD 5.51 0.00
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Fault Report: report_faults –slack tmgn
 report_faults –slack tmgn
Histogram of Uncollapsed Fault Distribution Cumulative Distribution of tmgn
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tmgn tmgn
values #faults values #faults
----------------------- -----------------------
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1.30 - 3.13: 8509 3.13: 8509
3.13 - 4.97: 22464 4.97: 30973
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4.97 - 6.80: 24549 6.80: 55522
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6.80 - 8.64: 14768 8.64: 70290
8.64 - 10.48: 5741 10.48: 76031
10.48 - 12.31: 19629 12.31: 95660
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12.31 - 14.15: 19186 14.15: 114846
14.15 - 15.98: 6372 15.98: 121218
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15.98 - 17.82: 7374 17.82: 128592
17.82 - 19.66: 4196 19.66: 132788
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> 19.66: 0 < inf: 132788
Infinite: 12220 Infinite: 12220
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Undefined: 0 Undefined: 0
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Here is the distribution of the timing margin for a particular design. The default of 10 buckets was
used.
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Both the histogram and cumulative reported simultaneously using the command.
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The group labeled “Infinite” are faults that have timing exceptions (i.e. set_false_path,
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Fault Report: report_faults –slack tdet
 report_faults –slack tdet

Histogram of Uncollapsed Fault Distribution Cumulative Distribution of tdet
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tdet tdet
----------------------- -----------------------
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1.30 - 3.15: 0 3.15: 0
3.15 - 5.01: 182 5.01: 182
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5.01 - 6.86: 3278 6.86: 3460
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6.86 - 8.71: 18560 8.71: 22020
8.71 - 10.57: 13594 10.57: 35614
10.57 - 12.42: 15070 12.42: 50684
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12.42 - 14.27: 17708 14.27: 68392
14.27 - 16.13: 1596 16.13: 69988
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16.13 - 17.98: 5867 17.98: 75855
17.98 - 19.66: 3812 19.66: 79667
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> 19.66: 0 < inf: 79667
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Undetected faults (ND/AU/UD) do not have a tdet defined and are put in the “Undefined” group.
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set_multicycle_path, etc.)
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Fault Report: report_faults –slack delta
 report_faults –slack delta
Histogram of Uncollapsed Fault Distribution Cumulative Distribution of delta
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delta delta
----------------------- -----------------------
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0.00 - 1.27: 39827 1.27: 39827
1.27 - 2.55: 11692 2.55: 51519
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2.55 - 3.82: 10103 3.82: 61622
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3.82 - 5.10: 9508 5.10: 71130
5.10 - 6.37: 5248 6.37: 76378
6.37 - 7.64: 2715 7.64: 79093
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7.64 - 8.92: 946 8.92: 80039
8.92 - 10.19: 255 10.19: 80294
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10.19 - 11.47: 79 11.47: 80373
11.47 - 12.65: 4 12.65: 80377
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> 12.65: 0 < inf: 80377
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Undetected faults do not have delta defined because they don’t have a tdet defined and are therefore
put in the “Undefined” group.
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set_multicycle_path, etc.).
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TetraMAX Workshop
Metric: Delay Effectiveness
Delay Effectiveness = (Area under green curve / Area under red curve) * 100
= (Area under Tdet curve / Area under Tmgn curve) * 100
 Delay Effectiveness
 Assumes uniform probability
ng
of ANY delay defect size
 Considers only faults with
ni
Fault Count
slacks less than max_tmgn
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 The lower the average delta,
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the higher the delay
effectiveness
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TEST-T> report_faults -slack effectiveness
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------------------------------------------
Slack
delay effectiveness 69.94%
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Note: Delay Effectiveness is very different from Test Coverage
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Another metric is SDQL (Statistical Delay Quality Level)

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• Applies probability that a delay defect of a particular size will occur

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• Units of DPPM due to Small Delay Defects

• Requires data from the fab
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Slack-Based ATPG Flow
read_netlist CORE.v -library
read_netlist DESIGN.v
run_build_model TOP
read_sdc DESIGN.sdc
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run_drc DESIGN.spf
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set_faults -model transition
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set_delay -launch system
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# Slack-Based ATPG setup
read_timing DESIGN.slack
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set_delay –max_tmgn 3.5
set_delay –max_delta_per_fault 0.5
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run_atpg –auto
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# Report commands
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report_faults -slack delta
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The read_timing command turns on Slack-Based ATPG functionality
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Note: TetraMAX does not support Slack-Based ATPG with the Full-Sequential ATPG engine
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TetraMAX Workshop
Slack-Based Test Does a Better Job
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Source: STMicroelectronics, Silicon Debug and Diagnosis Workshop, 2012 9- 42
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TetraMAX Workshop
Improved Pattern Quality
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Source: Stefano Zanatta – Avago Technologies, Adam Cron – Synopsys, Achieving Ultra-Low DPPM, Synopsys Webinar, 2017 9- 43
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Slack-Based Testing
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Slack Data
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Slack-Based ATPG
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 Manage faults for multiple fault models in a single ATPG session

 Setting the current fault model activates its corresponding faults
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 Faults in other fault models are inactive
Supports running DRC in multiple test modes
ni

Existing Patterns are deleted (when going back to DRC)
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
Existing active and inactive faults preserved
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
 Fault list is not preserved if returning to BUILD mode
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 Supports changing fault models (within TEST mode)
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 Existing patterns preserved
Existing active and inactive faults preserved
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
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TetraMAX Workshop
Persistent Fault Model Flow
 Enable Persistent Fault Models

set_faults -persistent_fault_models
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 Advantages of persistent fault models
 Direct credit
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 Fault grading existing patterns against other fault models
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 Reduces pattern count
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 Reduces ATPG run time
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 Simplifies File management
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 Update fault status with credit
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update_faults -direct_credit
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Direct Credit
update_faults -direct_credit
STR on Z pin A B Z
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P1 0 X 0
P2 1 1 1
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Stuck-At-0 on Z pin A B Z
P1 1 1 1
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A pattern for Slow-to-Rise on the Z pin will also detect a
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
Stuck-At-0
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TetraMAX Workshop
Combined Coverage with Persistent Fault Models
read_netlist core.v # Take direct credit for TD faults

read_netlist test_scan.v update_faults –direct_credit
run_build_model # Run fault sim to drop more faults
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set_drc test_scan_at_speed.spf # before Stuck-At top off
# Setup your at-speed constraints run_fault_sim
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run_drc write_patterns pat stil –format ...
set_faults -persistent_fault_models drc -force
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set_faults -model stuck # Remove all at-speed constraints
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add_faults -all set_drc test_scan_stuck.spf
set_faults -model transition run_drc
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add_faults -all report_faults -summary
set_delay -launch system run_atpg -auto
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run_atpg -auto write_patterns stuck_at.pat -format ...
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set_faults –model stuck exit
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Note: in the script that when persistent fault models are used, the faults lists for every fault model
used are populated “up front” in the script. Afterward, a given fault list is made “active” with the
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set_faults command.
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 Run ATPG for the Transition fault model
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 Describe guidelines and flow considerations for
Transition ATPG
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 Describe small delay defects
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Use PrimeTime to generate necessary files for
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
Slack-Based ATPG
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Begin Lab 9: Transition Delay ATPG
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report_patterns -all -type Obtain report of patterns and their type
set_atpg -chain_test Specifies bit sequence to load during chain test
write_patterns –format binary Write patterns in binary format
write_patterns –format wgl Write patterns in WGL format for translation to ATE
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write_patterns –format stil Write patterns in STIL format for translation to ATE
write_patterns -last 0 Writes the chain test, pattern 0
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write_patterns -sorted Writes patterns ordered by complexity
report_scan_cells –all Reports all scan cells
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report_scan_cells -shadow Reports only the shadow gates of scan cells
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add_pi_constraints X <port> Apply an input mask to a port
add_cell_constraints <0|1|XX| Control value loaded and/or mask the value
ip
OX|0X|1X> –chain <name> <pos> unloaded from a scan cell
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add_po_masks <port> Apply an output mask to a port
add_capture_masks <instance> Mask values captured on a non-scan or scan cell
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add_slow_cells <instance> Mask transitions driven by a slow cell
add_slow_bidis <port | -all> Mask the bidirectional loopback path
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TetraMAX Workshop
Agenda
DAY
3
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Tr
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12 Diagnosis
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13 Conclusion
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On-Chip Clocking Support ©2018 Synopsys, Inc. All Rights Reserved. 10-1
TetraMAX Workshop
Unit Objective
ng
 Describe the need to use PLL for generating fast clocks
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 List the various clocks used for ATPG with OCC
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 Describe the flow for Transition Fault ATPG using OCC
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TetraMAX Workshop
At-Speed Clocking
 To detect Delay defects, At-Speed clocks must be used during scan

testing
 For functional operation, At-Speed clocking may be supplied by:
ng
 External clock sources (i.e. top-level clock ports)
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 Internal clock sources (i.e. PLLs)
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 During scan testing, either external or internal clock sources can be
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used to test a design At-Speed
Ideally, the clock source used for scan testing should be the same as
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
for functional operation
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TetraMAX Workshop
Issues Testing At-Speed with External Clocks
 Capture speed is limited by ATE speed

 Capture speed is limited by PAD speed
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 Multiple internal clock domains require multiple external CLK pads
In PAD limited designs CLK are collapsed, at-speed testing becomes
ni

unsustainable
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Expensive testers are required for at-speed ATPG
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
 Using PLL clocks for at-speed ATPG is now a very common practice
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TetraMAX Workshop
Requirements for Using Existing PLL Clocks
 Switch between a slow external clock for shift and a fast (on-chip) clock
for At-Speed capture
 Synchronization between the fast and slow clocks
ng
 Allow ATPG to control how many fast clocks are passed on to the core
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on a per pattern basis
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 Avoid any glitches
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Effective capture speed
ATE Period
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ATE clock
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TetraMAX Workshop
On Chip Clock (OCC) Controller
Clock chain Capture performed
Controlled by TetraMAX using PLL clocks and
Clock bits
shift performed using
On chip clock generator
ATE clocks
Clock shaper pllclk1 intclk1

PLL
ng
refclk1
refclk2 divider
pllclk2 OCC intclk2 DFF DFF
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logic
pllclk3
control intclk3
PLL DFF DFF
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Multiplier
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External DFF DFF
Clocks
Scan chain2
Scan chain1
Each type of clock is declared
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to TetraMAX via an SPF or
with Quick STIL commands
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test_se External clocks
pllclk1
are asynchronous
ATE_clk
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test_se to internal clock
domains
ATE_clk
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10- 6
intclk1
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Reference Clocks — The frequency reference to the PLL. Free-running or the PLL may lose
synchronization. Reference clocks can not route directly to the clock inputs of FF’s
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nt
PLL Clocks — The output of the PLL. A free-running source that also runs at a constant frequency
which may or may not be the same frequency as its’ respective reference clock
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ATE Clocks — Shifts the scan chain. ATE clocks are only used and routed to the respective OCC
controller, they can not route directly to clock inputs of FF’s
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Internal Clocks — The OCC is responsible for gating and selecting between the PLL clocks and
U
ATE clocks to create the internal clocks. Internal Clocks are the output of the OCC
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External Clocks — Primary inputs that clock flip-flops directly or through combinational logic. Not
generated from PLLs and can not be used or declared as a Reference Clock
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TetraMAX Workshop
Fundaments of OCC
 OCC should be placed on internal clock generator after each PLL or

Divider
 No restriction on number of OCCs supported
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 Full automation of ATPG and DFT insertion available
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 ATPG will decide “per-pattern” which clocks should be pulsed
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Mix of OCC (internal) and external clocks is supported
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
 No inter-domain testing between internal and external clocks
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 Internal clocks are asynchronous to ATE, so relative timing is unpredictable
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TetraMAX Workshop
OCC IP Operation
 The OCC logic inserted by DFT Compiler supports several “modes of

operation” relating to the OCC
 Functional mode (on-chip clocks used)
ng
 OCC Bypass mode (external ATE clocks used for both shift and capture)
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 OCC mode – scan shift (external ATE clocks used)
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 OCC mode – At-Speed capture (on-chip clocks used)
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 If TetraMAX uses an SPF from DFT Compiler, the SPF will include
support for both OCC mode and OCC Bypass mode in a single SPF file
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 The active mode is selected by specify the active PatternExec for run_drc
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In the SPF, the PatternExec information will look something like this:
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PatternBurst Internal_scan {
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Procedures Internal_scan;
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MacroDefs Internal_scan;
ClockStructures Internal_scan;
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}
PatternBurst Internal_scan_occ_bypass {
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Procedures Internal_scan_occ_bypass;
MacroDefs Internal_scan_occ_bypass;
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}
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PatternExec Internal_scan {
PatternBurst Internal_scan;
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}
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PatternExec Internal_scan_occ_bypass {
PatternBurst Internal_scan_occ_bypass;
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}
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The PatternExec label references a specific PatternBurst label. The PatternBurst label references a
set of Procedures in the SPF that are specific to the targeted mode.
TetraMAX Workshop
OCC Flows in ATPG
 When OCC is used in TetraMAX, there are two options for declaring the
OCC information to TetraMAX:
 SPF from DFT Compiler
ng
 Quick STIL commands
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 If scan OCC insertion is done by DFT Compiler or an existing OCC is
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inferred, the SPF from DFTC will contain everything that TetraMAX
needs to know about the OCC operation
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 If an SPF with OCC details is not available, then Quick STIL commands
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can be used to describe the OCC to TetraMAX
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TetraMAX Workshop
DFT Compiler and TetraMAX OCC Flows
OCC Insertion Existing OCC 3rd Party Flow
DFTC + TMAX DFTC + TMAX TMAX ONLY
• Netlist • Netlist, • 3rd Party Netlist with OCC
• OCC Instantiated • DFTC Netlist with No SPF
• Clock chain instantiated
ng
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• Netlist, OCC and clock chain • Netlist, OCC and clock chain • TetraMAX: QUICK STIL
• DFTC: OCC insertion + • DFTC: Stitching • Edits may be required for
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Stitching • SPF Generated customizing procedures
• SPF Generated
ip
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• TetraMAX DRC • TetraMAX DRC • TetraMAX DRC
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• TetraMAX ATPG • TetraMAX ATPG • TetraMAX ATPG
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SPF Available SPF Not Available 10- 10
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TetraMAX Workshop
TetraMAX Flow: SPF Available
set_messages -log tmax.log –replace

read_netlist pll.v
read_netlist core.v
read_netlist top.v
ng
run_build_model top
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set_delay –common_launch_capture_clock
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set_drc test_scan.spf
run_drc –patternexec Internal_scan
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set_delay –launch system_clock
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add_faults –all
run_atpg –auto
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write_patterns pattern.stil –format STIL
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run_drc test_scan.spf –patternexec Internal_scan
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The -patternexec is needed only incase if the SPF file is common for the PLL bypass and PLL
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active. If the SPF does not contain PatternExec information, then –patternexec is not
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needed.
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TetraMAX Workshop
TetraMAX Flow: SPF Not Available
 Quick STIL commands used to describe OCC controller IP and other

scan information
 Declare clocks with the add_clocks command
ng
 Internal clock
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 ATE clock
Reference clock
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
 PLL clock
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 External clock
Declare the other parts of the scan architecture
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
add_pi_constraints
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add_scan_enables
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add_scan_chains
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TetraMAX Workshop
OCC QUICK STIL Flow (1/2)
read_netlist …
run_build_model top
add_scan_chains …
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add_scan_enables 1 test_se
add_pi_constraints …
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# The number of PLL cycles must be declared first
ai
set_drc -num_pll_cycle 2
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# Declare the ATE clock
ip
add_clocks 0 ate_clk2 -shift -refclock \
–timing {100 45 55 20}
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# Declare the Reference clock (if any)
add_clocks 0 ref_clk -refclock –shift \
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-timing {100 45 55 20}
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TetraMAX Workshop
OCC QUICK STIL Flow (2/2)
# Declare the PLL clock

add_clocks 0 U_pll/clka -pllclock
# Declare the Internal clock conditions for each cycle
ng
add_clocks 0 "u_my_pll_ctrl_1/intclk" \
-intclock -pll_source U_pll/clka -cycle { \
ni
0 "u_my_pll_ctrl/snps_clk_chain_0/clk_ctrl_data[0]" 1 \
1 "u_my_pll_ctrl/snps_clk_chain_0/clk_ctrl_data[1]" 1 }
ai
Tr
set_delay -common_launch_capture_clocks
run_drc
ip
set_faults -model transition
set_delay -launch system
ch
run_atpg –auto
ro
write_patterns pll_pat.stil –format stil
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TetraMAX Workshop
Black Box Requirement for DRC
 TetraMAX requires PLL clock to be defined on a black box for DRC

checks
 If the PLL module is not read, then define it as black box
ng
set_build –black_box {my_pll}
ni
 If a model for the PLL exists (via a library cell or netlist), then declare
ai
the instance associated with the PLL as a TIEX (black box)
Tr
set_build –instance_modify TIEX {my_pll}
ip
ch
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10- 15
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TetraMAX Workshop
DRC Violations
 Certain C rules are for PLL checks

 PLL controller and clocks are simulated by DRC
 Conditioning of the clock-chain and controller is checked
ng
 Timing issues in the PLL controller cannot be checked by the DRC engine
ni
 C34, C35, C36 and C39 can be downgraded in the presence of a user-
ai
defined controller containing asynchronous logic
Tr
 May be required if the user’s controller is not properly understood by the
TetraMAX DRC symbolic simulation engine
ip
 C39 violations require masking: add_cell_constraints OX
ch
NOTE: Full functional simulation is required to ensure user assumptions are
ro
verified
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10- 16
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na
C39 Violation: This violation occurs when a nonlogical clock propagates to any scan cell input.
Nonlogical clocks include reference clocks and controller clocks declared with the set_drc -
er
controller_clock command. TetraMAX ATPG will not simulate the effect of pulsing the
nt
nonlogical clocks on scan cells. Failure to satisfy this rule can result in patterns which fail in
rI
simulation. If a C39 violation cannot be prevented, you can downgrade it to a warning using the
set_rules command. In addition, you should use the command add_cell_constraints
Fo
XX to both load and unload all unknown values on the affected registers.
se
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TetraMAX Workshop
Reporting Internal and PLL Clocks
 Internal Clocks
report_clocks –intclocks
TEST-T> report_clocks -intclock
ng
ni
ai
Tr
 PLL Clocks
report_clocks –pllclocks
ip
ch
TEST-T> report_clocks -pllclocks
ro
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TetraMAX Workshop
Asynchronous Reference Clocks
ATE_CLK
100 ns
ng
REF_CLK1
ni
ai
REF_CLK2
Tr
ip
 ATE and REF clocks often need different frequencies
ch
 Depending on the relationship between the ATE clock and the REF
clock, some pattern formats don’t fully support the REF clock timing
ro
ic
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TetraMAX Workshop
Reference Clock and Pattern Formats
 Relation between reference clock and ATE clock

 Synchronous Single Pulse: Same period for reference and ATE clock
 All formats of patterns supported
ng
 Synchronous Multi Pulse: Period of Reference clock integer divisor of period of
ATE clock
ni
STIL, STIL99, and WGL format supported
ai

 Asynchronous: No relation between the periods of Reference clock and ATE clock
Tr
 STIL format only
ip
 Writing Patterns with Unsupported Reference Clock type results in
ch
M669 message
 Manual edits to the Verilog testbench are required in this case in order to supply
ro
the reference clock for simulation
ic
 All signals besides reference clocks are written correctly
10- 19
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Example reference clock declarations:
er
# ATE clock
nt
add_clocks 0 ate_clk -shift -refclock –timing {100 45 55 20}

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# Synchronous Single Pulse Reference clock

Fo
add_clocks 0 ref_clk -refclock –shift -timing {100 45 55 20}

# Synchronous Multi Pulse Pulse Reference clock
se
add_clocks 0 ref_clk -refclock –shift –ref_timing {50 15 40}

# Asynchronous Reference clock
U
add_clocks 0 ref_clk -refclock –shift –ref_timing {30 10 25}

ed
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TetraMAX Workshop
ATE Cycles During Scan Capture
 PLL clocks are asynchronous with respect to the ATE clock

 Depending on the PLL clocks speed, the internal clocks can come
anytime after the ScanEnable goes low
ng
 TetraMAX does not check if the fast clocks actually arrive while the
ni
ScanEnable is low
ai
 Define the minimum number of ATE clock cycles for which the
Tr
ScanEnable should remain low
set_atpg -min_ateclock_cycles <n>
ip
ch
 By default, ScanEnable is held low the same number of ATE cycles as
the number of PLL clock cycles
ro
set_drc -num_pll_cycles <n>
ic
10- 20
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na
If an SPF is used, the –num_pll_cycles is specified in the SPF with the PLLCycles
statement:
er
nt
ClockStructures Internal_scan {
rI
PLLStructures "occ1" {
PLLCycles 4;
Fo
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TetraMAX Workshop
Issue: Capture Window Too Small
 Clock pulses from OCC controller have bled over into next load_unload
ng
shift capture shift
fast_clk
ni
slow_clk
test_se
ai
int_clk
Tr
Two ATE clock cycles
ip
was not enough time to
ch
generate the fast clock
pulses from the OCC
ro
Simulation of OCC scan patterns can catch this issue
ic
10- 21
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TetraMAX Workshop
Solution: Increase the Number of ATE Cycles
Increase the number of
ATE clock cycles
during capture
ng
shift 4 capture cycles shift
fast_clk
ni
slow_clk
test_se
ai
f_clk_g
Tr
ip
ch
set_atpg -min_ateclock_cycles 4
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TetraMAX Workshop
Capture Cycles with OCC
 Capture cycles for Fast Sequential ATPG

set_atpg –capture_cycle N
For a given pattern, number of capture cycles can be from “2” to “N”
ng

 There can also be patterns where no internal clocks are pulsed during capture
ni
 The –num_pll_cycles value is the maximum number of internal clock
ai
pulses supported by the OCC and is also defined in the SPF
Tr
 Number of capture cycles for ATPG (specified by –capture_cycles)
must not exceed the maximum number of PLL clock cycles supported
ip
by the OCC
ch
set_drc –num_pll_cycles M (where N < M)
ro
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In the SPF, the number of PLL cycles, is defined as follows:
er
nt
PLLStructures "pll_controller" {
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PLLCycles 4;
Fo
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TetraMAX Workshop
PLL Clocks in Capture Cycle
 ATPG uses conditions declared in SPF for each internal clock to control
the number of fast PLL clock pulses used during the capture cycle
 Clock grouping is on by default and appropriate clock conditioning and
ng
masking is done if more than one clock is pulsed in the pattern
ni
 To avoid pulsing an internal clock during ATPG
ai
 add_cell_constraints (OCC w/ clock chain control)
Tr
ip
ch
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TetraMAX Workshop
Clock Grouping with OCC
 Clock grouping with OCC behaves the same way as when only external
clocks are used
ng
 With set_delay -common_launch_capture_clock
 All the OCC clocks treated asynchronously
ni
 Safe patterns generated: the same OCC clock will be used for both launch and
ai
capture
Tr
 By default, multiple “common clocks” may be pulsed in a given ATPG
ip
pattern
ch
set_delay –allow_multiple_common_clocks
ro
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TetraMAX Workshop
Multiple OCC Controller Usage During ATPG
 ATPG uses the clock chain bits to control which OCC clocks are pulsed
in each pattern
ng
Pattern#4 0 0 1 1 0 0
Pattern#3 1 1 0 0 1 1
Pattern#2 0 0 0 0 1 1
ni
ai
Pattern#1 1 1 1 1 0 0
Clock chain
Tr
DFF
DFF
PLL
PLL control1
control1
pll1_clk
ip
DFF
DFF
PLL
PLL control2
ch
pll2_clk
PLL control3
pll3_clk
ro
DFF
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10- 26
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TetraMAX Workshop
Report OCC Clocking
 To report the OCC clocking used by a given pattern:

report_patterns <pattern_#> -clocking
TEST-T> report_pattern 5 -clocking
ng
Clocking only:
Pattern 5 (fast_sequential-parallel_clocking)
ni
// PLL internal clock pulse: capture_cycle=0, node=I_CLOCK_GEN/pclk_occ/U4 (153)
// PLL internal clock pulse: capture_cycle=0, node=I_CLOCK_GEN/sdr_occ/U4 (201)
ai
// PLL internal clock pulse: capture_cycle=0, node=I_CLOCK_GEN/sys_occ/U6 (288)
// PLL internal clock pulse: capture_cycle=1, node=I_CLOCK_GEN/pclk_occ/U4 (153)
Tr
// PLL internal clock pulse: capture_cycle=1, node=I_CLOCK_GEN/sdr_occ/U4 (201)
// PLL internal clock pulse: capture_cycle=1, node=I_CLOCK_GEN/sys_occ/U6 (288)
ip
 In the above report, it shows that in pattern 5, three OCC clocks (pclk,
ch
sdr, and sys) were pulsed twice during scan capture (in cycle 0 and
cycle 1)
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TetraMAX Workshop
Verification of On-Chip Clocking
 Validation of OCC patterns must be done in a Verilog simulator

 PLL clock generation is black-boxed and not modeled in TetraMAX
Full Timing Validation (STA) must also be done
ng

ni
ai
Static Timing Analysis Constraints for On-Chip Clocking Support
Tr
ip
ch
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10- 28
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TetraMAX Workshop
Inter-Clock Domain Test with Synchronous OCC
 DFT Compiler supports the insertion of an OCC block that can manage
1x, 2x, and 4x synchronous clocks
 Outputs of DFT Compiler (both netlist and SPF) are ready for use in
ng
TetraMAX
ni
 Use this switch in the TetraMAX script
ai
set_drc -fast_multifrequency_capture on
Tr
 Insure inter-clock captures enabled
set_delay –nocommon_launch_capture_clock
ip
Mixtures of sync and async OCC controllers are handled safely by TetraMAX
ch

 Use this option to reduce pattern count
ro
set_drc –independent_sync_clocks
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TetraMAX Workshop
Synchronous Multi-Frequency Clocks
 OCC described so that ATPG generates its own clock sequences

 DRC confirms OCC operation but not synchronization - user specification
is assumed to be correct
ng
 Clock synchronization explicitly stated in SPF ClockStructures block
ni
 Latency statement in PLLStructures block
ai
 Used by clock chain re-sequencing
Tr
 ClockTiming block in ClockStructures top level
ip
 Turns on synchronized internal clocks feature
ch
 SynchronizedClocks block specifies which clocks are synchronized to which
other clocks
ro
 Period and Waveform statements and MultiCyclePath block specify timing
ic
details
10- 30
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Example ClockStructures block with Synchronous OCC:
er
nt
PLLStructures "TOTO" {
Latency 0;
rI
PLLCycles 10;
Fo
Clocks {
"clkate" Reference;
"dut/PLLCLK0" PLL { OffState 0; }
se
"dut/PLLCLK1" PLL { OffState 0; }

"TOTO/U2/Z" Internal { // This block is unchanged
U
"TOTO/U5/Z" Internal { // This block is unchanged

ed
}
}
ct
ClockTiming CTiming1 {
SynchronizedClocks group0 {
tri
Clock CLKX10 { Location "TOTO/U2/Z"; Period '10ns'; Waveform

es
'0ns' '5ns'; }
Clock CLKX5 { Location "TOTO/U5/Z"; Period '20ns'; Waveform
R
'0ns' '10ns'; }
MultiCyclePath 1 { From "TOTO/U5/Z"; To "TOTO/U2/Z"; }
}
}
}
TetraMAX Workshop
Internal Clocking Procedures (ICP)
 Removes all responsibility for finding clock pulse combinations from

ATPG, give complete control to user
 ATPG constrained to use only predefined clock sequences
ng
 DRC not run on OCC Controller, only on fanout from Internal Clocks
ni
 Clock synchronization implicitly assumed
ai
Additional syntax is in ClockStructures block
Tr

 InstructionRegister block in ClockController block
ip
 InstructionRegister used instead of Clock Chain
ch
 ClockConstraints block in ClockStructures top level
ro
 ClockingProcedure blocks specify allowed clock combinations
ic
10- 31
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Supported by all ATPG engines except Full Sequential
Full Sequential ATPG generates bad patterns when used with Internal Clocking Procedures
er
Stuck-At and Transition Delay fault models

nt
Launch and Capture in adjacent frames for Transition Delay Fault detection
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Clock Instruction Register members

Scan cells and/or Primary Inputs
Fo
Non-scan constant-value cells

External clocks (control outside of Inst Reg)
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TetraMAX Workshop
SPF Example With ICP
ClockStructures Internal_scan { ...
ClockController "PLL_STRUCT_0" { ClockingProcedure extraU1 {
PLLCycles 2; "dutm/clk1"=PP;
Clocks {
"dutm/clk1" Internal { OffState 0; }
"dutm/clk2"=P0;
"dutm/clk2" Internal { OffState 0; } CLKIR=11;
"clkref" Reference; "clkext0"=P0;
ng
"clkext0" External; // Clocking control }
"clkext1" External; // External clock ClockingProcedure intraU0 {
} "dutm/clk1"=00;
ni
InstructionRegister CLKIR { "dutm/clk2"=PP;
"dutc1/FF_0_reg/Q";
ai
"dutc1/FF_1_reg/Q";
CLKIR=01;
} "clkext1"=PP;
Tr
} }
ClockConstraints constraints1 { ClockingProcedure ClockOff {
// Force external clocks off when they’re unspecified "dutm/clk1"=00;
ip
UnspecifiedClockValue Off; "dutm/clk2"=00;
ClockingProcedure intraU1 { CLKIR=00;
ch
"dutm/clk1"=PP;
"dutm/clk2"=00;
}
CLKIR=11; }
ro
"clkext0"=00; }
}
ic
...
10- 32
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TetraMAX Workshop
ICP Setup and Commands
 Use of ICP must be declared during run_drc:

set_drc –clock_constraints <name>
 Default is to not use any ClockConstraints block
ng
 Use SDC timing exceptions to mask invalid transitions
ni
 Report a summary
ai
report_clocks –constraints
Tr
 Report information on all ICP’s
ip
report_clocks –constraints -all
ch
 Report procedure-specific information
report_clocks –constraints –procedure <proc_name>
ro
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TetraMAX Workshop
ICP Reporting Examples
TEST> report_clocks –constraints -all TEST> report_pattern 7 -clocking

----------------------------------------------- Clocking only:
Clock constraints1: Pattern 7 (fast_sequential)
MaximumConstraints sequential depth: 2 Clocking Procedures: U0to1
Defined Clocking Procedures: 3 // PLL internal clock pulse: capture_cycle=0,
Usable Clocking Procedures: 3 node=dutm/ctrl1/U17 (64)
ng
PLL clocks off Procedure: ClockOff // PLL internal clock pulse: capture_cycle=1,
node=dutm/ctrl2/U19 (94)
U0to1:
ni
CLKIR=10010 TEST> report_patterns -all -clk_summary
dutm/ctrl1/U17/Z=10
ai
dutm/ctrl2/U19/Z=01 Pattern Clocking Constraints Summary Report
-------------------- -----------------------------------------------
Tr
#Used Clocking Procedures
U1to0: #U0to1 6
CLKIR=01010 #U1to0 5
ip
dutm/ctrl1/U17/Z=01 -----------------------------------------------
dutm/ctrl2/U19/Z=10
ch
--------------------
ClockOff:
CLKIR=00000
ro
dutm/ctrl1/U17/Z=00
dutm/ctrl2/U19/Z=00
ic
--------------------
10- 34
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TetraMAX Workshop
Clocking Procedures Pattern Grouping
 ATPG can be controlled to keep patterns that use the same clocking
procedure together
 This allows the patterns to be “split” based on the clocking procedure
ng
 Each pattern file contains patterns from only one clocking procedure
ni
 A clocking procedure may have multiple pattern files
ai
 To group patterns by ClockingProcedure use:
Tr
set_atpg –group_clock_constraints {first_pass middle_pass final_pass}
write_patterns –occ_load_split
ip
 For best ATPG performance: {85 5 2}
ch
 Results in multiple pattern files per clocking procedure
ro
 For minimum number of pattern files: {100 0 0}
ic
 But this increases ATPG runtime substantially
10- 35
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The –group_clock_constraints arguments are specified in terms of percentages of the
fault list:
er
The first_pass argument specifies the target percentage of the fault list in the first pass through
nt
each clocking procedure. The first pass results in long blocks of patterns with just one clocking
rI
procedure.
The middle_pass argument specifies the target percentage of the fault list in the subsequent
Fo
passes through each clocking procedure. These passes are repeated until the final_pass number
is reached. The middle passes result in shorter blocks of patterns with just one clocking procedure.
se
The final_pass argument specifies the target percentage of the fault list in the final pass in
which any clocking procedure might be used. In this pass, there is no guarantee that any two
U
consecutive patterns will share the same clocking procedure.

ed
-occ_load_split
ct
This option, which is used in the internal clocking procedures feature, splits patterns into a separate
tri
file for each clocking procedure. Note that a new pattern file is saved each time a clocking
procedure changes from one pattern to the next, which can result in a large number of pattern files.
es
Because of this, you should you should use the -occ_load_split option only in combination
with the set_atpg -group_clk_constraints command.
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TetraMAX Workshop

 Describe the need to use PLL for generating fast
clocks
ng
 List the various clocks used for ATPG with OCC
ni
 Describe the flow for Transition Fault ATPG using
ai
OCC
Tr
ip
ch
Begin Lab 10: OCC for Transition Delay
ro
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10- 36
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TetraMAX Workshop
run_drc –patternexec Run DRC check using a particular PatternExec
Internal_scan section of the SPF
set_atpg –min_ateclock_cycles 5 Number of ATE clock cycles during for capture
set_drc -num_pll_cycle M Number of OCC fast clock cycles
add_clocks … Use Quick STIL commands to declare the OCC
ng
related clocks when an SPF is not available
report_clocks –intclocks Report the internal (OCC) clocks
ni
report_clocks –pllclocks Report the PLL clocks
ai
set_atpg –capture_cycle N Set the maximum number of capture cycles used
during ATPG. The number (N) selected must be
Tr
less that or equal to the number of fast clock
cycles (M).
ip
ch
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TetraMAX Workshop
Appendix
ng
OCC Implementation Details
ni
ai
Tr
ip
ch
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10- 38
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TetraMAX Workshop
OCC Controller Waveforms
 Synchronization required
 One pulse of ATE clock to switch in either direction
 3 pulses of PLL clock to capture (to prevent metastability)
ng
Count = 0 (no pulse)
ni
3 synchronization Count = 1 (pulse if enabled)
cycles 5 Count = 2 (pulse if enabled)
Count = 3 (terminal)
ai
fast_clk
Tr
4 9
slow_clk
ip
3 10
scan_en
ch
1 11
clk 2 8
ro
scan_en falling deselects scan_en rising takes effect
slow_clk asynchronously 6 7 on next falling clock edges
ic
10- 39
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Details of the OCC operation:
er
At first (1), the scan enable (scan_en) is active, so the slow ATE clock will be enabled.
nt
Next (2), scan enable falls.

rI
The slow clock first synchronizes the fall of scan enable (3), then the fast clock (4).
Once the fast clock gets a hold of the scan enable, it passes it through a metastability shift register,
Fo
and onto the counter (5).

According to the clk_enable settings scanned in by TetraMAX to the clock chain, some high-speed
se
pulses will be output from the controller (6).

After this the system stops and waits for the next event (7).
U
Scan enable comes active, again from the ATE (8).

ed
It gets synchronized by the high-speed clock (9) and by the ATE clock (10), and then the results are
shifted out while shifting in the next pattern (11).
ct
tri
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TetraMAX Workshop
Avoid Unified ATE Clock
REF_clock
PLL 10ns
OCC controller
Functional
ng
REF_clock path
PLL 5 ns
ni
OCC controller
ATE
Hold time
ai
slow_clock
violation only
for scan capture
Tr
 Avoid merging different clocks domains together
ip
 Use separate ATE clock for each controller, if possible
ch
 Use set_scan_configuration –internal multi in DFT Compiler to
control scan chain architecting when clocks do get merged
ro
 If OCC is broken, a unified ATE clock makes at-speed testing very difficult when
ic
the ATE clock is used for scan capture in OCC bypass mode (complex masking
required) 10- 40
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TetraMAX Workshop
Avoid Using Reference Clock as Shift Clock
REF_clock
PLL
OCC controller
ng
Using reference clock as shift clock:
ni

Will prevent using load_unload preambles and postambles to resolve timing
ai

issues
Tr
 Requires design to be shifted at reference clock speed
ip
ch
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10- 41
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TetraMAX Workshop
Avoid Using Reference Clock for Capture or in test_setup
ATE_clock
REF_clock
PLL
OCC controller
ng
ni
 Using reference clock as capture clock:
ai
 Will require logic to be always pulsed (C39 violation)
Tr
 Requires design to be shifted at reference clock speed
ip
 Using the reference clock to run specific configuration during
ch
test_setup sequence:
 Will force test_setup to run at reference clock speed and to have a pulse in
ro
every vector
ic
10- 42
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TetraMAX Workshop
Clock Bits Must Hold State
D Q D Q occ_so
occ_si SI SI
ng
launch_enable
capture_enable
test_se
SE SE
ni
ai
Tr
 Clock bits must hold state during capture to avoid losing the loaded
ip
state
ch
 C30 and C31 Errors in TetraMAX if this condition is not satisfied
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TetraMAX Workshop
Very Slow De-assertion of Scan Enable
Shift Capture
ng
fast_clk
slow_clk
ni
ai
test_se
Tr
ip
Very slow fall time
ch
Only full timing accurate simulation can catch it
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10- 44
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TetraMAX Workshop
Solution: Add load_unload Postamble*
Procedures {
"load_unload" {
W "_default_WFT_";
Shift {
ng
V { “slow_clk"=P; “test_se"=1; "_so"=##; "_si"=##; “ref_clk”=P; }
}
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// Postamble (notice that Scan Outs are masked)
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V { “slow_clk"=0; “test_se"=0; “_so”=XX; ref_clk=P; }
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}
shift postamble capture
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fast_clk
slow_clk
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ref_clk
test_se
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* Pulsing the reference clock must not disturb scan chain
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Very Slow Assertion of Scan Enable
Capture Shift
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fast_clk
slow_clk
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test_se
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Very slow rise time
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Only full timing accurate simulation can catch it
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Solution: Add load_unload preamble *
Procedures {
"load_unload" {
W "_default_WFT_";
V { “slow_clk"=0; “test_se"=0; “ref_clk”=P; } // Preamble
Shift {
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V {“slow_clk"=P; “test_se"=1; "_so"=##; "_si"=##; “ref_clk”=P;}
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}
}
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capture preamble shift
fast_clk
slow_clk
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ref_clk
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test_se
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* Pulsing the reference clock must not disturb scan chain
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Agenda
DAY
3
ng
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Tr
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12 Diagnosis
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13 Conclusion
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Path Delay Testing ©2018 Synopsys, Inc. All Rights Reserved. 11-1
TetraMAX Workshop
Unit Objective
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 Extract a set of critical paths from PrimeTime
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 Describe the syntax of a delay path
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 Run ATPG for the Path Delay fault model
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 Describe the Robust and Non-Robust faults classification
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 Analyze a Path Delay fault
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Automated Links for At-Speed Tests
PrimeTime Critical Timing Paths TetraMAX ATPG
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F Timing Exceptions
F
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F
F
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Test Constraints
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Automatic generation of critical paths and timing exceptions
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from PrimeTime to TetraMAX
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Automatic, complete timing constraints from ATPG
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Synopsys provides automated links to and from PrimeTime, the Industry leading sign-off timing
analysis tool.
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You can automatically generate both critical timing paths and timing exceptions from PrimeTime,
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and use these to generate at-speed tests using TetraMAX DSMTest.

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Likewise, you can use TetraMAX to automatically generate complete timing constraints for static
timing analysis.
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Path Delay Flow
Design Compiler®
.spf
Scan Netlist
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file
Gate Level
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PrimeTime®
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Critical
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SDC
Paths
file
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Path Delay
TetraMAX
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Patterns
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Main write_delay_paths Options
 write_delay_paths [-max_paths num_paths] [-slack crit_time]

[-nworst num_per] [-clock clock_name | -launch clock_name |
-capture clock_name] [-delay_type min|max] [-group
group_name] –pba [-version] filename
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-max_paths Specifies the max number of paths to be written (Default = 1)
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-delay_type Use min to extract hold paths
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-slack Writes paths with slack less than the specified crit_time (Default = ∞)
-nworst Specifies the number of paths to each endpoint (Default = 1)
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-clock Select paths in clock_name domain
-launch Select paths starting from clock_name domain
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-capture Selects paths ending at clock_name domain
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-group Selects paths from existing group_name
-pba Uses the exhaustive-effort level of path-based analysis to gather paths
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filename Name of file where paths are written
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write_delay_paths -slack 6 -max_paths 100 paths.txt
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The write_delay_paths command is part of the pt2tmax.tcl utility script. This utility
script is part of the TetraMAX installation and can be found here:
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$SYNOPSYS/auxx/syn/tmax/pt2tmax.tcl
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Path Delay Fault Models and ATPG Engines
 set_faults –model path_delay to target the setup-time path delay

fault model
 set_faults –model hold_time to target the hold-time path delay
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fault model
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 By default, setup-time path delay uses the Fast-Sequential ATPG Engine
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 Set an appropriate -capture_cycles value for Fast-Sequential path
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delay
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 Full-Sequential ATPG can also be used for path delay ATPG
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Control for using Fast-Sequential for setup-time path delay:
set_atpg –fast_path_delay | -nofast_path_delay
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Hold-time path delay can use Basic-Scan and/or Fast-Sequential ATPG engines.
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Path Delay ATPG : Setup Check
 Fault launched from a start point and

captured at an end point
 Failure if the transition of data at D of
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capture flop is too late
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 Separate launch and capture pulses
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 Setup Violation
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Path Delay ATPG : Hold Check
 Clock reaching the flops at different

time due to skew
 Change in launch flop disturbs the data
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of capture flop in same clock pulse
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 Failure if the transition of data at D of
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capture flop is too early
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 Same launch and capture pulse for a
given clock
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 Paths between different clock domains are
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rejected as ATPG Untestable
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 Hold Violation
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Hold Time Path Delay Flow Details
 Timing for Stuck-At ATPG is used (i.e., test does not need to be run
At-Speed)
 Hold-time violations are both launched and captured by a single clock pulse
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 Basic-Scan and Fast-Sequential engines are supported
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 Stuck-At patterns detect many hold time violations
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 Fault simulate hold time faults using Stuck-At patterns before running Hold-
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Time ATPG
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ATPG Script Examples
 Path Delay script  Hold-Time ATPG script with Stuck-At

pattern fault grading
read_netlist lib.v –lib read_netlist lib.v –lib
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read_netlist test.v read_netlist test.v
run_build_model –model top run_build_model –model top
add_pi_constraints 0 scan_en add_pi_constraints 0 scan_en
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read_sdc timing_exceptions.sdc set_drc test.spf
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set_drc test.spf run_drc
run_drc set_faults –model hold_time
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set_faults –model path_delay add_delay_paths path.txt; // Written with –delay_type min
add_delay_paths path.txt add_faults –all
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add_faults -all set_patterns –external stuck_at_pats.bin
set_atpg –capture_cycles 4 run_simulation
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run_atpg –auto run_fault_sim; // Fault sim Stuck-At pats for hold_time
write_patterns path_delay_pats.stil –format stil -replace set_patterns -internal
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run_atpg –auto
write_patterns hold_time_pats.stil –format stil –replace
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Path Delay Hold Time ATPG Script
 Hold-Time ATPG script with Stuck-At pattern fault grading

read_netlist lib.v –lib
read_netlist test.v
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run_build_model –model top
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set_drc test.spf
run_drc
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set_faults –model hold_time
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add_delay_paths path.txt ; // Written from PT with –delay_type min
add_faults –all
set_patterns –external stuck_at_pats.bin
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run_simulation
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run_fault_sim ; // Fault simulate Stuck-At patterns for hold_time
set_patterns -internal
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run_atpg –auto
write_patterns hold_time_pats.stil –format stil –replace
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Note : Since hold_time path delay ATPG is supported only by basic and fast-sequential engine there
is no requirement for switching off the full-sequential engine.
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Managing Faults
 Read the Paths file

add_delay_paths <path_file>
 Add Paths to be targeted for ATPG
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add_faults -all
set_delay -relative_edge
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 Inject both a slow-to-rise and a slow-to-fall fault
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 Need to set this option before add_delay_paths
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 Removing faults
remove_delay_paths
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 Report faults
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report_delay_paths
-verbose option includes information regarding launch and capture clocks and
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
nodes, transition direction of faults, fault status and the vector in which detection took
place (Post ATPG)
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Path File
 Path File
 ASCII file
 Contains the list of paths to be targeted for ATPG
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 Source of Path File
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 Use static timing analysis tool
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 PrimeTime
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 Create manually (not the preferred method)
 Paths
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Same paths as in STA
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
 Paths for ATPG
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 Critical paths (sensitive to delay)
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 Paths from different locations of the chip
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Path Syntax
$path {
[ $name path_name ; ]
[ $cycle required_time ; ]
[ $slack slack_time ; ]
[ $launch clock_name ; ]
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[ $capture clock_name ; ]
$transition {
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pin_name1 ^ | v | = | ! ;
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pin_name2 ^ | v | = | ! ;
…
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pin_nameN ^ | v | = | ! ;
}
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[ $condition {
pin_name1 0 | 1 | Z | 00 | 11 | ZZ | ^ | v ;
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pin_name2 0 | 1 | Z | 00 | 11 | ZZ | ^ | v ;
…
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pin_nameN 0 | 1 | Z | 00 | 11 | ZZ | ^ | v ; }
]
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$name - Assigns a name to the delay path
$cycle - Time between launch and capture clock edges
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$slack - Available time margin between the $cycle time and calculated delay of the path
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$launch - Launch clock primary input to be used

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$capture - Capture clock primary input to be used

$transition - (Required) Describes the expected transitions from the path startpoint through
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output pins of path cells and to the path endpoint

$condition - Allows the user to add more constraint for testing the associated path. The
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$condition statement is not included automatically from PrimeTime, but it can be added manually.
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V - falling transition
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^ - rising transition
= - transition same as previous node
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! - transition inverted with respect to previous node

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0 - node must be set to "0" during V2

1 - node must be set to "1" during V2
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Z - node must be set to "Z" during V2

00 - node must be set to "0" during V1 and remain during V2
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11 - node must be set to "1" during V1 and remain during V2

ZZ - node must be set to “Z" during V1 and remain during V2
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Path Example
$path {
$name qdsp_aclk_2 ;
$cycle 40 ;
$slack 0.80 ;
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$launch TCK ; // (rise edge)
$capture TCK ; // (rise edge)
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$transition {
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QdbxIc/Qdsp4Core/AluIc2/U806/a v ; // (nor1)
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QdbxIc/Qdsp4Core/AluIc2/U850/b ^ ; // (nd2)
QdbxIc/Qdsp4Core/AluIc2/U598/a v ; // (inv)
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QdbxIc/Qdsp4Core/AluIc2/U893/a v ; // (xor2)
QdbxIc/Qdsp4Core/AluIc2/AdderIc/sela ^ ; // (mux2)
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}
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$condition {
QdbxIc/Qdsp4Core/AluIc1/U702/b 1 ;
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} 11- 15
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Untestable Paths
 Some paths cannot be targeted by Path Delay ATPG

 Paths that require multiple launch or capture events
 Paths through RAMs or ROMs or any sequential element
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 Other paths may be determined to be “Untestable” or “Undetectable”
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 A combinational or sequential false path
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 Paths blocked by ATPG constraints
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 Paths including redundant logic
 Paths only valid in shift mode
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 Report untestable or violated Paths
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 Check P Rule violations and their description in On-Line Help
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 report_faults –class AU
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On Path Vs. Off Path Inputs
 On Path Input
 An input to a combinational gate along the circuit delay path through which a logic
transition will flow. On-path inputs are typically listed as nodes in the Path Delay
definition file
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 Off Path Input
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 An input to a combinational gate that must be sensitized to allow a transition to
flow along the circuit delay path
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 Off path input should settle to non-controlling values (‘0’ for OR/NOR, ‘1’ for
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AND/NAND) following application of the launch pulse (V2)
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D Q D Q
SI SI
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F1 F1
SE U0 U0 SE
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Off Path Input
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On Path Input
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Hazards Can Impact Path Delay Tests
 A hazard is a circuit condition where off-path inputs change when they

are supposed to remain constant
 Static Hazard: Off-path value changes momentarily
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 Dynamic Hazard: Off-path value changes multiple times
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 Hazards may invalidate a test pattern
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Increasing delay fault size
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Fault Free
Fault Detected
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U0
Test Invalidated
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Fault Detected
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V2@ t1 t2
V2 @ t1 Output sample time t2
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Hazard-Free Path Delay Test Example
G2
C
D
1 D
A G1 G4
F
1 C 1/1 1/1 1
G3 E
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B
0/0 1
F
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E
0 1 2 3 4
All off path Tested Path: STR -> ADF
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inputs do AB = (00), (10) is a hazard free test for path ADF
not change
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 Off-path inputs are stable and hazard-free throughout the test interval
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 This is useful for diagnostics
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Robust Path Delay Test
 When on-path nodes control the first occurrence of a transition

through all gates along the tested path
 Guarantees to produce an incorrect value at the output if the delay of
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the path exceeds the clock period, irrespective of other path delays
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Required Off-Path Input Values (AND gate)
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(01) (01)
On-path input
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On-path
Delay Test Model
Off-path
rising falling
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0 in V1 Robust (DR) X1 S1
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1 in V2
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X1: initial state is “don’t care”; final state is 1
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S1: steady 1 state 11- 20
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Robust Path Delay Test Example
First Transition
G2
C
D
1/0/1
3
A G1 G4 D
F
C 1/0/1/0
1 1 E
G3
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B
1/1 1 F
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E
0 1 2 3 4 5
Tested Path: STF -> ACEF
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AB = (01), (11) is a robust test for path ACEF
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 F will not change state until the transition on E has occurred, any delay
to D can never mask a delay fault that may occur on the tested path
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 If a test passes, then the path is not defective
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 If the test fails, the path may or may not be defective – depending on
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delay of the off path input values
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Non-Robust Path Delay Tests
 This allow the output to change before the on-path transition propagates
along the tested path
Guarantees the detection of a path-delay fault only when no other path
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
delay fault is present on off paths
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(01) (01) Required Off-Path Input Values (AND gate)
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On-path On-path input
Off-path Delay Test Model
rising falling
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0 in V1
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1 in V2
Non-Robust (DS) X1 X1
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X1: initial state is “don’t care”; final state is 1
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Non-Robust Path Delay Test Example
Assume X takes 2 A
additional time G2
units beyond A to X D 1/0/1 X
switch 1
A G1 G4
F
C C
1 1
G3 D
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B
A STF fault for
gate G3, adding 1/1 1
E
an additional E
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time unit
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Tested Path: STR -> ACEF F
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strobe
0 1 2 3 4
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AB = (11), (01) is a non-robust test for path ACEF
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 The pattern would pass even though there is a STF of 1 time unit at G3
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 If there is no defect at X, then it would fail
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Summary of Path Delay Fault Detections
 A Path Delay Fault can have three main types of detection:

 Hazard-Free Detected Robustly
 Guarantees that the test will fail if there’s a sufficient delay on the target path
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independent of delays on other paths and also independent of hazards
Detected Robustly
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
Guarantees that the test will fail if there’s a sufficient delay on the target path
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
independent of delays on other paths
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 Detected Non-Robustly
 Guarantees that the test will fail if there’s a sufficient delay on the target path only if
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there are no delays on the off-paths
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Characterization Tests
 Generate single path sensitization tests that have unambiguous

diagnostic results to target a Hazard-Free Robust test
 Use following command to enable the characterization pattern
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generation
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 set_delay –diagnostic_propagation
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 Default is –nodiagnostic_propagation
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 The pattern would fail only if the target path has a defect; it is not
affected by delay on any other path in the chip
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 Coverage may drop due to more stringent ATPG constraints
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Fault Classification
 Characterization Test (–diagnostic_propagation)

 DR: Fault detected and Hazard Free Robust test
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 DS: Fault detected Robustly but not Hazard free test
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 Regular Test (Default)
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 DR: Fault detected and Robust test
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 DS: Fault detected and Non Robust test
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Launch Cycle
 If Fast-Sequential Path Delay is used (default), the launch cycle will be

system clock launch for all Fast-Sequential Path Delay patterns
 The launch_cycle setting has no effect on Full-Sequential Path Delay;
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any launch type can be used
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 Last Shift Launch
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 Extra Shift Launch
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 System Clock Launch
 However, to generate only system clock launch patterns with Full-
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Sequential Path Delay, constrain Scan Enable to its inactive state
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Simulating Hazards
 On-path transition from non-dominating to dominating value

 No possibility of glitch on off-path: Robust Test
 Possibility of glitch on off-path: Non-Robust Test
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 Check for glitch on the off path input
 set_delay –simulate_hazards
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 Classify a test as DR if there is no glitch possible
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 Default Option
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 Do not check for glitch on the off-path input
 set_delay –nosimulate_hazards
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 May classify a Non Robust test as Robust
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Reconvergent Path
 Paths that branch apart and then come back together

 Marked as AU if V2 of off_path input blocks the propagation.
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 To allow test generation to occur
 set_delay -allow_reconverging_paths
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ip
ch
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* STF on above path is AU if we don’t allow reconverging paths
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Multi-Cycle Paths
 Some paths need more than single cycle for a valid capture
 Multi-Cycle paths can also be tested with modifications to the timing in
the SPF file
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 Paths that are not targeted for the specified frequency need to be
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masked
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 Timing exceptions (SDC)
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 set_delay –mask_nontarget_paths
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For DFTMAX designs in compression mode, don’t use set_delay –
mask_nontarget_paths as it may inhibit effective pattern generation due to the large number
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of X’s created by the masks.

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Multi-Cycle ATPG Flow
 In a design with 1-cycle and 2-cycle paths, test the path delay faults in
two runs
 1st run, targets 1-cycle faults
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 Setup the clock to work at-speed (e.g. 10ns period)
 Remove paths longer than one cycle
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remove_delay_paths -max_cycle 10
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 Generate and save test vectors
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 2nd run, targets 2-cycles faults
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 Remove timing exceptions for 2-cycle paths
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 Setup the clock to work at a multi-cycle period (e.g. 20ns)
 Remove paths less than two cycles
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remove_delay_paths -min_cycle 20
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 Generate and save test vectors 11- 31
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Analyze Fault
 Analyze UD or AU faults
analyze_faults <delay_path_name> -slow <r|f>
Can also be used for detected faults to see the pattern sequence
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
 Analysis steps
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 Generate the values necessary to launch the transition at the head of the selected
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path
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 Generate the values necessary to capture the transition at the tail of the path
Generate the values necessary to propagate the transition through the non-
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launch and non-capture nodes in the path till it reaches the capture point
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 Report success of each step unless it fails at some point
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Analysis Report
 Full Sequential Analysis performed for a Path Delay fault

Non-robust path sensitization unsuccessful ...
Test generation of LAUNCH DFF 15 @ frame 1 (cycle 0, frame 1) successful ...
Test generation of LAUNCH DFF 15 @ frame 1 (cycle 0, frame 1) and CAPTURE
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DFF 14 @ @ frame 3 (cycle 1, frame 0) successful ...
Test generation to OR 10 ( OFF-PATH input AND 9) successful ...
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Test generation to MUX 12 ( OFF-PATH input PI 2) successful ...
Test generation to AND 11 ( OFF-PATH input PI 1) unsuccessful ...
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Analyzing conflict data ...
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3 conflicting requirements found :
1. PI 1 required @ 1
2. AND 9 required @ 0
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3. DFF 15 required @ 1
The gate_report data is now set to "seq_sim_data"
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 Use the –verbose option of analyze_faults command for more details
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 Use the –display option of analyze_faults command to see the
simulated values of the entire path in the GSV
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A frame is a time division within a clock cycle.
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GSV Debug of Delay Path Violations
analyze_faults PATH_1 -slow f -display
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 Open expansion diamonds on inputs of displayed on-path cells to
display the off-path cells
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 See that at least one off-path cell is shown with a value opposite of the
required value
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 There are typically paths between these conflicting requirement cells
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 Gate IDs reported in “Analyzing conflict data ...” can be added to the
GSV with:
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 Show  Path, head=gateid, tail=gateid
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The GUI here shows a part of the Path for which the fault analysis is being done. The pin
data shown is the simulated values of the pattern, that is being used to detect the fault.
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The schematic show all the gates along the On-Path of the path. Off_path inputs are not
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shown , they can be expanded as needed.

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Since it is a STR analysis, you can see that there is a rising transition on the first clock
cycle ( Launch) on the Q pin of the flop . ( Start Point of the path)
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Analysis tips:
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• Specify set_delay –noallow_reconverging_paths. Reconverging paths can

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cause some confusing feedback when a fault isn’t testable.

• Use –verbose option
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• Use –fault_simulation option. Provides the fault simulator’s opinion as well as the
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test generator’s.
• Check which type of path sensitization (if any) is reported as successful
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Strong non-robust  candidate for a robust test

Weak non-robust  failed in search for a robust test
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TetraMAX Workshop

 Extract a set of critical paths from PrimeTime
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 Describe the syntax of a delay path
Run ATPG for the Path Delay fault model
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
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 Describe the Robust and Non-Robust faults
classification
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 Analyze a Path Delay fault
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Begin Lab 11: Path Delay ATPG
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write_delay_paths Write critical delay paths in PrimeTime
set_faults –model path_delay Set the path delay fault model
set_faults –model hold_time Set the hold time fault model
set_atpg –fast_path_delay Use Fast-Sequential ATPG for path delay testing
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add_delay_paths <file> Read delay paths file generated in PrimeTime
remove_delay_paths Remove previously added delay paths
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report_delay_paths Report current delay paths
set_delay –relative_edge Add both str and stf faults for a single delay path
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set_delay –diagnosic_prop Restrict path delay ATPG to only robust tests
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set_delay –simulate_hazards Simulate hazards to determine if test is robust
set_delay – Allow reconvergent off path values
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allow_reconverging_paths
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set_delay –robust_fill Fill non care bits with values to make test robust
set_delay –mask_nontarget_path Mask all scan cells besides the path endpoints
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Agenda
DAY
3
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12 Diagnosis
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13 Conclusion
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Diagnosis ©2018 Synopsys, Inc. All Rights Reserved. 12-1

TetraMAX Workshop
Unit Objectives
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 List the 2 main command used in TetraMAX diagnosis flows
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 Describe the difference between pattern-based and cycle-
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based Fail Data File formats
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 Understand how to interpret the TetraMAX diagnosis results
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Purpose of Failure Diagnosis
 Volume diagnostics
 Diagnose large numbers of parts
 In cooperation with YMS, identify yield killers
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 Accurate diagnostics
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 Run a few parts with a large amount of failure data
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 Intensive analysis done with specialized commands to ensure high confidence of
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results
 Typically done to locate a failure location in preparation for physical failure
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analysis (PFA)
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 Help with debug of simulation failures
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Yield Enhancement Process
 Diagnosis is essential part of yield enhancement process

 Diagnostic results (logical and physical) fed into a Yield Management
System (YMS)
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 Large volumes of device data are analyzed to identify common causes
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of yield loss
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 Detailed analysis / diagnosis can be performed on a representative
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device to understand the failure mechanism
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 Corrective action taken on design, library cell, process and / or reticle
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TetraMAX Workshop
High Level View
Design Flow Process Flow Yield
Design YMS
Process
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Library Development Diagnosis
Development Results
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Mask
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Netlist
Gen Fab
TetraMAX
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Library Diagnosis
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Failure
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TetraMAX Patterns Log
ATPG
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ATE
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Yield is affected by the physical design, library, mask generation or the fab process.
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Synopsys offer two YMS related products:

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Odyssey – Manufacturing-centric YMS

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Yield Explorer – Design-centric YMS

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Volume Diagnostics Flow
Scan Test Patterns
./sa_pat.stil …
./td_pat.stil
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Lot 1 Lot 2
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1 pad[1] 342 (exp=1, got=0) Failure logs files
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3 pad[4] 935 (exp=0, got=1)
…
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YDF
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Diagnose
Design
and save
Image
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TetraMAX fault candidates Yield Explorer
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TetraMAX Workshop
TetraMAX Diagnosis
 When a device fails testing, TetraMAX Diagnosis can be used to

determine the location of the failure
 To accomplish this, failure information from the ATE or simulation is put
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into a file (following a specified format) and diagnosis is run with the
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run_diagnosis command
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 TetraMAX analyzes the failure information and reports the locations and
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types of faults that could have caused the failure
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TetraMAX Workshop
TetraMAX Diagnosis Features
 Accuracy: pinpoints defect location in functional logic or on a scan

chain
 Diagnosis results have high accuracy if the fault(s) associated with the physical
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defect is in the resulting candidate fault list
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 Precision: uses failing and passing patterns
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 Diagnosis results have high precision if the resulting set of candidate faults is
small
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 High performance, scan-based fault simulation
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 Supports Physical diagnosis with a PHDS database
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 Ease-of-Use
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 Text reporting, Tcl API, and graphical results
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Definitions
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Physical Defect: A physical condition on a manufactured chip which causes it to not meet design
specifications.
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Fault: A logical representation of a defect, simplified to facilitate modeling in software.

Fault simulation: simulating the effect of faults in software.
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Fault Candidate: a fault which potentially explains the behavior of a physical defect on the device
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under test.
Pattern: an ATPG sequence possibly consisting of shifting and capturing values into the scan chain.
Consists of many clock cycles.
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Vector/Cycle: A cycle on ATE where stimulus is applied and/or the response is measured.
Failure: A mismatch on ATE where the DUT does not produce an expected result at a primary
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output (PO) or a scan cell.

Failing Pattern: A pattern with at least one failure.
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TetraMAX Diagnosis Flow
Verilog Library
TetraMAX ATPG
• Compile Design
Scan Design • Run design rule check
Netlist • Run ATPG
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Test Protocol
(STIL format) Simulation Coverage
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ATE Vectors
Test Patterns Reports
Binary Image
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ATE Tester
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• Tester failure data log
• Data log post process
Failure Data File
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TetraMAX ATPG
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• Run diagnosis
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Failure Analysis
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• Perform failure analysis
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TetraMAX Workshop
Requirements For Diagnosis
 Test Patterns (Stuck-At, Transition or Bridging)

 Recommended formats: Binary and STIL/WGL
Failure Data File from the ATE (pattern-based or cycle-based)
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
 Must use exactly the same TetraMAX environment that generated test
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patterns
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 Original Verilog netlist
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 Original test protocol file (.spf)
Original libraries
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
Tip: Write out an image file after DRC in the final run and use this image file for diagnosis to
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ensure the same environment
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TetraMAX Workshop
Diagnosis Commands
Diagnosis is primarily controlled using two commands:

 set_diagnosis
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 Specifies diagnosis options that will be persistent across multiple diagnosis runs
 run_diagnosis
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Executes the diagnosis
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
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read_netlist -lib mylib.v
read_netlist mydesign.v
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run_build_model
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set_drc mydesign.spf
run_drc
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set_patterns -external ./patterns/mypat.bin
run_diagnosis diag.fail
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Diagnosis Flow Using Binary Image
Binary File Saved During Pattern Generation
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Read Image
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Patterns Run Diagnosis Failure
file file
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Transcript
+
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Schematic
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Note that the patterns are not part of the binary image file. They need to be read into TetraMAX
separately.
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Advantages of Binary Image File
 File management is simplified

 Encapsulates design netlists, libraries and SPF files
 Simplifies data transfer when Diagnosis is performed by a different group than
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ATPG (i.e. a foundry)
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 Faster performance
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 No need to re-run build and DRC steps
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 Instance names can be “garbled” to provide an extra layer of security
by hiding the design context
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# Read the image
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read_image design_img.gz
set_patterns -external patterns.bin
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run_diagnosis fail_log.txt –display
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Note: To create a “garbled” image file, the image is written with the following command:
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write_image design_garb_img.gz –garble

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To translate a garbled name back to the original name:

• Read the original design database or ungarbled image file
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read_netlist specnetlist.v
• Run Build (if an image wasn’t read)
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run_build_model ...
• Perform design rule checking (if an image wasn’t read)
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run_drc ...
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• Supply the garbled name as argument to get ungarbled name in output.

report_instances u43259 -ungarble
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Secure Image
 Image file can be password protected

 Proprietary, undocumented encryption scheme
 Stronger protection of IP
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 Image creator can specify which TetraMAX commands the image
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receiver is allowed to execute
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 Image file can only be read with the private password
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 After read_image of a secure image file, receiver is limited to only the
commands explicitly allowed
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e.g. report_primitives, GSV, etc. can be permanently disabled
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
 Note: Tcl API commands are disabled after a secure image file is read
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TetraMAX Workshop
Secure Image Commands
 set_commands [-secure <command>]

[-nosecure <command | -all>]
 Allows the specified command along with all its options in the subsequently
written secure image
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 report_commands -secure
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 Lists all allowed commands that can be applied to the image file to be written
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 write_image <file_name> -password <string>
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 Writes an encrypted image which only allows execution of commands listed by
report_commands –secure
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 read_image <file_name> -password <string>
 Reads a secure image unencrypted by the given password
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 TetraMAX will allow only permitted commands to be run
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Instance names can be “garbled” to provide an extra layer of security by hiding the design context:
write_image -garble
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Sample Scripts With Secure Image
# Creating secure image

set_commands -secure help
set_commands -secure run_diagnosis
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set_commands -secure set_diagnosis
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set_commands -secure set_patterns
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write_image image_enc.gz -password top_secret \
-schematic_view –replace
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# Reading secure image
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read_image image_enc.gz -password top_secret
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set_patterns -external pat.bin
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run_diagnosis fail.log
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Tester Failure Data File
 Captures the ATE results of a failing device

 Two formats
Pattern-based failures, in terms of failing patterns
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
 Format used internally in TetraMAX
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 Cycle-based failures, in terms of failing vectors
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 Most ATE vendor testers can generate TetraMAX pattern-based failure
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files automatically
 Partnership with most major ATE vendors
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 Avoids complexity in translating failure file
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 Contact the ATE vendor for details on generating failure files that are formatted for
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TetraMAX
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TetraMAX Workshop
Pattern-based Failure Data Format
 TetraMAX expects the following fields per

line:
# Pattern Output Cell
 1. Failed ATPG pattern number
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50 vout 55
 Pattern 0 is first pattern - usually the chain test 50 abus 57
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 2. Device output which mismatched 58 vout 57
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83 xstrb
 Can be output pin name or chain name
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 3. Failed scan cell position # + expected values
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 If Device output is a scan chain output, and the 94 vout 5 1
pattern performs a chain unload operation
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97 xstrb 0
 Position 0 is closest to scan-out pin
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 4. Optional expected data
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The vout and abus ports are Scan Outputs.
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The xstrb port is regular functional output.

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TetraMAX Online Help

Contents  Fundamental Concepts  Understanding Failure Data Format
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Cycle-based Failure Data Format
 TetraMAX expects the following field per

line:
# C Output Cycle
 1. “C”
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C vout 2764
 Indicates this failure log is cycle-based C abus 2940
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 2. Device output which mismatched C vout 3048
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C xstrb 3785
 3. Cycle number that failed
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 Indicates vector number that failed, with first # + expected values
vector being number 1
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C vout 4212 1
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C xstrb 4908 0
 4. Optional expected data
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TetraMAX Workshop
Checking Expected Data in Failure Data File
 In some Diagnosis flows, custom scripts are used to convert failing tester
data to a TetraMAX failure log
 These translation scripts can be prone to error
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 If expected data exists in the Fail Data File, by default, TetraMAX will check
that the expected data is consistent with the data in the ATPG patterns
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 If a cycle-based fail file is used, any difference in the number of cycles on
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the ATE must be accounted for
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set_diagnosis <file> … -cycle_offset <d>
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 If cycle numbers start at 0 on ATE, use “1” as the offset
If extra initialization cycles exist in vectors run on the tester, use a negative integer
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
as the offset
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 If the offset is unknown, a range of offsets can be tested
run_diagnosis –find_offset {<begin_range> <end_range>}
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The set_diagnosis [-check_expected_data | -nocheck_expected_data]
controls if expected data is checked. It’s on by default.
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Note: the –find_offset option requires that the failure log contain expected values and there
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must be at least 10 failures in the failure log.

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Truncated Failure Data File
 ATE limitations may force a user to generate a truncated failure log file
 Only use the first N patterns for diagnosis
run_diagnosis –truncate <N>
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 Set the ATE fail memory limit (d = number of failures)
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set_diagnosis –failure_memory_limit <d>
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 Set the ATE failing cycles limit (n = number of failing cycles)
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set_diagnosis –failing_cycles_limit <n>
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 Assume last failing pattern is incomplete and ignore it
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set_diagnosis –incomplete
12 Out1 23
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ATE memory limit 15 Out2 56
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15 Out2 78 truncate here
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If last failure was captured for pattern P, generally, it’s safer to truncate to pattern P-1 because we
can’t be sure if all the failures for pattern P was captured.
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If there are many failures for the first failing pattern, we may not be able to diagnose that device
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with the given pattern order because we cannot be sure if we have full failure information for the
pattern.
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Failing patterns from the middle cannot be eliminated – only truncated from the end.
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TetraMAX Diagnosis Engines
 Two primary algorithms

 Functional diagnosis
 For physical defects in functional logic
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run_diagnosis …
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 Chain diagnosis
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 Faults that affect chain shifting
run_diagnosis … –chain_failure
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 The proper diagnosis engine is automatically selected based on the
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status of the chain test
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 Automatic selection controlled by:
set_diagnosis [-auto | -noauto]
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 If the chain test pattern failed, then chain diagnosis is run
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TetraMAX Workshop
Functional Logic Diagnosis
 For Basic-Scan and Fast-Sequential patterns

 Can be used for all pattern types, except IDDQ and Full-Sequential
Finds stuck-at faults that explain the behavior of the silicon
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
 Most physical defects behave as one or more Stuck-At faults when considering
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an individual failing vector
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Currently, there is no Diagnosis support for Full-Sequential or functional patterns.
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Functional diagnosis assumes that the chain shifting is functional.

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Note: The diagnosis engine does not make any assumptions on the nature of the defect based on the
type of fault tested. This means, for example, that any failures collected while running transition
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patterns could lead the diagnosis engine to find the Stuck-At fault type. Nevertheless, it is possible
to specify the logic diagnosis engine to search by preference for a defect of the delay type by using
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-delay_type option of the set_diagnosis command

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Chain Diagnosis Overview
 Use first pattern to test for scan chain integrity

 Typically a chain test pattern - only shifts – no capture
Failures on the first pattern can indicate type of chain defect
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
 Stuck-at fault, delay fault, hold-time issue
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 Uses all patterns to diagnose chain failure
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 Includes patterns that capture values
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 Accuracy improves with data from more failing patterns
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 Recommend at least 10
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 Usage:
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set_diagnosis –auto
run_diagnosis <failure_file> –chain_failure
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Chain diagnosis assumes that the functional logic is defect free. If this assumption is not true, the
diagnosis results can be misleading.
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The chain test can indicate the defect type. For example, if 0011 is used, a fast-to-rise defect might
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change the output to look like 0111…

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What is a proper chain test?

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There should be no capture clock: a proper chain test is a pattern without clock capture cycle (or
pulse clock in TetraMAX terminology) after a measure PO.
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A proper chain test is a pattern with at least all of the following transitions:
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0->0, 0->1, 1->0, 1->1

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There can be more complex chain tests that the user can specify with set_atpg. By default, the
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chain test is generated as the 1st pattern. see the set_atpg command options.
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If chain test is not failing during the shift operation, the chain diagnosis will not help. Therefore the
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TetraMAX Workshop
Chain Diagnosis Principle
 Assume a Stuck-At defect for simplicity

 Scan cells upstream will drive valid values to functional logic, but
appear stuck-at when unloaded
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 Scan cells downstream will drive invalid values to functional logic, but
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may capture valid values that can be observed
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 Algorithm uses these
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observations to
diagnose scan chain ?
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1 or 0 X
D D
physical defects Q Q
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SI SI
Stuck at 1/0
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Controllable but unobservable Uncontrollable(?) but observable
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If the first pattern is not chain test, a much lower accuracy algorithm that supports only stuck-at
chain defects will be used. It is strongly recommended that the first pattern be the chain test.
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Example of why there’s uncertainty in diagnosing chain defects.

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Given the following chain order with groups of flops G1, G2 and G3, and a fault location as
follows:
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G1, fault, G2, G3

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When shifting in, flops G2 & G3 have unknown values. When shifting out, flop G1 and upstream
flops will have a fixed value, based on the stuck-at value of the fault. TetraMAX looks at the flops
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with the fixed values in determining the fault location.

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If the functional logic fed by G3 outputs to G2, the G2 flops will have fixed values after capture.
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Therefore, we'll see G1 and G2 with fixed values. TetraMAX will say the fault is at the output of
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G2, instead of the real location further upstream.

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TetraMAX Workshop
Chain Diagnosis Output
 Defects are simulated, compared with tester results and assigned a
score based on how well they match
 Best candidates are shown with match scores
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 Examine identified scan cell, and the scan cells before and after it,
along with the connecting nets
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fail.log scan chain diagnosis results: #failing_patterns=79
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-----------------------------------------------------------
defect type=fast-to-rise
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match=100% chain=c0 position=178 master=CORE/c_rg0 (46)
match=100% chain=c0 position=179 master=CORE/c_rg2 (57)
match= 98% chain=c0 position=180 master=CORE/c_rg6 (54)
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defect type: type of defect
CORE/c_rg2 CORE/c_rg0
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match: how well simulated defect matches failure log file 179 178
chain: chain name D D
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Q Q
position: scan cell location in chain where position 0 is SI SI
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closest to the scan-out pin
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No GSV for chain diagnosis.
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Chain Diagnosis Tips:

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Follow-up only high confidence results

Low number of fault candidates returned
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Match score higher than 80%

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If too many candidates (low precision)

Capture more failing pattern data
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Try Fast-Sequential patterns with large number of capture cycles

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Add a set/reset test to the pattern set with set_atpg –add_setreset_test

For DFTMAX designs with high X-tolerance, generate xtol chain tests with the set_atpg
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–xtol_chain_test command. See the man page for usage details.

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Sample Output: Diagnosis Summary
Failure log file used Failures summary

TEST-T> run_diagnosis test.fail -display
Diagnosis summary for failure file test.fail
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#failing_pat=2, #failures=2, #defects=1, #faults=1, CPU_time=0.00
Simulated : #failing_pat=2, #passing_pat=4 #failures=2
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------------------------------------------------------------------------
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Defect 1: stuck fault model, #faults=1, #failing_pat=2, #passing_pat=4,
#failures=2
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------------------------------------------------------------------------
match=100.00%, #explained patterns: <failing=2, passing=4>
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sa1 DS i1/out (NOT)
sa0 -- i1/in (NOT) Simulation information
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sa1 -- f3/d (SDFF)
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------------------------------------------------------------------------
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Note: All information displayed in the report are accessible through
a Tcl API - useful for script automation and volume diagnostics
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#failing_patterns
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This indicates the total number of failing patterns in the failure file. A pattern is assumed to include
both a measure of all POs and an unload of the scan chain.
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#failures
In the main header, shows the number of failures in the failure log file. In each defect's header, it
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shows the number of failures the candidates in that defect caused.

#defects
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This indicates the number of different defects that appear to be causing the failures.
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#faults
Indicates the number of collapsed faults. In the main header, it indicates the total number of faults.
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In each defect's header, it shows the number of faults in that defect group.
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Sample Output: Fault Candidate
TEST-T> run_diagnosis test.fail -display

Diagnosis summary for failure file test.fail
Simulated : #failing_pat=2, #passing_pat=4 #failures=2
ng
------------------------------------------------------------------------
Defect 1: stuck fault model, #faults=1, #failing_pat=2, #passing_pat=4,
#failures=2
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------------------------------------------------------------------------
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sa1 DS i1/out (NOT)
sa0 -- i1/in (NOT) Failing and passing patterns
that are explained by the fault
sa1 -- f3/d (SDFF)
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------------------------------------------------------------------------
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Cell type The following faults are all equivalent
sa0 sa1 sa1 D
Fault pin pathname
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Fault types: sa0, sa1, str, stf, sa01, strf, bDOM, bOR, bAND, bUN
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Match score based on how well the fault matches the ATE failures
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Fault types:
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sa0 – Fault location behaves like a stuck-at 0.

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sa1 – Fault location behaves like a stuck-at 1.

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str – Fault location behaves like a slow-to-rise.

stf – Fault location behaves like a slow-to-fall.
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sa01 - Fault location behaves like a sa0 on some patterns, and a sa1 on others. This could be a
coupled open or a bridge type defect.
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strf - Fault location can cause a delay on both rising and falling transitions (slow-to-rise-fall).
bAND or bOR - The defect location behaves as a wired-AND or wired-OR type bridge.
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bDOM - The defect location behaves as the victim node of a dominant bridge.
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bUN - An unknown bridging type relationship exists. It indicates that there is some signal
correlation which does not behave as the well known bridging fault models.
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What is the Match Score?
 The match score is based on how well a fault candidate’s failing

behavior matches the failures seen on the tester
 Three components are computed over patterns simulated for each fault
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candidate
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 By default, all failing patterns and subset of passing patterns are simulated to
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compute the match score
For a Simulated Pattern
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Tester Results Simulation of a fault candidate
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F TFSF F T = tester
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S = simulator
x
F TFSP P F = fail
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P = pass
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TFSF—tester fail, simulator fail
Number of measures that failed on the tester and the fault candidate was detected in the simulator at
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the same location and pattern.

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TFSP—tester fail, simulator pass

Number of measures where the tester failed, but the fault candidate was not detected in the
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simulator at the same location and pattern.

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TPSF—tester pass, simulator fail

Number of measures where the fault candidate was detected, but the tester measure passed at the
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same location and pattern.

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Computing the Match Score
 Each candidate is assigned a score

 range: 0% - 100%
It’s possible for multiple candidates to get the same score
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
 Higher match scores indicates higher confidence that the fault
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candidate’s location is the same as the defect’s
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 Score components can be displayed with
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run_diagnosis –verbose option
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match=25.00%, (TFSF=1/TFSP=3/TPSF=0), #perfect/partial match: <failing=1/1, passing=2>
sa1 NO i1/out
sa0 -- i1/I
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TFSF
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match % = X 100
TFSF + TFSP + TPSF
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Terminology: Explaining Patterns
 A fault explains a failed pattern if the fault simulation results

match the ATE failure exactly for that pattern
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 Patterns that cannot be explained by any single stuck-at fault
are unexplained
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Physical defect detected Fault simulation of fault F1 Fault simulation of fault F2
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on ATE by pattern P1 (P1 explained by F1) (P1 unexplained by F2)
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1 1 1
1 1
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1
F 0 F 0 F
0
F1
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1 1
1 F2
1 F 1 F 1
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1 1 1
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“F” indicates a failure (mismatch on the ATE, or fault simulation detection).
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Fault F1 has identical behavior to the failure on the tester for pattern P1. Therefore, F1 explains
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pattern P1.
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But F2 had only one matching failure, so it did not match the behavior seen on the tester.
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Therefore, F2 does not explain P1.

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GSV Output
 Use –display option of run_diagnosis
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The schematic here is in design view, not primitive view
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N-Detect: Better Precision
 If diagnosis identifies many possible fault locations, using N-Detect

patterns may enhance precision
 Generate multiple patterns that detect the same fault
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 Increase confidence of defect location before beginning failure analysis
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TetraMAX Workshop
N-Detect Flow Example
run_diagnosis orig_fail.txt \
–write_fault_list flist.txt
read_faults flist.txt
set_atpg -decision random
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run_atpg –ndetect 10
write_patterns ndet.stil –format stil
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write_patterns ndet.bin –format binary
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ndet.stil ndet.bin
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new_fail.txt run_diagnosis new_fail.txt
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Better Results
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This flow can be used to gain higher confidence in diagnosis results. The fault candidates in the
diagnosis results can be written out as fault list, read back into tmax for additional pattern
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generation. The new pattern set can be re-run on the tester. The new failure log file can be re-
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diagnosed to see if the fault site remains the same.

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N-detect ATPG is recommended for pattern re-generation. Can try different fault models, such as
transition and bridging.
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TetraMAX Workshop
Physical Data Improves Diagnostics
 Many manufacturing defects have complex

logical behavior
 Short between two wires
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 Open in the middle of a long wire
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 Diagnostics need layout information to
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accurately model these defects
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 Bridging behaviors with adjacent nets
 Open behaviors in branches of high-fanout nets
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 Yield analysis and PFA engineers also need
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physical location/layer of defect candidates
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TetraMAX Workshop
High-Capacity Physical Database
 LEF/DEF is loaded once and used by both TetraMAX Diagnostics

TetraMAX and Yield Explorer
 Shared physical database (PHDS)
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 Physical data is stored on disk, not in
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memory
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 No need to partition large designs
LEF/DEF PHDS
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 High-performance access for TetraMAX
physical diagnostics
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 Dynamic extraction of adjacent nets and net
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branches
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Yield Explorer
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TetraMAX Workshop
PHDS Creation in TetraMAX
# Specify LEF/DEF directories
set_physical_db -lef_dir ./LEF -def_dir ./DEF
# Specify the directory to save the database
set_physical_db -database /home/proj/chipA/PHDS
Data Preparation # Specify the device name and version
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set_physical_db -device [list "CHIPA" "1"]
LEF/DEF
# Specify the top level DEF file
set_physical_db -top_def_file chipA.def
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Read LEF/DEF & # Read LEF/DEF and create the PHDS database
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Create database write_physical_db -replace
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Writing Physical Database...
PHDS LEF input directory : ./LEF
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DEF input directory : ./DEF
Top DEF file name : chipA.def
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PHDS output directory: /home/john/chipA/PHDS
Device name : CHIPA
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Device version : 1
Successfully created Physical Database.
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Note: PHDS may also be created in Yield Explorer
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PHDS Data Access Process (DAP) Server Setup in TetraMAX
# Specify PHDS database

set_physical_db –database /home/proj/chipA/PHDS
Server Setup # Specify port number where to connect PHDS db
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set_physical_db –port_number 9990
DAPListener # Start the job to access the database, the
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@9990 # DAPListener
open_physical_db
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PHDS
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Starting Data Access Process...
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Hostname : server1234
Port Number : 9990
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Physical Database Directory: /home/john/proj/PHDS
Successfully started Data Access Process.
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Note: a Data Access Server (DAS) may also be created in Yield Explorer
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TetraMAX PHDS Usage
# Read image and patterns

Data Usage read_image TOP.logical.img
set_patterns –external TOP.pat
TetraMAX Read Image
Image # Connect to PHDS database
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set_physical_db –hostname server1234
Patterns Read Patterns set_physical_db –port_number 9990
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set_physical_db –device [list “CHIPA” “1”]
set_physical_db –top_design TOP
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Connect PHDS
PHDS
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# Run physical diagnosis and save results
Diagnose run_diagnosis datalog1
Failures
write_ydf TOP.1.ydf –replace
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run_diagnosis datalog2
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YDF write_ydf TOP.2.ydf –replace
...
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run_diagnosis datalog392
write_ydf TOP.392.ydf –replace
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TetraMAX Workshop
Sample Output: Physical Diagnosis Summary
TEST-T> run_diagnosis fail_56.log

Setting top-level physical design name to 'RISC_CHIP'
Check expected data completed: 241 out of 241 failures were checked
Diagnosis summary for failure file fail_56.log
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Simulated : #failing_pat=30, #passing_pat=96, #failures=194
-----------------------------------------------
Defect 1: stuck-at fault model, #faults=1, #failing_pat=30, #passing_pat=96, #failures=241
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Observable points:
1693 1687 1696 1699 1672 1530 1529
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------------------------------------------------
Explained pattern list:
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40 41 47 48 50 51 54 55 58 59 67 69 70 71 72 73 77 78 79 80 85 88
92 93 94 95 97 98 99 101
--------------------------------------------------
Physical Pin Data
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sa01 DS I_RISC_CORE/I_ALU/U14/ZN (inv0d1)
Cell Boundary
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Pin_data: X=747110 Y=652790, Layer: METAL (38)
Cell_boundary: L=746115 R=747345 B=650175 T=653865 Subnet ID
Subnet_id=4
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---------------------------------------------------------------- Performance Data
Total Wall Time = 22.97 sec PHDS Query Time = 22.13 sec
PHDS queries: subnets(added/total)=10/40 bridges(added/total)=28/58
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Pin_data:
• X is the horizontal coordinate of one of the vertices of the pin associated with the location of the fault
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candidate.
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• Y is the vertical coordinate of one of the vertices of the pin associated with the location of the fault
candidate.
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• Layer is the physical layer where the pin object is defined.

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Cell_boundary:
• L is the horizontal coordinate of the leftmost boundary of the cell identified with the fault candidate.
• R is the horizontal coordinate of the rightmost boundary of the cell identified with the fault candidate.
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• B is the vertical coordinate of the bottommost boundary of the cell identified with the fault candidate.
• T is the vertical coordinate of the topmost boundary of the cell identified with the fault candidate.
U
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Also note that the performance data in the physical diagnosis report is slightly different than the standard
diagnosis report:
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The PHDS diagnosis report includes the wall time and the time it takes to query the PHDS database during
diagnosis.
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The second line in the report displays the number of extracted subnets and the number of bridge pairs queried
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in the PHDS database compared to the total number of subnets and bridging pairs identified during the
previous diagnosis run. This data helps you identify any matching issues between the logical and physical
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names during diagnosis.

The subnets and bridges extracted during a diagnosis run are displayed as “added”. The “total” includes
subnets and bridges extracted in previous diagnosis runs. For example, if the next diagnosis run extracts 10
subnets and 22 bridges, the second line appears as follows:
PHDS queries: subnets(added/total)=10/50 bridges(added/total)=22/80

TetraMAX Workshop
Physical Diagnosis: Subnets
 Physical topology is extracted from PHDS database

 Extracts subnet faults to more precisely localize defects on
high-fanout nets
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 Only considers physically possible combinations
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Physical Topology Subnets Extracted
A
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N.2 B
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E N.1
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C
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The default flow, dynamic subnet extraction, is performed during diagnostics. Static subnet
extraction (i.e. extracting all subnets upfront) is only recommended when you run volume
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diagnostics on a large number of failing parts. Otherwise, the additional runtime required for static
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extraction is greater than the total reduction in diagnosis runtimes.

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Physical Diagnosis: Bridge Extraction
 During run_diagnosis, PHDS is queried dynamically for bridging pairs

 Given a net, PHDS will return likely bridge pairs to this net
 Returns neighbor nets touched within “tolerance” distance
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 Different “tolerance” per layer
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 Bridge pairs will be used in diagnostics to improve accuracy
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Tolerance
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Neighbor
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Net
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Neighbor
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Net Corner-To-Corner Bridging
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Just like with subnets, bridging pairs are dynamically extracted from PHDS by default. A static
extraction flow is also available for volume diagnosis flows where it may give an overall diagnosis
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runtime advantage.
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Setting the tolerance:

• If pitch information exists in the technology files, default distance is equal to the pitch
Fo
• If no pitch, default is 1000nm

Changing default:
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set_physical –tolerance {METAL 50 METAL1 100}

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 List the 2 main command used in TetraMAX
diagnosis flows
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 Describe the difference between pattern-based and
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cycle-based Fail Data File formats
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 Understand how to interpret the TetraMAX
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diagnosis results
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Begin Lab 12: Diagnosis
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write_image <file> Write a binary image file
read_image <file> Read a binary image file
write_image <file> -password <string> Write a secure binary image file
read_image <file> -password <string> Read a secure binary image file
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set_commands –secure <command> Declare the allowed commands in a
subsequently written secure image file
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report_commands -secure Report the secure commands
set_diagnosis –check_expected_data
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Checked expected data in the fail data file
set_diagnosis –incomplete_failures Indicates that the fail data is not complete
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set_diagnosis –cycle_offset <n> Adjust cycle count in the fail data file
set_diagnosis -auto Automatically select the diagnosis engine
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run_diagnosis –display Display diagnosis results in the GSV
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run_diagnosis –truncate <n> Declare last pattern applied for diagnosis
run_diagnosis –chain_failure
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Run chain failure diagnosis engine
run_atpg –ndetect <n> Enable N-detect ATPG
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TetraMAX Workshop
Agenda
DAY
3
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Tr
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12 Diagnosis
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13 Conclusion
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Conclusion ©2018 Synopsys, Inc. All Rights Reserved. 13-1

TetraMAX Workshop
After Units 1-4, You Can Now
 Use TetraMAX to pass the run_build_model and run_drc steps

 Run ATPG and obtain generate coverage reports
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 Debug Test Coverage issues
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TetraMAX Workshop
After Unit 5-8, You Can Now
 Reduce the Test Pattern set using various methods including clock
grouping and DFTMAX compression
 Write scan patterns for validation in simulation and/or passing on to
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ATE
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 Simulate scan patterns using MAX testbench
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 Modify the SPF for At-Speed testing
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 Read an SDC file to apply At-Speed Timing Exceptions
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 Control Switching activity with Power-Aware ATPG
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TetraMAX Workshop
After Units 9-12, You Can Now
 Generate At-Speed Transition Delay, Slack-Based Transition Delay, and

Path Delay patterns
 Use On-Chip Clocking (OCC) to perform At-Speed testing
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 Run diagnosis to determine the
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cause of a failure on the ATE
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TetraMAX Workshop
On Demand Training
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Recorded “Flash”
Training Modules
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TetraMAX Workshop
Documentation on SolvNet
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In addition to the
OLH, TetraMAX has
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HTML and PDF docs
available on SolvNet
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TetraMAX Workshop
Reference Methodology Scripts
 Synopsys Recommended Scripts

 Available for download from SolvNet
 https://solvnet.synopsys.com/rmgen
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 ATPG flow options include:
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 Stuck-At
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 Transition Delay
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 Path Delay
 Bridging Faults
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 Power-Aware
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 On-Chip Clocking (OCC)
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 DFTMAX Ultra Compression
TetraMAX II
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
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TetraMAX Workshop
SolvNet: TetraMAX Reference Methodology
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TetraMAX Workshop
Course Evaluation
 Synopsys needs your feedback to improve our courses

 Please take the time to complete the course evaluation you will receive
by email
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TetraMAX Workshop
Thank You!
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TetraMAX Workshop
Appendix
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Downloading Lab Files From SolvNet
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TetraMAX Workshop
How to Download Lab Files (1/2)
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From the SolvNet home page:
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TetraMAX Workshop
How to Download Lab Files (2/2)
Locate Course Title
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2017.09
2016.03
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Click to download the .tar.gz file.
(You may be asked for your SolvNet password a second time)
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A README file will walk you through the installation steps
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TetraMAX Workshop
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TetraMAX Workshop
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Customer Support
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© 2018 Synopsys, Inc. All Rights Reserved 20181001
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Customer Support © 2018 Synopsys, Inc. All Rights Reserved. cs-1

Synopsys Support Resources
 Build a solid foundation:

Hands-on training for Synopsys tools
and methodologies
https://synopsys.com/support/training.html
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 Workshop Schedule and Registration
 Download Labs
(SolvNet ID required)
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 Drill down to areas of interest:
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SolvNet online support
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https://solvnet.synopsys.com
 Online technical information and access to
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support resources
 Documentation & Media
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 Ask an Expert:
Synopsys Support Center
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https://onlinecase.synopsys.com
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training.synopsys.com
CS - 2
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SolvNet Online Support
 Immediate access to
the latest technical information
 Product Update Training
 Methodology Training
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 Thousands of expert-authored
articles, Q&As, scripts and tool tips
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 Open a Support Center Case
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 Release information
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 Online documentation
License keys
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
 Electronic software downloads
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 Synopsys announcements (latest
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tool, event and product information)
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https://solvnet.synopsys.com CS - 3
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SolvNet Registration
1. Go to SolvNet page:
 https://solvnet.synopsys.com/
2. Click on:
 “Sign Up for an Account”
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3. Pick a username and password.
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4. You will need your “Site ID”
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 For Information on how to find your
Site ID, select the “Synopsys Site ID”
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link
5. Authorization typically takes
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just a few minutes.
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Support Center
 Industry seasoned Application Engineers:

 50% of the support staff has
>5 years applied experience
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 Many tool specialist AEs with
>12 years industry experience
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 Engineers located worldwide
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 Great wealth of applied knowledge:
Service >2000 issues per month
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
 Remote access, and interactive debug,
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available via WebEx
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Contact us:
Open a support case
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http://www.synopsys.com/Support/GlobalSupportCenters
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CS - 5
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Other Technical Sources
 Application Consultants (ACs):

 Tool and methodology pre-sales support
 Contact your Sales Account Manager for more information
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ni
 Synopsys Professional Services (SPS) Consultants:
ai
 Available for in-depth, on-site, dedicated, custom consulting
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 Contact your Sales Account Manager for more details
ip
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 SNUG (Synopsys Users Group):
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https://www.synopsys.com/community/snug.html
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CS - 6
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Summary: Getting Support
 Customer Training
https://www.synopsys.com/support/training.html
 Register for a Class
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 Download Labs
 SolvNet
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https://solvnet.synopsys.com
ai
Tool Documentation and Support Articles
Tr

 Product Update and Methodology Information / Training
ip
 Open a Support Case (Support Center)
ch
 Other Technical Resources
Synopsys Users Group (SNUG)
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
 Application Consultants
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 Synopsys Professional Services CS - 7
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Tmax 2017.09 SG

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CUSTOMER EDUCATION SERVICES

Synopsys Customer Education Services

Mountain View, California 94043

Workshop Registration: http://training.synopsys.com

For Internal Microchip Training Purposes Only

Destination Control Statement

690 E. Middlefield Road

Document Order Number: 30-I-021-SSG-017

TetraMAX Student Guide

Synopsys Customer Education Services

For Internal Microchip Training Purposes Only

Unit i: Introduction & Overview

Propagate Fault Effect (2/4) ............................................................................................ 1-8

Record the Test Pattern (4/4) ........................................................................................ 1-10

Testing Sequential Designs ............................................................................................ 1-11

The Full Scan Strategy ................................................................................................... 1-13

Test Patterns Overlap .................................................................................................... 1-15

TetraMAX Interfaces ..................................................................................................... 1-17

Launching TetraMAX .................................................................................................... 1-19

Tcl API Commands........................................................................................................ 1-21

Retrieving Attributes Values.......................................................................................... 1-23

Tcl API Example............................................................................................................ 1-24

Getting Help - SolvNet Resources ................................................................................. 1-26

Synopsys 30-I-021-SSG-017 i TetraMAX Workshop

For Internal Microchip Training Purposes Only

Unit 2: Building ATPG Models

Investigating Models Graphically .................................................................................. 2-22

ATPG Modeling Primitives: Partial List ....................................................................... 2-24

ATPG Modeling Primitives: Examples ......................................................................... 2-25

Memory DFT Strategies ................................................................................................ 2-27

Clock Stable and Load Stable ........................................................................................ 2-30

RAM Modeling: Basic Example .................................................................................... 2-32

Utility to Generate TetraMAX Memory Models ........................................................... 2-34

Unit Objectives Summary .............................................................................................. 2-36

Command Summary (Lecture, Lab) .............................................................................. 2-37

Unit 3: Running DRC

Synopsys 30-I-021-SSG-017 ii TetraMAX Workshop

For Internal Microchip Training Purposes Only

Controlling ATPG: Agenda ............................................................................................. 3-4

Debugging an S1 Violation ............................................................................................ 3-27

Change Pindata to test_setup to Debug Initialization Issues ......................................... 3-29

Stability Patterns ............................................................................................................ 3-30

Using the SWV .............................................................................................................. 3-32

Want to Quickly Return to TEST Mode? ...................................................................... 3-34

Fault Classes .................................................................................................................. 3-36

Faults Classifications Right After DRC ......................................................................... 3-38

Unused FF Output Pins become UU Faults ................................................................... 3-40

Undetectable Redundant (UR) Fault .............................................................................. 3-42

Constraints Can Create AU Faults ................................................................................. 3-43

Defining Nofaults........................................................................................................... 3-45

Synopsys 30-I-021-SSG-017 iii TetraMAX Workshop

For Internal Microchip Training Purposes Only

Fault List After Collapsing ........................................................................................... 3-50

Enabling Fast-Sequential ATPG .................................................................................... 4-12

When Can Fast-Sequential ATPG Help? ....................................................................... 4-14

Results after Fast-Sequential ATPG .............................................................................. 4-15

ATPG Guidelines ........................................................................................................... 4-17

Enabling Multicore Support ........................................................................................... 4-19

Multicore run_atpg Output ............................................................................................ 4-21

Post-ATPG: Reducing ND Faults .................................................................................. 4-23

Post-ATPG: Final Abort Limit Results.......................................................................... 4-25

Low Coverage: Analyze the Clocks .............................................................................. 4-27