Introduction

Prior to scan insertion, the tool performs limited rule

checks on the design

For scan insertion Tool identifies all sequential

elements I/O controlability and observability.

If tool fails to control or observe any fault location

from any PI's and PO's those locationstestable com
pletely or may not be testable

What Is BIST

On Chip/circuit

Test pattern generation

Response verification

Random pattern
generation,
very long tests
Response compression

Test Pattern Generation (TPG)

BIST
Control Unit

Circuitry Under Test

CUT

Test Response Analysis (TRA)