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 Table of Contents
Before you Begin .......................................................................................................................... 2

Lab 4: Top-Level SSN Insertion .................................................................................................... 3

Objectives .................................................................................................................................. 3
Introduction ................................................................................................................................ 3
Exercise 1: First DFT Insertion Pass: Performing Top-Level Boundary Scan and MemoryBIST Insertion
.................................................................................................................................................. 4
Exercise 2: Second DFT Insertion Pass: Inserting Top-Level EDT, OCC, and SSN ....................... 8
Exercise 4: Performing Scan Chain Insertion (Top-Level) using Tessent Scan .............................10
Exercise 5: Verifying the ICL-Based Patterns after Synthesis .......................................................11
Exercise 6: Generating Top-Level ATPG Patterns .......................................................................12
Exercise 7: Retargeting Block-Level ATPG Patterns at Top-Level ................................................14

Lab Answers ................................................................................................................................16

Lab 4.........................................................................................................................................16

NOTES:.........................................................................................................................................17

Lab: Top-Level SSN Insertion 1

 Before you Begin

You will need to:

1. Obtain lab data if you have not already done so.

2. Set environment variables.

Obtaining Lab Data

If the ssn_data directory, with lab subdirectories, is located in the home directory (e.g. cd ~), please
proceed to the lab exercises as you have already set up the lab database on this VM.

If this is the first time you are starting a session for this VM, the ssn_data directory will not be in the
home directory and you will need to download and extract it using the following instructions.

1. Double click on the Desktop icon Download_lab_data, . This launches a web browser.

2. On the resulting web page, select the file named tessent_ssn_data_v2021.2_20210907.tar.gz.

3. In the resultant window, select the Download button, enable the Save File button, then, select the OK
button to download the file.

4. Move the file in the Downloads directory to the home directory. If you are using the terminal
(Applications>Favorites>Terminal) you can use the following command:

mv ./Downloads/tessent_ssn_data_v2021.2_20210907.tar.gz .

5. In a terminal window, extract the files from the compressed tar file using the command:

tar xzvf ./tessent_ssn_data_v2021.2_20210907.tar.gz

You should now have a directory named ssn_data in your Home directory. That directory contains all the
files you need to perform the exercises, in this learning path.

Setting Environment Variables

The environment uses bash and is ready to use for the labs with all needed environment variables already
setup.

$SSN_LABS is an environment variable set up under the home directory that points to the training data
directory. If it is not already set up, you can execute SETENV SSN_LABS $HOME/ssn_data at your Linux
prompt to create it.

You are now ready to proceed with lab exercises.

Lab: Top-Level SSN Insertion 2

 Lab 4: Top-Level SSN Insertion

Objectives
Upon completing this lab, you should be able to:

• Insert boundary scan with auxiliary logic for top-level SSN signals

• Integrate SSN at the top-level

• Generate and simulate top-level patterns

• Retarget block-level ATPG patterns

Introduction
During top-level SSN insertion, the tool inserts other logic test elements into the design. This DFT insertion
flow is similar to the one where SSN is not present. This lab performs the SSN top-level workflow
described in lectures to insert SSN into the top-level design.

For the SSN top-level insertion flow, we will go through the following steps:

• First DFT Insertion Pass: Performing top-level BoundaryScan and MemoryBIST insertion (If the
top-level design contains memories)

• Second DFT Insertion Pass: Inserting top-level EDT, OCC, and SSN

• Synthesis for top-level Insertion

• Performing Scan Chain insertion

• Verifying ICL-based Patterns

• Generating top-level ATPG patterns

• Retargeting block-level ATPG patterns to the top-level

To insert SSN at the top-level of the design, we need to have these prerequisites:

• The IEEE 1149.1 interface should be available at the top-level during the logic test.

• All lower-level physical blocks should have SSN inserted before inserting SSN into the top-level
design.

Lab: Top-Level SSN Insertion 3

Exercise 1: First DFT Insertion Pass: Performing Top-
Level Boundary Scan and MemoryBIST Insertion
The first DFT insertion pass at the top-level adds DFT elements to the design. This step is similar to the
first DFT insertion pass of the standard hierarchical flow. However, it uses the auxiliary input and output
pins to connect the SSN bus_data ports and the bus_clock instead of using them for the EDT channels.

Instructions
Go to the Exercise1 directory in Lab4.

$ cd $SSN_LABS/Lab4/Exercise1

Invoke Tessent Shell using this command.

$ tessent –shell –logfile logfiles/Lab4_Ex1.log -replace

Set the context to insert DFT into the top-level design.

SETUP> set_context dft –rtl –design_id rtl1

Set the location of the TSDB.

SETUP> set_tsdb_output_directory ../tsdb_outdir

Open the TSDBs for all the child cores.

SETUP> open_tsdb \
../../Lab2/Exercise1/solutions/processor_tsdb_outdir
SETUP> open_tsdb \
../../Lab2/Exercise7/solutions/gps_tsdb_outdir

Notice that you opened the TSDB directories of the wrapped cores from the
solutions directory to make sure everything works correctly while going
through this lab.
Note
If you executed the previous two labs, you can simply change the paths to the
TSDB directories that were created during those labs.

Read the tessent cell library.

SETUP> read_cell_library \
../../libs/library/standard_cells/tessent/adk.tcelllib

Lab: Top-Level SSN Insertion 4

 Read the design Verilog files.

SETUP> read_verilog ../../libs/library/plls/pll.v \

–blackbox –exclude_from_file_dictionary
SETUP> set_design_sources –format verilog –y \
../../libs/library/pad_cells –extension v
SETUP> read_verilog ../../libs/rtl/chip_top.v
SETUP> read_verilog ../../libs/rtl/rds_process.v

Set the current design, and design level to chip level.

SETUP> set_current_design chip_top

SETUP> set_design_level chip

Set the DFT specification requirements to insert the top-level boundary scan and set the memory test
to ‘on’ even if there are no memories at the top-level. With this, the tool will perform design rule
checks (DRCs) for the memory clocks from the boundary of the child blocks all the way to the top.

SETUP> set_dft_specification_requirements \
–boundary_scan on \
–memory_test on

Toggle the enable to relock the PLL.

SETUP> add_dft_control_points PLL_1/enable \

-dft_signal_source_name all_test

For the top-level TAP controller, remap the TAP pins using the set_attribute_value
command.

SETUP> set_attribute_value TCK –name function –value tck

SETUP> set_attribute_value TDI –name function –value tdi
SETUP> set_attribute_value TMS –name function –value tms
SETUP> set_attribute_value TRST –name function –value trst
SETUP> set_attribute_value TDO –name function –value tdo

Specify all clocks so that the proper BSCAN cells get inserted automatically for them.

SETUP> add_clocks PLL_1/pll_clock_0 –reference REF_CLK \

–freq_multiplier 16
SETUP> add_clocks REF_CLK –period 48ns
SETUP> add_clocks INCLK –period 10ns

Ignore the warning message shown after the execution of the pll_clock.

Check the design rules and transition to analysis mode.

SETUP> check_design_rules

This should complete with no errors.

Lab: Top-Level SSN Insertion 5

 Create the DFT specification and report the configuration data.

ANALYSIS> set spec [create_dft_specification]

ANALYSIS> report_config_data $spec

Now we need to segment the boundary scan chains into smaller segments to be reused by scan
testing. This will enable the reuse of the boundary scan cells during the logic test.

ANALYSIS> set_config_value \
$spec/BoundaryScan/max_segment_length_for_logictest 80

Modify the auxiliary_input_ports and auxiliary_output_ports entries with the top-level ports you plan to
use for the SSN bus data ports and bus clock, where bus_in has {GPIO3_0 GPIO3_1} ports and
bus_out has {GPIO4_0 GPIO4_1} ports, and bus_clock has {GPIO3_2} port.

ANALYSIS> read_config_data -in ${spec}/BoundaryScan \

-from_string { \
AuxiliaryInputOutputPorts { \
auxiliary_input_ports : GPIO3_0, GPIO3_1, GPIO3_2; \
auxiliary_output_ports : GPIO4_0, GPIO4_1 ; \
} \
}
ANALYSIS> report_config_data $spec

Generate and insert the DFT hardware.

ANALYSIS> process_dft_specification

Extract the IJTAG network, create ICL netlist description for the design and create the IJTAG graybox
model.

INSERTION> extract_icl -create_ijtag_graybox on

Create patterns (testbenches) to verify the inserted DFT logic.

SETUP> set spec [create_patterns_specification]

SETUP> process_patterns_specification

Point to the libraries and run simulation. Use

the set_simulation_library_sources command.

SETUP> set_simulation_library_sources \
-v ../../libs/library/standard_cells/verilog/*.v \
-y ../../libs/library/plls \
-y ../../libs/library/memories \
-extension v
SETUP> run_testbench_simulations

Lab: Top-Level SSN Insertion 6

 Exit Tessent Shell.

SETUP> exit

Notice that all the previous commands have already been added to the script
in the following path solutions/run_bscan_insertion. To run the script properly,
make sure you are in the Exercise1 directory, then
Note execute ./solutions/run_bscan_insertion

Lab: Top-Level SSN Insertion 7

Exercise 2: Second DFT Insertion Pass: Inserting Top-
Level EDT, OCC, and SSN
In the second DFT insertion pass at the top-level, you insert any EDT, OCC, and SSN elements at the top-
level. You can use the DftSpecification to specify the physical order of lower-level cores from the SSN data
bus_in to bus_out.

Insert SSH, EDT, and OCC

This step is similar to the logic test insertion passes at the block-level, the tool creates the SSN hardware
based on the SSN wrapper of the DftSpecification. The tool creates the SSH, EDT, and OCC elements at
the same time.

Use any text editor and review the run_ssh_edt_occ_insertion dofile, notice the following:

• The synthesized netlist of each of the physical blocks is read.

• In the SSN wrapper, add the Datapath connections to point to the top-level ports that the previous
exercise equipped with auxiliary input and output logic during Boundary Scan creation. The tool
automatically maps the specified port connections to the corresponding auxiliary data pins and
automatically connects the auxiliary enable pins to the ssn_en DFT signal.

• There is only one EDT controller for the top-level, compared to the two EDT controllers used with
the block-level insertion.

• For the continuity patterns creation step, note that for the top-level, these patterns test both the
primary and secondary paths through the SSN multiplexer, as shown in this figure.

• The top-level SSN Mux was configured by an iProc to program the secondary datapath through
the multiplexer, you can check this iProc by reviewing this file.

$SSN_LABS/libs/ssn_datapath_configuration.pdl

• For each configuration of the multiplexers, use the ProcedureStep wrapper to create the
continuity patterns.

Go to the Exercise2 directory in Lab4.

$ cd $SSN_LABS/Lab4/Exercise2

Run this dofile.

$ ./run_ssh_edt_occ_insertion

Lab: Top-Level SSN Insertion 8

Exercise 3: Performing Synthesis for Top-Level
In the previous exercise, you used the command write_design_import_script, to create a design
load script of all the RTL files needed to be used with your synthesis tool.

Using any text editor, review the synthesis script.

$SSN_LABS/Lab4/Exercise2/solutions/chip_top.dc_synth_script

Go to the Exercise3 directory and look at the files there.

$ cd $SSN_LABS/Lab4/Exercise3
$ ls -ls

Using any text editor, review the synthesized netlist created for you to be used in subsequent steps.

$ vi chip_top_synthesized.vg

Close the file when you are done.

Lab: Top-Level SSN Insertion 9

Exercise 4: Performing Scan Chain Insertion (Top-
Level) using Tessent Scan
When inserting SSN, the scan insertion step at the top-level is very similar to the flow you use at the block-
level. The only difference is that you do not need wrapper chains, and typically only have a single scan
mode.

The boundary scan chains implemented in the section “First DFT Insertion Pass: Performing Top-Level
BoundaryScan and MemoryBIST insertion (if the top-level design contains memories)” were built so that
the EDT controller can control them during scan test, and they can serve as isolation from the outside.

Those chains were preconnected to the EDT ports and are left untouched during scan insertion.

Go to the Exercise4 directory.

$ cd $SSN_LABS/Lab4/Exercise4

Using any text editor, review the dofile run_scan_insertion, and notice the following:

• Locate the read_design commands and notice we are only reading the synthesized netlist for the
top or chip-level design and the graybox view for the child blocks.

• The pipeline stages are excluded from scan insertion.

• A single EDT mode is created for the top-level.

• The PDL for configuring the top-level SSN multiplexer is sourced to include all SSH nodes.

• The last step is to create the gate level IJTAG graybox view.

Run the dofile.

$ ./run_scan_insertion

Lab: Top-Level SSN Insertion 10

Exercise 5: Verifying the ICL-Based Patterns after
Synthesis
In this exercise, you will create and simulate the ICL verification patterns after synthesis to ensure that the
ICL network is fully functional and can be reliably used during ATPG and Pattern retargeting setup.

The only difference with the block-level ICL-based verification step is that you need to open the TSDB for
the child blocks and use the hierarchical IJTAG graybox view of the chip we created in Exercise 4, then
simulate the SSN continuity patterns and the ICL network patterns.

Go to the Exercise5 directory.

$ cd $SSN_LABS/Lab4/Exercise5

Review the create_post_synthesis_icl_verification_patterns script using any text editor. Notice the
PatternsSpecification generated by the create_patterns_specification command to see how it uses
the IJTAG graybox view that you created in the previous step to simulate the ICLVerify patterns and
the SSN continuity patterns.

You must complete simulating both the ICLNetwork patterns and SSN continuity patterns before
moving to the next step of the DFT flow.

Run the dofile.

$ ./create_post_synthesis_icl_verification_patterns

Lab: Top-Level SSN Insertion 11

Exercise 6: Generating Top-Level ATPG Patterns
Generating the ATPG patterns at the top-level is similar to generating the patterns at the block-level. The
blocks are in external mode when you create top-level ATPG patterns, so you only need to read in their
scan graybox views using the read_design -view graybox command.

You also need to import the timing_options files used for all blocks so the ATPG patterns created satisfy
the maximum frequencies within all the blocks. Review the TCL foreach code to see how the timing options
are imported for the individual blocks.

Step 1: Generate ATPG Patterns

Go to the Exercise6 directory.

$ cd $SSN_LABS/Lab4/Exercise6

The run_tk_chip_stuck and run_tk_chip_transition scripts in this directory illustrate the loading of the timing
options.

Review the two scripts using any text editor, notice that the first script creates stuck-at fault patterns,
while the second creates transition fault patterns.

Similar to the block-level process, the parallel load scan patterns are simulated first, followed by the serial
SSH loopback patterns and then one serial chain and 1 serial scan patterns.

Run the dofile run_tk_chip_stuck.

$ ./run_tk_chip_stuck

Question 1: Answer the following:

The total relevant test coverage: ___________________________

The number of test patterns: _____________________________

Run the dofile run_tk_chip_transition.

$ ./run_tk_chip_transition

Question 2: Answer the following:

The total relevant test coverage: ___________________________

The number of test patterns: ______________________________

Lab: Top-Level SSN Insertion 12

Step 2: Simulate ATPG Patterns

In this step, you simulate the patterns to confirm that the SSN network can successfully deliver packetized
data to the SSH. We do this by first simulating the parallel load patterns, once these are clean, simulate the
serial loopback patterns, followed by one serial chain pattern and one serial scan pattern.

Review the run_sims script using any text editor, notice that the sequence of patterns to be simulated
is repeated twice, for stuck-at and transition patterns.

Run the dofile run_sims.

$ ./run_sims

No errors should be reported between simulated and expected pattern values.

Lab: Top-Level SSN Insertion 13

Exercise 7: Retargeting Block-Level ATPG Patterns at
Top-Level
When SSN is present in the design the process of retargeting ATPG scan patterns is easier and even more
flexible than in regular hierarchical design without SSN.

When you use SSN, the design does not have a scan_mode to set at the top-level that configures the
channel access to the required blocks. Instead, you simply use the add_core_instances command to
specify which mode you want to retarget on a given set of block modules. During the DFT signoff process,
you typically retarget one block at a time so that you can speed up the simulation and use the IJTAG
graybox views of all blocks other than the one you are retargeting.

In this exercise, we will retarget the stuck and transition fault patterns for the processor_core into a set of
test benches independently from the stuck and transition patterns for the gps_baseband block.

Step 1: Retarget Processor_Core Patterns

Go to the Exercise7 directory.

$ cd $SSN_LABS/Lab4/Exercise7

The run_retarget_processor_core_stuck script in this directory illustrates the procedure of retargeting

processor_core patterns.

Review this script using any text editor, notice the following:

We set the context to retarget ATPG patterns from the lower-level child core using the
set_context patterns –scan_retargeting command.

Regardless of which blocks we are retargeting, we always load the IJTAG graybox view of all the blocks
when doing scan retargeting with SSN.

We import the same timing options for all the blocks that were used during synthesis.

We only add core descriptions for cores to be retargeted, here you can see we used
add_core_instances for the processor_core only.

Finally, we read in those core level patterns to be retargeted using the read_patterns command and
then write the simulation patterns.

Run the dofile run_retarget_processor_core_stuck.

$ ./run_retarget_processor_core_stuck

We can do the same with the transition fault patterns. Review the
run_retarget_processor_core_transition script, and then execute it.

$ ./run_retarget_processor_core_transition

Lab: Top-Level SSN Insertion 14

 You can now simulate these patterns to verify that no simulation mismatches occur. You can execute
this file.

$ ./run_retarget_processor_core_sims

Step 2: Retarget gps_baseband Patterns

For retargeting the two gps_baseband core patterns, we follow the same process in the previous step with
the processor_core, except for one difference, in the gps_baseband, we need to configure the multiplexer
to include these cores in the active datapath.

Question 1: Why didn’t we do the same with the processore_core?

______________________________________________________________________

Retarget gps_baseband stuck-at fault patterns.

$ ./run_retarget_gps_baseband_stuck

Retarget gps_baseband transition fault patterns.

$ ./run_retarget_gps_baseband_transition

You can now simulate these patterns to verify that no simulation mismatches occur, you can execute
this file.

$ ./run_retarget_gps_baseband_sims

This is the end of Exercise7 and Lab4.

Lab: Top-Level SSN Insertion 15

 Lab Answers

Lab 4
Exercise 6
The total relevant test coverage: 85.39%

The number of test patterns: 44

The total relevant test coverage: 58.83%

The number of test patterns: 2

Exercise 7
Why didn’t we do the same with the processore_core?

• The processor_core is always part of the active SSN datapath.

Lab: Top-Level SSN Insertion 16

 NOTES:

Lab: Top-Level SSN Insertion 17