Digital Logic & Processors

Design Aspects of Counters

 Application of Counter

COUNTER

INPUT OUTPUT
Application of Counter
 Application of Counter

1 PPH 1 PPM 1 PPS

Divide by Divide by Divide by
1 Hz
12 or 24 60 60
CLK
counter counter counter
 Digital Counters
• A digital counter is a set of flip-flops whose
states change in response to pulses applied at
the input to another. A counter is used to count
pulses.
• A counter can also be used as a frequency
divider to obtain waveforms with frequencies that
are specific fractions of the clock frequency.
• They are used for counting the number of
occurrences of an event and are useful for
generating timing sequences to control
operations in a digital system.
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 Modulus of the counter
• The number of states through which the counter
passes before returning to the starting state is
called the modulus of the counter.
• Hence, the modulus of a counter is equal to the
total number of distinct states including zero that
a counter can store.
• A counter may have a shortened modulus. This
type of counter does not utilize all the possible
states. The condition to determine the number of
flip-flops is

10/30/22
 COUNTERS
ASYNCHRONOUS SYNCHRONOUS
Flip-flops are connected in such a No connection between output of
way that output of first flip-flop first flip-flop and clock input of
drives the clock for the next flip- next flip-flop.
flop.
All the flip-flops are not clocked All the flip-flops are clocked
simultaneously. simultaneously.

Logic circuit is simple even for Design involves complex logic

more number of states. circuit as number of states
increases.

Main drawback is their low speed As the clock is simultaneously

as the clock is propagated given to all flip-flops there is no
through number of flip-flops problem of propagation delay.
before it reaches last flip-flop.
 Ripple (Asynchronous) Counter
• In ripple counter, the flip-flops within the
counter are not made to change the states at
exactly the same time, i.e., they are not clocked
simultaneously.
• In a ripple counter, also called an
asynchronous counter or a serial counter, the
clock input is applied only to the first flip-flop,
also called the input flip-flop, in the cascaded
arrangement.
• The clock input to any subsequent flip-flop
comes from the output of its immediately
preceding flip-flop.
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 Mod 8 Ripple Counter
• Since the modulus or mod number of the counter is 8, it
requires 3 flip-flops.

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Mod 8 Down Ripple Counter
Binary Ripple Counters with a Modulus of Less than 2N
Design a MOD 6 Ripple counter using JK flip-flops.
Count the number of states including zero states to get mod number = 6, and
in the immediate next state i.e., in 110 state, Q 2=1, Q1 =1
Connect Q2 and Q1 to a NAND gate and the output of the gate to clear input
of the flip-flops.
Hence after state 101, when the circuit enters into state 110, the NAND
output becomes 0 and hence the flip-flops will be in reset state, 000 and the
count continues.
Though the counter enters into 7th state, the time it spends in that state is
negligible (propagation delay of NAND gate).
Hence the counter is treated as a MOD 6 counter with states 000 to 101

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 Design a BCD Ripple counter using JK flip-flops.

• It is also known as MOD 10 ripple counter or Decade Ripple counter

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 Synchronous Counter

• In a synchronous counter, also known as a parallel

counter, all the flip-flops in the counter change state at
the same time in synchronism with the input clock signal.
• The clock signal in this case is simultaneously applied to
the clock inputs of all the flip-flops.
• The delay involved in this case is equal to the
propagation delay of one flip-flop only, irrespective of the
number of flip-flops used to construct the counter.
3-bit Synchronous counter or MOD 8 Counter
In the given count sequence, we find that flip-flop FF0 toggles with
every clock pulse, flip-flop FF1 toggles only when the output of
FF0, Q0 is in the ‘1’ state, flip-flop FF2 toggles only with those
clock pulses when the outputs of FF0 and FF1are both in the logic
‘1’ state. Such logic can be easily implemented with AND gates.

FLIP-FLOP INPUTS:

J2 = K2 = Q1.Q0 J1 = K1 = Q0 J0 = K0 = 1
COUNTER USED FOR FREQUENCY DIVISION

4
8 200 Hz
100 Hz 400 Hz
50 Hz 2
 16

Clock Input

800 Hz
 USING THE 7493 COUNTER IC
• Counters are available in IC form.
• Either ripple (7493 IC) or synchronous
(74192 IC) counters are available.

? HzHz
400
? HzHz
100 ?
800
HzHz

1600 Hz

7493 Counter IC
wired as a 4-bit
binary counter