OCR GCSE 9-1 Computer Science

Paper 1: Computer Systems

Systems Architecture
Learning Objectives
To be able to…
• Understand the purpose of the CPU, and the Von Neumann model

• Know what the following registers do: MAR, MDR, PC and ACC

• Understand the operation of the CPU’s ALU, CU and cache

• Outline the Fetch-Decode-Execute cycle

• Understand factors affecting the CPU’s performance

• Define the term and give examples of embedded systems

 CPU = Central Processing Unit
…the circuitry that controls the manipulation of data

Arithmetic/Logic Unit
The circuits that perform ALU

Registers
Registers
the operations on the data
Quick, small stores of
Control Unit data within the CPU

The circuits coordinating

CU
the activities of the CPU
CPU = Central Processing Unit
…Also has cache, which may be on-chip

Registers
Cache ALU
Very small and fast non-volatile memory,
which is used to store commonly accessed
instructions and data
CU
Cache
Cache Main Memory

The cache is checked first. If the data is there it’s called a ‘cache hit’. If not
(a ‘cache miss’), then the slower main memory is then checked.
 Von Neumann Architecture
• 3 major characteristics of this theoretical model…

ALU
Main Memory Input/ Output

CU

1st: System broken down into 4 units

 Von Neumann Architecture
• 3 major characteristics of this theoretical model…

2nd: Instructions to be executed are

stored in the memory (alongside the
Memory data) as binary values

= the stored program concept

 Von Neumann Architecture
• 3 major characteristics of this theoretical model…

3rd: Instructions
are executed
sequentially:
ALU
Memory One instruction at
a time is fetched
CU from memory and
passed to the CPU
• Computers have a system clock which provides timing signals to
synchronise circuits.

• CPUs are designed to operate at a specific frequency – and the system clock
is raised to this rate by the processor, giving the clock speed (Hz)

• The CPU needs a certain amount of clock ticks/cycles per instruction

Fetch-Execute Cycle
Fetch
The next instruction is retrieved by the CPU from main memory.

Decode operator + operand e.g. ADD R1 R5

The instruction is broken down to its individual components to determine
what the instruction is, and what data is being used.

Execute
The CU activates the necessary circuity/ data transfers. The output of this
stage is stored in a register, and data may be read/written from/to the
main memory during this stage.
 Special-Purpose Registers

• …Contrast with general-purpose registers, which temporarily hold

data or which can be used by a programmer
• Some common special-purpose registers are:

Program Counter (PC) = holds the memory address of the next

instruction to be executed. It increments after the fetch stage.

Accumulator (ACC) = holds the result of a calculation performed by

the Arithmetic/ Logic Unit.
Memory Address Register (MAR) = holds the memory address of
the data needing to be accessed by the CPU.

Memory Data Register (MDR) = holds the data being transferred to

or from the memory location by the CPU.

When reading, the data addressed by the MAR is held in the MDR

When writing, the data in the MDR is written to the address in the MAR

They act as buffer registers; they are there to compensate for the
difference in speed between the CPU and main memory.
Q: Using the names of CPU components, fill in the gaps. (10 marks)

At the start of the fetch-execute cycle, the memory address of the next
instruction to be executed is loaded from the (a) into the (b). The
instruction is fetched from main memory or (c) (stored in the (d)), and the
(e) is incremented to the next instruction’s address.

The (f) then decodes the instruction, and any further data required as part of
the instruction is fetched.

If applicable, the (g) performs calculations, and stores the result in the (h). It
can then be written back to memory, storing this result in the (i), which is
transferred to the address in the (j).
Q: Using the names of CPU components, fill in the gaps. (10 marks)

At the start of the fetch-execute cycle, the memory address of the next
instruction to be executed is loaded from the (a) PC into the (b) MAR. The
instruction is fetched from main memory or (c) cache (stored in the (d)
MDR), and the (e) PC is incremented to the next instruction’s address.

The (f) CU then decodes the instruction, and any further data required as
part of the instruction is fetched.

If applicable, the (g) ALU performs calculations, and stores the result in the
(h) ACC. It can then be written back to memory, storing this result in the (i)
MDR, which is transferred to the address in the (j) MAR.
Factors Affecting CPU Performance
 Clock Speed measured in Hz, = cycles per second
• The CPU is regulated with clock signals (cycle = time between 2 pulses)
• A set number of instructions can be executed per clock cycle

• The shorted these cycles are (the higher clock rate), the more
instructions are be executed per second

Clock Speed = Performance

 Cache Size
• Cache exists to speed up the operation of the fetch stage
• The larger the cache, the more commonly used instructions and data can
be stored, so more benefit from the speed-up

Cache Size = Performance

 Cache Type
• There is a trade-off between ‘cache latency’ (speed) and ‘hit rate’ (size)
• There are multiple levels of cache…

L1 – embedded in the CPU chip, and is the smallest and fastest.

L2 & L3 – may be physically situated between the CPU and RAM,

and are larger but slower, and exist to ‘back up’ L1 cache, where hits
are the least likely.
 Number of Cores
• A CPU can effectively have multiple processors (cores) on the same chip
• When software is optimised, multiple cores allow multiple instructions to
be executed simultaneously

Each core will have at least

their own L1 cache (maybe # of Cores = Performance
L2 as well), but share the
common L3 cache
(For multiple instructions)
Q: Compare and contrast the following two CPUs. (9 marks)

AMD Ryzen 7 2700 -- £225 Intel Core i7-8700k --

£270
8 Cores
Clock Speed: 3.2 GHz 6 Cores
Cache (L3): 16 MB Clock Speed: 3.7 GHz
Cache (L3): 12MB

Any valid comparison (1 mark), explanation of the effect (2 marks) – 3

E.g. The AMD CPU has a larger cache than the Intel CPU (1). This means more
commonly accessed instructions can be stored there (1). Therefore it is more likely
that a cache hit will occur, as opposed to having to access the slower RAM. (1)
Embedded Systems
 Embedded Systems
= A special-purpose computer encapsulated by a larger system

• …Your laptop/desktop is a non-embedded system

• A traditional embedded system can usually only perform specific
tasks, and cannot be easily programmed
Q: Give three other examples of embedded systems. For each,
state their purpose in the wider system. (6 marks)
E.g.
Temperature unit in a jacuzzi (1 mark), which will measure the temperature
at intervals so the water’s temperature can be adjusted. (1 mark)

The weight scale in a clothes dryer, which can be used to ensure the
maximum useable weight is not exceeded.

An automatic parallel parking system, which uses other car sensors to

make calculations based on the environment to park the car safely.
 Key Points

• CPU stands for Central Processing Unit (and is aka the processor)

• The Von Neumann model is what most computers are based on

• A key feature is that instructions and data are stored together in
main memory (RAM)

• Cache is not needed, but exists to speed up fetching

• Embedded systems are usually very simple, and focus on a single task
within a larger system