COMPUTER

ORGANIZATION
After Midterm
‫الر ِحي ِم‬
‫َّ‬ ‫ن‬
‫ِ‬ ‫ـ‬ ‫م‬‫ح‬ ‫الر‬
‫َّ ْ َ ٰ‬ ‫ِ‬
‫ـه‬‫َ‬ ‫ِب ْس ِم الل ّ‬
 ‫‪09‬‬
‫‪Before CONTROL HAZARDS‬‬
‫” حسبنا الله سيؤتينا الله من فضله ان الى اللهراغبون ”‬
 PIPELINING CONCEPT

CC 1 CC 2 CC 3 CC 4 CC 5 CC 6 CC 7 CC 8

lw $t0, 10($t1) IM REG ALU DM REG

sw $t3, 20($t4) IM REG ALU DM REG

add $t5, $t6, $t7 IM REG ALU DM REG

sub $t8, $t9, $t10 IM REG ALU DM REG

 Events on every pipe stage of the MIPS pipeline

Instruction fetch (IF)


Instruction to be executed is fetched from memory and stored in an instruction register.

The instruction's address is calculated by adding the program counter (PC) value to a fixed offset.
Instruction decode (ID)

Instruction is decoded to determine its operation and the register operands.

The instruction is also checked for data hazards and structural hazards.
Execution (EX)

Instruction's operation is executed. This stage includes reading the register operands, performing the
operation, and writing the result to a register or memory.
Memory access (MEM)

Data is transferred from memory to a register or from a register to memory. (lw,str)
Write back (WB)

The results of the instruction are written back to the register file.
 What Makes Pipeline Easy with MIPS?

Simple instruction set:The MIPS instruction set is designed to be simple and regular, with a small number of
instruction types and a consistent format for all instructions. This makes it easy to decode and execute instructions in a
pipeline.
Fixed instruction length: All MIPS instructions are the same length, which simplifies the fetch stage of the pipeline as
the instruction memory does not need to be searched for the next instruction.
Load/store architecture: Means that instructions that access memory are separated from instructions that perform
arithmetic operations. This allows for the separation of the memory access stage from the execution stage in the
pipeline, making the pipeline more efficient.
Register-register operations: The MIPS architecture only allows operations to be performed between registers, which
eliminates the need for memory-to-register and register-to-memory operations. This simplifies the pipeline by reducing
the number of memory accesses required. (RISC)
Separation of control and data flow: The MIPS architecture separates the control flow of the program from the data
flow, which allows for the execution of instructions to be decoupled from the decisions about which instruction to
execute next. This simplifies the pipeline by allowing the fetch and execution stages to proceed independently.
 What Makes Pipeline Hard with MIPS?

Data dependencies:

Some instructions depend on the result of previous instructions causes delays in the pipeline.

Control flow instructions:


Branches and jumps can cause the pipeline to stall the processor must wait for the instruction to
execute before it knows where to fetch the next instruction from

Structural hazards:

These occur when two instructions need to use the same functional unit

Exceptions: Occurs during the execution of a program that disrupts the normal flow of instructions.
When an exception occurs, the pipeline must be flushed, and the program must execute a special
handler routine. This can cause a significant reduction in performance.
 ‫‪09‬‬
‫‪Before CONTROL HAZARDS‬‬
‫” حسبنا الله سيؤتينا الله من فضله ان الى الله راغبون ”‬
 ‫‪10‬‬
‫‪CONTROL HAZARDS‬‬
‫” حسبنا الله سيؤتينا الله من فضله ان الى اللهراغبون ”‬
 Pipeline MIPS Hazards

Structural hazards

Not enough resources, such as functional units or registers, to execute all instructions
in the pipeline at the same time.


Data hazards

When an instruction depends on the result of a previous instruction that has not yet
completed execution.


Control hazards

when the instruction execution path changes dynamically, such as when a branch
instruction is encountered.
 Pipeline MIPS Hazards
MIPS was designed to be Pipelined
structural hazards are easy to avoid

Program
execution 2 4 6 8 10 12 14
Time
order
(in instructions)
Instruction Data
lw $1, 100($0) Reg ALU Reg
fetch access Pipelined
Instruction Data
lw $2, 200($0) 2 ns Reg ALU Reg
fetch access

Instruction Data
lw $3, 300($0) 2 ns Reg ALU Reg
fetch access

Instruction Data
lw $4, 400($0) Reg ALU Reg
2 ns fetch access

2 ns 2 ns 2 ns 2 ns 2 ns
 Pipeline MIPS Hazards

Data hazards
Based on the types of dependencies between the instructions

True data dependency

Anti-dependency

Output dependency


Based on the instruction pipeline stage

RAW (read after write)

WAW (write after write)

WAR (write after read)
 Pipeline MIPS Hazards
DATA Hazard
RAW (read after write) solution


Forwarding
P ro gra m
e x e c u ti o n 2 4 6 8 10
order Ti m e
( i n i n s t r u c ti o n s )

a dd $ s 0, $t0, $t1 IF ID EX MEM WB

s u b $ t2, $ s 0 , $ t3 IF ID EX MEM WB
 Pipeline MIPS Hazards
DATA Hazard
RAW (read after write) solution


STALLING
2 4 6 8 10 12 14
Program Time
execution
order
(in instructions)
lw $s0, 20($t1) IF ID EX MEM WB
Without a stall it is impossible
to provide input to the sub
instruction in time
sub $t2, $s0, $t3 IF ID EX MEM WB

2 4 6 8 10 12 14
Program Time
execution
order
(in instructions)

lw $s0, 20($t1) IF ID EX MEM WB

With a one-stage stall, forwarding
can get the data to the sub
instruction in time
bubble bubble bubble bubble bubble

sub $t2, $s0, $t3 IF ID EX MEM WB

 Pipeline MIPS Hazards


Example:
lw $t0, 0($t1) DATA Hazard
lw $t2, 4($t1) 
Software
Data hazard
sw $t2, 0($t1)
sw $t0, 4($t1)


Reordered code:
lw $t0, 0($t1)
lw $t2, 4($t1)
sw $t0, 4($t1)
Interchanged
sw $t2, 0($t1)
 Pipeline MIPS Hazards
Control hazards

Stalling

Program
execution 2 4 6 8 10 12 14 16
order Time
(in instructions)
Instruction
Reg ALU
Data
Reg Note that branch outcome is
add $4, $5, $6 fetch access computed in ID stage with
Instruction Data added hardware (later…)
beq $1, $2, 40 Reg ALU Reg
2ns fetch access

Instruction Data
lw $3, 300($0) bubble Reg ALU Reg
fetch access

4 ns 2ns

Pipeline stall
 Pipeline MIPS Hazards
Control hazards

predict branch-not-taken
Program
execution 2 4 6 8 10 12 14
order Time
(in instructions)
Instruction Data
add $4, $5, $6 fetch
Reg ALU
access
Reg

Instruction Data
beq $1, $2, 40 Reg ALU Reg
2 ns fetch access

Instruction Data
lw $3, 300($0) Reg ALU Reg
2 ns fetch access

Prediction success
Prediction failure
Program
execution 2 4 6 8 10 12 14
order Time
(in instructions)
Instruction Data
add $4, $5 ,$6 Reg ALU Reg
fetch access

Instruction Data
beq $1, $2, 40 Reg ALU Reg
fetch access
2 ns
bubble bubble bubble bubble bubble

Instruction Data
or $7, $8, $9 Reg ALU Reg
fetch access
4 ns
 ‫‪10‬‬
‫‪CONTROL HAZARDS‬‬
‫” حسبنا الله سيؤتينا الله من فضله ان الى اللهراغبون ”‬