Coprocessor

pipeline processor
Risc and Cisc
• KUNAL SHIMPI (A261) 70012100242
• MUSAB SAYYED (A241) 70012100222
• ATHARV SHIMPI (A257) 70012100238
• ADITYA PATIL (A253) 70012100234
 Coprocessor
• A co-processor is many times referred as a Math Processor.
As the coprocessor performs routine mathematical tasks, the
core processor is freed up from this computation and its time
is saved. By taking specialized processing tasks from core
CPU, coprocessor reduces the strain on the main
microprocessor, so that it can run at a greater speed.
• A coprocessor can perform  special tasks like complex
mathematical calculations or graphical display processing.
They perform such jobs faster than core CPU. As a result,
overall computer speed of the system increases
  coprocessor work ?
Independent type – 

It work in an asynchronous manner with the CPU . Whenever it performs any task,
some calculations, that is not synchronized with the CPU. Co-processor can take
decisions independently here. CPU can then do its own work without worrying
about co-processor’s work. Instead of synchronously waiting, CPU that issued the
request is freed up to perform another task.
Direct control type –
 
Direct control type such as floating-point units – controlled by coprocessor’s
instructions that are CPU instruction set’s part. The CPU that initiated the request
waits or  checks until co-processor completes operation. The coprocessor is not
independent here & is governed or controlled by the main CPU. CPU &
coprocessor works in synchronization here.
 Properties of Coprocessor  
1.Without primary microprocessor, coprocessor cannot
function.
2.Main processor has to identify and segregate computationally
intensive instructions in a program.
3.The instructions which have an intensive amount of
calculations are performed by coprocessor.
4.The main processor handles all other activities.
 Functionalities of a Coprocessor
• Coprocessors are incapable of retrieving instructions from
memory, managing memory, executing instructions(flow control
types) directly, performing I/O operations, etc.
• The coprocessor relies on the host (main) processor to retrieve
coprocessor instructions and take care of all other operations
not related to the coprocessor.
• A coprocessor is not the main processor of the system.
• Coprocessors enable a computer customization , so the clients
 do not need to pay if they do not require the additional
performance.
 Pipeline processor
•  A process of arrangement of hardware elements of the CPU
such that its overall performance is increased.
• Simultaneous execution of more than one instruction takes place
in a pipelined processor.
• Pipelining is the process of accumulating instruction from the
processor through a pipeline.
• It allows storing and executing instructions in an orderly process.
• It is also known as pipeline processing. Pipelining is a technique
where multiple instructions are overlapped during execution.
 Design of a basic pipeline
• In a pipelined processor, a pipeline has two ends, the input end
and the output end.
• Between these ends, there are multiple stages/segments such
that the output of one stage is connected to the input of the
next stage and each stage performs a specific operation.
• Interface registers are used to hold the intermediate output
between two stages. These interface registers are also called
latch or buffer.
• All the stages in the pipeline along with the interface registers
are controlled by a common clock.
 Stages of pipelines
• Stage 1 (Instruction Fetch) In this stage the CPU reads
instructions from the address in the memory whose value is
present in the program counter.
• Stage 2 (Instruction Decode) In this stage, instruction is
decoded and the register file is accessed to get the values
from the registers used in the instruction.
• Stage 3 (Instruction Execute) In this stage, ALU operations
are performed.
 Stages of pipelines
• Stage 4 (Memory Access) In this stage, memory operands are
read and written from/to the memory that is present in the
instruction.
• Stage 5 (Write Back) In this stage, computed/fetched value is
written back to the register present in the instructions.
 Reduced Instruction Set Architecture
(RISC)
• The main idea behind this is to make hardware simpler by
using an instruction set composed of a few basic steps for
loading, evaluating, and storing operations just like a load
command will load data, a store command will store the data. 
•  Reduce the cycles per instruction at the cost of the number of
instructions per program. 
• RISC approach: Here programmer will write the first load
command to load data in registers then it will use a suitable
operator and then it will store the result in the desired
location.
 Characteristic of RISC
1.Simpler instruction, hence simple instruction decoding.
2.Instruction comes undersize of one word.
3.Instruction takes a single clock cycle to get executed.
4.More general-purpose registers.
5.Simple Addressing Modes.
6.Fewer Data types.
7.A pipeline can be achieved. 
 Complex Instruction Set Architecture
(CISC)
• The main idea is that a single instruction will do all loading,
evaluating, and storing operations just like a multiplication
command will do stuff like loading data, evaluating, and
storing it, hence it’s complex. 
• The CISC approach attempts to minimize the number of
instructions per program but at the cost of an increase in the
number of cycles per instruction. 
• CISC approach: There will be a single command or instruction
for this like ADD which will perform the task.
 Characteristic of CISC
1.Complex instruction, hence complex instruction decoding.
2.Instructions are larger than one-word size.
3.Instruction may take more than a single clock cycle to get
executed.
4.Less number of general-purpose registers as operations get
performed in memory itself.
5.Complex Addressing Modes.
6.More Data types. 
 RISC
• Focus on software
• Transistors are used for more
registers
• Fixed sized instructions
• Requires more number of
registers
• Code size is large
• Complexity is in the compiler
CISC
• Focus on hardware
• Transistors are used for storing
complex Instructions
• Variable sized instructions
• Requires less number of
registers
• Code size is small
• Complexity is in the
microprogram
 RISC
• Simple instruction taking one
cycle
• Few instruction
• Highly pipelined
CISC
• Most of instructions may refer
memory
• Many instructions
• Not pipelined or less pipelined
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