Chap 3

3
Basic Language Elements
VHDL: Basics to Programming_Gaganpreet Kaur
Copyright 2011 Dorling Kindersley India Pvt. Ltd
Identifiers

User-defined words used to name objects in VHDL models Input and output signals as well as the name of a design entity and architecture May contain only alpha-numeric characters (A to Z, a to z, 0-9) and the underscore (_) character Rules for Idenfiers

The first character must be a letter and the last one cannot be an underscore. An identifier cannot include two consecutive underscores. An identifier is case insensitive An identifier can be of any length.
Identifiers
Examples of valid identifiers are: abc, ab_10 , Gate_design invalid identifiers are: _a10, my_gate@input, gate-input
Extended Identifiers
allow identifiers with any sequence of characters. An extended identifier is enclosed by the backslash ,\, character. case sensitive. An extended identifier is different from reserved words. Inside the two backslashes one can use any character in any order, except that a backslash as part of an extended identifier must be indicated by an additional backslash.
Data Object
Anything capable of holding a value is referred to as an object. VHDL is object based Langauage Associated with class, Type and Unique identifier
Definition: A data object holds a value of specified type. It is created by means of an object declaration. Example is
variable COUNT : INTEGER creates an object COUNT of class variable and type - integer
Types of Data Objects

CONSTANT VARIABLE SIGNAL FILE
Data Objects
Constant
single, specific value.
value cannot be changed during simulation. Uses keyword CONSTANT
CONSTANT const_name:TYPE [:= value]; Example: CONSTANT a: INTEGER:= 2; CONSTANT rise_time: TIME:= 5ns;
Constants
Deferred Constants: Constants which are declared but initialized later Used in packages Example: CONSTANT x : INTEGER;
Variables
data objects used for local storage can hold a single value.
allowed only with sequential constructs Used inside a subprogram or inside a
process value is updated immediately without any delay its value can be changed any number of times.
Variables
VARIABLE var_name:TYPE [:=initial value]; Example: VARIABLE a: INTEGER:= 2; VARIABLE inp: BIT_VECTOR(3 DOWNTO 0);
Variable assignment operator (:=)
Signals
used to model interconnections and capable of holding a list of values
can have more than one drivers also Each driver is a queue of events can be declared inside entity declaration, architecture body(declarative part) or inside a package declaration.
associated with it a signal driver
Signals
SIGNAL sig_name:TYPE [:=initial value]; Example: SIGNAL a: INTEGER:= 2; SIGNAL inp: BIT_VECTOR(3 DOWNTO 0);
Data Type
Each data object has a type associated with it. data type defines the set of values that the object
can have and the set of operations that are allowed on it VHDL as it is a strongly typed language . no implicit conversions Every type has associated with it a name and range of values.
Predefined Types
Bit: simplest and most important data type for a
digital system Based on binary logic values of 1 and 0. Any data object can be declared of the type bit before being used as:
SIGNAL x: BIT; -- data object signal of the type bit VARIABLE s: BIT:= 1; --data object variable of the type bit CONSTANT a: BIT:= 1; -- data object constant of the type bit
All arithmetic, logical and relational operators are allowed on Bit type.
Bit Vector: It is extension of 2 level bit logic to
present an array of values instead of a single value. The range of n-bit vector can be specified starting from 0 as index to n-1 as
Predefined Types
BIT_VECTOR(0 TO 7) or starting from n-1
BIT_VECTOR(0 TO 7) is of the form b7b6 b5b4 b3b2 b1b0 LSB MSB BIT_VECTOR(7 DOWNTO 0) is as b7b6 b5b4 b3b2 b1b0 MSB LSB bit _ vector value is always included in double quotes (). Example: SIGNAL x: BIT_VECTOR( 3 DOWNTO 0);
to 0 as BIT_VECTOR(7 DOWNTO 0).
Predefined Types
Std_ulogic:
nine value logic system.
good alternative to bit data type for
checking design errors includes forced values, weak values, dont care and unresolved levels.
Predefined Types
Std_logic: Subtype of std_ulogic. Eight valued logic system Does not include U (unresolved) logic level. Resolved data type which allows multiple driver
All arithmetic, logical and relational
operations are allowed on std_logic as well as std_ulogic types

Predefined Types
Integer:
Range -2,147,483,647 to + 2,147,483,647 ( 32 bit
integer) All arithmetic and relational operators are allowed with integers. Keyword INTEGER. Two subtypes:
natural, containing the integers from 0 to the largest integer( 0 to 2, 147,483,647) positive, containing the integers from 1 to the largest integer.(1 to 2,147,483,647) Example: SIGNAL x: INTEGER; VARIABLE a: NATURAL; CONSTANT b: POSITIVE:= 3;.
Predefined Types
Real:
Represent real numbers with a mantissa
part and an exponent part Greatest range allowed by the hosts floating-point representation. Keyword used is REAL. All arithmetic and relational operators are allowed with real numbers. Example: SIGNAL x: REAL;
Predefined Types
Character:
Single ASCII characters Keyword CHAR. single characters included in single quotes
() or string of characters included in double quotes (). Example: SIGNAL x: CHAR:= a;
Predefined Types
Time:
range is implementation defined at least equal to range of integers defined Time data type is used to represent simulation
times and delays. Represented as a numeric literal followed by a time unit as 32 s, 5 ns etc. includes both positive and negative values. redefined subtype of time, delay_length, it includes non-negative values. The addition, subtraction, identity and negation operators can be applied to yield results of type
User Defined Types

New type can be introduced by using the
type declaration, which names the type and specifies its value range
The syntax is TYPE identifier IS type_definition; and any data object of the defined type can be created as : SIGNAL x: identifier;
User Defined Types

User defined types
Scalar
Composite
Access
File
Array Integer
Record
Real
Enumerated
Physical
Scalar Data Type

Enumerated Type (Not Synthesizable) Defines a type that has a set of userFor ex.:
TYPE fourval IS (X,0,1,Z); SIGNAL start: fourval;
defined values consisting of identifiers and character literals
Values have position number associated with them and the position of left most element is 0.
Scalar Data Type

Physical Type ( Not Synthesizable ) Contains values representing measurement of physical quantities like distance, current, time etc. Provides a base unit and successive units are then defined in terms of this unit TYPE current IS RANGE 0 TO 1E9 UNITS na; ua = 1000 na; ma = 1000 ua; END UNITS;
Composite Data Type

Array Type
Represents a collection of values all belonging
to same type
For ex.: Type ADDRESS_WORD is array (0 to 63) of BIT; Type DATA_WORD is array (7 downto 0) of STD_LOGIC; Variable ADDRESS_BUS: ADDRESS_WORD
Array can be single dimensional or multi dimensional Arrays can be constrained or unconstrained
Composite Data Type

Record Type
Represents a collection of values that
may belong to different types
TYPE rec_name IS RECORD N1: TYPE; N2 : TYPE; .. .. N5: TYPE; END RECORD;
VARIABLE r1: rec_name ; To access the members of record r1, . Operator is used as r1.N1, r1.N2 and so on.
Composite Data Type

For ex.:
Type PIN_TYPE is range 0 to 10; Type MODULE is RECORD SIZE : INTEGER range 20 to 100; CRITICAL_DLY : TIME; NO_INPUTS: PIN_TYPE; NO_OUTPUTS: PIN_TYPE; END RECORD; Variable NAND_COMP: MODULE;
Access Data Type

Just like pointers in C (Not Synthesizable) Values belonging to an access type are pointers to
dynamically located object of some other type
for ex.: Type PTR is access MODULE;

Objects of access type can only belong to
VARIABLE class and its default value is NULL
for ex.: variable MOD1PTR, MOD2PTR : PTR; -- default value is NULL
Access Data Type

TYPE ptr1 IS ACCESS : INTEGER; VARIABLE r1: ptr1 ; r1:= NEW INTEGER(3) or -- dynamic allocation
Access Data Type

Two predefined functions are available to
manipulate the object
NEW Allocates memory of the size of object in bytes and returns the access value e.g. MOD1PTR := NEW MODULE; DEALLOCATE Takes the access value and returns memory back to the system e.g. DEALLOCATE (MOD1PTR);
File Data Type

is a stream of values of a specified type Represent files in the host environment Provide a mechanism by which a VHDL design communicates with the host Environment Not synthesizable construct Syntax:
TYPE file_name IS FILE OF type_name; Ex.: type vectors is FILE of bit_vector;

Indicates that a file of type vectors has a
sequence of values of type BIT_VECTOR
File Data Type

FILE file_name: file-type physical path; IS MODE
For file type object declaration three things are
required to be specified: User-defined Name of the file along with its type. MODE of file: two modes IN and OUT are allowed with file objects. With IN mode file can be read from while in OUT mode file can be written to. Physical path of file on the disk, where it is saved.
Operators

Logical or mathematical function takes one or two values and produces a single result. built into the syntax of the language cannot be user-defined. can be overloaded.
Operators
Operators in VHDL are of 5 types:
Arithmetic operators Logical operators Relational operators Shift and rotate operators Miscellaneous operators
Arithmetic Operators
Addition operators: Addition(+), Subtraction(-): basic arithmetic addition & subtraction works on integer type, floating point types . Both operands are of same type. defined for std_logic type in std_logic_arith_unsigned other types concept of operator overloading is used .e.g. c<= a + b, where c , a and b are integer/ real values
c<= 8- 5
Concatenation (&): used to join together two or more 1-d arrays or
single elements. 0101 & 1 ABC & DEF
Arithemtic
Adding
Multiplying
Unary
+ &
* / mod rem
+ -
op<= first_operand OPERATOR Second operator; -binary operators op <= OPERATOR value; -- unary operator
Multiplication(*):
binary operator operands to be of same type either integers or real
type physical type with a scalar value with result of type physical. e.g c<= a *b; t1< 10 * 1 ns;
Division(/) :
binary operator operands to be of same type either integers or real
type physical type with a scalar value with result of type physical or division of physical type with another physical type resulting in a scalar value.
Remainder(rem):
binary operator returns the reminder of division of two integer
values. A REM B = A (A/B)*B(A/B in an integer) The result is same as operand type with sign of first operator.
17 REM 4 =17 (17/4) *4= 17- 4*4=1 -17 REM 4 = -17 (-17/4) *4= -17+ 4*4= -1
Modulus(mod) :
binary operator integer values A MOD B = A B * N (in which N is an integer) N is so the
smallest value for which sign of the result is that of second operand that is, B.
17 MOD 4 =17 (17/4) * 1= 17- 4*1=13 -17 MOD 4 = -17 (-17/4) *5= -17+ 4*5= 3 17 MOD - 4 =17 (17/-4) *-5= 17- 4*5= -3
Unary operators
Unary operators + and - are sign operators where
+ indicates positive value and indicates a negative value.
Logical Operators
Logical
And
or
not
nand
nor
xor
Exnor
defined for the bit, boolean, std_logic and
std_ulogic types and their 1-d vectors can be applied to signals, variables and constants.
Relational Operators
Relational
/=
<
<=
>
>=
return boolean true or false Equality(=):
applied to any type
Shift Operators
Shift & Rotate
sll
srl
sla
sra
rol
ror
Op <= data OPERATOR integer;
Shift Operators
Shift left logical(sll):

logical shift operation shifts the bits to left vacated bits on the right are filled with zeros. logical right operation shifts the bits to right vacated bits on the left are filled with zeros
Shift right logical (srl):

Shift Operators
Shift left arithmetic(sla):

arithmetic shift operation shifts the bits to left vacated bits on the right are with rightmost bit.
Shift right arithmetic(sra): arithmetic right operation shifts the bits to right vacated bits on the left are filled with leftmost bit.
Rotate Operators
Rotate left (Rol):

Rotate left operation rotates the bits to left
Rotate right (Ror):

rotate right operation rotate the bits to right
Miscellaneous Operators
Miscellaneous
abs
**
Op <= ABS (numeric_data) Op <= operand ** integer
-- Syntax for operator abs -- Syntax for exponetiation **
Miscellaneous Operators
Absolute(abs):

works with any numeric data type returns the absolute value of the input numeric value. binary operator left operand is a numeric value either an integer or a floating type right operand is an integer indicates the exponent value
Exponentiation(**):
Shift Operators
Shift left arithmetic(sla):

arithmetic shift operation shifts the bits to left vacated bits on the right are with rightmost bit. arithmetic right operation shifts the bits to right vacated bits on the left are filled with leftmost bit.
Shift right arithmetic(sra):


Chap 3

Uploaded by

Document Information

Original Description:

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

Chap 3

Uploaded by

Copyright:

Available Formats

3

Basic Language Elements

VHDL: Basics to Programming_Gaganpreet Kaur

Copyright 2011 Dorling Kindersley India Pvt. Ltd

VHDL: Basics to Programming_Gaganpreet Kaur

Copyright 2011 Dorling Kindersley India Pvt. Ltd

VHDL: Basics to Programming_Gaganpreet Kaur

Copyright 2011 Dorling Kindersley India Pvt. Ltd

VHDL: Basics to Programming_Gaganpreet Kaur

Copyright 2011 Dorling Kindersley India Pvt. Ltd

Copyright 2011 Dorling Kindersley India Pvt. Ltd

Types of Data Objects

VHDL: Basics to Programming_Gaganpreet Kaur

Copyright 2011 Dorling Kindersley India Pvt. Ltd

single, specific value.

value cannot be changed during simulation. Uses keyword CONSTANT

VHDL: Basics to Programming_Gaganpreet Kaur

Copyright 2011 Dorling Kindersley India Pvt. Ltd

VHDL: Basics to Programming_Gaganpreet Kaur

Copyright 2011 Dorling Kindersley India Pvt. Ltd

allowed only with sequential constructs Used inside a subprogram or inside a

VHDL: Basics to Programming_Gaganpreet Kaur

Copyright 2011 Dorling Kindersley India Pvt. Ltd

Variable assignment operator (:=)

VHDL: Basics to Programming_Gaganpreet Kaur

Copyright 2011 Dorling Kindersley India Pvt. Ltd

associated with it a signal driver

VHDL: Basics to Programming_Gaganpreet Kaur

Copyright 2011 Dorling Kindersley India Pvt. Ltd

VHDL: Basics to Programming_Gaganpreet Kaur

Copyright 2011 Dorling Kindersley India Pvt. Ltd

VHDL: Basics to Programming_Gaganpreet Kaur

Copyright 2011 Dorling Kindersley India Pvt. Ltd

Copyright 2011 Dorling Kindersley India Pvt. Ltd

to 0 as BIT_VECTOR(7 DOWNTO 0).

VHDL: Basics to Programming_Gaganpreet Kaur

Copyright 2011 Dorling Kindersley India Pvt. Ltd

good alternative to bit data type for

VHDL: Basics to Programming_Gaganpreet Kaur

Copyright 2011 Dorling Kindersley India Pvt. Ltd

operations are allowed on std_logic as well as std_ulogic types

Copyright 2011 Dorling Kindersley India Pvt. Ltd

Copyright 2011 Dorling Kindersley India Pvt. Ltd

VHDL: Basics to Programming_Gaganpreet Kaur

Copyright 2011 Dorling Kindersley India Pvt. Ltd

() or string of characters included in double quotes (). Example: SIGNAL x: CHAR:= a;

VHDL: Basics to Programming_Gaganpreet Kaur

Copyright 2011 Dorling Kindersley India Pvt. Ltd

VHDL: Basics to Programming_Gaganpreet Kaur

Copyright 2011 Dorling Kindersley India Pvt. Ltd

User Defined Types

VHDL: Basics to Programming_Gaganpreet Kaur

Copyright 2011 Dorling Kindersley India Pvt. Ltd

User Defined Types

VHDL: Basics to Programming_Gaganpreet Kaur

Copyright 2011 Dorling Kindersley India Pvt. Ltd

Scalar Data Type

defined values consisting of identifiers and character literals

VHDL: Basics to Programming_Gaganpreet Kaur

Copyright 2011 Dorling Kindersley India Pvt. Ltd

Scalar Data Type

Copyright 2011 Dorling Kindersley India Pvt. Ltd

Composite Data Type