Professional Documents
Culture Documents
Hardware
Overview
The LCD Controller provides an interface to a STN or TFT LCD Panel. Display data is DMAed from external memory to the LCD controller. To LCD Panel
LCD Controller
LCD Controller
Supports both monochrome and color, single- and dual-panel Super Twisted Nematic (STN) LCD panels Supports 18 and 24-bit Thin Film Transistor (TFT) LCD color displays STN mode supports up to 15 gray-levels for monochrome and 3375 colors TFT mode supports up to 16M colors Supports all popular display resolutions up to 1024x768 maximum 256 entry, 16-bit palette RAM Monochrome STN supports 1,2, or 4 bits-per-pixel via palette RAM
LCD Controller
Color STN supports 1,2,4, or 8 bits-per-pixel via palette RAM TFT supports 1,2,4,or 8 bits per-pixel via palette RAM; 16 and 24 bits per pixel direct LCD timing programmable AHB DMA engine transfers display data from external memory to dual 64x32 FIFOs Supports big and little endian pixel format, as well as WinCE LCD panel clock can either be generated internally from the AHB clock or provided via an external oscillator
LCD controller provides an additional clock divider that can be used to divide the source clock further to generate the LCD panel clock (see NS9750 Hardware Reference Manual for programming limitations on clock divider value)
Vertical Timing
D[ : ]
Blan ing
Blan ing
Horizontal Timing
Vertical Timing
Horizontal Timing