Logic Design

using MOSFETs
LECTURE# 04
VLSI DESIGN

Saad Arslan COMSATS INSTITUTE OF INFORMATION TECHNOLOGY, ISLAMABAD 1

Assignment #1
Due on Thursday, February 25, 2016
Do not copy
◦ Please
◦ Never ever

Saad Arslan COMSATS INSTITUTE OF INFORMATION TECHNOLOGY, ISLAMABAD 2

Complex Logic Gate in
CMOS
XOR and XNOR Gates
We often use XOR and XNOR gates,
which have logic functions
Pull-up using

Is also correct
𝑎 Mp Mp 𝑎

In order to implement XOR 𝑏 Mp Mp 𝑏

◦ We consider compliment function (for
implementing using CMOS) 𝒂⊕ 𝒃
◦ For pull-down network
𝑎 Mn Mn 𝑎
◦ For pull-Up Network
𝑏 Mn Mn 𝑏
◦ Please note the switch is assert low
◦ and will be inverted

Saad Arslan COMSATS INSTITUTE OF INFORMATION TECHNOLOGY, ISLAMABAD 3

Complex Logic Gate in
CMOS
XOR and XNOR Gates cont.
Also, XNOR

◦ replacing <–> in XOR 𝑎 Mp Mp 𝑎

◦ or replacing <–>

𝑏 Mp Mp 𝑏
𝒂⊕ 𝒃
𝑎 Mn Mn 𝑎

𝑏 Mn Mn 𝑏

Saad Arslan COMSATS INSTITUTE OF INFORMATION TECHNOLOGY, ISLAMABAD 4

Sequential Logic Circuits
SR Latch
Combinational logic circuits
◦ Depends only upon current input logic combination
◦ No storage

Sequential logic circuits

◦ Depends upon current input and past output
◦ Feedback

SR Latch truth table

Operation 𝑆 𝑄
Hold
Set
Reset
Not allowed
𝑅 𝑄
Saad Arslan COMSATS INSTITUTE OF INFORMATION TECHNOLOGY, ISLAMABAD 5
Sequential Logic Circuits
SR Latch CMOS Circuit
SR Latch CMOS Circuit
The next latch state
M1 M5
◦ For only

Following can be done M2 M6

𝑹
◦ SR latch using NAND gate 𝑺
◦ Clocked SR latch
𝑸 𝑸
◦ JK Latch
M3 M4 M7 M8

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 Transmission Gates (TG)
Bi-directional switches 𝑋
Use both nMOS and pMOS to efficiently transfer logic 1 and 0
TGs can be used to implement multiplexors 𝐴 𝐵
◦ Simple 2 to 1 mux using TG ()
𝑆 𝑆
0 A
𝐴 𝐴
𝑋
1 B
𝑋
𝑆 𝑍 𝑆 𝑍
𝐴 0
𝑍
𝐵 1 𝐵 𝐵 𝐴 𝐵
𝑆 𝑆 𝑆
𝑋
Saad Arslan COMSATS INSTITUTE OF INFORMATION TECHNOLOGY, ISLAMABAD 7
Transmission Gates (TG)
Four to One Mux
𝑆0
◦
𝐴
𝑋 𝑆1
0 0 0 A C 𝑆0
0 1 1 B D
𝐵
1 0 2 A C
𝑆0 𝑆1 𝑍
1 1 3 B D

𝐴 0
𝐶
𝐵 1
𝑍
𝐶 2
𝑆0 𝑌 𝑆1
𝐷 3

𝑆0 𝐷
𝑆1
𝑆0
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Transmission Gates (TG)
2 input XOR
How many MOSFETs are used here?
◦ Inverters x2 4 MOSFETs
◦ TG x2 4 MOSFETs
𝐴
Total Eight MOSFETs 𝐵 𝐴𝐵

𝐴 𝐴 𝑌¿ 𝐴 𝐵+ 𝐴 𝐵

𝐵 𝐵 𝐴𝐵
𝐴

Saad Arslan COMSATS INSTITUTE OF INFORMATION TECHNOLOGY, ISLAMABAD 9

Transmission Gates (TG)
3-variable Boolean function
Implement the following Boolean function

𝐴
𝐴
1 𝐶
𝐴𝐶+ 𝐴𝐵𝐶
𝐴𝐵 +¿ 𝐴+ 𝐴𝐵
𝐴 𝐶𝐶 𝑌¿ 𝐴𝐶+ 𝐴𝐵𝐶
𝐴𝐵
𝐵 𝐵 𝐵𝐶
𝐶
Saad Arslan COMSATS INSTITUTE OF INFORMATION TECHNOLOGY, ISLAMABAD 10
Transmission Gates (TG)
OR Gate
Static CMOS logic allows us to implement NOR GATE
◦ We can implement OR directly using a combination
◦ TG and PMOS

OR Gate logic function

𝐴

𝐴 𝐴𝐴 𝑌¿ 𝐴 𝐴+ 𝐴 𝐵
¿ 𝐴+𝐵

𝐵 𝐴𝐵

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Conclusion
That was it for static CMOS logic
◦ Which allowed to implement combinational and sequential logics

Later in the course we will discuss

◦ Dynamic CMOS Logics

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Physical Structure of CMOS
Integrated Circuits
A CMOS IC is a electronic switching network
◦ Created in a small area
◦ Using complex physical and chemical processes

In the design hierarchy the last task is to

◦ Translate circuit schematics in to silicon form
◦ Called physical deisgn

In this chapter we will examine the structure of CMOS IC

◦ At the microscopic level

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Integrated Circuit Layers
A silicon IC is a collection of patterned material layers
◦ The layers are of metals, insulators and semiconductor (silicon)

The layers are stacked upon one another in a specific order

◦ To form 3D structures that act as electronic switching network

The silicon forms the transistors, diodes etc

Metals forms the interconnects and contacts
The insulator do their job of blocking current (insulating layers)
◦ Usually when designing layout, the insulating layers are implied
◦ And not explicitly shown in the design

Insulating layers are usually silicon dioxide () called quartz glass

◦ Which is visually transparent

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Integrated Circuit Layers cont.
Consider an example Metal 1
◦ With two layers
Insulator
◦ As shown in figure
Substrate
Metal 1 and Substrate
◦ Is electrically isolated by insulator

Side view Top view

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Integrated Circuit Layers
Adding more layers
The metal 1 layer is filled/coated Metal 2
◦ with insulator Metal 1
Insulator
Then it is subjected to CMP Side view
◦ Chemical Mechanical Planarization Substrate
◦ In which the surface is etched and sanded
◦ To flat the surface for next layer

Next, the surface is coated with

◦ Metal 2 layer,
Top view
◦ As shown in figure

Side view shows, order of stacking

Top view shows, pattern of each layer

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