Physical Structure

of CMOS ICs
LECTURE# 06
VLSI DESIGN

Saad Arslan COMSATS INSTITUTE OF INFORMATION TECHNOLOGY, ISLAMABAD 1

Electrical Conduction in
Silicon
Intrinsic Semiconductor
In pure crystalline form, silicon is a poor conductor (semiconductor)
◦ Atomic density of
◦ Small number of electrons are available for current flow
◦ Due to thermal excitation, upon gaining thermal energy,
◦ jump from valance to conduction band

A sample of purse silicon crystal is an intrinsic material

◦ The number of free electrons represented by (intrinsic carrier density)
◦ is a function of temperature. At ,
◦ The value of is very small compared to

Upon gaining thermal energy an electron may break its covalent bond
◦ It becomes a free (mobile) electron, leaving behind a vacancy, called a hole
◦ The two newly particles are independent, but known as electron-hole pair

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Electrical Conduction in
Silicon Charge Carriers
It is important to study free charge carriers
◦ As they are responsible for current flow

As discussed earlier, the process of electron-hole pair generation

◦ An intrinsic material will have same number of electrons and holes
◦ ( is number of free electrons, is number of holes)

The product of and ,

◦ Is called mass-action law and governs relative carrier density
◦ When a material is in equilibrium (no current is flowing)

In order to increase charge carrier

◦ Intrinsic silicon is doped with trivalent or pentavalent impurity

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Electrical Conduction in
Silicon Donor Doping
Pentavalent impurity (Phosphorus or Arsenic atoms), donor impurity
◦ Donate an electron to crystal, making the semiconductor n-type
◦ The number of donor impurity atoms added to a is given by
◦ Donor doping concentration () is typically between to

As intrinsic semiconductor has small number of electrons

◦ So if doping concentration is high, and, each atom donates one electron
◦ # of electrons () in n-type material, will be
◦ # of holes () in n-type material, will be given by mass-action law,

Note that will have even lower value than of intrinsic material
◦ As some of the newly donated electrons will recombine with holes

In an n-type sample, electrons are majority & holes are minority carriers

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Electrical Conduction in
Silicon Acceptor Doping
Trivalent impurity (Boron etc. atoms), acceptor impurity
◦ accepts an electron from crystal, leaves a hole, making semiconductor p-type
◦ The number of acceptor impurity atoms added to a is given by
◦ Acceptor doping concentration () is typically between to

Adding acceptor impurity will result in increased # of holes

◦ # of hole () in p-type material, will be
◦ # of electrons () in p-type material, will be

Also will have even lower value than of intrinsic material

◦ As some of the newly created holes will recombine with electrons

In an p-type sample, holes are majority & electrons are minority carriers

Saad Arslan COMSATS INSTITUTE OF INFORMATION TECHNOLOGY, ISLAMABAD 5

Example 3.1
Suppose that the donor doping density is . The intrinsic carrier density is
. Find electron and hole concentration.
The electron density is
◦

The hole concentration is (using mass-action law)

Please note that this is an n-type semiconductor, where

◦ electrons are majority carriers & holes are minority carriers
◦ hole density is even less than that of intrinsic material

Saad Arslan COMSATS INSTITUTE OF INFORMATION TECHNOLOGY, ISLAMABAD 6

Electrical Conduction in
Silicon Doped Semiconductor
The conductivity of a semiconductor with- carrier densities and
◦ , is charge on an electron
◦ Where and are electron and hole mobilities, respectively.
◦ Mobility have units of , depicts how mobile a particle is. For intrinsic silicon, at room
temperature
◦ and
◦ Indicates that electrons can easily move freely compared to holes.

For the above value of mobilities

◦
◦ Comparing with quartz glass which has resistivity of

We can approximate and

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Example 3.2
Consider a sample of silicon that is doped p-type with boron added at a
density of . Consider
The majority charge carriers are holes, with density

The minority charge carriers are electrons, with density

Conductivity of the doped semiconductor is

Resistivity
We observe that

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Physical Structure of MOSFETs
Doped Regions
We have now build bases towards understanding the
◦ physical structure of MOSFETs

The polarity of nMOS or pMOS is defined by

◦ Polarity of source and drain regions
◦ nMOS has n+ source and drain, while pMOS has p+ source and drain regions

The devices are designed so that the channel has

◦ Same polarity as of source and drain, only when device is conducting
Gate Gate

Source Drain Source Drain

nMOS pMOS
Saad Arslan COMSATS INSTITUTE OF INFORMATION TECHNOLOGY, ISLAMABAD 9
Physical Structure of MOSFETs
nMOS
An nMOS has its drain and source regions labeled as “n+”
◦ Indicating they are heavily doped, around
◦ p-substrate region is p-type, with normal doping

PN junctions are formed between substrate and n+ regions

◦ So any current flow is blocked

Gate Gate

Source Drain Source Drain

nMOS pMOS
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Physical Structure of MOSFETs
pMOS
An pMOS has its drain and source regions labeled as “p+”
◦ Indicating they are heavily doped, Large

In order to create PN junction to block current flow

◦ n-well is form within p-substrate
◦ n-well region is n-type, with normal doping, medium-low

nMOS and pMOS have opposite electrical characteristics

Gate Gate

Source Drain Source Drain

nMOS pMOS
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Physical Structure of MOSFETs
Current Flow in nMOS
MOSFETs are voltage controlled switches
◦ Gate voltage, opens or closes the switch
◦ When positive gate voltage applied, the channel is formed, switch closes

The Gate and substrate of the a MOS forms a capacitor

◦ With gate oxide acting as dielectric in between, with permittivity
◦ Applying gate voltage, result in charge accumulation on both plates
◦ Further increasing gate voltage create free electrons on –ive plate (substrate)
+𝑉
A capacitor stores charge Q, such that Area ()
◦
𝑡 𝑖𝑛𝑠
+𝑄
𝜖
−𝑄

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Physical Structure of MOSFETs
Current Flow in nMOS cont.
The dashed-line shows capacitor in a MOS
MOSFET gate, per unit area capacitance is MOSFET is derived from
• M (Metal used in earlier gates)
defined as
• O (Oxide, Gate oxide)
◦ Oxide Capacitance , has units • S (Semiconductor, Substrate)
So, gate capacitance (for a gate with area ) 𝑉𝐺

Gate Oxide
We have permittivity for free space Gate
𝑡 𝑜𝑥
+¿¿ +¿¿
n n
◦ permittivity

Thinner gate oxide (small ) is desirable p-substrate

◦ Nowadays

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Example 3.3
Consider a gate oxide that has thickness of , and . Find gate capacitance
Oxide capacitance

Gate Area

Gate capacitance

Please be careful with units, all variables must have same units like or
• , ,
• ,

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Physical Structure of MOSFETs
Current Flow in nMOS cont.
When gate voltage () increase beyond threshold voltage ()
◦ An electron inversion layer (channel) is formed between drain and source
◦ is defined by fabrication sequence.

The channel charge (in substrate between drain and source) is given by
◦ from
◦ -ive sign due to the fact that electronic (negative) charge is being measured

We know current is rate of charge flow

◦ ;units
◦ is channel transit time

Physically, is average time for an electron to go from source to drain.

◦ ;where is channel length, is particle velocity

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Physical Structure of MOSFETs
Current Flow in nMOS cont.
Putting and in current equation

◦ because

The velocity of a electron, in a material under influence of an electric field

◦ because

Substituting velocity in current

◦ where is voltage across channel ()

When seeing MOSFET (drain-source) as a resistor

◦ is device trans-conductance

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Physical Structure of MOSFETs
Current Flow in pMOS
For pMOS, all polarities are reversed.
◦ where is voltage across channel ()

When seeing MOSFET (drain-source) as a resistor

◦ is device trans-conductance

is a negative value for pMOS, when is less than

◦ Channel exists

So negative voltage is applied to gate

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Physical Structure of MOSFETs
Driving Gate Capacitance
In static CMOS circuits, input is applied to the gate of a MOSFET
◦ So the driving circuit (input) will see the MOSFET as a capacitor

Firstly, voltage across a capacitor cannot be change suddenly

◦ This will cause delay in operation

Secondly, capacitors store energy so

◦ Every time the input is changed, the capacitor will be charged & discharged
◦ Charging capacitor means providing energy, discharging means wasting energy

We know that power delivered is, rate of change of energy provided

Power, in electric circuit, can be measured as

◦ where capacitor current

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Physical Structure of MOSFETs
Driving Gate Capacitance cont.
Equating the two power equations, to calculate electric energy
◦

So every time, a MOSFET input in changed from 0 to VDD

◦ Energy is provided, for every MOSFET in the circuit

Also the interconnect use to provide charge/discharge current to capacitor

◦ Has finite resistance, so interconnect dissipates power ( as heat

We had two observations

◦ Switching delays are due to physical characteristics (, , length etc.)
◦ Every switching activity requires energy transfer and power dissipation

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