Digital Logic Design

EEE241

Combinational Logic

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Combinational Logic

 Outline
 Combinational Circuits
 Analysis
 Design
 Binary Adder/Subtractor
 Multiplier
 Comparator
 Encoder/Decoder
 Multiplexers/Demultiplexers

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Combinational Circuits
 Recall
 Single/multiple inputs  Single output
 Many realistic problems use multiple outputs
 Named as combinational circuits
 Combinational circuit
 Output depends only on input(s)

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Combinational Circuits
 What happens if we add memory to the circuit?

 Becomes a feedback system

 Sequential Circuits

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Combinational Circuit Analysis
 Determine the function of circuit
 Instead of developing the circuit based on the function
 Circuit analysis
 Determine the output functions as algebraic expressions
 Determine the truth table of the outputs
 What is the output function of this circuit?

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Combinational Circuit Analysis
 Analysis steps
1. Label all gate outputs with symbols
2. Determine Boolean function at the output of each gate
3. Express functions in terms of input variables + simplify

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Combinational Circuit Analysis
 Substitution
T1  ( xy )
T2  ( xT1 )
T3  ( yT1 )
F  (T2T3 )  (( xT1 )( yT1 ))
 xT1  yT1  x( xy )  y ( xy )
 x( x  y)  y ( x  y)
 xx  xy  xy  yy
 xy  xy  x  y
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Combinational Circuit Analysis:
Example
 What are the outputs F1 and F2 of the following circuit?

 Here
 T2 = ABC
 T1 = A+B+C
 F2 = AB + AC + BC
 T3 = F 2 ’ T 1
 F1 = T 3 + T 2

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Combinational Circuit Analysis:
Example
 Analysis by truth table

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Combinational Circuit Design
 Design procedure
1. Determine the number of inputs and outputs
2. Assign symbols
3. Derive the truth table
4. Obtain simplified functions for each output
5. Draw the logic diagram

 Truth tables: input and output columns

 Multiple methods to solve

 Boolean algebra, map methods, computer aided solution

 Issues to consider
 Number of gates
 Gate inputs
 Propagation delay
 Number of interconnections
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Combinational Circuit Design: Example

 Design a circuit that converts a BCD number to Excess-3

code

 Step 1: Inputs and Outputs

 Input: BCD digit
 4 inputs: A, B, C, D
 Output: Excess-3 digit
 4 outputs: w, x, y, z

 Step 2: Truth table

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Combinational Circuit Design: Example

 Step 3: Minimize output functions

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Combinational Circuit Design: Example

 Step 4: Simplification
 z = D’
 y = CD+C’D’
= CD+(C+D)’
 x = B’C+B’D+BC’D’
= B’(C+D)+BC’D’
= B’(C+D)+B(C+D)’
 w = A+BC+BD
= A+B(C+D)

 Step 5: Circuit Diagram

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Binary Adders
 Addition is important function in computer system

 What does an adder do?

 Add binary digits
 Generate carry if necessary
 Consider carry from previous computation

 Binary adders operate bit-wise

 A 16-bit adder uses 16 one-bit adders

 Binary adders come in two flavors

 Half adder adds two bits and generates result and carry
 Full adder considers carry input in addition to half adder
 Two half adders make one full adder

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Binary Half Adder
 Specification
 Design a circuit that adds two bits and generates the sum and a carry

 Input/Output
 Two inputs: x, y
 Two outputs: S (sum), C (carry)

 Functionality

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Binary Half Adder

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Full Adder
 Half adder works only for a single bit
 When multiple bits are involved, carry bits should be considered
 Solution  Full adder

 Specifications
 A circuit that adds three bits and
generates a sum and a carry

 Input/output
 Three inputs: x, y, Cin
 Two outputs: S (Sum), Cout (Carry)

 Truth table
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Full Adder
 Derive and minimize Boolean expressions

S  xyCin  xyCin  xyCin  xyCin  x  y  Cin

Cout  xy  xCin  yCin  ( x  y )Cin  xy

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Full Adder

 Circuit

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Full Adder from Half Adders

 How can two half adders make a full adder?

 Observations
 Three inputs x, y, z can be added in two steps
 x+y+z = (x+y) + z
 What about the carry?
 Carry can occur when adding x+y and when adding z

 Full adder: S = x  y  z , C = xy + (x  y)z

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Binary n-bit Adder
 How can we build an n-bit adder from full adders?
 One adder for each bit (n total)
 Connect carry to next adder’s input
 Output: sequence of sums and a final carry
 4-bit adder circuit (Ripple Carry Adder)

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Full Adder from Half Adders

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Ripple Carry Adder
 How long does it take to complete an addition?
 Carry needs to propagate through circuit – a problem

 Speed of addition is critical

 Fundamental arithmetic operation

 How can we speed up addition?

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 Determine carries ahead of time (carry look-ahead)
Carry-Lookahead Adder
 Recall
 For the design of the parallel adder to work, the signal must propagate
through the gates before the correct output sum is available
Total propagation time = propagation delay of a
typical gate x the number of gates

 Let’s look at S3
 Inputs A3 and B3 are available immediately.
 However, C3 is available only after C2 is available.
 C2 has to wait for C1, etc.

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Carry-Lookahead Adder
 Full adder: Si = AiBiCi , Ci+1 = Ai.Bi + (AiBi).Ci
 Create new signals
 Gi = Ai.Bi  carry generate for stage i
 Pi = Ai  Bi  carry propagate for stage I

 Full adder equations expressed in terms of Gi and Pi

 Si = Pi  Ci
 Ci+1 = Gi + Pi Ci

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Carry-Lookahead Adder

 Full adder functionality can be expressed

recursively
 Si = Pi  Ci
 Ci+1 = Gi + Pi Ci

 Carry of each stage

 C0 = input carry
 C1 = G 0 + P 0C 0
 C2 = G1 + P1C1 = G1 + P1 (G0 + P0C0) = G1 + P1G0 + P1P0C0
 C3 = G2 + P2C2 = … = G2 + P2G1 + P2P1G0 + P2P1P0C0
 C4 = G3 + P3G2 + P3P2G1 + P3P2P1G0 + P3P2P1P0C0
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Carry-Lookahead Adder
 Circuit
 SOP form
 Only 2 stages

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4-bit Adder with Carry Lookahead
 Complete adder
 Same number of stages
for each bit

 Drawback?
 Increasing complexity of
lookahead logic for more
bits

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Subtraction

 How can we perform subtraction?

 Subtract one number from another

 Do we need subtractors?
 Actually not
 Subtraction can be done using adders
 N – M = N + (2’s complement of M)
 How do we determine 2’s complement?
 1’s complement and adds 1

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Subtraction

 How to take 1’s complement then?

 Invertors (NOT) gate
 Can we do something else?
 Yes
 XOR gate
 x  0 = x (use for Addition)
 x  1 = x’ (use for Subtraction)

 How can we add 1?

 Input carry

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Binary Subtractor
 Adder/Subtractor circuit

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Overflow
 n-bit addition can generate (n+1)-bit number
 Called “overflow”
 Needs to be detected by computer system

 How can we detect overflow in addition?

 End carry

 Necessary for signed numbers or subtraction

 Most significant bit indicates sign

 If carry into sign position and out of sign position differ,

then overflow
 Result would be correct with extra position
 How can we detect this?
 XOR gate
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Overflow Conditions
 Overflow conditions
 When both numbers have same sign, and
 If carry into sign position and out of sign position differ
 There is no overflow if signs are different (pos + neg, or neg + pos)
 Example: 2’s complement signed numbers with n = 4 bits

 Result would be correct with extra position

 Detected by XOR gate (output =1 when inputs differ)
 Can be used as input carry for next adder circuit 33
BCD Adder
 Add two decimal numbers
 (09)+(09)+(1) = 019 ‐ don’t forget carry

 How to begin?
 Truth table
 Can we use existing circuit?

 Binary adder
 Almost works for
decimal addition

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BCD Adder (Truth Table)

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BCD Adder (Truth Table)

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BCD Adder

 If C=1, need to add 6 to the binary sum

 How to implement?
 Need another adder

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BCD Adder

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BCD Adder

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Multiplier
 Product is 1 when both inputs are 1
 Which gate can be used?
 AND

 2-bit multiplier

 A multiplier is composed of AND gates and adders

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Multiplier
 Circuit diagram

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Multiplier
 4-bit x 3-bit multiplier
 J=3, K=4

 How many AND gates

 J x K gates

 How many adders

 (J-1) K-bit adders

 How many output bits

 J + K bits

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Magnitude Comparator
 Need to compare two numbers: A and B
 A>B, A<B, A=B

 How can we determine that two numbers are equal?

 Equal if every digit is equal
 A3A2A1A0 = B3B2B1B0 if and only if
A3 = B3 and A2 = B2 and A1 = B1 and A0 = B0

 Which gate?
 XNOR (Equivalence)

 What about A < B and A > B?

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Magnitude Comparator
 Case 1: A > B
 Look at most significant bit where A and B differ
 If A = 1 and B = 0, then A > B
 If not, then A ≤ B

 Functionality (4-bits)
 If difference in first digit: A3B3′
 If difference in second digit: x3A2B2′
 Conditional that A3 = B3 (x3 =1 if : A3=B3 )
 Similar for all other digits

 For A > B
 (A > B) = A3B3′ + x3A2B2′ + x3x2A1B1′ + x3x2x1A0B0′
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Magnitude Comparator
 Case 2: A < B
 swap A and B for A > B

 Functionality
 (A = B) = x3x2x1x0
 (A > B) = A3B3′ + x3A2B2′ +
x3x2A1B1′ + x3x2x1A0B0′
 (A < B) = A3′B3+ x3A2′B2 +
x3x2A1′B1 + x3x2x1A0′B0

 Can be extended to arbitrary

number of bits
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Other Arithmetic Blocks

 Encoders (Enc)
 Decoders (Dec)
 Multiplexers (Mux)
 De-multiplexers (DeMux)
 Tri-state logic

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Motivation – ALU Design
 ALU – Arithmetic and Logic Unit
 Add, Subtract, AND, OR

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Motivation – CPU Design
 Instruction Management

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Decoder
 Selects one output based on a binary input
 Converts n-bit code into 2n outputs, only one being active
at a time
 Selects output x if input is binary representation of x

 Applications
 Binary-to-octal decoder
 Memory address selection
 Selection of any kind

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Decoder
 Example: 3-to-8-line decoder

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Decoder: Circuit
 When is output 0 chosen?
 If x’ y’ z’

 When is output 1 chosen?

 If x’ y’ z

 Circuit for line decoder

 Sequence of minterms
 Combine variables to
minterms

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Advanced Decoder
 Sometimes, you need to activate circuits
 Reason: Take output only when required
 Solution: Use enable pins
 Decoder with enable
 Generates output only when active-low enable is high
 Example:
 2-to-4-line decoder with enable
 NAND implementation

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Advanced Decoder
 Enable bit allows construction of large decoders using
smaller ones
 Example: Construct a 4-to-16 decoder only using 3-to-8
decoders
 Active-high enable

 Can we use this circuit

to construct a 5-to-32
decoder?
 NO
 Absence of enable

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Decoders: Example
 Design a full adder using a 3-to-8-line decoder
 Truth table

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Encoders
 Translates 2n input lines into n output lines
 Input: 2n lines
 Output: n bits
 Output is binary coding of input that is 1

 Truth table (n=3) (positive polarity)

 Note: only one input should be allowed to be active at a time

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Encoders

x = D 4 + D5 + D 6 + D 7
y = D 2 + D3 + D 6 + D 7 How many OR gates are required?

z = D 1 + D3 + D 5 + D 7 Can you see any problem here?

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Encoders: Problems
 Only one input can be active at a time
 Simultaneous active inputs result in undefined output
 When all inputs are zero x = D4 + D5 + D6 + D7
 Equal to the case when D0 is 1
y = D2 + D3 + D6 + D7
z = D1 + D3 + D5 + D7
 Example
 If D3 and D6 are active simultaneously, what is the
output?
 111

 How can we solve this problem?

 What should the output be if multiple lines are active?
 Different solutions:
 Any one (random)
 Give priority to lower or higher lines
 Indicate invalid input (requires extra bit, valid bit V)

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Priority Encoder
 Simple encoder, with additional functionality
 If multiple inputs are 1, give priority to one of them

 Example: 4-to-2 priority encoder with priority given to one bit

 Which bit has the highest priority?

 D3

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Priority Encoder

Valid bit V = D0 + D1 + D2 + D3

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Priority Encoder
 Circuit diagram

x = D 2 + D3
y = D 3 + D 1 D2’
V = D0 + D 1 + D 2 + D 3

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Multiplexer (MUX)
 Selects from 1 of many inputs and directs it to the output

 Input
 2n lines

 Output
 1 line

 Selection may be controlled by select lines

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Multiplexer (MUX)
 Example
 2-to-1 MUX

 How to design?
 4-to-1 MUX
 Selection code directs input
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4-to-1 MUX

What are the values of Y?

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Multiplexer (MUX)
 A MUX only selects one bit
(output)
 How to select multiple bits
(outputs)?
 Example: What if you want to
choose one of two 4-bit
numbers?
 Solution: Use multiple MUX

 Quadruple 2-to-1 line MUX

 Enable bit sets output to 0 if 1

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Use MUXes for Boolean Functions
 MUXes can also be used to implement the Boolean
function
 Use MUX to implement the following function

F = x’y’z + x’yz’ + xy’z + xyz

 Concept
 MUX is a decoder + OR gate
 Use the selector to direct correct value to output

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Use MUXes for Boolean Functions
 Example
 F(x,y,z) = (1,2,6,7)

 Truth table

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Use MUXes for Boolean Functions

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Use MUXes for Boolean Functions
 Example
 F(x,y,z) = (1,3,4,11,12,13,14,15)

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Use MUXes for Boolean Functions

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Demultiplexer (DeMUX)
 Receives information from 1 input and directs it to one of
2n possible outputs
 Input
 Data bit
 n selection lines

 Output
 2n lines

 Can be achieved by decoder circuit with enable D active

low
 Enable D acts as data bit ( “disable”)
 n code lines act as selection
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Use MUXes for Boolean Functions
 Example:
 Design a full adder using MUXes

 Expressions
 S(x,y,z) = Σ(1,2,4,7); C(x,y,z) = Σ(3,5,6,7)

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Use MUXes for Boolean Functions

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Three-State (Tri-state) Gates
 What is the truth table for F ?

 The two gates will try to drive F at the same time

 Not a good idea to wire their outputs
 Sometimes it is necessary to “disconnect” a gate

 Three state:
 0 or 1 Boolean value
 “High impedance”, Z state
 High impedance acts as if gate were disconnected

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Multiplexer with Tri-state Gates
 2-to-1 MUX

 4-to-1 MUX with Enable

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