DIGITAL PRINCIPLE AND SYSTEM DESIGN – REPOSITORY

(Common to ECE, BME, CSE, IT, MED)

Sub. Code /Sub. Name:19EC303/ Digital Principle and system design

At the end of the course learners will be able to

Apply
CO1 Understand Boolean algebra and minimization of logic expressions

CO2 Analyze
Design and analyze various combinational digital circuits
Analyze
Introduce the analysis and design procedures for synchronous sequential
CO3
circuits
Analyze
Introduce the analysis and design procedures for asynchronous sequential
CO4
circuits
Remember
Introduce the electronic circuits involved in the making of logic gates
CO5

UNIT-I DIGITAL FUNDAMENTALS

PART-A

Q.no CO Question Marks/Rubrics KL

1 CO1 Find the octal equivalent of hexadecimal numbers of AB.CD 2 K5

2 CO1 Add, subtract and multiply the following numbers in binary 2 K2
(110010)2 and
(11101)2.
3 CO1 State the principle of duality 2 K1
4 CO1 Implement AND gate using only NOR gates 2 K6

5 CO1 Convert (0.6875) 10 to binary 2 K3

6 CO1 Prove the following using DeMorgan’s Theorem 2 K2

[(X + Y)'+(X + Y) '] '=X + Y.
7 CO1 Write short notes on weighted binary codes. 2 K2

8 CO1 Illustrate NOR Operation with a truth table 2 K2

9 CO1 What is Excess-3 Code? 2 K1
10 CO1 Simplify Z = (AB +C) (B'D + C'E')+(AB+C)' (OR) F=x’y’+xy+x’y 2 K4
11 CO1 Realize G = AB'C +DE+F' (OR) Represent a OR gate using 2 K4
NAND gate
12 CO1 Convert (1001010. 1101001) 2 to base 16 & (231.07)8 to base 10 2 K2

13 CO1 Convert the (1011111011) 2 into gray code. 2 K2

14 CO1 Find the complement of the function F= X'YZ' + X'Y'Z. 2 K1

15 CO1 Define Self complementary Code? 2 K1
16 CO1 What are Universal Gates? Why are they named so? 2 K1
17 CO1 What bit must be complemented to change an ASCII letter from 2 K1
capital to lower
case and vice versa?
18 CO1 Express the following Boolean expression in to minimum number 2 K5
of literals.
XYZ+X'Y+XYZ'.
19 CO1 What are the limitations of K-map? 2 K1
20 CO1 Analyse the following Boolean functions using three variable 2 K4
maps. F(X,Y,Z) =∑(0,2,3,6,7).
21 CO1 K1
What are the advantages of K-Map method reduction 2
22 CO1 Prove the commutative law 2 k5

23 CO1 Convert the following binary number into gray code 2 K2

a)1010 b)1101
24 CO1 The ASCII Code message, 100 0111 100 1111 100 0100 is 2 k2
stored in memory of a computer. What is the message?
25 CO1 Complement the expression A’B + CD’ 2 K1

26 CO1 Simplify Y = AB’ + (A’ + B)C. 2 K4

27 CO1 Express the boolean funtion F=A+B’C as Sum of minterms 2 K5

28 CO1 Why digital electronics are more widely used as compared to analog 2 K1
electronics?
29 CO1 For the boolean expression F=A’C+A’b+AB’C+BC find the minimal 2 K1
SOP Expression.
30 CO1 Write the boolean expression in SOP form F=(b+d)(a’+b’+c). 2 K2

31 CO1 Draw logic diagrams to implement the following boolean 2 K2

expression.Y=[(A+B’)(Y’+C)]
32 CO1 List the truth table of the funtion F=YZ+X’Z’. 2 K1

33 CO1 Convert (51)10 to an octal number. 2 K2

34 CO1 Find the binary equivalent for the given Hexadecimal 2 K1

number(308.A)16
35 CO1 Give the procedure to convert Excess 3 to grey code number. 2 K1

36 CO1 Perform 2’s complement subtraction for the given 2 K2

numbers.X=1010100 and Y=1000011.
37 CO1 Convert decimal code 6,514 to BCD code. 2 K2

38 CO1 Obtain 2’s complement of the Number 1111111. 2 k2

39 CO1 List out the universal gates .why it is called so? 2 k1

40 CO1 Solve X(X+Y)=X by duality theorem. 2 k3

41 CO1 List out the advantages and disadvantages of digital system. 2 k1

42 CO1 What are all the techniques used to minimize boolean expression. 2 k1

43 CO1 Prove A(A+B)=A 2 k5

44 CO1 Prove (A+B) (B+C) =B+AC 2 k5

 45 CO1 Write the truth table of the given logic circuit and state the nature of the 2 k1
circuit.

46 CO1 In which way Boolean algebra is different from ordinary algebra 2 k1

47 CO1 What are the conditions of inputs A,B and C? If output of 3 inputs OR 2 k1
gate is ‘0’.
48 CO1 A Basic 2 -Input logic circuit has output high only when any one of 2 k1
the input is high. What type of logic circuit it is?
49 CO1 Simplify the logic diagram using K-Map 2 k4

50 CO1 What is the difference between SOP and POS? 2 k1

PART-B

Q.no CO Question Mark KL

1 CO1 Simplify the following switching function using Quine Mc Cluskey 13 K4
method
and realize expression using gates F(A,B,C,D) =
∑(0,5,7,8,9,10,11,14,15)
2 CO1 Simplify the following switching function using karnaugh map 13 K4
methodand
realize expression using gates F(A,B,C,D) =
∑m(0,2,8,10,12,13,14,15)+∑d(5,7)
3 CO1 Simplify the function F(w,x,y,z)=∑m(2,3,12,13,14,15) using 13 K4
Tabulation
method. Implement the simplified function using gates.
4(a) Demonstrate by means of truth tables the validity of the DeMorgan’s 04 K1
theorem for three variables : (XYZ)’=X’+Y’+Z’ (OR) State and prove
De Morgan’s theorems for 2-variables
4(b) CO1 Simplify the following Boolean functions by means of a 4 variable 05 K4
map F(A,B,C,D)=∑m(0,2,4,5,8,10,14,15)
4(c) Implement the following Boolean function only with NAND gates, 04 K6
using a
minimum number of gate inputs F(A,B,C,D)=AB+CD
5 CO1 Simplify the Boolean function in Sum of Products(SOP) and Product 13 K4
of Sum(POS) F(w,x,y,z)=∑m(0,1,2,5,8,9,10).

6(a) Express the following function in sum of min-terms and product of 06 K5

max-
CO1 terms : F(X,Y,Z)=X+YZ.
6(b) Find the Min term expansion off(a,b,c,d)= a ' (b'+d)+acd' 07 K3

7 CO1 Write short notes on Demorgans theorem, Absorption law and 13 K1

consensus
law.
8 CO1 Minimize the following function using Karnaugh map F(A,B,C,D) = 13 K6
∑m(0,1,2,3,4,5,6,11,12,13)
9 CO1 Minimize the expression using K-map and Quine Mc-cluskey method 13 K6
Y= A’BC’D + A’BC’D+ABC’D’+ABC’D’+AB’C’D+A’B’CD’
10(a) Convert the following numbers in to decimal: (11011.101) 2, (5432)8 04 K2
10(b) Perform the following arithmetic operation using 2’s complement 03 K5
CO1 arithmetic: (11011100)2-(10011011)2
10(c) Express the following functions in sum of minterms and product of 06 K5
maxterms : F(ABCD)=A’B+BD+AC’
11 CO1 Explain the rules for Binary Addition and Subtraction using 1's & 2’s 13 K2
complement. Give examples.
12 CO1 Explain about common postulates used to formulate various algebraic 13 K2
structures.
13 Simplify the Boolean function F(A,B,C,D) = Σ m (1,3,7,11,15) + Σ d 13
CO1 (0,2,5) .If don't care conditions are not taken care, What is the simplified K4
Boolean function .What are your comments on it?

14(a) Explain the procedure for obtaining NOR- NOR circuit for any AND- 06 K5
CO1 OR network with a suitable example.
14(b) Simplify the given Boolean function in POS form using k-map and 07 K4
draw the logic diagram using NOR gates.
F(A,B,C,D) =ΠM(0,1,4,7,8,10,12,15)+d(2,6,11,14)
15 (a) CO1 Draw the multiple level NAND circuity for the following expressions 07
w(x+y+z)+xyz . K1
15(b) What are the advantages of tabulation method over K-Map method 06
16 (a) CO1 Show that the dual of the Exclusive-OR is also its complement 08 K2

16(b) What are simultaneous functions? Why simultaneous functions are used in 05 K1
digital systems?

17 CO1 Implement the following boolean function F Using the two level forms of 13 K6
logic a)NAND-AND b)AND-OR
F(a,b,c,d)= Σ m(0,4,8,9,10,11,12,14)
18 CO1 Implement the following boolean function F Using the two level forms of 13 K6
logic a)OR-NAND b)NOR-OR
F(a,b,c,d)= Σ m(0,4,8,9,10,11,12,14)

19 CO1 Simplify the Boolean functions: 13 k4

a)F(a,b,c,d)= ΠM (1,3,5,7,13,15)
b)F(a,b,c,d)= ΠM (1,3,6,9,11,12,14)
20 CO1 Implement the following boolean function F, together with the don’t -care 13 k6
conditions d,using two NOR gates
f(a,b,c,d)=Σ m(2,4,10,12,14)
d(a,b,c,d)= Σ m (0,1,5,8)
21 CO1 Find the dual and complement of the following boolean expression 08 K1
F(X,Y,Z)=X’YZ+X’YZ’+XY’Z’+XY’Z
K3
Draw the output of the 3 input XOR Gate .With the given inputs A,B,C 05
22 CO1 Implement the following boolean function with Exclusive OR and AND K6
Gate 13
F=AB’CD’+A’BCD’+AB’C’D+A’BC’D
23 CO1 Draw the logic diagram using only 2 input NOR Gate to implement the 13 K3
following functions
F(A,B,C,D)=(A XOR B)’(C XOR D)
24 CO1 Simplify the logic expression using boolean algebra and draw the logic 13 k4
circuit for f= Σ m(0,12,6,10,11)
25 CO1 Simplify the logic function 13 k4
F(a,b,c,d)=ΠM (3,5,6,11,13,14,15)+d(4,9,10) using K-Map in SOP and
POS form

PART -C
Q.no Question Mark KL
CO

1 Define prime implicate and essential prime implicate. 04 K1

CO1 Minimize the expression using Quine Mc Cluskey method 11 K5
F=∑m(0,1,9,15,24,29,30) + ∑d(8,11,31)
2 Express the following function in a simplified manner using K map 15 K6
CO1 technique
(i) G=πM(0,1,3,7,9,11).
(ii) f(W,X,Y,Z)=∑m(0,7,8,9,10,12) + ∑d(2,5,13).
3 Simplify the following function using five variable map: 15 K5
CO1 F(A,B,C,D,E)=A’B’CE’+B’C’D’E’+A’B’D’+B’C’D’+A’CD+A’BD
 4 Simplify the following expression 15 K5
CO1 Y= m1+m3+m4+m7+m8+m9+m10+m11+m12+m14
using Quine Mc Cluskey method & K map technique
5 Reduce the expression using tabulation method F(X1,X2,X3,X4,X5) = 15 K6
CO1 ∑m(0,2,4,5,6,7,8,10,14,17,18,21,29,31) + ∑d(11,20,22)

6 Minimise the following function using K-Map F(X1,X2,X3,X4,X5) 15 K6

CO1 =∑m(1,2,3,5,6,10,11,15,18,19,20,21,22,23,25,26,27,31) + ∑d(4,7,30)

UNIT-II COMBINATIONAL CIRCUIT DESIGN

PART-A

Q.no CO Question Marks/Rubrics KL

1 CO2 What is combinational circuit ? Give example. 2 KL1

2 CO2 Write the design procedure for combinational circuits. 2 KL1

3 CO2 Give the truth table and logic diagram for Half adder. 2 KL1

4 CO2 Which adder is used for single bit addition ?Explain 2 KL1
5 CO2 Sketch the logic diagram and truth table for Full adder circuit. 2 KL1

6 CO2 Construct 4-bit parallel adder using Full adders . 2 KL3

7 CO2 Design the logic circuit of Half subtractor using truth table. 2 KL5

8 CO2 Draw the logic diagram and give the truth table for full subtractor. 2 KL1

9 CO2 Relate carry generate, carry propagate, sum and carry-out of a 2 KL1
carry look ahead adder.
10 CO2 How does priority encoder differs from ordinary encoder. 2 KL1
11 CO2 How many select lines will a 32:1 multiplexer will have 2 KL1
12 CO2 Convert a two-to-four line decoder with enable input to 1:4 2 KL1
demultiplexer.
13 CO2 Give other name for Multiplexer and Demultiplexer. 2 KL1
14 CO2 What is a data selector? 2 KL1

15 CO2 What is Demultiplexer? 2 KL1

16 CO2 State the characteristic equation of 4 × 1 multiplexer. 2 KL1

17 CO2 List out various application of Multiplexer 2 KL1
18 CO2 Develop the following function using suitable multiplexer F= 2 KL3
Σm(0,2,5,7).
19 CO2 Draw the logic diagram of a 4 line to 1 line Multiplexer. 2 KL1

20 CO2 What do you mean by comparator 2 KL1

21 CO2 Evaluate the logic circuit of a 2 bit comparator 2 KL5

22 CO2 Examine a single bit magnitude comparator to compare two words 2 KL4
A and B.
23 CO2 Distinguish between demultiplexer and decoder. 2 KL4

24 CO2 What is the function of decoders enable input? 2 KL1

25 CO2 What do you mean by a decoder?explain it with block diagram. 2 KL1

26 CO2 What do you mean by encoder? 2 KL1

27 CO2 Compare the function of decoder and encoder. 2 KL4

28 CO2 Can more than one decoder output be activated at one time?Justify 2 KL5
your answer
29 CO2 Give the truth table for 4 bit priority encoder. 2 KL1

30 CO2 Draw a combinational logic circuit which can compare whether 2 KL1
two bit binary numbers are same or not.
31 CO2 Mention the uses of decoders. Or Application of decoder. 2 KL1

32 CO2 The following switching functions are to be implemented using a 2 KL6

Decoder: f1=∑ m( 8, 4, 2, 1, 10,14 ) f2 = ∑ m ( 11 9, 5, 2, )f3= ∑
m ( 7, 6, 5, 4, 2). How many line decoders to be used.
33 CO2 The output Y of a 2-bit comparator is logic 1 whenever the 2-bit 2 KL4
input A is greater than the 2-bit input B. For how many number of
combinations the output is logic 1?
34 CO2 List out the types of Modelling available in HDL program. 2 KL1

35 CO2 Write the HDL program for the An Half adder 2 KL1

36 CO2 Give the HDL Program for the full subtractor. 2 KL1

37 CO2 What is the purpose of cascading inputs of 7485 2 KL1

38 CO2 List out the advantages of carry lookahead adder. 2 KL1

39 CO2 Explain Data flow, structural, behavioral modelling. 2 KL1

40 CO2 An 8X1 Mux has inputs A,B,C and connected to the selection 2 KL5
lines s2, s1, s0 repectively. The data inputs I0 through I7 are
I1=I2=I7=0; I3=I5=1;I0=I4=D and I6=D'. Determine the Boolean
funtion.
41 CO2 Draw the logic diagram of 1X4 data distributor 2 KL1

42 CO2 List out the applications of decoders 2 KL1

43 CO2 Draw the logic diagram of 3to 8 decoder 2 KL1

44 CO2 Show how full adder can be converted into full subtrator using 2 KL4
inveter circuit.
45 CO2 Which one is called the basic building block of arithmetic unit. 2 KL1
list out its types.
46 CO2 What are all the 2 types of digital logic circuits available? 2 KL1

47 CO2 What is priority Encoder? 2 KL1

48 CO2 Suggest a solution to overcome the limitation on the speed of an 2 KL4

adder.
49 CO2 Write the HDL program for the 2:1 MUX 2 KL1

50 CO2 Write the HDL program for the an one bit magnitude comparator 2 KL1

PART-B

Q.no CO Question Mark KL

1 CO2 (i)How will you design a full adder using two half adders and an OR 13 KL1&
gate. (6) KL5
(ii) write the verilog HDL cod for full adder using Structural
modelling.(7)
2 CO2 (i)Design a 4-bit decimal adder using 4-bit binary adders. 13 KL5
(7) &KL4
(ii)Simplify the function using multiplexer F=Σm(1,3,4,8,9,15)
(6)
3 CO2 (i)Construct full subtractor using Demultiplexer. (5) 13 KL5&KL1
(ii) Draw 4 × 1 multiplexer and 1 × 4 demultiplexer using gates and
explain its operation. (8)
4 CO2 Develop a combinational circuit that converts 4 bit Gray Code to a 4 13 KL5
bit binary number. Implement the circuit. &KL1

5 CO2 (i) How would you design a 3:8 decoder using basic gates?(7) 13 KL5
(ii)Implement the following function using 8 to 1 multiplexer Y( A ,B &KL5
,C D) = ∑ ( 11,9,5,2,1,0, 13, 15, ) (6)
6 CO2 Using 8 to 1 multiplexer, realize the Boolean functionT = f(w, x, y, z) 13 KL4
= Σ(0,1,2,4,5,7,8,9,12,13)
7 CO2 (i)What is a decoder? Draw the logic circuit of a 3 line to 8 line 13 KL2
decoder and explain its working. (6)
(ii)What is parallel adder? Draw and explain block diagram for 4 bit
parallel adder.(7)
8 CO2 (i)What is a Multiplexer Tree? Why is it needed? Draw the block 13 KL3
diagram of a 32:1 Multiplexer Tree and explain how input is directed
to the output in this system.(Hint:largest available MUX IC is 16 to
1)(7)
(ii)Explain the operation of octal to binary encoder. (6)
9 CO2 (i)How will you form an 8 bit adder using 2 four bit adder IC’s 7483? 13 KL1 &
Explain with diagram.(7) KL5
(ii)Design a logic circuit that has three inputs, A, B, and C, and whose
output will be HIGH only when a majority of the inputs are HIGH.(6)

10 CO2 (i) Analyze the design of 8 x 1 multiplexer using only 2 x 1 13 KL4&KL5

multiplexer. (7)
(ii) Formulate the following Boolean function using 4 x 1
multiplexers.
F (A ,B,C,D) = (1,2,3,6,7,8,11,12,14) .(6)
11 CO2 (i)A certain logic circuit has four inputs A, B, C, and D. The output X 13 KL5
of the circuit is logic 1 if two or more inputs are logic 1.Implement
using logic gates.(6)
(ii) Realize F(w, x, y, z)= Σ (1,4,6,7,8,9,10,11,15) using 8 to 1
Multiplexer.(7)
12 CO2 (i) Develop a Full adder using decoder.(5) 13 KL5
(ii) Deduce the design of a 1:8 demultiplexer circuit.(6)

13 CO2 (i)Explain the working and draw the logic diagram of Binary to Octal 13 KL2
decoder. (6)
(ii) How to construct a 8:1 MUX from two 4:1 MUX and OR gate(7)
14 CO2 (i)Demonstrate 4-bit magnitude comparator with three outputs:A>B, 13 KL3
A=B and A<B.(7)
(ii) Build a 4-bit Priority Encoder circuit using gates.(6)

15 CO2 Create the HDL program for 2:4 decoder &full adder 13 KL5

16 CO2 (i)Design 4 bit Magnitude comparator and draw the logic circuit.(7) 13 KL5&
(ii)What is a digital comparator. Explain the working of a 2-bit KL2
digital comparator with the help of Truth Table(6)

17 CO2 (i)Construct 4X16 decoder with two 3X8 decoder (7) 13 KL5
(ii)Write the HDL program for 4X16 decoder using Data flow
model(6)
18 CO2 (i)Design 32:1 MUX using two 16:1mux(8) 13 KL5
(ii)Implement the boolean funtion with 4X1MUX and external gates
F(A,B,C,D)= Σ (1,3,4,11,12,13,14,15)(5)
19 CO2 Design a logic circuit that has three inputs and one output. The output 13 KL5
is 1 when the binary value of the input is less than 3.The output is 0
otherwise
 20 CO2 (i)Implement full adder with two 4X1 MUX (7) 13 KL5
(ii)Design Decimal to BCD encoder(6)
21 CO2 Design BCD to7segment display decoder. 13 KL5

22 CO2 Construct 4 bit binary parallel adder/subtractor and explain .also 13 KL5
implement this using IC7483
23 CO2 (i)Design a 2 bit magnitude comparator. 13 KL5
(ii)write the HDL program for the same
24 CO2 How is carry look ahead adder faster than a ripple carry adder? 13 KL2
Explain in detail with neat sketches.
25 CO2 Develop the HDL program of decimal adder in structural modeling. 13 KL5

PART -C
Q.no Question Mark KL
1 CO2 Implement the following Boolean function using an 8:1 multiplexer 15 KL5
considering D as the input and A,B,C as selection lines :
F( A, B, C, D) = AB’+BD+B’CD’
2 CO2 With necessary diagrams, explain in detail about the working of a 15 KL3
4-bit look ahead carry adder. Also mention its advantages over
conventional adder.(15)
3 CO2 Design a circuit that converts 4 bit gray number to binary number and 15 KL5
implement the same with EX-OR gate
4 CO2 Write the HDL gate level description of priority encoder and explain 15 KL5
with the logic diagram
5 CO2 Design A Full Adder And A Full Subtractor and write the HDL 15 KL5
program for it.
6 CO2 Implement the boolean function using 8 to 1 Multiplexer 15 KL5
F( A, B, C, D) = A’BD’+ACD+B’CD+A’C’D.Also implement the
function using 16 to 1 multiplexer

UNIT-III SYNCHRONOUS SEQUENTIAL CIRCUITS

PART-A

Q.no CO Question Marks/Rubrics KL

1 CO3 Summarize the characteristic table and equation of JK flip flop. 2 K2

2 CO3 Write any two application of shift register. 2 K2
3 CO3 With reference to a JK flip flop what is racing? 2 K1
4 CO3 Identify how many JK- flip-flops are required to design a MOD 35 2 K3
counter?
5 CO3 What are the significances of state assignment? 2 K1
6 CO3 How many states are there in a 3-bit ring counter? what are they? 2 K5

7 CO3 Give block diagram of Master -Slave D Flip flop 2 K1

8 CO3 Draw the diagram of T- Flip flop and discuss its working. 2 K3
9 CO3 Classify the shift registers. 2 K4
10 CO3 Analyze how many flip-flops are required to design a synchronous 2 K4
MOD 60 counter?
11 CO3 Develop the HDL code to realize a D - flip flop 2 K6
12 CO3 Define state table 2 K1
13 CO3 Realize a JK flip flop using D flip flop. 2 K3
14 CO3 Write down the steps involved in the design of synchronous 2 K2
sequential circuits.
15 CO3 Recall the Characteristics equation of JK-flip flop 2 K1
16 CO3 Write the difference between synchronous and asynchronous 2 K5
sequential circuit.
17 CO3 Differentiate between latch and flip flop. 2 K4
18 CO3 Define Ripple counter 2 K1
19 CO3 What is meant by edge triggered flip flops?.List any two mechanisms 2 K2
to achieve edge triggering of flip flop
20 CO3 Design a 4 bit binary synchronous counter with D flip flops. 2 K6
21 CO3 Explain the difference between the performance of asynchronous and K2
synchronous counter 2
22 CO3 Draw the block diagram of a 4 bit serial in serial out right shift 2 K1
register.
23 CO3 What is Ring counter? 2 K1
24 CO3 State the rules for state assignment. 2 K1
25 CO3 State the excitation table of JK-flip flop 2 K1
26 CO3 Draw the logic diagram and write the function table of D Latch. 2 K1
27 CO3 What is shift register ? 2 K1

28 CO3 How many clock pulses are required to completely load serially a 8- 2 K2
bit shift register?
29 CO3 Why stepper motors are very popular in digital systems? 2 K1

30 CO3 Write the counting sequence of a 3-bit ripple counter. 2 K2

31 CO3 What happens to a 4 –bit Parallel-In, Serial-Out shift register when 2 K2

recirculating lines are added?
32 CO3 Compare moore and melay model. 2 K2

33 CO3 What is lockout? How it is avoided? 2 K1

34 CO3 What will be the state of JK flipflop in the following cases 2 K1

a) J=K=1, Qn=0 b) J=0,K=1,Clear low
35 CO3 What is buffer register? 2 K1

36 CO3 What is Universal Shift register? 2 K1

37 CO3 Define Bidirectional shift register. 2 K1

38 CO3 List out the applications of shift register. 2 k2

39 CO3 What is the difference between serial and parallel transfer? What type 2 k1
of register is used in each case?
40 CO3 If a SISO shift register has N stages and if the clock frequency is f, 2 k3
what will be the time delay between input and output?
41 CO3 Difference between edge triggering and level triggering. 2 k1

42 CO3 Define counters. 2 k1

43 CO3 How many states are there in a 3-bit ring counter? What are they? 2 K1

44 CO3 What is Twisted ring counter? 2 K1

45 CO3 How many flip-flops are needed to build an 8-bit shift register? 2 k1

46 CO3 Define MOD counter. 2 k1

47 CO3 Why T flip-flop is called as a Toggle switch? 2 k1

48 CO3 Draw the state diagram of MOD 10 counter. 2 K2

49 CO3 Assume that the 5-bit binary counter starts in the 00000 state. What 2 k4
will be the count after 144 input pulses?
50 CO3 When the counter is called as Synchronous counter? 2 k1
 PART-B

Q.no CO Question Mark KL

1 CO3 Implement T flip-flop using D flip-flop and JK using D flip flop. 13 K5

2 CO3 Design a synchronous counter with the following sequence: 0,1,3,7,6,4 13 K6

and repeats. Use JK Flip flop.
3 CO3 Design a MOD-10 Synchronous counter using JK flip-flop. Write 13 K6
execution table and state table.
4(a) How a race condition can be avoided in a flip-flop? 04 K1
4(b) State the problem faced by ripple counter. 05 K1
4(c) CO3 Draw the logic diagram for a 3 stage asynchronous counter with 04 K2
negative edge triggered flip-flop.
5 CO3 Write the HDL description of T flip-flop, JK flip-flop ,SR flip flop and 13 K2
D flipflops.
6(a) Describe the operations of R-S flip-flop with a neat sketch 05 K5

6(b) Design a sequential circuit with two D flip flops A and B and one 08 K6
CO3
input When X=0 the state of the circuit remains the same. When X=1
the circuit goes through the state transitions from 00 to 10 to 11 to 01,
back to 00 and then repeats.
7 CO3 Illustrate a serial adder using a full adder and a flip flop. 13 K5

8 CO3 Explain the operation of master slave flip flop and show how the race 13 K5
around condition is eliminated in it
9 CO3 Design and implementation of SR Flip Flop using NOR gate. 13 K6

10(a) Outline the procedure for analyzing asynchronous sequential circuit 06 K1

10(b) Write the VHDL code for a 4 bit binary up counter and explain 07 K2
CO3

11 CO3 Design the sequential circuit specified by the following state diagram 13 K6
using T flip flops

12 CO3 Explain the different types of shift registers with neat diagram. 13 K2

13 CO3 With logic diagram explain the universal shift register as a storage 13
device K2
14(a) Write the design procedure for a 3-bit synchronous up counter using JK / 06 K2
T- flip flop and draw the diagram
CO3
14(b) Write the design procedure for 3 bit parallel- in serial-out shift register 07 K2
and write the HDL code to realize it.
15 (a) CO3 Analyse the difference between a state table, characteristic table and an 06
excitation table. K4

15(b) Write the HDL code for up-down counter using behavioural model. 07 K3
16 (a) CO3 Explain the operations of a 4 bit bidirectional shift register 06 K4

16(b)
Design and explain the working of an UP-Down ripple counter. 07 K6
17 CO3 Design a sequence detector to detect the input sequence 101 13 K6
(overlapping). Use JK Flip flops.
18 CO3 Draw the block diagram of Johnson counter and explain. 13 K2
 19 CO3 Consider the design of a 4 bit BCD counter that counts in the following 13 K3
way: 0000 , 0010 , 0011 , ………. , 1001 , and back to 0000.
(i) Draw the state diagram.
(ii) List the next state table.
(iii) Draw the logic diagram of the circuit.
20 CO3 Carry out the following conversions. 13 K5
a) JK to D b) JK to T c) SR to T
21 CO3 Draw the output waveform of clocked T flip-flop for the given inputs 13 K2

22 CO3 Explain the types of modeling using examples from any sequential K2
circuits. 13
23 CO3 Design BCD ripple counter using JK flip-flop. 13 K6

24 CO3 Write and verify a Verilog behavioral model of a 3-bit counter that counts 13 k4
the sequence 0,2,4,6,0,…
25 CO3 Design a synchronous counter for 13 K6
4->6->7->3->1->4 ….
Avoid lockout condition. Use JK type design.

PART –C
Q.no Question Mark KL
CO

1 CO3 Analyze and design a sequential circuit with two T Flip flop A and B, one 15 K5
input x and one output z is specified by the following next state and output
equation is A(t+1)= BX’+B’X; B(t+1)=AB+BX+AX; Z=AX’+A’B’X
(i)Draw the logic diagram of the circuit.
(ii) List the state table for the sequential circuit
(iii) Draw the Corresponding state diagram.
2 CO3 Design a synchronous counter which counts in the sequence 15 K6
000,001,010,011,100,101,110,111,000 using D flip-flop.
3 CO3 Design a decade counter using JK Flip-Flop. 15 K6
4 CO3 A sequential circuit with two D flip-flops A and B, one input x , and 15 K5
one output z is specified by the following next state and output
equations: A(t+1) = A'+B, B(t+1)=B'X, Z =A+B'
(i)Draw the logic diagram of the circuit.
(ii)Derive the state table.
(iii)Draw the state diagram of the circuit.
5 CO3 A sequential circuit with two D flip flops A and B two inputs X and Y 15 K6
and the output Z is specified by the following input equations.:
A(t+1)=X’Y+XA; B(t+1)=X’B+XA; X=B
(i) Draw the logic diagram of the circuit.
(ii) Derive the state table and state diagram and state whether it is a
Mealy or a Moore Machine
6 CO3 Design sequence detector that detects a sequence of three or more 15 K6
consecutive 1’s in a string of bits coming through an input line and
produces an output whenever this sequence is detected.