8051

INTERRUPTS

MC & ES CLASS 09 – 25th August September 2023

 INTERRUPT VS POLLING
Single microcontroller serve several devices at a time
Two methods: Interrupt vs polling
In interrupt when any device needs microcontroller service, device sends a
signal to microcontroller
Program associate with interrupt is known as Interrupt Service Routine
(ISR)/Interrupt handler
In polling, microcontroller continuously monitors the device, when
required it performs the service
Several advantage are involved with Interrupts.
 INTRODUCTION TO
INTERRUPTS
The most powerful and important features are interrupts in 
8051 microcontroller.
In most of the real-time processes, to handle certain conditions properly,
the actual task must be halt for some time – it takes required action – and
then must return to the main task.
Interrupts in 8051 microcontroller are more desirable to reduce the regular
status checking of the interfaced devices or inbuilt devices.
Interrupt is an event that temporarily suspends the main program, passes
the control to a special code section, executes the event-related function
and resumes the main program flow where it had left off.
 INTRODUCTION
Interrupt may be generated by internal chip operations or provided by external
sources.
Any interrupt can cause 8051 to perform a hardware call to an interrupt
handling subroutine that is located at a predetermined absolute address in
program memory.
Five interrupts are provided in 8051.
Three of these are generated automatically by internal operations.
Two interrupts are triggered by external signals connected to INT0 and INT1
pins
All interrupt functions are under control of program.
The programmer is able to alter control bits in the
Interrupt Enable register (IE), the interrupt priority
register(IP) and Timer Control register (TCON).
The programmer can block all or any combination of
the interrupts from acting on the program by suitably
setting or clearing bits in these registers.
After the Interrupt has been handled by interrupt subroutine, the
interrupted program must resume operation at the instruction where
the interrupt took place.
Program resumption is done by storing the interrupted PC address on
stack in RAM before changing the PC to the interrupt address in
ROM.
The PC address will be restored from the stack after an RET1
instruction is executed at the end of the interrupt subroutine.
TYPES OF INTERRUPTS IN 8051 MICROCONTROLLER

The 8051 microcontroller can recognize five different events that cause
the main program to interrupt from the normal execution. These five
sources of interrupts in 8051are:
Timer 0 overflow interrupt- TF0
Timer 1 overflow interrupt- TF1
External hardware interrupt- INT0
External hardware interrupt- INT1
Serial communication interrupt- RI/TI
 TIMER INTERRUPTS
When a timer/counter overflows, the
corresponding Timer flag ,TFO or TF1 is set to 1.

The flag is cleared to 0 when the resulting interrupt

generates a program call to the appropriate timer
subroutine in memory.
 SERIAL PORT INTERRUPTS
If a data byte is received , an interrupt bit, RI is set to 1 in the SCON
register.
Similarly after transmission TI is set to 1.
These are ORed together to provide single interrupt to the processor,
which is called as serial port single interrupter.
These bits are not cleared when the interrupt generated program call is
made by the processor
The program that handles serial data communication must rest RI/TI to
0,so that next byte can be transmitted or received.
 EXTERNAL INTERRUPTS
INTO INT1 external interrupt pins
Interrupts on these pins can set IEO and IE1 interrupts
in TCON register to 1 by two different methods
One Method: INTX pin reaches low level
Second Method: High to low transition on INTX pins
Go Back to ITO & IT1 in TCON: these two options are
visible.
 RESET
The RESET button you are pressing in any microcontroller kit is the
interrupt.
This is non maskable interrupt or not to be blocked.
No combination of bits in any register can stop or mask the reset action.
Unlike other interrupts, where PC is stored for program resumption,
It is an absolute command to jump to program address ooh and commence
running from this address.
Whenever a high level is applied to the RST pin, the 8051 enters a reset
condition.
INTERRUPT ENABLE
REGISTER
 EA- global interrupt enable/disable:
0 - disables all interrupt requests.
1 - enables all individual interrupt requests.

ES - enables or disables serial interrupt:

0 - UART system cannot generate an interrupt.
1 - UART system enables an interrupt.

ET1 - bit enables or disables Timer 1 interrupt:

0 - Timer 1 cannot generate an interrupt.
1 - Timer 1 enables an interrupt.

EX1 - bit enables or disables external 1 interrupt:

0 - change of the pin INT0 logic state cannot generate an interrupt.
1 - enables an external interrupt on the pin INT0 state change.

ETO and EXO are similar to ET1 & EX1 but operate for 0 counter part.
INTERRUPT PRIORITY

Interrupt priority after Reset:

Priority Type of interruptior Interrupt source Intr. bit / flag

1 External Interrupt 0 INT0

2 Timer Interrupt 0 TF0

3 External Interrupt 1 INT1

4 Timer Interrupt 1 TF1

5 Serial interrupt (TI/RI)

IF YOU WANT TO CHANGE
THIS PRIORITY
This is by default Priority
Then Interrupt Priority Register will help you to
change this priority
INTERRUPT PRIORITY
REGISITER
• PS- Serial Port Interrupt priority bit
Low Priority 0
High Priority 1

PT1 - Timer 1 interrupt priority

Low Priority 0
High Priority 1

PX1 - External Interrupt INT1 priority

Low Priority 0
High Priority 1

PT0 - Timer 0 Interrupt Priority

Low Priority 0
High Priority 1

PX0 - External Interrupt INT0 Priority

INTERRUPT PRIORITY
If two interrupt requests of equal priority arrive at the same time
then the interrupt to be serviced is selected according to the
following priority list:
External interrupt IE0
Timer 0 interrupt TFO
External Interrupt IE1
Timer 1 interrupt TF1
Serial Communication Interrupt RI or TI
INTERRUPT CONTROL
All interrupts are under the control of
programmer. At any time he can enable or
disable one or two or any combination of
interrupts .

Bit EA in IE register can enable or disable all

five interrupts.
The Timer and Serial interrupts are internally generated by the
microcontroller, whereas the external interrupts are generated by
additional interfacing devices or switches that are externally
connected to the microcontroller. These external interrupts can be
edge triggered or level triggered.
When an interrupt occurs, the microcontroller executes the
interrupt service routine so that memory location corresponds to
the interrupt that enables it. The Interrupt corresponding to the
memory location is given in the interrupt vector table below.
INTERRUPT DESTINATIONS
MC&ES DATA MOVEMENT
INSTRUCTIONS
DATA MOVEMENT
INSTRUCTIONS
MOV destination, source

PUSH source ,pop destination

XCH destination source

Immediate addressing mode
Register Addressing Mode
Direct Addressing Mode
Indirect Addressing Mode
SOURCES OF DATA TRANSFER

Internal RAM
External RAM
Internal special function Registers
Internal & External ROM
 FINALLY
MOV MOVX MOVC
PUSH&POP
XCH
28 DIFFERENT MNEMONICS
COPY THE DATA
3 MAIN TYPES
 1.IMMEDIATE DATA METHOD
MOV A,#25H // load 25H in to A
MOV R7,#07H // load the decimal value 07Hinto R7
MOV R4,#62 // load the decimal value 62 into R4.
MOV A,#0AAH : zero before A
MOV DPTR,#4532H // DPTR=4532H
CAUTION
NO IMMEDIATE DATA AS DESTINATION

NUMBERS MUST START WITH DECIMAL NUMBER

Register to Register moves using the register addressing
mode occurs between registers A & R0 to R7.
2.REGISTER ADDRESSING
MODES
MOV A,Rr MOV A,RO
MOV Rr,A MOV R5,A
A, DPTR, R0 TO R7 REGISTERS USED
OTHER REGISTERS SFRs DIRECT ADDRESSING MODE
CAUTION:
R-R MOVE USING REGISTER ADDRESSING BETWEEN
A &RO-R7
3.DIRECT ADDRESSING MODE
128 BYTES OF RAM
SFRS
BY USING SINGLE BYTE ADDRESS OF RAM &
SFRS
RAM 00 TO 7FH
SFRS 80 TO FF H
MOV A, add
MOV add, A
MOV Rr, add
MOV add , #n
MOV add1,add2
MOV A,80h port 0 to A MOV 80h,A
MOV 3Ah,#3Ah
MOV R0,12h
MOV 8Ch,R7 timer 0 higher byte
MOV 5Ch, A
MOV 0A8h,77H 77 to IE register
 CAUTIONS
Above 7F USE only SFR available locations not
to use all 80-FF
Moving data to port changes the port latch,
moving data from port gets from port pints
self memory to memory address errors
4.INDIRECT
Register to hold actual address
RO,R1 &DATA POINTER
MOV @Rp,#n MOV@ Rp, add MOV@Rp , A
MOV A,@RO MOV ADD,@RO MOV@R1,A
MOV@RO,80H
MOV@R1,A,MOV@R0,80h,MOVadd,@Ro
MOV@R1,#35h
The number in Register Rp must be a RAM
Address
Only Register R0 & R1 are permitted in this
indirect
EXTERNAL DATA
MOVES/MOVX,MOVC
X STANDS FOR EXTERNAL DATA MOVEMENT
MOVX A,@R1:COPY FROM EXTERNAL
MEMORY LOCATION TO A
MOV@DPTR,A ; FROM A TO EXTERNAL
LOCATION
MOVX @RO,A
MOVXA,@DPTR
CAUTION
All External MUST INVOLVE A REGISTER
DPTR Can Address 64k
Register Can Address 256 Bytes
Normally Used With External RAM Or I/O Address
O0 to FF Two Types Of RAM Internal & External
CODE MEMORY READ ONLY
MOVC,A@A+DPTR:
CODE BYTE AVAILABLE AT A & DPTR
MOVC A,@A+PC
MOV DPTR,#1234h
MOV A,#56H
MOVC A,@A+DPTR 128Ah into A
CAUTION
All data is moved from code memory to A
Normally used with internal or external
ROM 4K/64K