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07 ISA Part 03 Conditional Executions
07 ISA Part 03 Conditional Executions
• For an addition, C is set to 1 if the addition produced a carry (that is, an unsigned
overflow), and to 0 otherwise.
• For a subtraction, including the comparison instruction CMP, C is set to 0 if the
subtraction produced a borrow (that is, an unsigned underflow), and to 1
otherwise.
• For non-additions/subtractions that incorporate a shift operation, C is set to the
last bit shifted out of the value by the shifter.
• For other non-additions/subtractions, C is normally left unchanged.
Detailed Format :
Detailed Format :
Question :
• What will be the result :
• ADD R1, R2, R2, LSL #3
• RSB R3, R3, R3, LSL #3
• RSB R3, R2, R2, LSL #4
• SUB R0, R0, R0, LSL #2
• RSB R2, R1, #0
Solution :
• What will be the result :
• ADD R1, R2, R2, LSL #3 R1 = R2 + 8 R2
• RSB R3, R3, R3, LSL #3 R3 = 8R3 – R3
• RSB R3, R2, R2, LSL #4 R3 = 16R2 – R2
• SUB R0, R0, R0, LSL #2 R0 = R0 – 4R0
• RSB R2, R1, #0 R2 = 0 – R1
Q. Write a small assembly program for ARM, required that 2 numbers stored in
R1 and R2 registers, the bigger num is to be placed in R10, if 2 num are equal
Put it in R9.
Q. Write a small assembly program for ARM, required that 2 numbers stored in
R1 and R2 registers, the bigger num is to be placed in R10, if 2 num are equal
Put it in R9.
;MOV R10, R2
If C Z
R3>R4 1 0
R3<R4 0 0
R3=R4 1 1
TST Instruction
• TST is similar to compare, but it does ANDing and then sets
conditional flags.
• If the result of ANDing is zero, then zero flag is set.
• It can be used to verify at least one of the bits of a data word
is set or not.
• Write instruction to verify the LSB of a word in register R1 is
set or not.
• TEQ R1,#45