RT-LEVEL COMBINATIONAL

CIRCUIT
Prepared by :Mariyum Jamshid
 Design Methodology
• Top down
• Bottom up
• In general a hybrid of the two is used
 Top Down Design Methodology
• We define the top level blocks and identify the
sub blocks necessary to build the top level
block.
• We further sub divided the sub-blocks until we
come to leaf cells which are the cells that
cannot further be divided.
Top Down Design Methodology
 Top Down Design Methodology
• In other words
• Define the final (top level) module
• Analyze the components which are composed
of top module step by step
 Bottom Up Design Methodology
• We first identify the building blocks that are
available to use
• We build bigger cells using these building
blocks
• These cells are then used for higher level
blocks until we build the top level block in the
design
Bottom Up Design Methodology
 Bottom Up Design Methodology
• In other words,
• Design the basic components
• Assemble basic components to larger design
until the top design is completed
 Design Methodology Example

• Ripple Carry Counter:

• Made up of negative edge triggered toggle flip
flops(T-FF)
• Each of the T-FF can be made up of from
negative edge triggered D-FF and inverter.
 Design Methodology Example
Ripple Carry Counter
 4-bit carry ripple counter design block

// Define the top-level module called ripple carry counter.

//It instantiates 4 Toggle flipflops
module ripplecounter (clk,rst,q);
Input clk, rst;
output [3:0]q;
// initiate 4 T-FF to update the count
tff tf1(q[0],clk,rst);
tff tf2(q[1],q[0],rst);
tff tf3(q[2],q[1],rst);
tff tf4(q[3],q[2],rst);
endmodule
 Toggle FlipFlop Module
module tff(q,clk,rst);
// tff takes clk and reset as input
// q is output
input clk,rst;
output q;
wire d;
// by referring the diagram of tff,
// instantiate d flip flop and not gate
dff df1(q,d,clk,rst);
not n1(d,q);
endmodule
 Data FlipFlop module
module dff(q,d,clk,rst);
input d,clk,rst;
output q;
reg q;
// store the output value
always @(posedge clk or posedge rst)
begin
// refer the truth table to provide
// values to q based on reset.
if(rst) q=1'b0; //When rst is high, it resets the counter to 0
else q=d;
end
endmodule
4-bit carry ripple counter simulation block
module tb;
// input to be stored in reg and output as net(wire)
reg clk;
reg rst;
wire [3:0]q;
// instantiate the ripplecounter design block
ripplecounter dut(clk,rst,q);
// generate clock pulse
// initially provide 0
// then inside always block toggle
// clock every 5 time units
initial
clk = 0;
always
#5 clk = ~clk;
// provide reset values as the input
initial
begin
rst = 1;
#15 rst = 0;
#180 rst = 1;
#10 rst = 1;
#20 $finish;
end
initial
$monitor("time=%g,rst=%b,clk=%b,q=%d",$time,rst,clk,q); endmodule
 Gate Level Modeling
• We can define our design in terms of logic
gates, i.e. and, or, xor, nand, nor, xnor and not
• Requires explicit knowledge of gates
connection
• Difficult to debug
• Almost impossible for large designs
 2:1 MUX Example
module muxgate (a, b, out, outbar, sel);
input a, b, sel;
output out, outbar;
wire out1, out2, selb;
and a1 (out1, a, sel);
not i1 (selb, sel);
and a2 (out2, b , selb);
or o1 (out, out1, out2);
not i2 (outbar,out);
endmodule
4:1 MUX Example
Test bench for 4:1 MUX
IN0

IN1
OUTPUT
IN2

IN3

S1
S0
Test bench
/* $display is a system task to display expressions, values and
strings (similar to printf in C),
%b displays in binary format see details in 3.3.1.
#1 timing delay. It means that the instruction will be executed
after 1 time unit.*/
Test bench Output
Simulate the design given below
 Design code:

module example_2_bl(out, a, b, c, d);

input a, b, c, d;
output out;
wire x, y;
and gate_1(x, a, b);
or gate_2(y, c, d);
xor gate_3(out, x, y);
endmodule
 Simulation code
`timescale 1ns / 1ns
module example_2_bl_tb;
wire t_out;
reg t_a, t_b, t_c, t_d;
example_2_bl my_bravelearn(.a(t_a), .b(t_b), .c(t_c), .d(t_d), .out(t_out));
initial
begin
// 1
t_a = 1'b0; t_b = 1'b0; t_c = 1'b0; t_d = 1'b0;
#5 //2
t_a = 1'b0; t_b = 1'b0; t_c = 1'b0; t_d = 1'b1;
#5 //3
t_a = 1'b0; t_b = 1'b0; t_c = 1'b1; t_d = 1'b0;
#5 //4
t_a = 1'b0; t_b = 1'b0; t_c = 1'b1; t_d = 1'b1;
#5 //5
t_a = 1'b0; t_b = 1'b1; t_c = 1'b0; t_d = 1'b0;
#5 //6
t_a = 1'b0; t_b = 1'b1; t_c = 1'b0; t_d = 1'b1;
 Simulation code continued
#5 //7
t_a = 1'b0; t_b = 1'b1; t_c = 1'b1; t_d = 1'b0;
#5 //8
t_a = 1'b0; t_b = 1'b1; t_c = 1'b1; t_d = 1'b1;
#5 //9
t_a = 1'b1; t_b = 1'b0; t_c = 1'b0; t_d = 1'b0;
#5 //10
t_a = 1'b1; t_b = 1'b0; t_c = 1'b0; t_d = 1'b1;
#5 //11
t_a = 1'b1; t_b = 1'b0; t_c = 1'b1; t_d = 1'b0;
#5 //12
t_a = 1'b1; t_b = 1'b0; t_c = 1'b1; t_d = 1'b1;
#5 //13
t_a = 1'b1; t_b = 1'b1; t_c = 1'b0; t_d = 1'b0;
#5 //14
t_a = 1'b1; t_b = 1'b1; t_c = 1'b0; t_d = 1'b1;
#5 //15
t_a = 1'b1; t_b = 1'b1; t_c = 1'b1; t_d = 1'b0;
#5 //16
t_a = 1'b1; t_b = 1'b1; t_c = 1'b1; t_d = 1'b1;
end
endmodule
1-Bit Comparator
 Design code of 1-Bit Comparator
module eql-primitive ( input wire iO, i1, output wire eq 5 ):
// internal signal declaration
wire iO-n, il-n, PO, pi;
//primitive gate instantiations
not unit1 (iO-n, iO); // iO-n = -iO;
not unit2 (il-n, il); // il-n = - i l ;
and unit3 (PO, iO-n, il-n); // pO = iO-n & i l-n;
and unit4 (pl, iO, il); // p1 = iO & i l ;
or unit5 (eq, PO, pl); // eq = pO I pl ;
endmodule
Gate types Syntax Description

and and g(out, i1, i2, …) Performs AND operation on two or more inputs

or or g(out, i1, i2, …) Performs OR operation on two or more inputs

xor xor g(out, i1, i2, …) Performs XOR operation on two or more inputs

nand nand g(out, i1, i2, …) Performs NAND operation on two or more inputs

nor nor g(out, i1, i2, …) Performs NOR operation on two or more inputs

xnor xnor g(out, i1, i2, …) Performs XNOR operation on two or more inputs
Gate types Syntax Description
The buffer (buf) passes input to the output as it is. It
buf buf g(out, in) has only one scalar input and one or more scalar
outputs.

The not passes input to the output as an inverted

not not g(out, in) version. It has only one scalar input and one or more
scalar outputs.

bufif1 g(out, in, It is the same as buf with additional control over the
bufif1 control) buf gate and drives input signal only when a control
signal is 1.

notif1 g(out, in, It is the same as not having additional control over
notif1 control) the not gate and drives input signal only when a
control signal is 1.

bufif0 g(out, in, It is the same as buf with additional inverted control
bufif0 control) over the buf gate and drives input signal only when a
control signal is 0.

It is the same as not with additional inverted control

notif0 notif0 g(out, in, over the not gate and drives input signal only when a
control) control signal is 0.
• Note:
• bufif1 and notif1 provide ‘Z output when a
control signal is 0.
• bufif0 and notif0 provide ‘Z output when a
control signal is 1.
• https://
vlsiverify.com/verilog/gate-level-modeling