DATA

TYPES:
What is data type?

• In programming, data type is a classification that specifies which type of value a

variable has.
• For example, A string, is a data type that is used to classify text.
• An integer is a data type used to classify whole numbers.
DATA
TYPES:
▶ SystemVerilog added lot of new data types and improved the existing data
types to improve run time memory utilization of simulators.
▶ In System Verilog data types can be classified into 2-state types and 4-state
types.
▶ 2-state types can take only 0, 1, where as 4-state types can take 0,1,X,Z.
▶ 2-state types consume less (50%) memory and simulate faster when compared
to 4-state types.
▶ SV introduces a new 4-state data type called logic that can be driven in both
procedural blocks and continuous assign statements.
▶ But, a signal with more than one driver needs to be declared a net-type such
as wire so that System Verilog can resolve the final value.
DATA
TYPES:
DATA
TYPES:
 DATA TYPES

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STRUCTURAL DATA
TYPES
WIRE AND REG
structural data types called nets, which model hardware connections between
circuit components. The wire nets act like real wires in circuits. The reg type
holds their values until another value is put on them, just like a register
hardware component.

The declarations for wire and reg signals are inside a module but outside any
initial or always block.
 BEHAVIORAL DATA TYPES
INTEGER, REAL, AND TIME
An integer declares one or more variables of type integer. These variables can hold values ranging from -
2^31 to (2^31)-1.
Integer Syntax:
integer integer_variable_name;

A real declaration declares one or more variables of type real. The real variables are stored as 64-bit
quantities, and store the real values. Real numbers can be specified in either decimal notation (for example,
14.72) or in scientific notation (for example, 39e8).

Time is a 64-bit quantity that can be used in conjunction with the $time system task to hold simulation time.
Time is not supported for synthesis and hence is used only for simulation purposes.
Syntax
time time_variable_name;
LOGIC

Logic is the improved version of reg form Verilog to SystemVerilog, so it Can be

driven by continuous assignments, gates, and modules in addition to being a
variable. declaration:
In Verilog behavior modeling, always, and initial procedural blocks use reg data type
whereas, in dataflow modeling, continuous assignment uses wire data type.
SystemVerilog allows driving signals in the ‘assign’ statements and procedural
blocks using logic data type. The logic is a 4-state data type that allows capturing the
Z or X behavior of the design
PARAMETERS

Parameters represent constants, hence it is illegal to modify their value at

runtime. However, parameters can be modified at compilation time to
have values that are different from those specified in the declaration
assignment. This allows the customization of module instances. A
parameter can be modified with the defparam statement, or in the
module instance statement.

parameter size = 16 ;
VOID
DATA
TYPE:
▶ void is used in functions to return no value.
▶ Void data type represents non-existent data.
▶ This type can be specified as the return type of function, including no return
value.

Syntax:

function void display ();

$display ("Am not going to return any value");
endfunction
EVE
NTS:
▶ Events are static objects useful for synchronization between the process.
▶ Events operations are of two staged processes in which one process
will trigger the event, and the other processes will wait for an event to be
triggered.
▶ Events are triggered using -> operator or ->> operator
▶ wait for an event to be triggered using @ operator or wait() construct
▶ System Verilog events act as handles to synchronization queues. thus, they can
be passed as arguments to tasks, and they can be assigned to one another or
compared.
Syntax:
->event_name;
@(event_name.triggered);
 SIGNED/UNSIGNED
• byte, shortint, int, integer and longint defaults to signed
– Use unsigned to represent unsigned integer value
Example: int unsigned ui;
• bit, reg and logic defaults to unsigned
• To create vectors, use the following syntax:
logic [1:0] L; // Creates 2 bit logic vector

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USER DEFINED DATATYPES
In Complex testbenches some variable declarations might have longer data type
specification.
User-defined types use keyword typedef which is an extension of SystemVerilog
data type.
typedef int myint; // Declaration
myint a,b; // Usage of user defined data type.
 ENUMERATION

A set of integral named constants is called an enumerated type. It defines a set of

named values having an anonymous int type.
An enumerated type defines a set of named values. The simplest enumerated type
declaration contains a list of constant names and one or more variables.

enum {red, yellow, green} traffic_signal; //Anonymous int

type -> red = 0, yellow = 1 and green = 2
 STRINGS
• String – dynamic allocated array of bytes
• SV provides methods for working with strings

Str1 == Str2 Equality

Str1 != Str2 Inequality

<, <=, >, >= Comparison

{Str1, Str2, … Strn} Concatenation

Str1[index] indexing – return 0 if out

of range
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 STRING METHODS

• len • atoi, atohex,

• putc atoct,
• getc atobin
• • atoreal
toupper
• • itoa
tolower
• • hextoa
compare
• • octtoa
icompare
• • bintoa
substr
• realtoa

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WHAT ARE LITERALS?

Literals are the constant values assigned to the constant variables. We can say that
the literals represent the fixed values that cannot be modified. It also contains
memory but does not have references as variables. For example, const int =10; is a
constant integer expression in which 10 is an integer literal.

Types of literals

•Integer literal
•Float literal
•Character literal
•String literal