10.

VHDL
VHDL OVERVIEW
• VHDL => VHSIC Hardware Description Language
• VHSIC => Very High Speed Integrated Circuits
• VHDL is used to model the physical hardware used in digital systems.
• VHDL make use of Object Oriented methodology (modules developed for the
current project can be reused in the future)
VHDL STRUCTURE
• There are 3 sections in aVHDL code
– Library,Entity andArchitecture
VHDL STRUCTURE
• Library and Package:
– Groups of procedures, functions, user defined data types and constants that are
related can be aggregated into a module that is called package.
– A package can be shared across manyVHDL models.
– A library is a collection of related packages.
– Packages and libraries serve as repositories for functions, procedures, and data
types.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

The packages are "std_logic_1164" and "std_logic_unsigned" and

the library is "ieee".
VHDL PACKAGE
• std_logic_1164:
– Data types:
• std_logic (‘1’,‘0’,‘Z’,‘-’ ..)
• std_logic_vector array of std_logic
– Operators:
• and,or,not,nand,nor,xor,xnor
– Functions:
• rising_edge() Detects rising edge of std_logic signal and returns true
• falling_edge() Detects falling edge of std_logic signal and returns true
VHDL PACKAGE
• std_logic_arith:
– Defines some types and basic arithmetic operations for representing integers in
standard ways.
– Data types:
• unsigned type
• signed type
– Operators:
• Arithmetic +, -,*, /,rem. Mod
• Relational <, <=, =, /=,>=, >
• Shift,Rotate shl,shr,ror,rol
– Functions:
• conv_signed()
• conv_unsigned()
• conv_std_logic_vector()
VHDL STRUCTURE
• Entity declaration specify:
– The name of the entity
– A set of port declarations defining the inputs and outputs and the port type of
the hardware design
– Port type can be IN, O UT,INO UT and BUFFER
VHDL STRUCTURE
• Architecture:
– Specify the design internal implementation
– Describes the behavior,interconnections and relationship between different
inputs and outputs
– Three implementation models:
• Dataflow
• Behavioral
• Structural
DATA OBJECTS
• Constant:
– Holds values that can’t be changed within a design
– constant BUS_WIDTH :integer := 8;
– constant PERIOD :time := 10 ns;
• Variable:
– Variables are used in processes (variables behave as expected in software programming
languages)
– variable HEIGHT :integer := 8;
– Variables are modified with := HEIGHT:=HEIGHT+1
• Signal:
– Represents wire connections (physical signals)
– Signals are used in structural and dataflow description
– signal SUM, CARRY :bit;
– Signals are modified with <= SUM<=‘1’;
VHDL DATATYPE
● Bit type (0,1)
● bit vectors (group of multi-bit signal → bus)
● Example
– SIGNAL x:BIT;
– SIGNAL y:BIT_VEC TOR (3 D O W N TO 0);
– SIGNAL w: BIT_VEC TOR (0TO 7);
● Signal assignment operator <=
– x <= '1';
– y <= "0111";
– w <= "01110001";
VHDL DATATYPE
● std_logic (0, 1,-,Z …)
● std_logic_vector (group of multi-bit signal → bus)
● Example
– SIGNAL x:std_logic;
– SIGNAL y:std_logic_vector (3 D O W N TO 0) := “1101”;
– SIGNAL z:std_logic_vector (0TO 7);
● Signal assignment operator <=
– x <= '1';
– y <= "0111";
– z <= "01110001";
VHDL PACKAGE
• std_logic_unsigned:
– This library package extends the std_logic_arith to handle std_logic values as
unsigned integers
– It defines all of the same arithmetic (+, -,*), comparison (<, <=, >, >=, =, /=) and
shift (shl, shr) operations as the std_logic_arith library.
– This difference is that the extensions will take std_logic_vector values as
arguments and treat them as unsigned integers
VHDL PACKAGE
• std_logic_signed:
– This library package extends the std_logic_arith to handle std_logic values as
signed integers
– It defines all of the same arithmetic (+, -,*), comparison (<, <=, >, >=, =, /=) and
shift (shl, shr) operations as the std_logic_arith library.
– This difference is that the extensions will take std_logic_vector values as
arguments and treat them as 2’s complement signed integers
VHDL DATATYPE: SIGNED AND UNSIGNED
● Defined in the STD_LOGIC_ARITH package of the IEEE library
● For arithmetic operations.
● Signal Declaration Examples
SIGNAL x:SIGNED (7 D O W N TO 0);
SIGNAL y:UNSIGNED (0TO 3);
● Syntax is similar to that of STD_LOGIC_VECTOR
● An UNSIGNED value is a number never lower than zero.
For example,
– Unsigned ‘‘0101’’ = the decimal 5
– Unsigned‘‘1101’’ signifies 13.
– Signed ‘‘0101’’= the decimal 5
– Signed ‘‘1101’’signifies -3 (Two's complement)
VHDL DATATYPE
● BOO LEA N (TRUE,FALSE)
● variableVAR1:boolean := FALSE;
● INTEGER (32 bit)
● SIGNAL SUM: integer range 0 to 256 :=16;
● REAL
● constant Pi :real := 3.14159;
● These datatypes are defined in package ‘standard’ and is predefined in the compiler
VHDL OPERATORS
● Logical Operators
VHDL OPERATORS
● Arithmetic Operators
VHDL OPERATORS
● Relational Operators
VHDL MODELLING
• Architecture:
– Specify the design internal implementation
– Describes the behavior,interconnections and relationship between different
inputs and outputs
– Three implementation models:
• Dataflow
• Behavioral
• Structural
DATAFLOW MODEL
• The dataflow representation describes how data moves through the system.
• This is typically done in terms of data flow between registers (RegisterTransfer
level).
• The data flow model makes use of concurrent statements that are executed in
parallel as soon as data arrives at the input.
• Generally Dataflow modeling is used to describe combinational circuits.
DATAFLOW MODEL
FULLA D D ER
DATAFLOW MODEL
2 TO 4 DEC O DER
BEHAVIORAL MODEL
• The behavioral modeling describes how the circuit should behave.
• Behavioral modeling represents digital circuits at a functional and algorithmic
level.
• It is used mostly to describe sequential circuits, but can be used to describe
combinational circuits.
• We describe the behavior of an entity using sequential statements. And this
makes it very similar to high-level programming languages in syntax and
semantics.
• The primary mechanism to write a program in behavioral style is by using
something called a“process”.
BEHAVIORAL MODEL: PROCESS
• A process block contains statements that theVHDL compiler executes
sequentially.
• Statements inside the process block may describe the working of the entity or
a portion of the entity.
• The sequential execution of statements means that the compiler will execute
them in the same order as we write them.
• This way of execution is very similar to other high-level programming
languages like C ,C++, JAVA, etc.
BEHAVIORAL MODEL
• Sequential statements
• Case Statement
• case expression is
• when choice1 => sequential-statements;
• when choice2 => another sequential-statements;
• ....
• when others => more sequential-statements;
• end case;
BEHAVIORAL MODEL
• Sequential statements
• If Statement
• if boolean-expression then
• sequential-statements;
• elsif boolean-expression then
• sequential-statements;
• else
• sequential-statements;
• end if;
BEHAVIORAL MODEL: PROCESS
• PROCESS DECLARATION
optional_label: process (optional sensitivity list)
declarations
begin
sequential statements
end process optional_label;

The sensitivity list is a list of signals. A change in value

on one or more of these signals, causes the process to
be activated:
process (ALARM_TIME, CURRENT_TIME)
begin
if (ALARM_TIME = CURRENT_TIME) then
SOUND_ALARM <= '1';
else
SOUND_ALARM <= '0';
end if;
end process;
BEHAVIORAL MODEL
2 TO 4 DECO DER
BEHAVIORAL MODEL
BEHAVIORAL MODEL
2 TO 4 DECO DER
(USING CASE STATEMENT)
STRUCTURAL MODEL
• In this modeling, an entity is described as a set of interconnected components.
• A component instantiation statement is used to reuse a design. It allows us to
write reusable code.
• InVHDL, we widely use structural modeling for large designs.
• We define a smaller entity in a separate file and can use it in a larger entity as a
component.
• We use signals to interconnect components and eventually create large
systems using small sub-systems.
STRUCTURAL MODEL
• For example, imagine you have created a full adder and want to design a 4 bit-
adder.
• Then you don’t have to write it entirely from scratch.
• You can use those pre-written entities (full-adder) as components in your 4
bit-adder code.
• To use them,you just need to map its inputs and outputs according to your
design requirements.
STRUCTURAL MODEL
STRUCTURAL MODEL
STRUCTURAL MODEL
• COMPONENT
• The component instantiation statement is the primary mechanism used for describing
structural model.
• A component instantiated in a structural description must first be declared using a
component declaration.
• In an architecture, components must be declared before the begin statement.
• Port Maps
• The ports in a component declaration must usually match the ports in the entity
declaration one-for-one.
• The component declaration defines the names, order, mode and types of the ports to
be used when the component is instanced in the architecture body.
• Instancing a component implies making a local copy of the corresponding design entity
- a component is declared once within any architecture, but may be instanced any
number of times.
STRUCTURAL MODEL
• MUX 4 TO 1 FRO M MUX 2 TO 1AS C O MPONENT
STRUCTURAL MODEL
• MUX 4 TO 1 FRO M MUX 2 TO 1AS C O MPONENT
VHDL (SEQUENTIAL CIRCUITS)
VHDL (SEQUENTIAL CIRCUITS)
VHDL (SEQUENTIAL CIRCUITS)
VHDL (SEQUENTIAL CIRCUITS)
VHDL (SEQUENTIAL CIRCUITS)