DC Power

DQA2
Roberto Lai
EX:8542
 Contents
1. Power Delivery Map
2. North Bridge, South Bridge Power Analysis
3. FLASH ROM , H/W Monitor , Device
Power Analysis
4. Source Power Sequence, ATX Power
Analysis
5. Leakage Voltage, Leakage Current
6. PCI Loading
7. REGULATOR
wer Delivery Map
Power Delivery Map
ATX P/S
with 1A Stby current
Processor
5VSB 5V 3.3V 12V -12V
+/-5% +/-5% +/-5% +/-5% +/-10% VCCVID
VID voltage 1.2V
BG GMCH
regulator 30mA VccCORE
1.5V
Vc c CORE/Vtt
2.46A
1.15V-1.75V
VRM 9/0 60A VccAGP
1.5V
370mA

VccHI
1.5V regulator 1.5V
90mA

VttFSB
2.5V regulator 1.15V-1.75V
2.4A

2.5V Standby VccSM

regulator 2.5V
2.8A

VccGPIO
3.3V
1.25V regulator 30mA
Memory Vcca_DAC
1.5V
Vdd/Vddq 65mA
2.5V
5.92A
ICH4
1.5V Standby Vtt
regulator 1.25V
VccCORE
2.1A 1.5V
970mA

VccHI
1.5V
90mA

Vccsus1_5
1.5V
3.3V Standby 85mA
regulator
V_CPU_IO
1.15V-1.75V
45mA

Vcc3_3
3.3V
610mA
Vccsus3_3
3.3V
70mA

CK-408
Vcc
3.3V
280mA

LPC Su per I/O

Vdd
3.3V
25mA

CNR Connector PCI Slot (per slot) AGP Slot FWH

USB
5V 1.0A 5V 5.0A 5V 2.0A Vdd
3.3V 1.0A 3.3V 7.6A 3.3V 6.0A Vdd 3.3V
12V 0.5A 12V 0.5A 12V 1.0A 5V 67mA
3.3Vaux 1.0A 3.3Vaux 0.375A 3.3Vaux 0.375A 2.0A
-12V 0.1A -12V 0.1A 1.5V 2.0A
5VDual 0.5A
 North Bridge Power Analysis
Signal Pin Description

Signal Name Type Description Min Nom Max

VTT Vol AGTL+ Bus Termination Voltage Inputs: These pins provide the AGTL+ NA NA 1.75
Bus termination.
VCC1_5 Vol 1.5 V Power Input: These pins are connected to a 1.5 V power source . 1.425 1.5 1.575
(include AGP and Core)
VCC1_8 Vol 1.8 V Power Input Pins: These pins are connected to a 1.8 V power source. 1.71 1.8 1.89

VCCSM Vol DDR I/O Power Input Pins: These pins are connected to a 2.5 V power 2.375 2.5 2.625
source for DDR.

HVREF Ref Host Address and Data Reference Voltage: Reference voltage input for the 2/3*VT 2/3*V 2/3*VT
data, address, and common clock signals of the host AGTL+ interface. T-2% TT T+2%
SDREF Ref DDR Reference Voltage: Reference voltage input for DDR. 0.48*V 0.5*V 0.52*VC
CCSM CCSM CSM
HI_REF Ref Hub Interface Reference: Reference voltage input for the hub interface. 0.48*V 0.5*V 0.52*VC
CC1_8 CC1_8 C1_8
AGPREF Ref AGP Reference: Reference voltage input for the AGP interface. 0.48*V 0.5*V 0.52*VC
CC1_5 CC1_5 C1_5
HSWNG I Host Reference Voltage: Reference voltage input for the compensation logic. 1/3*VT 1/3*V 1/3*VT
CMOS T-2% TT T+2%

VCCA_FSB PLL Power Input Pins: These pins provide power for the PLL.

VCCA_DPLL PLL Power Input Pins: These pins provide power for the PLL.

VCCA_SM PLL Power Input Pins: These pins provide power for the PLL.

VCCQ_SM PLL Power Input Pins: These pins provide power for the PLL.
 North Bridge Power Analysis
About Reference voltage:
The DDR system memory reference voltage is used by the DDR-SDRAM devices to compare the input signal levels
Of the data , command, and control signal.

How to measure NB Power ?

Preparation:
1.Measure signal close with NB side.
2.To find all DC voltage on NB.
3.To find DC voltage spec.
Measure:
1.Oscilloscope proofread.
2.To find ground point.
3.Measure
Note:
1.Position Scale:50mV
2.Resolution Scale:200μ S
3.Bandwidth:20MHz
 South Bridge Power Analysis
Signal Name Type Description Min Nom Max
Vcc3_3 Vol 3.3V supply for core well I/O buffers. This power may be shut off in S3,S4,S5 3.135 3.3 3.465
or G3 state

Vcc1_5 Vol 1.5V supply for core well logic. This power may be shut off in S3,S4,S5 or G3 1.425 1.5 1.575
state.

VccSus3_3 Vol 3.3V supply for resume well I/O buffers. This power is not expected to be shut 3.135 3.3 3.465
off unless the system is unplugged in desktop configurations. Or the main
battery is removed or completely drained and AC power is not available in
mobile configurations.
VccSus1_5 Vol 1.5V supply for resume well logic. This power is not expected to be shut off 1.425 1.5 1.575
unless the system is unplugged in desktop configurations. Or the main battery is
removed or completely drained and AC power is not available in mobile
configurations.
V5REF Ref Reference for 5V tolerance on Core well inputs. This power may be shut off 4.75 5 5.25
in S3, S5 or G3 states.

V5REF_SUS Ref Reference for 5V tolerance on Resume well inputs. This power is not expected 4.75 5 5.25
to be shut off unless the system is unplugged.
Note: V5REF_SUS only affects 5V tolerance for the USB OC[3:0]# pins and
can be connected to VccSUS3_3 if 5V tolerance on these signals is not required.
VccRTC Vol 3.3V (can drop to 2.0V min. in G3 state) supply for the RTC well. This 2.0 3.6
power is not expected to be shut off unless the RTC battery is removed or
completely drained.
Note: Implementations should not attempt to clear CMOS by using a jumper to
Pull VccRTC low. Clearing CMOS in an ICH2-based platform can be done by
using a jumper on RTCRST# or GPI, or using SAFEMODE strap.
HIREF Ref Analog Input. Expect voltage are: 0.343 0.357
•0.9V for HI 1.0 (Normal Hub Interface) Series Termination.
•350mV for HI 1.5 (Enhanced Hub Interface) Parallel Termination.
This power is shut off in S3,S4,S5 and G3 state.
 South Bridge Power Analysis
How to measure NB
Power ?
Preparation:
1.Measure signal close with S
B side.
2.To find all DC voltage on S
B.
3.To find DC voltage spec.
Measure:
1.Oscilloscope proofread.
2.To find ground point.
3.Measure
Note:
1.Position Scale:50mV
2.Resolution Scale:200μ S
3.Bandwidth:20MHz
 H/W Monitor Power Analysis
VCC12

R25 F_2.2K_X-P
CPU FAN
E R24 D1
R37 F_1K_X-P B 4.7K X_1N4148-S-LL34
C R54
0/0805_X-P-F
R12
Q11
FANIO3 23
F_SI2303DS-SOT23_X-P
27K

1
D
+ CFAN1 R13
R33 Q10 C4 10K
G F_2N7002_X-P 47u/16V CPUFAN_C 3
23 FANPWM2 2

2
F_510_X-P S 1
D1x3-WH

For FANPWM and FANIO pin description as below :

SYMBOL I/O FUNCTION
FANPWM1 O Fan speed control. Use the Pulse Width Modulation (PWM) technical knowledge
FANPWM2 to control the Fan's RPM.

FANIO I/O 0V to +5V amplitude fan tachometer input. Alternate Function: Fan on-off
control output. These multifunctional pins can be programmable input or output.

How to choice Q11 transistor :

FAN Spec:
Operation Voltage DC 7.0 ~ 13.8V
Rated Voltage DC 12V
Rated Current 0.32A
Input Power 3.84 Watt
 H/W Monitor Power Analysis
Analysis:
It can easily show the Fan power pin voltage drop too much when the Fan sink c
urrent over 400mA.
Vce (max)= 11.80V – 10.04 = 1.76V,Q11 (MMBT2907) spec Vce (max)=40V
I-fan = Ic = 640 mA, Q11 spec Ic (max) = 600mA ( margin )
Pd =V x I=1.76Vx640mA = 1126 mw, Q11 spec Pd (max)=300mw(over too muc
h)
So Q11 will be damaged !
Changed Q11 from MMBT2907 to Mosfet 2303:
It can see the Fan power pin voltage drop too small (around 30mV) when the F
an sink 680mA.
Pd = 30mV x 680 mA = 20.4mw, so it can work fine.
Conclusion:
1.When Q11 use transistor, it must work in saturation or cut-off region.
2.Change Q11 from MMBT2907 to Mosfet 2303(Id=1.7A)

MMBT2907 2303
 FLASH ROM & Device Power Analysis

Flash Rom PIN DESCRIPTION

Symbol Pin Name Functions Min Nom Max

VDD Power Supply To provide power supply (3.0-3.6V) 3.135 3.3 3.465

Device Power Analysis :

Voltage Plane Min Nom Max

Measure Skill:
For Flash Rom
AMR/CNR VCC5 4.75 5 5.25
1.Measure Flash Rom Side
AMR/CNR VCC3_3 3.14 3.3 3.47 2.Measure skill in common with NB &SB
KB/MS VCC5 4.75 5 5.25

USB_VCC 4.75 5 5.25

For On Board Device
Game Port VCC5 4.75 5 5.25 1.Measure AMR/CNR, KB/MS, USB, Game Port, VGA Side
VGA Connector 4.75 5 5.25
2.Measure skill in common with NB & SB
 ATX Power Analysis

Power Signal Control

Definitions
Power Supply Connector Pin Description

PS-ON PS-ON is an active low signal that turns on all of the main power rails including 3.3V, 5V, -
5V, 12V, and -12V power rails.
5VSB 5VSB is a standby voltage that may be used to power circuits that require power input
during the powered-down state of the power rails.
PW-OK PW-OK is a power good signal and should be asserted high by the power supply to indicate
that the +5 VDC and +3.3 VDC outputs are above the under voltage thresholds of the power
supply.

ATX Power Analysis:

Voltage Rail Min Nom Max

Measure Skill:
1.Measure ATX Power Side
+5 VDC 4.75 5 5.25
2.Measure skill such as NB &SB
-5 VDC -5.5 -5 -4.5
+12 VDC 11.4 12 12.6
-12 VDC -13.2 -12 -10.8
+3.3 VDC 3.14 3.3 3.47
+5VSB 4.75 5 5.25
 Source Power Sequence
Target:
1.Measure Power Pin(Vcc3,Vcc5,+12V,PW_OK) wrong motion
when system power on and power off.

Measure Skill:
1.Measure power pin(Vcc3,Vcc5,+12V,PW_OK) side.
2.Measure skill in common with NB & SB.

Power On

Power Off
 Leakage Voltage & Leakage Current
Item Voltage Spec
CPU VCCP 0.1 Measure Process (Leakage Voltage)
1.Oscilloscope proofread.
North Bridge VCCP,VCC1_8,V_DIMM 0.1
2.To find ground point.
South Bridge VCCP,VCC3,VCC1_8 0.1 3.Run 3D Mark 2001.
AGP VDDQ,VCC3,VCC5,+12V 0.1
4.Power off (standby voltage exist ) and use multimeter to measure
leakage voltage.
PCI +12V,VCC3,VCC5 0.1

DDR VCC2_5 0.1

SDRAM VCC3 0.1 Measure Process (Leakage Voltage)

ATX +12V,+5V,+3.3V 0.1 For Battery
1.Power off (standby voltage exist)
FLASH ROM VCC3 0.1
2.Use meter to measure Battery leakage voltage.
KB/MB VCC5 0.1 For 5VSB
GAME PORT VCC5 0.1
1.Power off (standby voltage exist)
2.Use AC/DC Clamp meter to measure ATX connector 5VSB
CNR VCC3,VCC5 0.1

Leakage Voltage

Item Spec
Battery 8μA

5VSB 1A

Leakage Current
 PCI Loading
Introduction:
PCI systems compliant with the PCI Bus Power Management Interface Specification may also support an optional auxiliary power source
(3.3Vaux) connecting it to pin 14A of its PCI slot connectors.

3.3Vaux DC Characteristics:
PC system manufacturers who choose to support 3.3Vaux are required to physically route 3.3Vaux to all PCI slots on their motherboard.
Since most systems support a minimum of four PCI slots, it is essential to account for any auxiliary power required by the PCI slots and to
budget the available auxiliary power appropriately. The following table defines the DC operating environment that a 3.3Vaux enabled system
Must deliver.
Parameter Min Typ Max Units
3.3Vaux 3.0 3.3 3.6 Volts
IMAX_ENABLED - - 375 mA

IMAX_DISABLED - - 20 mA

3.3Vaux Minimum Required Current Capacity :

At a minimum, systems supporting 3.3Vaux must be capable of fully powering at least one 3.3Vaux enabled PCI slot while the PCI bus is in
B3. In the case of a 4 PCI slot system for example, the minimum required 3.3Vaux current capacity for that system would be 435mA (1
enabled slot, and 3 disabled slots).
 PCI Loading

Measure Skill:
1.Use Electronic Load to load current on VCC3_SB pin.
2.Measure skill in common with NB & SB.

For S3 Mode:

Parameter Load Specification SPEC

VCC3_SB Output Voltage at 3.135V~

MaximumLoad:375mA+40mA=415mA(Und 3.465V
er DC loading: 415mA)
VCC3_SB Output Voltage 3.135V~
Transient375mA+40mA=415mA(0~415mA) 3.465V

For S0 Mode:

Parameter Load Specification SPEC

VCC3_SB Output Voltage at Maximum Load: 3.135V~

3x375mA=1.125A(Under DC loading: 3.465V
1.125A)
VCC3_SB Output Voltage 3.135V~
Transient3x375mA=1.125A(0~1.125A) 3.465V
 REGULATOR
VDDQ Regulator Item SPEC

Output Voltage at Maximum Load

(Under DC loading: 2A)

S
VDDQ: G
Output Voltage Transient
1.425
C290 VDDQ |
Q32 (0~2A)
1.575
IPB15N03L

D
X_102P Run Worst Case Program
(Run 3DMark2001)
VCC3

VCC3

C5 104p Regulator Item SPEC

D
VCC1.2
Q2 G Output Voltage at Maximum Load
VCC1.2: 2N7002
(Under DC loading: 30mA)
1.21
S
Output Voltage Transient
VCC1.2 |
(0~30mA)
EC1 + 1.29
10u/1206 Run Worst Case Program
(Run 3DMark2001)

VCC3SBY
Regulator Item SPEC

C294 C298 Output Voltage at Maximum Load

104p
(Under DC loading: 4A)
D

2.3
V_DIMM : Q31
IPB15N03L
105p/0805 VCC1.8
V_DIMM
Output Voltage Transient
|
G (0~4A)
V_DIMM 2.7
D7
Run Worst Case Program
C A
S

(Run 3DMark2001)
C259
1N5817S
105p/0805
 REGULATOR
VCC3SBY
VCC1_5SB
Q41

2N7002
D S Regulator Item SPEC
+ EC31
10u/16V Output Voltage at Maximum Load
VCC1_5SB:

G
R289
C354 200RST
U13A (Under DC loading: 1.2 A)

8
105p TI-LM358-SOIC8_#A
+
3 VREF1_25 1.425
1
-
2 VCC1_5SB Output Voltage Transient |
C327
(0~1.2A) 1.575
Vref*[1+(R1/R2)]=Vout

4
R286
1KST Run Worst Case Program
103p (Run 3DMark2001)

VCC3
Q26 VCC1.8
NDS351S-SOT23 Regulator Item SPEC
D S

9VSB
Output Voltage at Maximum Load
C246 C312 (Under DC loading: 2A)
+ R301 100 104p
105p/0805 1.71
G

EC28
VCC1_8: X_10u/16V U13B R287 VCC1_8 Output Voltage Transient |
8

TI-LM358-SOIC8_#B 100RST
5 VREF1_25 (0~2A) 1.89
+
0 R291 7
6
-
Run Worst Case Program
C350 R285 (Run 3DMark2001)
4

220RST
X_100P

V_DIMM
Regulator Item SPEC
C247
C237 Output Voltage at Maximum Load
104p 105p/0805
(Under DC loading:1A)
1.2
D

Q25
P3055LD Output Voltage Transient
DDR_VTT |
DDR_VTT G (0~1A)
DDR_VTT: Run Worst Case
1.3
DS

Program
G (Run 3Dmark2001)
Q28
P3055LD
S
 REGULATOR
5VSB
Regulator Item SPEC
C348
104p
Output Voltage at Maximum Load
5VUSB USE 2 MOSFET
(Under DC loading: 2.2 A)

D
1.2A
Q40 Output Voltage Transient
NDS351S-SOT23
G (0~2.2A)
5VDUAL 4.75
5VDUAL Run Worst Case Program |

D S
(Run 3DMark2001) 5.25
5VDUAL: G
Q14
P45N02LD-S-TO252
Measure Voltage
C32
Overshoot (S0~S3)

S
Low RDS ON MOSFET
104p
Measure Voltage
VCC
Undershoot (S3~S0)

VCC3
Regulator Item SPEC
C269
Output Voltage at Maximum Load
105p/0805
Q34 (Under DC loading: 1.2A)
S

P45N02LD-S-TO252
G

VCC3SBY Output Voltage Transient

(0~1.2A )
VCC3SBY: 3.135
D

C291
105p + EC23 VCC3SBY Run Worst Case Program |
S

10u/16V
G (Run 3DMark2001) 3.465
Measure Voltage
1.2A Q29
NDS351S-SOT23 Overshoot (S0~S3)
D

C277
Measure Voltage
105p
5VSB Undershoot (S3~S0)
 REGULATOR
For 5VDUAL AND VCC3SBY overshoot when system S0->S3 or S3->S0.

S0->S3 S3->S0