Chapter: Memory Management

Memory
 Memory
Computer has 2 types of memory:

a) Main Memory: temporarily stores data and instructions

executed by the computer. CPU retrieve instructions from
main memory and executes it.

b) Secondary Memory: directly is not accessed by CPU. It is

an external storage.
 Logical and Physical Address Space
1. Logical Address or Virtual address:
a. The address generated by CPU.
b. Logical address is address of instruction / data as used by
program at some time.

Set of all logical address generated by program is Logical

address space
 Logical and Physical Address Space
2. Physical Address:
a. It is the address used seen by memory management unit
(MMU).
b. It refers to actual location in the main memory.
c. The user can never view physical address of program

Set of all logical address that a process actually occupies is Physical

address space

The logical address is used like a reference, to access the

physical address

MMU is used to map logical and physical addresses.

 Address Binding
Address Binding: Assigning an address to data or
instruction.

Address binding is a process of generating address where the

data/instruction is to be stored in memory.

3 types of address binding:

1. Compile time binding

2. Load time binding
3. Run time binding
 Address Binding
Address Binding: Fixing a physical address to the logical address
of a process address space

Compile time binding: it is known to compiler at compile time

where a program will reside in physical memory (Main Mem.)

Load time binding: if program location in memory is unknown until

run-time.

Execution/Run time binding: If the process can be moved during

its execution from one memory segment to another, then binding
must be delayed until run time. The absolute addresses are
generated by hardware.
 Address Space of process
We can provide protection of
address space by using two
registers:- a base and a limit

Base register holds the smallest

legal physical memory address

Limit register specifies the size

of the range.
e.g. For example, if the base register
holds 300040 and the limit register is
120900, then the program can legally
access all addresses from 300040
through 420939 (inclusive)
 Address Protection

Protection of memory space is accomplished by having the

CPU hardware compare every address generated in user mode
with the registers.

Any attempt by a program executing in user mode to access

operating-system memory or other users’ memory results in
a trap to the operating system
 Protection

Base register and limit registers can only be updated by OS in kernel

mode.
 Logical and Physical Address Space
•The run-time mapping from logical (virtual) to physical
addresses is done by a hardware device called the memory-
management unit (MMU).

•The base register is now called a relocation register.

•The value in the relocation register is added to every address

generated by a user process at the time the address is sent to
memory.
Logical and Physical Address Space
 Swapping
Technique of removing a process from main memory and storing it
into secondary memory, then bringing it back into main memory
for continued execution.

It is a technique used in multiprogramming environments which

have limited memory capacity.

Action of moving process out of main memory is called Swap Out

Action of moving process into main memory is called Swap In

Area on the disk where swapped out process are stored is

known as Swap Space.
 Swapping
During Swap-Out foll.
Things are checked:
While in Main Memory was
user program modified?
Yes: write it back to Sec.
Memory

No: Sec. Memory already has

a copy of it, no need to
write.
Overwrite J3 with new
program. I.e bring new
program
Contiguous File Allocation

Relocation Register contains base address of the process

Contiguous File Allocation
The address generated by the CPU is a logical address which
is not known to the Main Memory. The Physical memory or
the Main Memory knows only the Physical address.

Therefore the address generated by the CPU(Logical Address)

is compared with a Limit Register and if the value is low, It is
added to the value in Relocation Register to yield a Physical
Address.
Contiguous File Allocation
In simple,
1) CPU generates Logical address(say 345)
2) 345 is compared with value in Limit Register.
3) If 345 > Limit Register then TRAP
4) If 345 < Limit Register then value is added with Relocation
Register(say 300) to get physical address. ie: 345+300 =
645(Physical address)
Therefore if CPU can generate logical address in the range 0 to
345, then the corresponding physical address can range
from R+0 to R+345 where R is the value in Relocation
Register.
So, the address a user sees and the address a RAM sees to
access a data are different.
Partitions
P1 needs 10mb space
P2 needs 30mb space
P3 needs 20mb space
P1 finishes its execution P4 need 25mb
So space is free

Free
P3 finishes its execution P5 require 25Mb space
So space is free
Partition Allocation
One method of allocating contiguous memory is to divide all available
memory into equal sized partitions, and to assign each process
to their own partition.

Partition Allocation
Algorithms:

a) First Fit:
– Checks all partitions
serially
– When partition with size
= or > encounters, it is
allocated for storage.
Partition Allocation Algorithms
b) Best Fit: This approach will check all the free partitions and
will allocate that free partition to a process which leads to
minimum internal fragmentation.

Disadvantage:
1) Complexity is more
2) Overhead to check all the partitions to find best suitable
space

c) Worst Fit: Allocate the largest memory hole

 Fragmentation
1. Internal Fragmentation: memory is allocated in blocks
of a fixed size, whereas the actual memory needed will
rarely be that exact size.
Partition of greater size is allocated to process of small size,
rest of the space of that partition is wasted.
 Fragmentation
External Fragmentation: means that the available memory
is broken up into lots of little pieces, none of which is big
enough to satisfy the next memory requirement, although
the sum total could.
– Due to non utilization of space, even space is empty
Fragmentation
– For Fixed sized partitions
There is:
• Internal Fragmentation
• External Fragmentation

– For Variable sized partitions

There is:
• External Fragmentation
Partition Allocation Table
Contains information of space/ memory used by memory
management module for allocation of memory to a process

a) No. of partitions in main memory

b) Size of each partition
c) Starting location of partition
d) Status of partition (allocated or free)
Memory Allocation - Example

Given 3 free memory partitions of 10KB, 20 KB and 15KB ( in

order) How would each of the first-fit, best- fit and worst fir
algorithms place processes of 15KB, 10KB, 20KB and 5KB (in
order)
Memory Allocation - Example
For 15KB
Memory Allocation - Example
For 10KB
Memory Allocation - Example
For 20KB
Memory Allocation - Example
For 5KB
Memory Allocation - Example
Paging / Paged Memory Management
– Paging is a memory management scheme that allows
processe’s physical memory to be discontinuous, and
eliminates problems with fragmentation by allocating
memory in equal sized blocks known as pages.
Paging
Paging / Paged Memory Management

– Every process is divided in to number of pages

– Memory is divided into partitions whose size is same as page
size : frames
– Each frame has frame no.
– Page size is same as frame size
– Put any page in any free frame
– Paging allows non-contiguous memory allocation
– Page numbers, frame numbers and frame sizes are
determined by the machine architecture
– Paging leads to Internal Fragmentation
Pages size and Frame size is always in powers of two
Paging / Paged Memory Management

– CPU generates logical address and put the pages into

random frames

– Mapping is required to map which page is stored in which

page number

– From frame no. physical address could be found

Paging / Paged Memory Management

– Physical address space of a process in non- contiguous

– Implementation:
• Frames: Fixed sized blocks of the physical memory
• Pages: Fixed sized slots of the logical memory
– When a process is to be executed, its pages are loaded into
any available memory frames.
– Page Table: is a data structure. Used to translate logical
address to physical address
– CPU generated logical addresses to fetch the instructions.
Address Translation
– Address generated by CPU is divided into:

a) Page Number (p): used as an index into page table, which

contains base address of each page in the physical memory.

b) Page Offset (d): combined with base address to define

physical memory address that is sent to the memory unit.
Actual address of any byte in page or frame (Position of
instruction in page or frame)

• Address of physical memory, where page resides.

• The number of bits in the offset determines the maximum size of
each page, and should correspond to the system frame size.
Address Translation
Address Translation
Translation of Address to memory
How many address combinations can be generated from
bits:
1 bit  2^1=2 i.e 0 or 1
2 bit  2^2=4 i.e 00,01,10,11 ……..so on
n bits  2^n combination of address locations can be
generated.

If we have n bit address, and system is byte addressable

(every location/partition is of 1 Byte) it will support
memory of:
2^n x 1Byte
Translation of Address to memory
Translate n bit address to memory

Q1. Assume memory is byte addressable and address is of size

14bit. Compute size of memory.
Ans

Using 14 bits how many address combinations we can generate?

2^14.

2^4 x 2^10 =16 K *1 Byte

= 16KB
Translation of Address to memory
Translate n bit address to memory

Q2. Assume memory is 2 Byte addressable and address is of

size 22bit. Compute size of memory.
Ans

Using bits how many address combinations we can generate?

2^22.

2^2 x 2^20 = 4M
4M x 2Byte= 8MB
Translation of Address to memory
Translate n bit address to memory

Q3. Assume memory is Byte addressable and address is of size

34bit. Compute size of memory.
Ans

Using bits how many address combinations we can generate?

2^34.

2^4 x 2^30 = 16G

16G x 1Byte= 16GB
Translation of Address to memory
Translate n bit address to memory

Q3. Assume memory is Byte addressable and address is of size

34bit. Compute size of memory.
Ans

A. 16GB
B. 8 GB
C. 32 GB
D. 14 GB
Translation of Address to memory
a) 210 means 1K i.e 1Kilo (1024)

b) 220 means 1M i.e 1Mega

c) 230 means 1G i.e 1Giga

d) 240 means 1T i.e 1Tera

e) 250 means 1P i.e 1Peta

No. of bits required to address memory
If memory size is given then compute how many bits are required
to address that memory.

Memory Size= Total no. of locations x size of each location

Total no. of locations= Memory Size/ size of each location

No. of bits required to address memory
Q1. Memory size is of 64KB. System is Byte addressable. How
many bits are required to represent 64KB?

Ans: 64KB/1B
= 64K

26 x 210= 216

Total 16 bits are required to rep. memory of 64 KB

No. of bits required to address memory
Q2. Memory size is of 32KB. System is Byte addressable. How
many bits are required to represent 32KB?

Ans: 32KB/1B
= 32K

25 x 210= 215

Total 15 bits are required to rep. memory of 32 KB

No. of bits required to address memory
Q2. Memory size is of 256MB. System is Byte addressable. How
many bits are required to represent 256MB?

Ans:
Total 28 bits are required to rep. memory of 256MB
Address Translation
How to break logical address into page number and page
offset?

Physical Address= frame x page size + offset

Example
Q. Using a page size of 4 bytes and physical memory of 32 bytes,
find the physical address if logical address is:
a) 4
b) 10
Solution:
Example- Page Table
Example
Q. Using a page size of 4 bytes and physical memory of 32 bytes,
find the physical address if logical address is:
a) 4
b) 10
Solution:
Note
if logical address space can hold 2^13 addresses:
Means
a) logical address is 13 bit long.
b) logical address space is 2^13= 8KB if system is Byte
addressable
Example
Q1. LA=24bit
PA=16bit
Page Size =1KB. System is byte addressable.
Find total number of pages and frames.
Sol:
We need to compute 4 things in sequence:
a) Total addressable locations from L.A and P.A
b) Total locations and offset from page size and total bits to
represent page size.
c) Total pages.
d) Total frames.
Example
Solution:
a)Total addressable locations from L.A and P.A: 2
pow(number of bits)
b)Total locations and offset from page size and total bits to
represent page size:
total addressable locations and offset = Page size/ size of
each location (i.e. byte addressable)
Find offset and divide LA into page and offset bits
Divide PA to frame and offset bits

a)Total pages: (2 power number of page bits)

b)Total frames: (2 power number of frame bits)
Example
Sol: Total addressable locations from 24 bits
224 = 24 x 220 = 16M
Every location is byte addressable
So Total memory:
16Mx1B= 16MB
Total addressable locations from 16 bits
216 = 26 x 210 = 64K
Every location is byte addressable
So Total memory:
64Kx1B= 64KB
c) Page size= 1KB
total addressable locations and offset = Page size/ size of each
location
= 1KB/1B
=1K locations
Example
c) Page size= 1KB
total addressable locations and offset = Page size/ size of each
location
= 1KB/1B
=1K locations
Total bits required to represent 1K locations:
210 i.e. 10 bits
So offset is 10bit.

d) Total pages with 14bit

214 = 24 x 210 = 16K pages
e) Total frames with 6bit
26 = 64 frame
Example
Q2. LA=33bit
PA=24bit
Page Size =2KB. System is byte addressable.
Find total number of pages and frames.
Sol:
a) Total pages = 4M
b) Total frames= 8K
Hardware Support: for Page Table
Implementation
Each operating system has its own methods for storing page
tables.
– Some allocate page table for each process
– Pointer to page table is stored with other register values (e.g.
instruction pointer) in PCB.
– When the dispatcher starts a process, It:
• Reload user register
• Define correct hardware page table value from stored user table

Page lookups must be done for every memory reference, and

whenever a process gets swapped in or out of the CPU, its
page table must be swapped, along with the instruction
registers.
Hardware Support: for Page Table
Implementation
1. Keep page table in a register .
2. Keep page table in memory but keep its initial address in a
register known as PTBR.
Disadvantage: two memory access
3. Use Translation Look Aside Buffer (TLB)
Hardware Support: for Page Table
Implementation
Hardware implementation of page table: Methods:
1. Use Registers
– One option is to use a set of registers for the page
table
– The use of registers for the page table is satisfactory if
the page table is reasonably small (for example, 256
entries).
– Most contemporary computers, however, allow the page
table to be very large (for example, 1 million entries).
– The use of fast registers to implement the page table is
not feasible.
Hardware Support: for Page Table
Implementation
2. An alternate option is to:

– Store the page table in main memory, and to use a

single register ( called the page-table base register,
PTBR ) to record where in memory the page table is
located.
– Process switching is fast, because only the single
register needs to be changed.
– The address of a page table in memory is pointed by:
page table base register
Hardware Support: for Page Table
Implementation
The problem with this approach is the time required to
access a user memory location.
 If we want to access location i, we must first index into
the page table, using the value in the PTBR offset by the page
number for i.
This task requires memory access. It provides us with the
frame number, which is combined with the page offset to
produce the actual address.

Two memory access

is needed to access a byte (one for the page-table entry, one
for the byte). Thus, memory access is slowed by a factor of 2.
Hardware Support: for Page Table
Implementation
– Solution to two memory accesses:
– Use a very special high-speed memory device called
the translation look-aside buffer, TLB.
– Each entry in the TLB consists of two parts:
– a key (or tag) and a value.
– When the associative memory is presented with an item, the
item is compared with all keys simultaneously.
– If the item is found, the corresponding value field is returned.
– The benefit of the TLB is that it can search an entire table
for a key value in parallel, and if it is found anywhere in
the table, then the corresponding lookup value is
returned.
Hardware Support: for Page Table
Implementation

– TLB is not large enough to hold the entire page table.

– So used as a cache device.
– The percentage of time that the desired information is found
in the TLB is termed the hit ratio.
– The percentage of time that the desired information is not
found in the TLB is termed the miss ratio.
Paging hardware with TLB
Example

– 40% slowdown to get the frame

Effective access time = hit ratio x time taken for TLB hit +
miss ratio x time taken for TLB miss
Example

Explanation:
- TLB hit takes 120 nanoseconds total ( 20 to find the
frame number and then another 100 to go get the data )
- TLB miss takes 220 ( 20 to search the TLB, 100 to go
get the frame number, and then another 100 to go get
the data.

- Effective access time = hit ratio x time taken for TLB

hit + miss ratio x time taken for TLB miss
Problem
Memory Protection
• It is accomplished by Protection Bits associated with each frame
→ Valid – Invalid Bit
• These bits are kept in page table
• Every reference to the memory goes through page table and finds
correct frame number.
• When bit is set to valid: indicates that associated page is in
process's logical address space and is valid page.
• When bit is set to invalid: indicates that associated page is not
in process's logical address space and is invalid page.
Memory Protection
 Overlays
• The main problem in Fixed partitioning is the size of a process
has to be limited by the maximum size of the partition. In order
to solve this problem, earlier people have used some solution
which is called as Overlays.
• The concept of overlays is that whenever a process is running it
will not use the complete program at the same time, it will use
only some part of it.
• Then overlays concept says that whatever program part you
required, you load it once the other part is done, then you just
unload it, means just pull it back and get the new part you
required and run it.
 Overlays
• “The process of transferring a block of program code or other
data into internal memory, replacing what is already stored”.

Sometimes it happens that compare to the size of the biggest

partition, the size of the program will be even more, then, in that
case, you should go with overlays.
• So overlay is a technique to run a program that is bigger than the
size of the physical memory by keeping only those instructions
and data that are needed at any given time.
 Overlays

What will be the maximum size of memory required to load and run this program?
Overlays
Segmentation
• It is a memory management scheme in which the memory
allocated to the process is non contiguous
• Logical address space is divided into number of small blocks
called segments
• Segments are of variable sized.

A C compiler might create separate segments for the following:

1. The code
2. Global variables
3. The heap, from which memory is allocated
4. The stacks used by each thread
5. The standard C library
Segmentation
• Users view memory as a collection of variable size segments.
With no necessary ordering of these segments

• Segmentation is memory-management scheme that supports user

view of memory

• A program is a collection of segments. A segment is a logical unit

such as:
main program, function, object, local variables, global
variables, data structures : stack, symbol table, arrays
User’s View of a Program
Logical View of Segmentation

1
4
1
2

3 2
4
3

user space memory space

Segmentation Architecture
• Each segment has a name and its length.
• Logical address consists of a two tuple:
<segment-number, offset>,
• Segment table – maps physical addresses; each table entry has:
– base – contains the starting physical address where the
segments reside in memory
– limit – specifies the length of the segment
• Segment-table base register (STBR) points to the segment
table’s location in memory
• Segment-table length register (STLR) indicates number of
segments used by a program;
segment number s is legal if s < STLR
Address Translation: Segmentation Hardware
Problems
Q1.if Segment 2 is 400 bytes long and begins at location 4300,
then a reference to byte 53 of segment 2 is mapped onto
location?
Ans: base address: 4300
Limit: 400
53<400 (I.e limit)
4300+53=4353.
Problems

Q2. A reference to byte 852 of segment 3 is mapped to?

Ans: 3200+852=4052.

Q3. A reference to byte 1222 of segment 0 is mapped to?

Ans: would result in a trap to OS, as this segment is only 1000
bytes long.
MCQ
1. Which one of the following is the address generated by
CPU?
a) physical address
b) absolute address
c) logical address
d) none of the mentioned
MCQ

c) logical address
MCQ
2. Memory management technique in which system stores and
retrieves data from secondary storage for use in main
memory is called
a) fragmentation
b) paging
c) mapping
d) none of the mentioned
MCQ
2.
b) paging
MCQ
3. The address of a page table in memory is pointed by
a) stack pointer
b) page table base register
c) page register
d) program counter
MCQ
3.
b) page table base register
MCQ
4. Program always deals with
a) logical address
b) absolute address
c) physical address
d) relative address
MCQ
4.
a) logical address
MCQ
5.
The page table contains
a) base address of each page in physical memory
b) page offset
c) page size
d) none of the mentioned
MCQ
5.

a) base address of each page in physical memory

MCQ
6.
Operating System maintains the page table for
a) each process
b) each thread
c) each instruction
d) each address
MCQ
6.

a) each process
MCQ
7. Locality of reference implies that the page reference being made
by a process
a. will always be to the page used in the previous page reference.
b. will always be to the page used in the previous page reference.
c. will always be to one of the pages existing in memory.
d. will always lead to a page fault.
MCQ
Ans 7: b