MAIN MEMORY

One of the functions of the operating system is memory management. It manages

the main memory and the movement of the process during its execution. Memory
management keeps track of the memory location. This presentation discusses the
mechanisms on how to obtain optimal memory.

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Topics

■ Background
■ Swapping
■ Contiguous Memory Allocation
■ Segmentation
■ Paging
■ Structure of the Page Table
■ Example: The Intel 32 and 64-bit Architectures
■ Example: ARM Architecture

2
Objectives

■ To provide a detailed description of the different ways on

organizing a memory hardware
■ To provide details on various memory-management techniques

3
 Background on Main Memory

■ Consists of large array of words or bytes

■ Program must be brought (from disk) into memory and placed
within a process for it to be run
■ Memory unit only sees a stream of addresses + read requests, or
address + data and write requests
■ Register access in one CPU clock (or less)
■ Main memory can take many cycles, causing a stall
■ Cache sits between main memory and CPU registers
■ Protection of memory required to ensure correct operation

The following are some important point we need to know about the main memory.
A memory contains a large array of words and bytes placed in their own addresses.
These instructions which are stored from disk are brought to the memory and are
placed in the cpu for processing based on the program counter.
The CPU can access only the memory and registers.
And Registers are the fastest storage devices; furthermore, it can access in one CPU
clock or less.
Since the memory can take many cycles and the registers can take a clock cycle or
less, it may cause a stall. A stall means a temporarily slowing down of the process. A
solution to this is by using cache.
Cache sits between main memory and CPU registers as a solution to the stalling
problem.
Memory protection is required to ensure correct operation. It is a way of controlling
the memory access rights, to prevent any access from a process which has not been
allocated to it.

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 Main Memory or Physical Memory

- RAM
- Internal memory
- Physical memory

The main memory can be referred to as RAM or random access memory, internal
memory or physical memory. In our discussion, we may use any of these terms.
Secondary storage on the other hand are the hard disks or flash drives.
The operating system is the first program loaded in the memory. It usually occupies
the lower address of the memory for faster access since it is nearer to the hardware
for interrupts.
The table in the slide is the block diagram of the main memory. The numbers at the
left side are addresses and are expressed in decimal. Processes are placed
contiguously in the main memory. Not all processes or programs stored in the hard
disk are allocated space in the main memory. Only those processes that are to be
executed are placed in the memory. The problem is that the memory size is not that
large. The applications that we are running in our computers or devices demand
memory space for its execution.
So if we have 2GB of main memory, and our applications need millions of bytes of
memory space, and we run applications concurrently, how can this be managed by
the system?
The mechanism to resolve this issue and much more are tackled in this module.

5
 Basic Concept of Memory Hardware

The CPU can only access the main memory and the registers. Instructions or data
from secondary storage devices have to be brought to the memory for the CPU’s
execution.
CPU registers are accessible within one cycle of CPU clock.
But the memory takes many cycles of the CPU clock to complete.
In this case, the cpu has to stall since it needs the data from the memory and this can
cause a problem. A solution to this is to add a cache or a fast memory between the
cpu and the main memory. A cache is a memory buffer that will accommodate the
speed differential between the 2 devices.
In the memory, there will be many processes. Processes must be protected such that
they will not be accessed by other processes. This protection can be provided by the
hardware.
Processes are placed in legal addresses. These addresses refer to addresses assigned
to the user process. It cannot use the operating system’s address space. And to
protect the user processes, we need 2 registers , namely, the base and limit registers.
The base registers stores the smallest physical memory address while the limit
register specifies the size of the range.
In this example, the base address is 300040 and the limit address is 120900. this
means that the program can access addresses from 300040 until 420940 (that is

6
300040+120900).

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 Hardware Address Protection

This flowchart serves as the trap for processes that will try to access other processes
in the memory.
To protect a memory space, the CPU hardware compares the address generated in
user mode with the registers. A program executing in the user mode that will try to
access the operating system’s memory or other user’s memory, will be trapped by the
operating system and will be treated as fatal error.
in addressing a process, we need the base and limit registers. These registers are
loaded by the operating system. Since it is only the operating system that can operate
in the kernel mode, then it implements a special privilege instruction that can change
the values in the registers. Other user programs do not have access or are not
allowed to modify the contents of the registers.

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 Address Binding

■ Is the process of mapping from one address space to another

address space
■ Logical address - address generated by the cpu during the process
execution
■ Physical address - is the address where the process was loaded in the
memory

Address binding Is the process of mapping from one address space to another
address space.
It makes use of logical address and physical address. These are the two types of
addresses.
A logical address is the address generated by the cpu during the process’ execution.
And a physical address refers to the location in the memory unit or it is the address
where the process was loaded in the memory.
The logical address is translated by the MMU or Memory Management Unit which
generates the physical address of the process in main memory.

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 Address Binding

■ 3 ways for Address binding

– Compile time – generates absolute code if uses a priori of the
physical address of the code
– Load time - Must generate relocatable code if memory
location is not known at compile time
– Execution time - Binding delayed until run time if the process
can be moved during its execution from one memory
segment to another

There are three ways to bind addresses, and these are at compile time, load time and
execution.
Compile time: An absolute code is generated if the physical address of the process is
known before compile time. (the physical address is embedded in the executable of a
program during compilation)
If the absolute code is known at a later time, tendency is that the code will be
recompiled.
Load time: Must generate relocatable code if memory location is not known at
compile time. The loader translates the relocatable address to absolute address. To
generate an absolute address, the base address of the process is added to the logical
address by the loader. In this case, if the base address changes, the process will be
reloaded.
Execution time: Binding delayed until run time if the process can be moved during its
execution from one memory segment to another
- Need hardware support for address maps (e.g., base and limit registers)

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 Multistep Processing of a User Program
From source
Count
code

(when compiled)
14 bytes from beginning of Count
module Source code

Relocatable address – address

that is adjusted for the process
that is to be executed

(When linked) 74102 Count

A B

In this slide, we have 2 figures. Figure B represents the flowchart of the different
steps that a process may go through. And in figure A, it represents an example of a
variable until it will have an absolute address.
Any user program may go through several steps; consequently, there will be different
ways in addressing. An address in the source code (such as count variable) is symbolic
and a compiler will bind this symbolic address to a relocatable address. A relocatable
address will simply be placed in an address before the module, example: count is
placed 14 bytes from the beginning of the module)The linkage editor or loader will
bind the relocatable address to absolute address (an example of this bounded
address 74102).

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 Logical Address Space and Physical Address
Space
■ Logical Address - the set of all logical addresses generated by a
program
■ Physical Address - refers to the set of all physical addresses that
correspond to these logical addresses
■ For compile time and load time address binding – same physical
and logical address space
■ For execution time – different physical and logical address spaces

Logical address is the address generated by the cpu while the physical address is the
address seen by the memory unit or the address which refers to the location in the
memory unit.
The compile time and load time binding methods generate the same logical and
physical addresses, unlike the execution time binding scheme where it generates
different logical and physical addresses.
Logical address is referred as virtual address.
A logical address space is the set of all logical addresses generated by a program and
a physical address space refers to the set of all physical addresses that correspond to
these logical addresses.
This is how it is in the execution time binding address scheme.

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 Memory Management Unit (MMU)

■ Computer hardware component that handles the memory and

caching operations associated with the processor
■ Memory mapping - translates addresses between the CPU and
physical memory
■ Example: Base-register scheme

Memory Management Unit is a computer hardware component that handles the

memory and caching operations associated with the processor.
Its task is to execute the run-time mapping from virtual to physical addresses.
A simple mapping uses the base-register scheme. The base register is referred as the
relocation register.

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 Relocation Register or Base-Register Scheme

– Base register = relocation

register
– Relocation register is added
to every address generated
by the user process when it is
sent to the memory
– Implements dynamic
loading
– Routines are kept on disk in
a relocatable load format
Dynamic Relocation using a
Relocation Register
Operating System Concepts, 9th edition Siberscahtz, Gelvin, and Gagne

The job of the MMU is to map virtual address to physical address.

In this figure, we have the memory, MMU and the CPU. The base address is at 14000.
if the user attempts to use address 0, then it will have a relocated address at 14000
(since base is 14000+0). If there is an access to address 234, then, its physical address
will be 14234.
The user program does not have any idea on the physical address of the process. It
deals with logical addresses.
The user generates logical addresses and these are mapped to physical address
before they are used.
The logical address space, therefore, is bound to the physical address space.
The routine or instruction is not loaded unless it is called. (standbys not allowed) This
is referred to as Dynamic Loading.

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 Dynamic Loading

■ Better memory-space utilization

■ loads a routine only when it is called
■ operating system only provides the library routines to implement
dynamic loading

In a program execution, the entire program is loaded to the memory. The size of a
process is limited to its physical memory space.
Dynamic loading obtains a better memory-space utilization. It loads a routine only
when it is called. All routines are placed on disk in a relocatable load format.
When the routine is for execution, it is loaded to the memory.
And when a routine calls another routine, the calling routine checks if the routine
called is loaded; otherwise, it calls the relocatable linking loader to load the called
routine into the memory and update the program's address table. Then the control is
passed to the called routine.
Dynamic loading is implemented by user programs. The operating system only
provides the library routines to implement dynamic loading.

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 Static and Dynamic Linking

■ Static Linking - system libraries and program code are combined

by the loader into the binary program image
– Disadvantage: every program must have its own copy of the
system library functions.
■ Dynamic Linking – uses shared libraries when compiling programs
– Useful for libraries

Static linking is when the system libraries and the program code are combined by the
loader into the binary program image
Example: when we run an exe (.exe) file, everything in the binary file are loaded into
the virtual address space of the process.
But other programs also need to run functions from the system libraries. And if these
libraries will be used, then then they will be loaded.
In this case, the libraries are embedded in the executable binary file. The program is
statically linked to its libraries and the linked codes are loaded once they are
executed.
A Disadvantage on static linking is that every program must have its own copy of the
system library functions, which could take up more memory space.
On the other hand, Dynamic linking uses shared libraries when compiling programs
and these shared libraries are dynamically linked to the program. The libraries are
linked only during at run time.

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 Swapping

■ Mechanism wherein a process is swapped out of the memory to a

backing store.
■ Backing store – fast disk large enough to accommodate copies of
all memory images for all users
– must provide direct access to these memory images
■ Roll out, roll in – variant in swapping policy
– Implemented in higher priority and low priority processes

Swapping takes place in the memory. Swapping is a mechanism where a process is

swapped out of the main memory to a backing store. The swapped area in the
memory is made available for other processes.

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 Swapping

Schematic View of Swapping

Operating System Concepts, 9th edition Siberscahtz, Gelvin, and Gagne

In this figure, process P1 is swapped out of the memory while Process 2 is swapped
in.
Let us have a round robin execution as an example for swapping scheme. When a
process finishes its time quantum, it is swapped out, and another process will be
swapped in the memory.
The swapping concept is also applied in priority-based scheduling algorithms. When a
higher priority process enters the ready queue, then, the memory manager can swap
it with lower priority processes. Then when the higher priority process is finished
executing, the lower priority is swapped in back to the memory. The state of the
lower priority process is stored in the PCB, that’s why the lower priority can return
back to its previous state. This variant of swapping for priority processes is called roll-
in and roll out.
The system has a ready queue. When the cpu scheduler schedules a process for
execution, it calls a dispatcher. Example a process P1 is to be executed next by the
cpu. The dispatcher checks if P1 is in the ready queue. If the process is not in the
ready queue and if there is no free memory, then the dispatcher swaps out a process
and swaps in P1.

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Context Switch Time

■ Involves storing the context or state of a process so that it can be

reloaded when execution is resumed
■ Example: user process is 10MB, backing store (hard disk) has a
transfer rate =40MB/sec
The transfer rate of the 10MB file to and from the memory is:
= (10MB ) / (40MB/sec)
= ¼ sec or 250 milliseconds
If there is an average latency of 8ms, the swap time = 258ms
Swapping in and out = 516ms.

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 Swapping on Mobile Systems
■ Not typically supported
– Flash memory based
■ Small amount of space
■ Limited number of write cycles
■ Poor throughput between flash memory and CPU on mobile platform
■ Instead use other methods to free memory
– iOS asks apps to voluntarily relinquish allocated memory
■ Read-only data thrown out and reloaded from flash if needed
■ Failure to free can result in termination
– Android terminates apps if low free memory, but first writes application state
to flash for fast restart

Operating System Concepts, 9th edition Siberscahtz, Gelvin, and Gagne

Mobile systems are flash memory based. Flash memory is non-volatile

computer memory. It can be electrically erased and reprogrammed. It may use NOR
and NAND flash. This is used in flash drives and in mobile devices.
In iOS Swapping, if the fone experiences low memory, the systems asks the
application to release its allocated memory. The read only data are thrown out of the
memory and are reloaded if needed. If the system cannot free the memory space,
then the application is terminated.
Android’s implementation is quite different. If it experiences low memory, then it first
stores the application state to flash memory, then, it terminates the application.

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 Contiguous Memory Allocation

■ The memory must accommodate user processes and the operating

system
■ The lower memory – where the operating system is locates
■ High memory – for user processes
■ Relocation registers used to protect user processes from each other,
and from changing operating-system code and data
– Base register contains value of smallest physical address
– Limit register contains range of logical addresses – each logical
address must be less than the limit register
– MMU maps logical address dynamically

In contiguous memory allocation, the memory must accommodate user processes

and the operating system.
There are basically 2 partitions of the memory, the resident operating system and the
user processes.
Programmers usually place the operating system in the lower memory because it is
where the interrupt vectors are located.
Swapping In contiguous memory relocation makes use of Relocation registers. These
registers used to protect user processes from each other, and from changing
operating-system code and data.
It also makes use of base registers which contains the value of smallest physical
address.
Limit register contains range of logical addresses which should be less than the limit
register
And for mapping logical and physical addresses, the MMU maps the addresses
dynamically.

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 Memory Mapping and Protection
500 100040

Hardware Support for Relocation and Limit Registers

Operating System Concepts, 9 th edition Siberscahtz, Gelvin, and Gagne

This hardware support for relocation and limit registers is quite the same with the
process on hardware address protection.
The relocation register contains the value of the smallest physical address and the
limit register contains the range of logical addresses.
Example: if the relocation register is 100040 and the limit register is 500, then, each
logical address must be less than 500.
The MMU or the Memory Management unit maps the logical address dynamically by
adding the relocation register.
The relocation register provides a way to change the operating system size
dynamically. Only the called process is loaded in the memory.

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 Multiple Partition Allocation
■ Multiple-partition allocation
– Degree of multiprogramming is limited by the number of partitions
– Variable-partition sizes for efficiency (sized to a given process’ needs)
– Hole – block of available memory; holes of various size are scattered throughout memory
– When a process arrives, it is allocated memory from a hole large enough to accommodate it
– Process exiting frees its partition, adjacent free partitions combined
– Operating system maintains information about:
a) allocated partitions b) free partitions (hole)

a b c d

Operating System Concepts, 9th edition Siberscahtz, Gelvin, and Gagne

In a multiple partition allocation, the degree in multiprogramming is limited by the

number of partitions. Here, we have variable partitions whose sizes depend upon the
size of the processes. The hole is a block of available memory which is scattered in
the memory.
When a process arrives in the memory, it is allocated a space in the memory, and
when a process has finished its execution, it frees up tis space in the memory.
Let us refer to the 4 memory locations. In figure a, the memory is full. In figure b,
process 8 exits and frees up the space. In figures c and d, process 9 and 10 are
allocated in the freed up space by process 8. and still, there is a free space in the
memory.
The operating system needs information on allocated partitions and free partitions.

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 Static and Dynamic Memory Allocation

■ Static Memory Allocation - declaring variables before runtime

– Example:
F1{
int sum =0;
……. }
■ Dynamic Memory Allocation – assigning a memory space during
runtime

Lets us differentiate these two types of allocations.

Static memory allocation is an allocation technique which allocates a fixed amount
of memory during compile time and the operating system internally uses a data
structure known as Stack to manage this
Dynamic memory allocation - is when an executing program requests that
the operating system give it a block of main memory.

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 Dynamic Storage-Allocation Problem

Most commonly used strategies:

■ First-fit: Allocate the first hole that is big enough

■ Best-fit: Allocate the smallest hole that is big enough; must search
entire list, unless ordered by size
– Produces the smallest leftover hole

■ Worst-fit: Allocate the largest hole; must also search entire list
– Produces the largest leftover hole

Operating System Concepts, 9 th edition Siberscahtz, Gelvin, and Gagne

With dynamic allocation, requesting memory space during runtime, can cause a
problem. It may be that there is no available space at that instant.
The dynamic storage-allocation problem is concerned on how to give of free holes to
a requesting process. Free holes would refer to free memory space.
There are advantages and disadvantage of the different strategies.
We have the following strategies:
--first fit
--best-fit
--and worst-fit

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 Fragmentation

■ External fragmentation – total memory space exists to satisfy a

request, but it is not contiguous
– Solution:
■ compaction - possible if dynamic relocation
■ Paging and segmentation
■ Internal Fragmentation - when allocated memory may be slightly
larger than requested memory; this size difference is memory
internal to a partition, but not being used

Fragmentation refers to the small free spaces left after processes are loaded and
freed from the memory. This usually is generated after files are created, deleted and
modified.
Memory fragmentation can be external or internal.
External fragmentation is when processes are loaded to freed up memory spaces and
these memory spaces are not contiguous. When a process has finished it is now
removed from the memory.
Internal fragmentation is when allocated memory may be slightly larger than
requested memory; this size difference is memory internal to a partition, but not
being used
One example is when the free space is 100Mb and the process size is 800MB, the
700MB is unused. This unused space can be assigned to another process.
The solution for external fragmentation is compaction, that is to shuffle the memory
contents and place the memory together in 1 block. This is possible only If dynamic
relocation

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 First-Fit Memory Allocation
■ Searching for the first available free space – start of the beginning of
wholes or where the first-fit search ended
Example:

Given the following Size

Jobs (in order), how
would these jobs fit in Jobs Size (KB) 60KB 10KB
or be allocated in the
four memory A 80 90KB 10KB
partitions? B 120
C 180
200KB 30KB
D 50

Job C waits 130KB

The memory must always be updated with free memories and used memories. It is in
the free partitions that the processes are placed or allocated.
The first-fit memory allocation allocates the first available block/space that is big
enough for a process/job.
Two implementations:
--if searching for available space is always at the top/beginning <>
----Job A fits the 90KB hole, then again search from start, Job B can be allocated to
the 200KB block, Job C cannot be allocated anymore, so it waits for a block to be
freed up. Job D takes the 60KB hole.
The gray boxes indicate the unused spaces during the allocation. And to sum it up,
there is 50KB unused space.
--if search starts where first-search ended <>
----Job A fits the 90Kb hole, then this time, we search starting at the next free space,
where we had our last first-fit allocation. Job B is allocated to the 200KB block.
Locating an available space for Job C, since the last free space is too small for the job,
then, we can start our search from the start. Still, no block can allocate job c. So it
waits for a free space. Then lastly, we have Job D. The last first-fit allocation was on
block 200KB. After allocating 120KB of the 200Kb block, it now leaves us with 80KB
unused space. Job D, therefore can use this space. This is an example of internal

26
fragmentation.

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 Best-Fit Memory Allocation
■ allocates the smallest free partition that is close to the actual size of
the job or process
Given the following
Jobs (in order), how
Size
would these jobs fit in
or be allocated in the 60KB 10KB
Jobs Size (KB)
four memory
partitions? A 80 90KB 10KB
B 120
C 180
200KB 20KB
D 50

130KB 10KB

The next algorithm is the Best-Fit Allocation. It allocates the smallest free partition
that is close to the actual size of the job or process. This algorithm searches the entire
list of free partitions and considers the smallest hole that is big enough of the job or
process.
Let us use the same example.
We shall be searching the entire list of free locations in the memory. <>
So, first is Job A with 80KB fits in 90KB location.
Job B fits well with 130KB. Job C with 200KB and Job D with 60KB.
Now let’s check the unused spaces: <> When we sum up the unused spaces, we only
have 50KB.

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 Worst-Fit Memory Allocation
■ Searching the list for the largest whole
Example:

Given the following Size

Jobs (in order), how
would these jobs fit in Jobs Size (KB) 60KB
or be allocated in the
A 170 90KB 40KB
four memory
partitions? B 120
C 180
200KB 30KB
D 50

130KB 10KB
Job C waits

The Worst-Fit algorithm searches for the largest whole for a process.
For example: <>Job A is allocated the 200KB block. Job B is allocated the 130KB
block. Job C has to wait since there is no free block that s large for it. And Job D has to
be allocated to 90KB block. For Worst-fit, the system selects the largest whole for the
process/job.
And for the total unused space, for worst fit it is 170KB.
So, what do we do with the unused space?

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 Internal Fragmentation
Suppose that the following Jobs (in the order below) are to be allocated in these
five memory partitions of 200Kb, 100Kb, 500Kb, 300Kb and 450Kb. Use the Best-Fit
Algorithm.
Jobs Size Size
Size Size
(Kb) B
200K 200K
B
200K D
B(80) D
A 65 b b b F
(40)
100K (10)
B 120
A(35) 100K
b A(35) 100K
C 280 b A(35)
b
D 40 500K
b 500K
500K
E 125 b
b
F 30 300K
C(20) 300K
b C(20) 300K
G 130 b C(20)
b
450K
b 450K E
E(325) 450K
b G
b
(195)

The Internal fragmentation implementation is applicable to any of the algorithms.

In this example, we shall be placing the jobs in the black table to the free memory
partitions, using the Best-fit algorithm. We search for the whole list for a free space
that fits enough for the job.
We first search a block for job A. 100Kb block is allocated to A, leaving 35Kb unused
space. Job B is assigned to 200Kb bock, with an unused space of 80Kb. Job C is
allocated to 300Kb with 20Kb unused space. Job D with 40Kb can be assigned to the
unused space in the first block. <>
The unused space in block 1 is 40Kb. Job E is placed in the last block leaving 325Kb
unused space. Job F and G can fit into the first and last blocks respectively. The
unused space in the last block can still be utilized by a process.

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 Segmentation

■ Memory-management scheme that gives the user’s view of the

process
■ A program is divided into segments and a segment is a logical unit.
Examples: main program, procedure , function, method
object, local variables, global variables
common block, stack, symbol table, arrays

Memory-management scheme that gives the user’s view of the process.

We see a program as a set if instructions and variables; however, a program can be
divided into segments and each segment is a logical unit.
Examples of segments from a program: main program, procedure , function, method,
object, local variables, global variables, common block, stack, symbol table, and
arrays

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 Segmentation: User’s View of a Program

Operating System Concepts, 9th edition Siberscahtz, Gelvin, and Gagne

This is a user’s view of a whole program. The program is divided into segments.

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 Logical View of Segmentation
1

4
1

3 2
4

user space physical memory space

Operating System Concepts, 9th edition Siberscahtz, Gelvin, and Gagne

This is the logical view of the different segments in a program. Each segment has a
location in the memory and this is how a segment is accessed in the memory. It
makes use of addresses. We see our variables as words, but the memory sees it as a
location.
Each segment has a different address.

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 Segmentation
Main
Process Segment Table
Memory
Segment Size Memory
No. address
Segment 1 1 200 100 100

2 100 500 200

Segment 2 3 400 300
300

400
Segment 3
500

600

Segmentation divides the job into different sizes of segments. Each segment has a
logical address space of the program
When a process is executed, the different segments are placed in different available
blocks in the memory.
The operating maintains a segment map table for every process. The segment table
contains the starting address of the segment and the size of the segment. Each
segment has its own memory address.
To refer to the main memory, it uses the segment and the offset value.

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 Paging

■ memory-management scheme that permits the physical address

space of a process to be noncontiguous
■ Avoids external fragmentation
■ Uses frames and pages
■ breaking physical memory into fixed-sized blocks called frames
– Size is power of 2, between 512 bytes and 16 Mbytes
■ breaking logical memory into blocks of the same size called pages
■ Keeps track of all free frames

Paging is a memory-management scheme that permits the physical address space of a

process to be noncontiguous. This scheme avoids external fragmentation but has a
disadvantage of an internal fragmentation. Paging allows the operating system to retrieve
processes from the secondary storage to the main memory.
The main memory is divided into frames. Frames are fixed sized blocks in the physical
memory while pages are blocks of the same size in the logical memory.
When a process is to be executed, its pages are loaded to any available frames in the backing
store. The backing store is also divided into pages.
Pages keeps track of free frames and makes use of page tables.

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 Paging: Address Translation Scheme

■ Division of an address from the CPU:

– Page number (p) – used as an index into a page table which
contains base address of each page in the physical memory
– Page offset (d) – combined with base address to define the
physical memory address that is sent to the memory unit

page number page offset

p d
m -n n
For given logical address space 2m and page size 2n

An address generated by the CPU is divided into page number and page offset.
The page number (p) is used as an index into a page table which contains base
address of each page in physical memory.
And the page offset(d) is combined with the base address to define the physical
memory address that is sent to the memory unit

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 Paging Hardware

Hardware support for Paging

Operating System Concepts, 9th edition Siberscahtz, Gelvin, and Gagne

This is the hardware support for paging.

The cpu generates an address which is composed of the page number(p) and
offset(d). The page number is used as an index to a page table.
The page table contains the base address of each page in the physical memory. The
base address together with the offset defines the physical memory address.

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 Paging Model of Logical and Physical Memory

Operating System Concepts, 9th edition Siberscahtz, Gelvin, and Gagne

The figure contains a logical memory, page table and physical memory. The page size
is defined by the hardware. The size of the page is in the power of 2 from 512 bytes
to 16MB per page.
The logical memory contains 4 pages, from page0 to page3.
The page table stores the page number and the frame number.
For example: page 2 in the logical memory has a frame address of 3 in the physical
address. In the page table, we can easily see 2,3 which defines page2 and frame
address3.

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 Paging Page
no.
Example 0

1
The size of the page table is , where n=2 2n
and the size of the logical memory is 2m 2
(where m=4). The logical memory has 4
byte-page size and the physical memory 3
of 32 bytes (8 pages).
Ex: In the logical memory,
“a” or logical address 0 is located in Page
0 and offset 0.
“b” or logical address 1 is located in Page
0 and offset 1.
What is the physical memory address of
“b” or logical address 1?
Specific address = (5x4) + 1 = 21

n=2 and m=4 32-byte memory and 4-byte pages

Operating System Concepts, 9th edition Siberscahtz, Gelvin, and Gagne

When a process is to be executed, the system has to know its size. Each page of the
process needs one frame. A process needing 3 pages, needs 3 frames. When a
process arrives, the first page is loaded into one of the free frames. The page number
and frame number are placed in the page table.
The size of the page table is 2^n , where n=2 and the size of the logical memory is
2^m (where m=4). The logical memory has 4 byte page size and the physical memory
of 32 bytes (8 pages).
For example: “a” is located in page0, offset 0. The logical address 0 is page 0 and
offset 0. In the page table, we see that page 0 is mapped to frame 5 in the physical
memory which has the
specific address = (5 x4)+0; where 5 is the frame size, 4 is the page size and 0 is the
offset.
Lets have another example:
Logical address 9 is in page 2, offset 1. in the page table, page 2 is mapped to frame1.
the physical address = (1x4)+1 = 5
And for logical address 14. it is in page3, offset 2. in the page table, page 3 is mapped
to frame 2. physical address = (2x4)+2 = 10
In this structure, we can say that paging is a dynamic relocation.

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 Free Frames

Before allocation After allocation

Operating System Concepts, 9th edition Siberscahtz, Gelvin, and Gagne

Page keeps track of free frames.

In the list, the available frames are 14, 13 , 18 20 and 5.
Example: In figure A, there are free frames (frame 13,14, 18, 20 and 15). If there are
processes arriving, the first page of the first process will be loaded to a free frame. .
The first page of the process is placed into one of the free frames. Then the page
table is updated with the page number and frame number.
So, in the memory, page 0 is loaded to frame 14. and after the 2 other pages are
allocated with the other free frames. Then, the system updates the page table
specifying the page number with its frame number.

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 Page Table - Implementation
■ PTBR (Page-Table Base Register) –
points to the page table
■ PTLR (Page Table Length Register) –
specifies the size of the page table
■ TLB (Translation Look-aside Buffers) -
memory cache used to lessen the time
to access a user memory location
– Also called Associative Memory
■ Two Memory Accesses for data /
instructions
– Page table
– Data / instruction

The page table is paced in the main memory. It contains PTBR and PTLR.
PTBR or page table register points to the page table.
PTLR or page table length register indicates the size of the page table
The page table is implemented such that the data/instruction are required two
memory accesses namely:
-- to access page table
-- to access data/instruction
The TLB is a memory cache used to lessen the time to access a user memory location.
It uniquely identifies each process in providing its address-space protection. The TLB
usually have 64 to 1,024 entries.
In the TLB comparison, it makes a parallel search. The logical address contains p and d
(for its page transaltion). If the page number p, is in the TLB, them the system will
retrieve the frame number (in the diagram, refer to “TLB hit”); otherwise, the frame
number is retrieved from the page table in the memory (refer to TLB miss).

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 Internal Fragmentation on Paging

Example:
■ Page size = 2,048 (size = 2n )
■ Size of process = 58,800 bytes
■ No. of pages = 28 and excess bytes = 1,456

It was mentioned earlier that when a process is executed, its size has to be verified
because the process will be placed in pages. So, if the size of the process is 58,800
bytes, and the page size is 2,048, then ,the no. of pages needed for this process is 28
pages, with an excess of 1,456 bytes. The remaining bytes are still placed in a page
but with free space.
If the size of the remaining page is just a few bytes (like 2 bytes), then there will be
internal fragmentation.
Another disadvantage of paging is having a page table can consume additional
memory.

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 Internal Fragmentation
■ Example: The following are logical address references (in decimal), what
are their page numbers and offsets? Assume that the page size = 1KB
a) 2314
b) 9467
c) 900000
d) 55000

Logical Address Page number Offset

2314 2 266
9467 9 251
12000 11 736
1800 1 776

To solve for the page number and offset, first is to get the exact amount of 1KB, then
divide this from the given logical address. The remainder is the offset.

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 Example: Consider a logical address space of 64 pages of 1024 words each,
mapped onto a physical memory of 32 frames. How many bits are in the
logical address and physical address?

Logical address: pages: 2^6 + 2^10 = 16 bits

Physical address: frames: 2^5 + 2^10 = 15 bits

To compute for the

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 Protection

■ Protection in a page environment makes use of protection bits which

are associated with each frame.
– Valid and invalid bits
■ The bits are placed in a page.

Protection in a page environment makes use of protection bits which are associated
with each frame.
The bits are placed in a page, which may be read-write or read-only . Lets have one
example on this.

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 Page: Protection (Valid or Invalid)

8 pages = 16383/2048
Example:
A 14-bit address space (where: 214
= 16,384) (address is: 0-16,383)
A process is addressed to pages 0-
10,468
Page size = 2KB
Process uses 5 pages: 10,468/2048
Pages: 0-4
page 5 = 228 bytes (excess from
10,468%2056)

Operating System Concepts, 9th edition Siberscahtz, Gelvin, and Gagne

In paging, the memory is protected by adding bits to the frames in the page table. A
bit can be read-write or read-only.
Every process that is to be executed is referenced through the page table. With the
additional bits. The system identifies if a process is allowed to write to a frame.
A valid or invalid bit is added to the page table. A valid bit means that the page is in
the logical address space of the process and is considered as a legal page. However,
an invalid page means that the page is not in the process’ logical address space. The
operating system sets a page to “invalid” if a process is not allowed to access the
page.
Example: (refer to slide example)
A 14-bit address space (where: 214 = 16,384) (address is: 0-16,383)
Page size = 2KB
The system has 8 pages.
A sample process is addressed to pages 0-10,468
It therefore occupies 6 pages with the last page containing 228 bytes only.
Pages: 0-4 has 2048 bytes each (pages size) (5 pages)
page 5 = 228 bytes ( the excess bytes)
If there is an attempt to access page 6 or 7, then, an error will be generated.
It is possible though that another bit can be added to the page table that will indicate

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that the page is execute-only.

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 Shared Pages

■ Shares common code (time-sharing environment), reentrant code

■ Similar to threads implementation in sharing the memory space
■ Reentrant code – doesn’t change during execution
– Each process :
■ can execute the same code at the same time
■ has its own registers and data storage
■ has its own data
Example:

An advantage in shared pages concept is its ability to share pages. This is used in
time-sharing environment.
It can be implemented using reentrant codes.
A Reentrant code is a program written so that several users can share the same copy
of the program in the memory.
It does not change during execution.
Each user can execute the same code at the same time.
Each process has its own registers, data storage and data.

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 Shared Pages

Example:
A text editor that
shares it code to 40
users.
Text editor = 150KB
code
Data space = 50KB

Let’s have an example on shared pages.

Consider text editor code where it has 150Kb and data space of 50KB. If there are 40
users, then, the system needs 200KB per user, with a total 8,000KB (that is for all
users).
If a reentrant code is used, then, the system only needs 150KB +(40*50KB) = 2,150KB
storage space.
In the diagram, considering a 50KB page size for the text editor. With 150KB size, it
has 3 pages. These pages are labeled as ed1, ed2 and ed3.
Each process uses the same text editor. In shared pages, each process is mapped to
the same frame where the editor pages are located. Each process has its own data
storage.

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Page Table

■ Hierarchical Paging
■ Hashed Page Table
■ Inverted Page Table

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 Hierarchical Paging

■ Referred as Multilevel Paging

■ Page tables are stored in the memory

Hierarchical paging is also referred as multilevel paging. The entries of the first level
table are pointers to the level 2 page table, and entries of level 2 are pointers to level
3 page table, and so on.
All page tables are stored in the memory.

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 Two Level Paging
Example:
- A logical address of 32 bits
machine with 4K page size)
- Page number -> 20 bits
- 10 bit page number
- 10 bit page offset
- Page offset -> 12 bits

212

Page Offset

10 10 12

In this example of a two level page table,

Let us assume that the logical address of a system is 32 bits and the page size is 4KB.
The page number is 20 bits and the offset is 12 bits. (why 12bits for offset, because
the page size is 4KB = 2^12)
Since this is 2 level paging, then we further page the table with 10 bits for page
number and 10 bits for the offset number.
In the figure, the outer page (p1) is mapped to the offset within the page of the inner
page table.

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 Hashed Table Paging

■ Used for address spaces larger than 32 bits

■ Hashed value is the virtual page number
■ The virtual page number are the bits that are not part of the page
offset.
■ Each entry in the hash table has a linked list of elements hashed to
the same location
■ 3 fields for each element in the hash table
– Virtual page number
– Value of mapped page frame
– Pointer to the next element in the linked list

The Hashed table paging is an approach for address spaces larger than 32 bits. The
hash value is the virtual page number. Each entry in the hash table is linked to

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 Hashed Table Paging

Virtual page 1 Virtual page 2

Hashing is indexing an original value.

The algorithm of hash table paging starts with the system hashing the virtual page
number in the virtual address into the hash table.
--The virtual page number is compared with the first field in the linked list
--If the virtual page number matches with the first field in the linked list, then field 2
in the page frame forms the physical address; otherwise, the system continues to
search for a match.
--if there is no match, the system searches for other virtual page number entries.

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 Inverted Page Tables

■ Maintained by the operating system for all processes

■ Consists of one page table entry for every frame in the memory
■ A single page table represents the paging information of all the
processes
■ Decreases memory storage
■ Increases time in searching the table
■ Has only one page table in the system

Inverted page table is a global page table that is maintained by the operating system
for all processes. Then umber of entries equals the number pf frames in the memory.

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 Inverted Page Tables

Where:
P=page number
d = offset
Pid = Process ID

The Inverted page table consists of one-page table entry for every frame of the main
memory.
In the diagram, the logical address contains the process ID, page number and offset.
The page number specifies the page number range of the logical address.
The process ID is included in the page table because two processes can have the
same set of virtual addresses. The PID serves as an address space identifier that is
used to its corresponding frame addres.
The page table can also have an additional bit, and that is the control bit that gives
information like valid or invalid bit.
How the Inverted Page table works: The CPU generates the virtual address. When a
logic address is referenced in the memory, the virtual address is matched by the
memory-mapping unit and the system searches for a match to obtain to frame
address or number. If there is a match, the ith number is sent as the real address.
Howeve,r, if there is no match, the system a Segmentation fault.

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 Examples of Architecture (Memory)

■ Intel 32 Architecture
– Has two Implementations
■ segmentation
■ segmentation with paging
– Size for each segment: 4GB
– 2 Partitions:
■ Partition 1: Up to 8K – private to the process (local)
■ Partition 2: up to 8K (second group) – shared among
processes (global)

We’ll have 2 sample architectures: Intel 32 and ARM

Intel 32 implements its architecture using segmentation and segmentation with
paging. Each segment has 4GB.

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 Example

The CPU generates the logical address. The logical address is passed to the
segmentation unit which generates a linear address. The linear address is given to the
paging unit. The paging unit generates the physical address in the memory. Intel 32
page sizes can eb 4KB or 4MB.
The 32 bit linear address comes from the number of bits from the page number and
page offset. (so, 10 + 10 + 12)

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 ARM (Advanced RISC Machine) Architecture

• Used in mobile platform chip

• Uses pages with 4KB and 16 KB pages
• One-level paging for sections and two-level for smaller pages

ARM means Advanced RISC Machine. RISC means Reduced Instruction Set
Architecture. ARM processors are usually small in size and has lower power
consumption. IT makes use of RISC so that means it has reduced complexity.

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 ARM (Advanced RISC Machine) Architecture

32 bits

outer page inner page offset

4-KB
or
16-KB
page

1-MB
or
16-MB

ARM Memory Management Unit

section

ARM means Advanced RISC Machine. RISC means Reduced Instruction Set
Architecture. ARM processors are usually small in size and has lower power
consumption. IT makes use of RISC so that means it has reduced complexity.
The ARM implements the translation tables. The MMU translates the Virtual
Addresses of the code and data to the Physical Addresses in the actual system. The
translated address is sent to the hardware. The ARM MMU controls the memory
access permissions, memory ordering, and cache policies for all divisions in the main
memory.

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End of Presentation

59
References:

■ https://developer.arm.com/docs/den0024/a/the-memory-
management-unit
■ Siblerschatz, Galvin, and Gagne. Operating System Concepts (9th
Edition)

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