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12/15/23
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Introduction to 8051
Microcontrollers
• Intel’s 8031, 8051, and 8096 and Motorola’s 68HC11 are examples
of microcontrollers.
• All the microcontroller chips listed above have the same basic
architecture.
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Intel 8051 Architecture
• The main features -8051chips are
o 8 bit CPU,
o 4Kbytes of on chip Program memory,
o 128 bytes of on chip data RAM,
o 4 ports of 8bit each,
o Two 16 bit timers,
o Full duplex serial port and
o On-chip clock oscillator.
• In addition to the above features, the 8051 provide Boolean
processing; six interrupt capabilities and full-fledged CPU for
control applications.
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8051 Architecture
• The power supply +VCC and VSS takes two pins and the built-in
clock oscillator requires two pins (–XTAL1 and XTAL2) for
connecting the crystal.
• The four control signals pins of 8051 are PSEN {Program Store
Enable}, ALE, EA(External Access) and RST (Reset).
• The register banks are identified with 2 bits in the processor status word.
• The PSW has two bits for identifying the register bank, i.e., 00 represents bank
0, 01 represents bank 1, 10 represents bank 2, and 11 represents bank 3.
• In the 8051, bitwise operations are also possible with special instructions using
the bit addresses. The bit-addressable memory is both bit-addressable (from
00H to 7FH) and byte-addressable (from 20H to 2FH). Bit operations are helpful
in many control algorithms.
• Using general-purpose scratch pad memory, programmers can read and write
data at any time for any purpose. This memory ranges from the byte address
30H to the address 7FH.
• The bit addresses of all the bits of the accumulator and B registers
are given as
Bit
Address
F7 F6 F5 F4 F3 F2 F1 F0
Upon 0 0 0 0 0 0 0 0
Reset
6 - Reserved
5 - Reserved
4 - Reserved
• In this mode, the clock generator -switched off and only the
internal memory is active.
• Only way to revoke the processor from power down mode -reset
the system.
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THE STACK OPERATION
• In the 8051, the stack is configured as a series of memory locations
following the Last-In First-Out (LIFO) pattern.
• The stack pointer (SP) is an 8-bit register within the SFR area, with
the address 81H.
• The other instructions of the 8051 that affect the stack and the
stack pointer are ACALL, LCALL, RET, and RETI.
• The data pointer register (DPTR) is used to access the data in the
external memory with 16-bit addresses.
Mnemonic Operation
Direct Indirect Register Immediate
MOV A,
A = <src> √ √ √ √
<src>
MOV <dest>,
<dest> = A √ √ √
A
MOV <dest>,
<dest> = <src> √ √ √ √
<src>
INC SP:
PUSH <src> √
MOV “@SP”, <scr>
• Data can only be read from the program memory and not written
into because the program memory is generally ROM.
• The ADDC instruction is also used to add any 8 bit data with
Accumulator along with Carry bit.
• The lower order byte -result is stored in A register and the higher
order byte - stored in B register.
<byte> =
ORL <byte>,
<byte> OR # √
# data
data
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Logical Instructions
XRL A, A = A XOR
√ √ √ √
<byte> <byte>
<byte> =
XRL
<byte> XOR √
<byte>, A
A
XRL <byte> =
<byte>, # <byte> XOR √
data # data
CLR A A = 00H Accumulator only
CLP A A = NOT A Accumulator only
Rotate ACC
RL A Accumulator only
Left 1 bit
Rotate Left
RLC A through Accumulator only
Carry
Rotate ACC
RR A Accumulator only
Right 1 bit
Rotate Right
RRC A through Accumulator only
Carry
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Branching Instructions
• 8051 supports unconditional jumping and subroutine calling in
three different ways.
• They are Absolute jump AJMP, ACALL, long jump LJMP, LCALL, and
short jump SJMP.
• The internal data memory map of 8051 has a bit- addressable area
also.
• Figure 10.6 shows the flag bits affected by the various instructions.
ANL C,/bit √
ORL C,bit √
ORL C,/bit √
MOV C,bit √
CJNE √
• The output of the port latch is connected to the port pin through a transistor
driver with internal pull up resistor. The port can be operated as an input after
writing 1 to all the bits of port 1 latch.
• 8051 ports are organized such that most instructions read the data from the
pin for read operation and some instructions read the data from the latch.
• So, the input buffer consists of the select logic and the related control signals
– ‘Read Latch’, ‘Read Pin’ for discriminating this.
• But, as it is reload mode, the TL0 will be loaded with TH0 i.e.,
FDh. The value of TH0 will never be changed. TH0/1 is set to a
known value and TL0/1 is the SFR that is constantly
incremented.
• In mode 3, all the bits that are related to Real Timer 1 will
simply hold its count and will not run and the situation is
similar to keeping TR1=0.
Write TCON
Start timer
Continue
• To set the bit TR1 of TCON (D6 bit), any one of the following
two commands can be used -MOV TCON, #40h OR SETB TR1
• If the event being counted occurs more than 500,000 times per
second, it will not be able accurately counted by the 8051.
Bit AF AC AB AA A9 A8
Address
Bit position D7 D6 D5 D4 D3 D2 D1 D0
Bit Address BC BB BA B9 B8
Name EA - - PS PT1 PX1 PT0 PX0
Explanation
Enable
Interrupts
Serial Timer 1 External 1 Timer 0 External 0
- Undef Undefin
Interrupt Interrupt Interrupt Interrupt Interrupt
Made 0 to ined ed
Priority Priority Priority Priority Priority
disable all
interrupts
1
INT1
IT1 IE1
Interrupt
0 polling
sequence
TF1
RI
TI
Interrupt
enables
Global
Enable Interrupt
enabled
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Timing of Interrupts
• 8051 micro-controller samples the hardware signal level on its pins once in
every machine cycle. A machine cycle is the time taken by the controller to
access one memory location or I/O device.
• As 8051 takes 12 clock cycles to complete one machine cycle, the interrupt
signal applied at the pins of 8051 must be available for at least 12 clock
periods.
• External interrupts are applied at the pins INT0 and INT1. The sensing of
voltage level applied to this pin can also programmed in 8051. The interrupts
can be either level triggered or edge triggered as set by the IT0 and IT1 bits of
the SFR TCON
• A ‘0’ on these bit positions will make both the hardware interrupts to be level
triggered. Level triggered means a low level voltage on the interrupt pins will
activate the interrupts.
Bit Address 8F 8E 8D 8C 8B 8A 89 88
Name TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0
Interrupt 0
Interrupt 1 type
Timer 0
Timer 1 Extern type control. control. Set
run
run al Set to 1 by External to 1 by
Timer control
Timer 1 control Interru software for Interrupt software
0 bit. Set
Explanation Overflow bit. Set to pt 1 edge 0 edge for edge
Overflo to 1 by
flag 1 by edge triggering detect triggering
w flag softwar
software detect and cleared bit and
e to
to run. bit for level cleared for
run.
triggering level
triggering
Bit Address 8F 8E 8D 8C 8B 8A 89 88
• However, if the first byte still hasn’t been read by the time
reception of the second byte is complete, one of the bytes will
be lost. The serial port receive and transmit registers are both
accessed at Special Function Register SBUF.
• The SM0 and SM1 bits can select any one of the four
operating modes described in the next section.
• The reception is started by enabling REN in SCON register. Once the data
reception is complete, the RI flag is set.
• The baud rate in Mode 0 is fixed at one twelfth of the clock frequency. Baud
rate= (Clock frequency/12)
300 A0h
1200 D0h
2400 FAh
9600 FDh
• To write a byte to the serial port one must simply write the
value to be transmitted to the SBUF (99h) SFR. For example, to
send the letter "A" to the serial port, the following instruction
can be written.
MOV SBUF, #’A’
• Reading data received by the serial port is equally easy. To read a byte
from the serial port one just needs to read the value stored in the SBUF
(99h) SFR after the 8051 has automatically set the RI flag in SCON.
• The circuit connections are shown in Figure are such that the port is not
damaged and also the port is not sourcing over current. This ensures safe
operation of the ports and switches.
• An LED gives out light illuminating when it is forward biased and has enough
current flowing through it. LED indicators are easy to interface with the
microcontrollers as output device.
• LEDs can be driven with a minimum current of about 10mA. A driver IC can be
used for illuminating LEDs.
– Start: MOV A, P3
– MOV P1, A
• In common anode display, the anode of all segment LEDs are tied
together and taken out.
• So, to illuminate a segment, the common anode is connected to
the supply and then the segment input i.e. a to f is connected to a
low level logic 0.
• In common cathode display, the cathodes of all the LEDs are
connected together and taken out.
• So, to illuminate a segment, the corresponding segment input is
connected to the high level voltage or logic 1 and the common
cathode is connected to the ground. This will forward bias the LEDs
and illuminate them.
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Seven Segment Display
• Also the seven segment display is assumed to be common anode type. The
common anode is connected to the supply +5V.
• The interfacing diagram for displaying the BCD code obtained from key
connected to port3 and displaying the same in seven segment display
connected to port 1