Advanced Computer Architecture

Professional Elective-1
ECE-III Year
AY 2023-2024
• Unit-1 Introduction
• Unit-2 Instruction Set
• Unit-3 Computer memory system overview
• Unit-4 Characteristics of RISC and CISC, Control
Memory
• Unit-5 Processor Structure and Function
• Unit-6 Input/Output
Books:
• 1. William Stallings, “Computer Organization and
Architecture – Designing for Performance”,
Prentice Hall, 9th Edition, 2013
• 2. John P.Hayes, “Computer Architecture and
Organization”, Tata McGraw Hill, 3rd Edition,
2002.
 Chapter 1
Introduction
Contents:
• Introduction:
1. Organization and Architecture
2. Structure and Function
3. Computer Evolution
4. Brief history of computers
5. Designing for performance.
• Computer System:
6. Components
7. Function
8. Interconnection Structures
9. Bus interconnection
10. PCI.
1. Architecture & Organization 1
• Architecture is those attributes visible to the
programmer
— Instruction set, number of bits used for data
representation, I/O mechanisms, addressing
techniques.
— e.g. Is there a multiply instruction?

• Organization is how features are implemented

— Control signals, interfaces, memory technology.
— e.g. Is there a hardware multiply unit or is it done by
repeated addition?
 Computer Architecture & Organization

• Attributes of a system •Instruction set, number of

visible to the programmer bits used to represent various
• Have a direct impact on data types, I/O mechanisms,
the logical execution of a techniques for addressing
Architectural
program Computer memory
attributes
Architecture
include:

Organizational
Computer
attributes
Organization
include:

•Hardware details transparent •The operational units and

to the programmer, control their interconnections that
signals, interfaces between the realize the architectural
computer and peripherals, specifications
memory technology used
 Architecture & Organization 2

• All Intel x86 family share the

same basic architecture
• The IBM System/370 family
share the same basic
architecture
• This gives code compatibility
— At least backwards
• Organization differs between
different versions
 2. Structure & Function
• Structure is the way in which components relate to each
other
• Function is the operation of individual components as part
of the structure

Structure Function
• CPU All computer functions are:
• Main Memory — Data processing
• I/O — Data storage
• System Interconnection — Data movement
— Control
Functional View
a) Data movement (b) Storage
(c) Processing from/to (d) Processing from
storage storage to I/O
3. Computer Evolution
• The First Generation: Vacuum Tubes
• The Second Generation: Transistors
• The Third Generation: Integrated Circuits
• Later Generations: LSI, VLSI, ULSI
4. A brief history of Computers
• The First Generation: Vacuum Tubes
ENIAC - background
• Electronic Numerical
Integrator And Computer
• John Mauchly and John
Eckert
• University of Pennsylvania
• Trajectory tables for
weapons
• Started 1943
• Finished 1946
— Too late for war effort
• Used until 1955
ENIAC – Details
• Decimal (not binary)
• 20 accumulators of 10
digits
• Programmed manually by
switches
• 18,000 vacuum tubes
• 30 tons
• 1500 square feet
• 140 kW power consumption
• 5,000 additions per second
von Neumann/Turing
• Stored Program concept
• Main memory storing programs and data
• ALU operating on binary data
• Control unit interpreting instructions from memory and
executing
• Input and output equipment operated by control unit
• Princeton Institute for Advanced Studies
— IAS
• Completed 1952
Structure of von Neumann machine
 IAS - details
• 1000 x 40 bit words
Binary number
2 x 20 bit instructions
• Set of registers (storage in
CPU)
Memory Buffer Register (MBR)
Memory Address Register
(MAR)
Instruction Register (IR)
Instruction Buffer Register
(IBR)
Program Counter (PC)
Accumulator (AC)
Multiplier Quotient (MQ)
IAS details
 The memory consists of 1000 storage locations, called words, of 40
binary digits (bits) each.
 Binary number.

 Word can contains 2 x 20 bit instructions.

 Each instruction consisting of an 8-bit operation code and a 12-bit address

designating one of the words in memory (numbered from 0 to 999 ).

IAS Instruction Set
 Commercial
Computers IBM
• 1947 -Eckert-Mauchly Computer • Punched-card processing
Corporation equipment
• UNIVAC I (Universal Automatic • 1953 - the 701
Computer) — IBM’s first stored program
• US Bureau of Census 1950 computer
calculations — Scientific calculations
• Became part of Sperry-Rand • 1955 - the 702
Corporation — Business applications
• Late 1950s - UNIVAC II • Lead to 700/7000 series
— Faster
— More memory
 • The Second Generation: Transistors
Transistors
• Replaced vacuum tubes
• Smaller
• Cheaper
• Less heat dissipation
• Solid State device
• Made from Silicon (Sand)
• Invented 1947 at Bell Labs
• William Shockley et al.
Transistor Based Computers
• Second generation machines
• NCR & RCA produced small
transistor machines
• IBM 7000
• DEC - 1957
— Produced PDP-1
• The Third Generation: Integrated Circuits (IC)

Microelectronics
• Literally - “small electronics”
• A computer is made up of gates, memory cells
and interconnections
• These can be manufactured on a semiconductor
• e.g. silicon wafer
Moore’s Law
• Increased density of components on chip
• Gordon Moore – co-founder of Intel
• Number of transistors on a chip will double every year
• Since 1970’s development has slowed a little
— Number of transistors doubles every 18 months
• Cost of a chip has remained almost unchanged
• Higher packing density means shorter electrical paths, giving
higher performance
• Smaller size gives increased flexibility
• Reduced power and cooling requirements
• Fewer interconnections increases reliability
Growth in CPU Transistor Count
IBM 360 series
• 1964
• Replaced (& not compatible with) 7000 series
• First planned “family” of computers
— Similar or identical instruction sets
— Similar or identical O/S
— Increasing speed
— Increasing number of I/O ports (i.e. more terminals)
— Increased memory size
— Increased cost
• Multiplexed switch structure
DEC PDP-8
• 1964
• First minicomputer (after miniskirt!)
• Did not need air conditioned room
• Small enough to sit on a lab bench
• $16,000
— $100k+ for IBM 360
• Embedded applications & OEM
• BUS STRUCTURE
• Later Generations

Semiconductor Memory
• 1970
• Fairchild
• Size of a single core
— i.e. 1 bit of magnetic core storage
• Holds 256 bits
• Non-destructive read
• Much faster than core
• Capacity approximately doubles each year
Intel
• 1971 - 4004
— First microprocessor
— All CPU components on a single chip
— 4 bit
• Followed in 1972 by 8008
— 8 bit
— Both designed for specific applications
• 1974 - 8080
— Intel’s first general purpose microprocessor
5. Designing for performance

Speeding it up
• Pipelining
• On board cache
• On board L1 & L2 cache
• Branch prediction
• Data flow analysis
• Speculative execution
Performance Balance
• Processor speed increased
• Memory capacity increased
• Memory speed lags behind processor speed
Solutions
• Increase number of bits retrieved at one time
— Make DRAM “wider” rather than “deeper”
• Change DRAM interface
— Cache
• Reduce frequency of memory access
— More complex cache and cache on chip
• Increase interconnection bandwidth
— High speed buses
— Hierarchy of buses
I/O Devices
• Peripherals with intensive I/O demands
• Large data throughput demands
Solutions:
— Caching
— Buffering
— Higher-speed interconnection buses
— More elaborate bus structures
— Multiple-processor configurations
Typical I/O Device Data Rates
Key in Balance
• Processor components
• Main memory
• I/O devices
• Interconnection structures
Improvements in Chip Organization and
Architecture
• Increase hardware speed of processor
— Fundamentally due to shrinking logic gate size
– More gates, packed more tightly, increasing clock
rate
– Propagation time for signals reduced
• Increase size and speed of caches
— Dedicating part of processor chip
– Cache access times drop significantly
• Change processor organization and architecture
— Increase effective speed of execution
— Parallelism
Problems with Clock Speed and Logic
Density
• Power
— Power density increases with density of logic and clock speed
— Dissipating heat
• RC delay
— Speed at which electrons flow limited by resistance and
capacitance of metal wires connecting them
— Delay increases as RC product increases
— Wire interconnects thinner, increasing resistance
— Wires closer together, increasing capacitance
• Memory latency
— Memory speeds lag processor speeds
• Solution:
— More emphasis on organizational and architectural approaches
6. Components
• CPU

—Control unit
—Arithmetic and Logic unit
• Main memory
—Temporary storage for code and results
• I/O devices

—Data and instructions need to get into the system and

results out
Hardware and software approaches
Computer Components:
Top Level View
7. Computer function
• Two steps:
—Fetch cycle
—Execute cycle
Instruction Cycle State Diagram
Interrupts
• Mechanism by which other modules (e.g. I/O) may
interrupt normal sequence of processing
• Program
— e.g. overflow, division by zero
• Timer
— Generated by internal processor timer
— Used in pre-emptive multi-tasking
• I/O
— from I/O controller
• Hardware failure
— e.g. memory parity error
Program Flow Control
Interrupt Cycle
• Added to instruction cycle
• Processor checks for interrupt
— Indicated by an interrupt signal
• If no interrupt, fetch next instruction
• If interrupt pending:
— Suspend execution of current program
— Save context
— Set PC to start address of interrupt handler routine
— Process interrupt
— Restore context and continue interrupted program
Transfer of Control via Interrupts
Instruction Cycle with Interrupts
Program Timing
Short I/O Wait
Program Timing
Long I/O Wait
Instruction Cycle (with Interrupts) -
State Diagram
Multiple Interrupts - Sequential
Multiple Interrupts – Nested
Time Sequence of Multiple Interrupts
8. Interconnection Structures
• All the units must be connected
• Different type of connection for different type of unit
— Memory
— Input/Output
— CPU
Computer Modules
Memory Connection
• Receives and sends data
• Receives addresses (of locations)
• Receives control signals
— Read
— Write
— Timing
Input/Output Connection
• Similar to memory from computer’s viewpoint
• Output
— Receive data from computer
— Send data to peripheral
• Input
— Receive data from peripheral
— Send data to computer
• Receive control signals from computer
• Send control signals to peripherals
— e.g. spin disk
• Receive addresses from computer
— e.g. port number to identify peripheral
• Send interrupt signals (control)
CPU Connection
• Reads instruction and data
• Writes out data (after processing)
• Sends control signals to other units
• Receives (& acts on) interrupts
9. Bus Interconnection
• There are a number of possible interconnection systems
• Single and multiple BUS structures are most common
• e.g. Control/Address/Data bus (PC)
• e.g. Unibus (DEC-PDP)

• A communication pathway connecting two or more devices

• Usually broadcast
• Often grouped
— A number of channels in one bus
— e.g. 32 bit data bus is 32 separate single bit channels
• Power lines may not be shown
Data Bus
• Carries data
— Remember that there is no difference between “data”
and “instruction” at this level
• Width is a key determinant of performance
— 8, 16, 32, 64 bit
Address bus
• Identify the source or destination of data
• e.g. CPU needs to read an instruction (data) from a given
location in memory
• Bus width determines maximum memory capacity of
system
— e.g. 8080 has 16 bit address bus giving 64k address
space
Control Bus
• Control and timing information
— Memory read/write signal
— Interrupt request
— Clock signals

Bus Interconnection Scheme

Physical Realization of Bus Architecture
Single Bus Problems
• Lots of devices on one bus leads to:
— Propagation delays
– Long data paths mean that co-ordination of bus use
can adversely affect performance
– If aggregate data transfer approaches bus capacity
• Most systems use multiple buses to overcome these
problems
Traditional (ISA)
(with cache)
High Performance Bus
Bus Types
• Dedicated
— Separate data & address lines
• Multiplexed
— Shared lines
— Address valid or data valid control line
— Advantage - fewer lines
— Disadvantages
– More complex control
– Ultimate performance
Bus Arbitration
• More than one module controlling the bus
• e.g. CPU and DMA controller
• Only one module may control bus at one time
• Arbitration may be centralised or distributed
10. PCI Bus
• Peripheral Component Interconnection
• Intel released to public domain
• 32 or 64 bit
• 50 lines
PCI Bus Lines (required)
• Systems lines
— Including clock and reset
• Address & Data
— 32 time mux lines for address/data
— Interrupt & validate lines
• Interface Control
• Arbitration
— Not shared
— Direct connection to PCI bus arbiter
• Error lines
PCI Bus Lines (Optional)
• Interrupt lines
— Not shared
• Cache support
• 64-bit Bus Extension
— Additional 32 lines
— Time multiplexed
— 2 lines to enable devices to agree to use 64-bit transfer
• JTAG/Boundary Scan
— For testing procedures
PCI Commands
• Transaction between initiator (master) and target
• Master claims bus
• Determine type of transaction
— e.g. I/O read/write
• Address phase
• One or more data phases
PCI Read Timing Diagram
PCI Bus Arbiter
PCI Bus Arbitration
End of Unit-1
Internet Resources
• http://www.intel.com/
—Search for the Intel Museum
• http://www.ibm.com
• http://www.dec.com
• Charles Babbage Institute
• PowerPC
• Intel Developer Home
ENIAC
Vacuum Tubes
IBM 701
Example of IBM 700/7000 Series
Evolution of Intel Microprocessors
Evolution of Intel Microprocessors