Fine Grained & Coarse Grained

Architectures
 Clustering

• To reduce the costs of using programmable

routing, many reprogrammable FPGA
architectures will cluster the logic elements
together using fast, short length routing.
• This clustering allows larger functions to be
created using only the faster routing of the
cluster.
 Routing
• Programmable routing is done with
– Multiplexers
– Pass transistors
– Tri state buffers
 Global routing architectures
• Island
• Cellular
• Long line
• row
Island architecture

Main feature is the

connections between logic
clusters are made through
segmented routing
Cellular routing architecture
Long line routing architecture
Row routing architecture
Programmable I/O architectures
• Variations of I/O signalling standards
• Double data rate
• Programmable input delays
 Specialized function blocks

• Embedded memory
• Embedded arithmetic logic
• High speed serial I/O
• Embedded microprocessors
 Embedded memory
• FPGA contains a lot of small blocks of memory
modules which can be used independently or
combined to form larger memory blocks
• They also different configurations such as
multi-port or registered input/output for data
and address.
• More dense blocks of SRAM are included in
FPGA
 • High speed serial I/O
• Embedded arithmetic • Multi gigabit serial
logic transreceivers
• DSP blocks are included • They perform full
• Adders and multiplier duplex
unit are included serialization ,deserializat
ion
• Encoding and decoding
and error control coding
• Introduced in xilinx
virtex 2
Embedded microprocessors
ARM or MIPs based 32
RISC processor core
with an APEX-20KE
fabric