INTRODUCTION TO VHDL

DESIGN FLOW IN MODERN DIGITAL SYSTEM DESIGN

 VHDL FUNDAMENTALS

Objective: To provide an introduction of digital design, simulation and to introduce the hardware description
language VHDL.
VHSIC Hardware Description Language
• Very High Speed Integrated Circuit
• IEEE standard
• IEEE 1076-1987
• IEEE 1076-1993
• A language for describing digital designs with several levels of abstraction
• Dataflow – describes how the data flows from the inputs to the output most often using NOT, AND and
OR operations.
• Behavioral – describes how the output is derived from the inputs using structured statements.
• Structural – describes how gates are interconnected similar to schematic approach.
 VHDL DATA TYPES AND OPERATORS

fs- femtosecond 10 -15

ps- picosecond 10-12
ns- nanosecond 10-9
µs- microsecond 10-6
VHDL DATA TYPES AND OPERATORS
 VHDL PROGRAM FORMAT:
LIBRARY Declarations :
LIBRARY is a set of functions which are used in the program. To declare the LIBRARY two lines are required in the program, one is the name
of the library and second is the USE clause, as shown in the syntax.
LIBRARY library_name;
USE Library_name_package_name.package_parts;
The packages required in the program are,
1) ieee.std_logic_1164 (from the ieee library),
2) standard (from the std library) and
3) work (work library).

The declarations of the libraries are as follows,

LIBRARY ieee;
USE ieee.std_logic_1164.all;

In the program the ieee library must be declared along with the STD_LOGIC (or STD_ULOGIC) data type used in the design.
The purpose of packages is :
1) std_logic_1164 package of ieee library declares a multi-level logic system and indicates the data types, text i/o, etc. for the VHDL design.
2) std_logic_1164 : Shows the STD_LOGIC (8 levels) and STD_ULOGIC (9 levels) multi-valued logic systems.
3) std_logic_arith shows the SIGNED and UNSIGNED data types and related arithmetic and comparison operations.
4) std_logic_signed has functions that allow operations with STD_LOGIC_VECTOR data to be performed of type SIGNED.
5) std_logic_unsigned has functions that allow operations with STD_LOGIC_VECTOR data to be performed as if the data were of type
UNSIGNED.
 VHDL FUNDAMENTALS
1. Library Declaration which contains the list of
libraries used in the program. e.g. : ieee, std, work,
etc.
2. Entity which declares the I/O pins of the circuit
• Port
• Signal
3. Architecture which describes the detailed logical
design aspects of the IC.
• implementation of an entity
• support for behavioral and structural models
• can be written in one of three basic coding styles:
Dataflow, Behavioral, structural
 Signal
 input/output signals (std_ulogic (from IEEE 1164
architecture dataflow of half_adder is
library)) begin
 internal signals inside an architecture sum <= a xor b;
 assignment carry <= a and b;
 Delays end dataflow;
 Vectors of signals (bus)
DATA FLOW, BEHAVIORAL AND STRUCTURAL MODELS

Data Flow
 ENTITY AND ARCHITECTURE REPRESENTATIONS
• A digital system should be declared in two parts in VHDL.
• The first part includes the entity declaration which defines input and output
characteristics of the system to be implemented.
• system_name is the name assigned to the system to be described.
• The keyword port defines actual ports of the device.
• Each port entry will have a unique name indicated by port_name.
• A port_mode can be in, out, or inout. As the name implies, the in keyword
declares that the related port will get data from outside world.
• The out keyword declares that the related port will feed data to outside world.
• The inout keyword declares that the related port can be used for both input and
output purposes.
• VHDL requires variable and port types to be used in entity declaration to be
strongly defined.
• Therefore, port_type should be declared within library elements included to the
design by library and use keywords.
 ENTITY AND ARCHITECTURE REPRESENTATIONS

• Second part of digital system declaration defines its

architecture.
• The user should give a specific name to architecture of
the digital system as architecture name.
• The system name defined in the entity part should also
be used in architecture definition.
• Then, variable, signal, constant, and component
declarations should be made.
architecture dataflow of half_adder is
• The first three of these are related to data definitions and begin
assignments within the design. sum <= a xor b;
carry <= a and b;
• These should have valid types defined in the included end dataflow;
library_elements in the entity declaration.
 DATA FLOW MODEL

https://sustechvhdl.readthedocs.io/lecture/chapter3.html
 BEHAVIORAL MODEL

https://sustechvhdl.readthedocs.io/lecture/chapter4.html
STRUCTURAL MODEL
 STRUCTURAL MODELING

Component Declaration

Component instantiation
ENTITY AND ARCHITECTURE REPRESENTATIONS
 DATA FLOW MODELING

Half Adder Data Flow

//concurrent statements
(simple signal assignment)
 B E H AV I O R A L M O D E L I N G

// process (sensitivity list)

//Sequential signal assignment

statements (within process)
COMPONENT INSTANTIATION
 VHDL DESCRIPTION OF CONCURRENT STATEMENTS

• VHDL models combinational circuits by what are called concurrent statements.

• Concurrent statements are statements which are always ready to execute.
• These are statements which get evaluated any time and every time a signal on the right
side of the statement changes.
VHDL DESCRIPTION OF CONCURRENT STATEMENTS

• If the gates have delays of 2 ns, 1 ns, and 3 ns, respectively, and A changes at time 5 ns, then the gate
outputs D, E, and F can change at times 7 ns, 6 ns, and 8 ns, respectively.
• Even though the statements execute simultaneously, the signals D, E, and F are updated at times 7 ns, 6 ns,
and 8 ns
 VHDL DESCRIPTION OF ARRAY

• A one-dimensional array of bit signals is referred to as a bit-vector.

• If a 4-bit vector named B has an index range 0 through 3, then the four elements
of the bit-vector are designated B(0), B(1), B(2), and B(3).
• One can declare a bit-vector using a statement such as:
B: in bit_vector(3 downto 0);
• The statement B <= "1100" assigns ‘1’ to B(3), ‘1’ to B(2), ‘0’ to B(1), and ‘0’ to
B(0).
VHDL DESCRIPTION OF COMBINATIONAL CIRCUITS

architecture Equations of FullAdder is

begin -- concurrent assignment statements
Sum <=X xor Y xor Cin after 10 ns;
Cout <= (X and Y) or Cin and ( X xor Y) after 10 ns;
end Equations;
VHDL DESCRIPTION OF COMBINATIONAL CIRCUITS
 USE OF MODE BUFFER

• Assume that all variables are 0 at 0 ns, but A changes to 1 at 10 ns.

• All signals remain at ‘0’ until time 10 ns. The change in A at 10 ns results in statement 1
reevaluating. The value of D becomes ‘1’ at time equal to 15 ns.
• The change in D at time 15 ns results in statement 2 reevaluating.
• Signal E changes to ‘1’ at time 20 ns.
 VHDL MODELS FOR MULTIPLEXERS

Using Concurrent Statement

Conditional signal assignment statement

VHDL MODELS FOR MULTIPLEXERS
VHDL MODELS FOR MULTIPLEXERS

-- concurrent
statements

4 to 1 Multiplexer
VHDL MODELS FOR MULTIPLEXERS
 SEQUENTIAL STATEMENTS AND VHDL PROCESSES

• Modeling sequential logic requires primitives to model selective activity conditional on clock, edge-
triggered devices, sequence of operations and so on.
• When a process is used, the statements between the begin and the end are executed sequentially.
• The expression in parentheses after the word process is called a sensitivity list, and the process executes
whenever any signal in the sensitivity list changes.
• if the process begins with process(A, B, C), then the process executes whenever any one of A, B, or C
changes. Whenever one of the signals in the sensitivity list changes, the sequential statements in the process
body are executed in sequence one time.
• When a process finishes executing, it goes back to the beginning and waits for a signal on the sensitivity list
to change again.
• The process executes once when any of the signals A, B, C, or D changes. If C changes when the process
executes, then the process will execute a second time because C is on the sensitivity list.
 SEQUENTIAL STATEMENTS AND VHDL PROCESSES

• The sensitivity list of the process only includes A, B, and C, the only external inputs to the circuit.
• Let us assume that all variables are ‘0’ at 0 ns. Then A changes to ‘1’ at 10 ns. That causes the process to
execute. Both statements inside the process execute once sequentially, but the change in D does not
happen right at execution.
• Hence, execution of statement 2 is with the value of D at the beginning of the process. D becomes ‘1’ at
15 ns, but E stays at ‘0’.
• Since the change in D does not propagate to signal E, this VHDL model is not equivalent to two gates. If
D was included in the sensitivity list of the process, the process would execute again making E change at
20 ns.
SEQUENTIAL ASSIGNMENT STATEMENTS (VARIABLES, SIGNALS)
SEQUENTIAL ASSIGNMENT STATEMENTS (VARIABLES, SIGNALS)
SEQUENTIAL STATEMENTS AND VHDL PROCESSES
• variables: Temporary location; they are used to store intermediate values within "process".
• signals: Update signal values. Run process activated by changes on signal. While process is running all signals in system
remain unchanged.
• Differences:
• variables: They are local; no delay; declared within process
• signals: They are global (before begin); delay due to wire; declared before key word begin
• IN: Data flows in to the entity, and the entity cannot write to these signals. The IN mode is used for clock inputs, control
inputs, and unidirectional data inputs.
• OUT: Data flows out of the entity, and the entity cannot read these signals. The OUT mode is only used when the signal is
not used in any way by the entity.
• BUFFER: Data flows out of the entity, but the entity can read the signal (allowing for internal feedback). However, the
signal cannot be driven from outside the entity, so it cannot be used for data input.
• INOUT: Data can flow both in and out of the entity, and the signal can be driven from outside the entity. This mode
should be used only when necessary (for instance, a bidirectional data bus). Otherwise, error checking of the design is
reduced, and the code becomes more difficult to understand. You should not use mode INOUT in your designs for this
class.