Work by:

CHINTA SONIA
20011P0409
 Introduction to cortex
• In 2004, ARM introduced its new Cortex family of processors.

•Cortex processor comes with many new features previously

avaliable only in high end processors.

• Built on success of ARM7.

• The cortex processor is a low power processor designed for

embedded applications.

•They are necessary :

-to realize digital signal processing with low cost.
-to meet the requirements of smart phones in the market.
 Types of Cortex Processors
The Cortex family is subdivided into three
different profiles:

• Cortex-A
• Cortex-R
• Cortex-M
•The Cortex-A has been designed as a high-end
application processor. Cortex-A processors are capable of
running operating systems such as WinRT and Linux .The
key applications for Cortex-A are consumer electronics
such as smartphones, tablets, Digital TV Appliances.

•The Cortex-R series processors deliver fast and

deterministic processing and high performance, while
meeting challenging real-time constraints in a range of
situations.

•The Cortex-M processor family is both cost and energy-

efficient microcontrollers. These processors are found in
a variety of applications like loT, and in everyday
consumer devices. Cortex-M cores are commonly used.
 Cortex-M3
• The ARM Cortex-M3 processor, the first of the Cortex
generation of processors released by ARM in 2006.

• It was primarily designed to target the 32-bit microcontroller

market.

• The Cortex-M3 processor provides excellent performance at

low gate count and comes with many new features previously
available only in high-end processors.

• The Cortex-M3 processor builds on the success of the ARM7

processor to deliver devices that are significantly easier to
program and debug and yet deliver a higher processing
capability.
 Features
• It is a 32-bit microprocessor.

• It has -32 bit data path

- 32 bit register bank
- 32 bit memory interfaces.

• It has a Harvard Architecture, which means that it has a

separate instruction bus and data bus (This allows
instructions and data accesses to take place at the same
time, and as a result of this, the performance of the
processor increases because data accesses do not affect the
instruction pipeline.)
•The above feature results in multiple bus
interfaces on Cortex-M3, each with optimized
usage and the ability to be used simultaneously.

•The instruction and data buses share the same

memory space.

•The Cortex-M3 processor has an optional

Memory Protection Unit (MPU).

•It is possible to use an external cache if it's

required.
•The Cortex-M3 processor includes a number of fixed
internal debugging components.

•The debugging components provide debugging

operation supports and features, such as breakpoints
and watchpoints.

•In addition, optional components provide debugging

features, such as instruction trace, and various types of
debugging interfaces.

•It has 3-stage pipeline with branch speculation.

•Low gate count and suitable for low power designs

•.Maximum of 240 external interrupts can be
configured.

•It is fully Thumb compatible.

•It supports mix of 16 bit and 32 bit instructions for

very high code density.

•It supports handler mode and thread mode.

•It has Configurable Nested Vector Interrupt

Controller(NVIC).
 Modes supported and Privilege levels
• The Cortex-M3 processor has two modes and two
privilege levels.

MODES:
-Handler mode
-Thread mode

LEVELS:
-Privileged level
-User level
•The operation modes (thread mode and
handler mode) determine whether the
processor is running a normal program or
running an exception handler like an interrupt
handler or system exception handler.

•The privilege levels (privileged level and user

level) provide a mechanism for safeguarding
memory accesses to critical regions as well as
providing a basic security model.
•When the processor is running a main program (thread mode),
it can be either in a privileged state or a user state/level, but
exception handlers can only be in a privileged state/level.

• When the processor exits reset, it is in thread mode, with

privileged access rights.

•In the privileged state, a program has access to all memory

ranges (except when prohibited by MPU settings) and can use all
supported instructions.
ARCHITRCTURE
The Nested Vectored Interrupt Controller(NVIC)

• The highly configurable NVIC is an integral part of the Cortex-

M3 processor and providesthe processor's outstanding
interrupt handling abilities.

• In its standard implementation it supplies a Non-Maskable

Interrupt (NMI) and 32 general purpose physical interrupts
with 8 levels of pre-emption priority.

• It can be configured to anywhere between 1 and 240 physical

interrupts with up to 256 levels of priority through simple
synthesis choices.
• The Cortex-M3 processor uses a re-locatable vector table
that contains the address of the function to be executed for a
particular interrupt handler.

• The NVIC supports nesting (stacking) of interrupts, allowing

an interrupt to be serviced earlier by exerting higher priority.

• It also supports dynamic reprioritization of interrupts.

•Priority levels can be changed by software during run time.

• Interrupts that are being serviced are blocked from further

activation until the interrupt service routine is completed, so
their priority can be changed without risk of accidental re-
entry.
 The Memory Protection Unit(MPU)
• The Memory Protection Unit (MPU)• The MPU is an optional
component of the Cortex-M3 processor that can improve the
reliability of an embedded system by protecting critical data
used by the operating system from user applications,
separating processing tasks by disallowing access to each
other's data, disabling access to memory regions, allowing
memory regions to be defined as read-only and detecting
unexpected memory accesses that could potentially break the
system.

• The MPU enables the application to be broken down into a set

of processes.
•The MPU separates the memory into distinct regions
and implements protection by preventing disallowed
accesses.

•The MPU supports up to 8 regions each of which can be

divided into 8 subregions.

•The protection for the regions is implemented with rules

that are based on the type of transaction (read, write or
execute) and privilege of code performing the access.

•The MPU also supports overlapping regions, which are

regions that cover the same address.
 Debug and Trace
• The debug access into a Cortex-M3 processor based
system is through the Debug Access Port (DAP) that
can be implemented as either a Serial Wire Debug
Port (SW-DP) for a two-pin (clock and data) Interface
or a Serial Wire JTAG Debug Port (SWJ-DP) that
enables either JTAG or SW protocol to be used.

• Debug actions can be triggered by various events like

breakpoints, watchpoints, fault conditions, or
external debug requests.
 Decoder, ALU, Register bank
• The Cortex-M3 core contains a decoder for traditional Thumb
and new Thumb-2instructions, an advanced ALU with support
for hardware multiply and divide, control logic, and interfaces
to the other components of the processor.

• The Cortex-M3 processor is a 32-bit processor, with a 32-bit

wide data path, register bank and memory interface. There
are 13 general-purpose registers, 2 stack pointers, a link
register, a program counter and a number of special registers
including a program status register.
 Bus Interconnect
• The bus interconnect connect the processor and
debug interface to the external buses.
• There are several bus interfaces on the Cortex-M3
processor.
• They allow the Cortex-M3 to carry instruction
fetches and data accesses at the same time.
• The main bus interfaces are as follows:-
-Code memory buses
-System bus
-Private peripheral bus
THANK YOU