DRAM Operation

Tzu-Yun Liu
Email: r12943149@ntu.edu.tw
Tel: 0978427052
Reference:
1. DRAM Course for Semiconductor Academy - from Micron DEG PE department
2. DRAM 原理： https://blog.csdn.net/qq_45683435/article/details/103164968
3. Youtube / DRAM Memory Cell Arrays ： https://www.youtube.com/watch?v=I-9XWtdW_Co&ab_channel=ComputerScience

1
Structure of DRAM
• Many cells = Array • Array + Peripheral circuits
BL BL = Bank

WL Sense Amplifier

WL
Array

• A single DRAM memory cell

• WL is a switch to turn ON or OFF the transistor.
• BL is a path for WRITE in or READ out.
2
Operations of DRAM

• Read Operation:
 Precharge → Activate → Sense → Read out
• Write Operation:
 Precharge → Input → Sense → Write in

3
 Why do DRAM need Sense Amplifier ?
• Cstorage is small, while CBL is large
• Cstorage is charged → ① ; Cstorage is discharged → 0
• Cstorage store ① , T1 turns on.
• CBL has a small voltage difference.

 Sense Amplifier (SA) can

sense difference and Large
amplify the signals. T1 ( > 10 x Cstorage)
Cstorage V V
① : Vcc = VDD = high voltage level
Small CBL
0 : Ground = VSS = low voltage level 4
Sense Amplifier (SA)

Tn1
BL
Tp1
VCC = VDD = X = VSS = GND

XT Tn2
p2 Vref
• BL & Vref has only a little difference.
• When BL > Vref , Tp1 & Tn2 ON
→ BL becomes VDD, V becomes VSS
5
Operations of DRAM
• Read Operation:
 Precharge → Activate → Sense → Read out

• Write Operation:
 Precharge → Input → Sense → Write in

6
 Read Operation:
Precharge → Activate → Sense → Read out
1. Vref = Vcc / 2 (controlled by EQ)
Precharge
Vref

SA
Reference line Vref

① : Vcc = VDD = high voltage level

0 : Ground = VSS = low voltage level 7
 Read Operation:
Precharge → Activate → Sense → Read out

2. WL turns on, the voltage on BL changes depends on C storage

Vref → Vref -
Vref → Vref +

0 SA Precharge
Reference line Vref

① : Vcc = VDD = high voltage level

0 : Ground = VSS = low voltage level 8
 Read Operation:
Precharge → Activate → Sense → Read out

3. Vref + → 1 ; BL read “ 1 ”
1

→
Vref + Vref +

Precharge
Vref
Reference line

Vref
① : Vcc = VDD = high voltage level
0 : Ground = VSS = low voltage level 9
 Read Operation:
Precharge → Activate → Sense → Read out
4. BL charges the capacitor
5. Output the data by Tc1

OUTPUT 1
Precharge
Precharge
Reference line
OUTPUT 2

① : Vcc = VDD = high voltage level

0 : Ground = VSS = low voltage level 10
Operations of DRAM
• Read Operation:
 Precharge → Activate → Sense → Read out

• Write Operation:
 Precharge → Input → Sense → Write in

11
Write Operation:
Precharge → Input → Sense → Write in
1. Vref = Vcc / 2 (controlled by EQ)

Vref

SA
Reference line Vref

12
 Write Operation:
Precharge → Input → Sense → Write in
3. Input = 0 and flows to SA.

Precharge

Reference line

① : Vcc = VDD = high voltage level

Write Enable
0 : Ground = VSS = low voltage level 13
 Write Operation:
Precharge → Input → Sense → Write in
3. SA makes input signals become strong “0”.

0
0
0

Precharge

Reference line

① : Vcc = VDD = high voltage level

0 : Ground = VSS = low voltage level 14
 Write Operation:
Precharge → Input → Sense → Write in
4. WL turn ON, WRITE 0 in the capacitor.

0 Precharge

Reference line

① : Vcc = VDD = high voltage level

0 : Ground = VSS = low voltage level 15
Thank you for your attention

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