Bi-CMOS Technology
Bi-polar transistors provide higher gain.
The deficiency of MOS technology lies in the limited load
driving capabilities of MOS transistors. This is due to the
limited current sourcing and current abilities associated
with both p and n transistors.
Bi-CMOS gates may be an affecting way of speeding up
VLSI circuits.
Bi-CMOS Inverter
Two bipolar transistors (T3 and T4), one nMOS and one pMOS transistor
(both enhancement-type devices)
The MOS switches perform the logic function & bipolar transistors drive
output loads
Simplified BiCMOS Invereter
Operation:
Vin = 0
T1 is off. Therefore T3 is non-conducting
T2 ON - supplies current to base of T4
T4 base voltage set to Vdd.
T4 conducts & acts as current source to charge load CL towards Vdd.
Vout rises to Vdd
Vin = 1
T2 is off. Therefore T4 is non-conducting.
T1 is on and supplies current to the base of T3
T3 conducts & acts as a current sink to discharge load CL towards 0V.
Vout falls to 0V
Inverter has high drive capability but occupies a relatively small area.
Comparisons between CMOS and Bipolar
Technologies
CMOS Technology Bipolar Technology
Low static power dissipation High power dissipation
High input impedance Low input impedance
Scalable threshold voltage ……………..
High noise margin Low voltage swing logic
High packing density Low packing density
CMOS Technology Bipolar Technology
High delay sensitivity to Low delay sensitivity to
load load
Low output drive current High output drive current
Low gm High gm
Bidirectional capability Essentially unidirectional
A near ideal switching ……………...
device
Bi-CMOS Fabrication
The production of npn bipolar transistors with good performance
characteristics can be achieved by extending the standard n-well CMOS
processing to include further masks to add two additional layers such as
the n+subcollector and p+ base layers.
The npn transistor is formed in an n- well and the additional p+ base region
is located in the well to form the p-base region of the transistor.
The second additional layer, the buried n+subcollector (BCCD), is added to
reduce the n-well (collector) resistance and thus improve the quality of the
bipolar transistor.
The arrangement of BiCMOS npn transistor is shown in below fig.
Bi-CMOS Fabrication
Arrangement of BiCMOS npn transistor
N-well BiCMOS fabrication steps:
Applications of BiCMOS
Full custom ICs
ALU’s, Barrel Shifters
SRAM, DRAM
Microprocessor, Controller
Semi custom ICs
Register, Flip-flop ,Standard cells
Adders, mixers, ADC, DAC
Gate arrays
Flash A/D Converters
