8051 Core Specification

Outlines
   

Introduction Architecture Operation Registers

Introduction


 

MCSMCS-51 family, originally designed by Intel in the 1980s 1980 Used in a large percentage of embedded systems Includes several on-chip peripherals, like timers onand counters 128 bytes of on-chip data memory and up to 4K onbytes of on-chip program memory on-

Features (1/2)
        

8-bit CPU optimized for control applications Extensive Boolean processing (single-bit logic) capabilities (single64K Program Memory address space 64K Data Memory address space Up to 4K bytes of on-chip Program Memory on128 bytes of on-chip Data RAM on32 bi-directional and individually addressable I/O lines biTwo 16-bit timer/counters 166-source/5-vector interrupt structure with two priority levels source/5-

Features (2/2)

Outlines
   

Introduction Architecture Operation Registers

Architecture
     

Memory Organization CPU Clock Interrupt Structure Port Structures Timer/Counters Reset

Memory Organization (1/3)



Logical separation of program and data memory

 

Separate address spaces for Program (ROM) and Data (RAM) Memory Allow Data Memory to be accessed by 8-bit addresses quickly 8and manipulated by 8-bit CPU 8Only be read, not written to The address space is 16-bit, so maximum of 64K bytes 16Up to 4K bytes can be on-chip (internal) of 8051 core onPSEN (Program Store Enable) is used for access to external Program Memory

Program Memory
   

Memory Organization (2/3)



Data Memory
Includes 128 bytes of on-chip Data Memory which onare more easily accessible directly by its instructions  There is also a number of Special Function Registers (SFRs)  Internal Data Memory contains four banks of eight registers and a special 32-byte long segment which is 32bit addressable by 8051 bit-instructions bit External memory of maximum 64K bytes is accessible by movx movx


Memory Organization (3/3)



Internal Data Memory, 128 bytes

CPU Clock


8051 microcontroller has a clock input pin

Interrupt Structure


The 8051 provides 4 interrupt sources

Two external interrupts  Two timer interrupts


Additional description follows in Operations chapter

Port Structures (1/3)

  

The 8051 contains four I/O ports All four ports are bidirectional Each port has SFR (Special Function Registers P0 through P3) which works like a latch, an output driver and an input buffer Both output driver and input buffer of Port 0 and output driver of Port 2 are used for accessing external memory

Port Structures (2/3)



Accessing external memory works like this

Port 0 outputs the low byte of external memory address (which is time-multiplexed with the byte timebeing written or read)  Port 2 outputs the high byte (only needed when the address is 16 bits wide)


Port Structures (3/3)

 

Port 3 pins are multifunctional The alternate functions are activated with the 1 written in the corresponding bit in the port SFR

Read-ModifyRead-Modify-Write Feature (1/2)



When reading a port some instructions read the latch and others read the pin The instructions that read the latch rather than the pin are the ones that read a value (possibly change it), an then rewrite it to the latch are called read-modify-write instructions read-modify-write

Read-ModifyRead-Modify-Write Feature (2/2)

Timer/Counters


The 8051 has two 16-bit Timer/Counter 16registers

Timer 0  Timer 1


 

Both can work either as timers or event counters Both have four different operating modes from which to select (all modes are described in Operations chapter)

Reset


The reset input is the RST pin

Outlines
   

Introduction Architecture Operation Registers

Instruction Set
 

Optimized for 8-bit control applications 8Fast addressing modes for accessing internal RAM in order to facilitate byte operations on small data structures Good for systems that require a lot of Boolean processing because of its extensive support for oneone-bit variables as a separate data type

Addressing Modes (1/3)



Direct Addressing
 

Operand is specified by an 8-bit address field in the 8instruction This address mode is possible only for addressing internal Data RAM and SFRs The instruction specifies a register which contains the address of the operand The address register for 8-bit addresses can be R0 or R1 of 8the selected bank, or the Stack Pointer The address register for 16-bit addresses can only be 16-bit 1616data pointer register, DPTR pointer Both internal and external RAM can be indirectly addressed

Indirect Addressing
   

Addressing Modes (2/3)



Register Instructions


Special instructions are used for accessing four register banks (containing R0 to R7) This instructions have 3-bit register specification within the 3opcode This way of accessing registers is much more efficient because of no need for the address byte When such instruction is executed one of registers in selected ban is accessed Register bank is selected by two bank select bits in PSW

Addressing Modes (3/3)



RegisterRegister-Specific Instructions


These are instructions which are specific to a certain register and they dont need an address byte (they always operate with don the same register) The value of a constant follows the opcode MOV A, #10 loads the Accumulator with the decimal number 10 Only Program Memory can be accessed and it can be a read Used for reading look-up tables in Program Memory and lookcase jump instruction jump

Immediate Constants
 

Indexed Addressing
 

Instruction Types of 8051

     

Arithmetic Instructions Logical Instructions Data Transfers Lookup Tables Boolean Instructions Jump Instructions

Arithmetic Instructions

Logical Instructions

Data Transfers

Lookup Tables

Boolean Instructions

Jump Instructions

Timer/Counters


8051 has two 16-bit Timer/Counter registers 16 

Timer/Counter 0 Timer/Counter 1

  

These registers can be used as timers or as event counters When a register is in Timer state, it is incremented Timer every machine cycle In Counter state, the register is incremented when Counter there is a 1-to-0 transition at its external input pin, pin 1-toT0 or T1 Both registers have additional four operating modes

Timer/Counter Modes


The selection for Timer or Counter is done by Timer Counter control bits C/T in the TMOD register Both Timer/Counters have four operating modes, which Modes 0, 1 and 2 are the same for both Timer/Counters, Mode 3 is different Modes are selected by bit pairs (M1, M0) in TMOD SFR Another SFR used for work with Timer/Counters is TCON containing flag (TFx) and control (TRx) bits

Mode 0
     

Both Timer 1 and Timer 0 in Mode 0 operate as an 8-bit 8Counters (with a divide-by-32 prescaler) divide-byTimer register is configured as a 13-bit register consisting of all 8 13bits of TH1 and the lower 5 bits of TL1 The upper 3 bits of TL1 are indeterminate and should be ignored Setting the run flag (TR1) does not clear the register Timer interrupt flag TF1 is set when the count rolls over from all 1s to all 0s Mode 0 operation is the same for Timer 0 as for Timer 1. Just substitute Timer 0 for the corresponding Timer 1 signals

Mode 1


Mode 1 is the same as Mode (for both Timers), except that the Timer register is configured as 1616-bit register

Mode 2


Both Timer registers are configured as an 8-bit 8Counters (TL1 and TL0) with automatic reload Overflow from TL1 (TL0) sets TF1 (TF0) and also reloads TL1 (TL0) with the contents of Th1 (TH0), which is preset by software The reload leaves TH1 (TH0) unchanged

Mode 3
    

Mode 3 is different for Timer 1 and Timer 0 Timer 1 just holds its count. It operates the same as when TR1 is set to 0 For Timer 0 is different, TL0 and TH0 of Timer 0 are established as two separate counters TL0 uses Timer 0 control bits for its work: C/T, GATE, TR0, ~INT0, and TF0 TH0 is locked into a timer function (counting machine cycles) and takes over the use of TR1 and TF1 from Timer 1. TH0 is now actually in control of Timer 1 interrupt 1 Mode 3 is provided for applications that require an extra 8-bit 8timer or counter
 

With Timer 0, 8051 looks like it has three Timer/Counters When Timer 0 in Mode 3, Timer 1 can be turned on and off by switching it out of and into its own Mode 3, or can still be used in any application not requiring an interrupt

Interrupt (1/3)


8051 provides 4 interrupt sources

2 external interrupts  2 timer interrupts


 

They are controlled via two SFRs, IE and IP Each interrupt source can be individually enabled or disabled by setting or clearing a bit in IE (Interrupt Enable). IE also exists a global disable bit, which can be cleared to disable all interrupts at once

Interrupt (2/3)


  

Each interrupt source can also be individually set to one of two priority levels by setting or clearing a bit in IP (Interrupt Priority) A low-priority interrupt can be interrupted by highlowhighpriority interrupt, but not by another low-priority one lowA high-priority interrupt cant be interrupted by any highcan other interrupt source If interrupt requests of the same priority level are received simultaneously, an internal polling sequence determines which request is serviced, so within each priority lever there is a second priority structure

Interrupt (3/3)


This internal priority structure is determined by the polling sequence, shown in the following table

External Interrupts


External interrupts ~INT0 and ~INT1 have two ways of activation

 

LevelLevel-activated TransitionTransition-activated

  

This depends on bits IT0 and IT1 in TCON The flags that actually generate these interrupts are bits IE0 and IE1 in TCON OnOn-chip hardware clears that flag that generated an external interrupt when the service routine is vectored to, but only if the interrupt was transition-activated transitionWhen the interrupt is level-activated, then the external requesting levelsource is controlling the request flag, not the on-chip hardware on-

Timer 0 and Timer 1 Interrupts



Timer interrupts are generated by TF0 and TF1 flags in their respective Timer/Counter registers Similarly like in the case of transition-activated transitionexternal interrupts, the flag that generated an interrupt is cleared by the on-chip hardware onwhen the service routine is vectored to

Handling of Interrupts (1/5)



When interrupt occurs (or correctly, when the flag for an enabled interrupt is found to be set (1)), the interrupt system generates an LCALL to the appropriate location in Program Memory, unless some other conditions block the interrupt Several conditions can block an interrupt
  

An interrupt of equal or higher priority level is already in progress The current (polling) cycle is not the final cycle in the execution of the instruction in progress The instruction in progress is RETI or any write to IE or IP registers

Handling of Interrupts (2/5)



If an interrupt flag is active but not being responded to for one of the above conditions, must be still active when the blocking condition is removed, or the denied interrupt will not be serviced Next step is saving the registers on stack. The hardware-generated LCALL causes only the contents of hardwarethe Program Counter to be pushed onto the stack, and reloads the PC with the beginning address of the service routine In some cases it also clears the flag that generated the interrupt, and in other cases it doesnt. It clears an doesn external interrupt flag (IE0 or IE1) only if it was transitiontransition-avtivated.

Handling of Interrupts (3/5)



Having only PC be automatically saved gives programmer more freedom to decide how much time to spend saving other registers. Programmer must also be more careful with proper selection, which register to save The service routine for each interrupt begins at a fixed location. The interrupt locations are spaced at 8-byte 8interval, beginning at 0003H for External Interrupt 0, 000BH for Timer 0, 0013H for External Interrupt 1 and 001BH for Timer 1, shown in the following tables

Handling of Interrupts (4/5)

Handling of Interrupts (5/5)



Execution of service routine continues from that location until the end, that is until it encounters RETI. RETI instruction does two things
 

It informs the processor that this interrupt routine is finished Secondly, reloads the PC from the top bytes from the stack

Similar result could be accomplished with RET, with the distinction that the interrupt control system would be thinking an interrupt was still in progress

Reset
       

The reset input is RST pin To accomplish a reset the RST pin must be held high for at least two machine cycles In the response on the RST signal, CPU generates an internal reset The external reset signal is asynchronous to the internal clock In the internal reset algorithm, 0s are written to all the SFRs except the port latches and Stack Pointer The port latches are initialized to FFH and Stack Pointer to 07H Driving ALE and PSEN pins to 0 while reset is active could cause the device to go into an indeterminate state The internal RAM is not affected by reset. On power up the RAM content is indeterminate

Outlines
   

Introduction Architecture Operation Registers

8051 Registers

PSW: Program Status Word (bit addressable)



The PSW register contains several status bits that reflect the current state of the CPU

IE: Interrupt Enable Register (bit addressable)



If the bit is 0, the corresponding interrupt is disabled. Otherwise, the interrupt is enabled.

IP: Interrupt Priority Register (bit addressable)



If the bit is 0, the corresponding interrupt has a lower priority and if the bit is 1, the interrupt has a higher priority

TCON: Timer/Counter Control Register (bit addressable)

TMOD: Timer/Counter Mode Control Register (not bit addressable)