+
Chapter A Top-Level View of
Computer
3 Function and Interconnection
William Stallings, Computer Organization and Architecture,9 th
+ Objectives 2
CLO4 Describe in detail the essential elements of computer
organisation including internal bus, memory, Input/Output
( I/O) organisations and interfacing standards and discuss
how these elements function;
Attop level, what are main components of a
computer?
How are they connected?
After studying this chapter, you should be able to:
Understand the basic elements of an instruction cycle and
the role of interrupts.
Describe the concept of interconnection within a computer
system.
Understand the difference between synchronous and
asynchronous bus timing.
Explain the need for multiple buses arranged in a hierarchy.
Assess the relative advantages of point-to-point
interconnection compared to bus interconnection.
+ 3
Contents
CLO4 Describe in detail the essential elements of computer
organization including internal bus, memory, Input/Output
( I/O) organizations and interfacing standards and discuss
how these elements function.
3.1- Computer Components
3.2- Computer Function
3.3- Interconnection Structures
3.4- Bus Interconnection
+ 4
10 Questions must be
answered:
No Question
.
1 Explain about major components of computer in a Top-lever view.
2 What general categories of functions are specified by computer
instructions?
3 Refer to the figure 3.6, list and briefly define the possible states that
define an instruction execution?
4 Give an explanation for interrupt.
5 Give an explanation for low program performance if no interrupt is
used.
6 In general, when a control transfer occur?
7 When an interrupt occurs, what will the current instruction be behaved?
8 List and briefly define two approaches to dealing with multiple
interrupts?
9 List 3 types of transfers which computer’s interconnection structure
(e.g., bus) must support and give simple explanation.
10 What bus will be used when:
(a) Register’s value is moved to a memory location.
(b) CPU wants to read a value from a memory location.
+ 5
3.1- Computer Components
Contemporary (now aday) computer designs are based on
concepts developed by John von Neumann at the Institute
for Advanced Studies, Princeton (Stored Program)
Referred to as the von Neumann architecture and is based
on three key concepts:
Data and instructions are stored in a single read-write memory
The contents of this memory are addressable by location,
without regard to the type of data contained there
Execution occurs in a sequential fashion (unless explicitly
modified) from one instruction to the next
Hardwired program
The result of the process of connecting the various components
in the desired configuration
+
Programmin
g:Hardware
and Software
Approaches
Lập trình là gì?
Đọc phần note của
slide để có lời giải
thích
7
Read by yourself for more details
Software
• A sequence of codes or instructions Software
• Part of the hardware interprets each
instruction and generates control signals
• Provide a new sequence of codes for each new
program instead of rewiring the hardware
Major components:
I/O
• CPU Components
• Instruction interpreter
• Module of general-purpose arithmetic and
logic functions
• I/O Components
+ • Input module
• Contains basic components for accepting
data and instructions and converting them
into an internal form of signals usable by
the system
• Output module
• Means of reporting results
8
Computer
Components
:
Top Level
View
+ Computer CPU MEM 9
Components Memory Memory buffer
: Means for address
register (MAR)
register (MBR)
• Contains the data
communicat • Specifies the
address in
to be written into
memory or
receives the data
ions memory for the
next read or write read from
memory
Communicat
e between I/O address I/O buffer
two objects register register
= transfer (I/OAR) (I/OBR)
• Specifies a • Used for the
data back particular I/O exchange of data
and forth device between an I/O
module and the C
between
them.
CPU IO
+ 10
3.2- Computer Function
CPU thực thi lệnh như thế nào?
Basic Instruction Cycle – 2 bước của chu kỳ lệnh cơ bản
(1) Fetch cyle: Lệnh kế tiếp từ bộ nhớ (địa chỉ trong PC) được
chuyển vào thanh ghi IR
(2) Execute cycle: Từ opcode của lệnh hiện hành, một mạch xử lý
phù hợp trong ALU được kích hoạt để thực thi lệnh
11
Categories of actions
Các hành động của phần cứng
• Data • Data
transferred from transferred to or
processor to from a
memory or from peripheral
memory to Communications device by
processor transferring
between the
Processor Processor processor and
an
-memory -I/O • I/O module
Data
Control processin
g
• An instruction • The processor
may specify may perform
that the some
sequence of arithmetic or
execution be logic operation
altered on data
+ Instruction Lệnh máy: Mô tả 1
hành động- Một thí dụ
12
structure:
4- bit opcode
maximum of 16 actions
Tập lệnh giả định này được dùng cho
việc chạy chương trình ở slide kế tiếp
+ Example
of
Program
Execution
1940(h)
1(h): 0001
Load AC from memory 940(h)
5941(h)
5(h) 0101
Add to AC from memory 941(h)
2941(h)
2(h): 0010Store AC to memory
941
Add 2 memory cell at addresses
940, 941. The result is stored at
941 Khi thực thi 1 lệnh, PC tự động tăng 1
đơn vị sang địa chỉ của lệnh kế tiếp
+ 14
Instruction Cycle State Diagram
Lặp nếu trong lệnh Opcode Addr1 Addr2
có nhiều toán hạng
Vector:
nhóm trị,
thí dụ
{1,2,3,4,5}
String:
chuỗi ký
tự, thí dụ
“abcde”
Array :vec
tor, mảng
+ Interrupts – Ngắt 15
- Interrupt: A signal will pause CPU
5V Interrupt pin
normal CPU execution for doing Interrupt occurs: 5V 0v
something else.
- Interrupt sources: IO Module
Program Flow Control 16
Xem giải thích trong phần note
+ 17
Transfer of Control via
Interrupts
- Chuyển điều khiển:
Buộc CPU tạm ngưng
thực thi code ở vùng nhớ
này để thực thi code ở
vùng nhớ khác.
- Tập lệnh giúp CPU xử
lý 1 intterupt được gọi là
Interrupt Handler được
ấn định sẵn trong bộ nhớ
ROM
+ 18
Instruction Cycle With
Interrupts
CPU thực thi HOÀN TẤT lệnh
hiện hành rồi mới xử lý interrupt.
CPU
5V Interrupt
Interrupts Disabled/Enabled: pin
OS decides whether CPU accepts interrupt or not
IO Module
+ 19
Program
Timing:
Short I/O
Wait
Vẫn là thí dụ cũ nhưng hình vẽ dựa trên thời gian
thực thi đoạn code nào. Vùng ĐEN: CPU không
chạy lệnh nào cả Hiệu suất thấp
+ 20
Program
Timing:
Long I/O
Wait
Với long IO wait, user
program vẫn phải chờ. Tuy
nhiên hiệu suất vẫn cao hơn
khi không dùng interrupt.
Instruction Cycle State
21
Diagram
With Interrupts
22
Multiple Transfer of
Control
interrupt:
Tình huống
code interrupt
này lại kích
hoạt interupt Multiple
khác (nested) Interrupts
Hiệu suất giảm
nhiều.
+ Tình huống nhiều ngắt xẩy ra:
-Cách giải quyết 1: Chỉ dùng cơ chế tuần tự
thông qua cơ chế độc chiếm bằng phần cứng.
-Cách giải quyết 2: ấn định độ ưu tiên cho
các interrupt(cơ chế nhường) Hệ điều hành
quản ly.
+ Kỹ thuật độc chiếm bus: Tại 1 Ex
23
thời điểm chỉ có 1 IO được phép am
ple
ngắt CPU
Bus
Status line
0: Rảnh
Prober Prober 1: bận
IO 1 IO 2
Các bước IO tạo ngắt:
1- Thăm dò nếu status line =1 Chờ
2- Nếu Status = 0:
2.1- Bật Status = 1
2.3- Tạo ngắt
2.3- Chờ CPU xử lý xong
2.3- Tắt Status về 0
+ Time Sequence of Ex
24
Multiple am
ple
Interrupts
+ 25
I/O Function
I/O module can exchange data directly with the processor
Processor can read data from or write data to an I/O
module
Processor identifies a specific device that is controlled by a
particular I/O module
I/O instructions rather than memory referencing instructions
In some cases it is desirable to allow I/O exchanges to
occur directly with memory
The processor grants to an I/O module the authority to read
from or write to memory so that the I/O memory transfer can
occur without tying up the processor
The I/O module issues read or write commands to memory
relieving (làm giảm nhẹ) the processor of responsibility for the
exchange
This operation is known as direct memory access (DMA)
+ 3.3-
26
Interconnection
Structures
Đầu ra của thành phần này nối vào
đầu vào của thành phần khác.
The interconnection structure must 27
support the following types of transfers:
Memory
Processo I/O to I/O to or
to Processo
r to processo from
processo r to I/O
memory r memory
r
An I/O
module is
allowed to
exchange
data
directly
Processor Processor
Processor with
reads an reads data Processor
writes a memory
instruction from an sends data
unit of without
or a unit of I/O device to the I/O
data to going
data from via an I/O device
memory through
memory module
the
processor
using
direct
memory
access
28
A communication Signals transmitted by
pathway connecting two any one device are
or more devices
• Key characteristic is that it is a
shared transmission medium
available for reception by
all other devices attached
to the bus
3.4-
• If two devices transmit during
the same time period their
signals will overlap and
Bus
become garbled
I n t e r-
Typically consists of
multiple
Computer systems
contain a number of
different buses that
conne
communication lines
• Each line is capable of
transmitting signals
representing binary 1 and
provide pathways
between components at
various levels of the
ction
binary 0 computer system
hierarchy
Bus is a set of
connecting lines.
System bus 3 buses: Data/
• A bus that connects major The most common
computer components computer interconnection Address/
(processor, memory, I/O) structures are based on
the use of one or more
Control bus.
system buses
29
Data Bus
Data
lines that provide a path for moving data
among system modules
May consist of 32, 64, 128, or more separate
lines
The
number of lines is referred to as the
width of the data bus
The number of lines determines how many
bits can be transferred at a time((n: bus width
n bits/ transmission)
Thewidth of the data bus is a key factor in
determining overall system performance
+ Address Bus
30
Used to designate the source or destination of the
data on the data bus
If the processor wishes to read a word of data from
memory it puts the address of the desired word on
the address lines
Width determines the maximum possible memory
capacity of the system ( n: bus width 2n mem.
words)
Also used to address I/O ports
The higher order bits are used to select a particular
module on the bus and the lower order bits select a
memory location or I/O port within the module
+ Control Bus 31
Usedto control the access and the use of the data
and address lines
Because the data and address lines are shared by all
components there must be a means of controlling
their use
Control
signals transmit both command and timing
information among system modules
Timingsignals indicate the validity of data and
address information
Command signals specify operations to be
32
Bus Interconnection Scheme
Fig. 3.17- Example Bus 33
Configuration
Configuration/cấu hình:
một cách lắp đặt cụ thể
Fig. 3.17- Example Bus 34
Configuration
+ Elements of Bus Design
35
Dedicated: chuyên dụng, multiplex: đa thành phần, đa hợp, dùng chung
Synchronous- đồng bộ- At a time, only one device can uses the bus. The others must
wait until the bus is idle.
Asynchronous- không đồng bộ- At a time, some devices can use the bus concurrently
Arbitration: phân xử, quản lý
36
Timing of Synchronous Bus Operations
Bus
Pulse Generator Component Component
Mạch tạo xung 1 2
Digital logic- mạch Synchronous bus:
số: Buộc phải có Bus in which all
xung kích hoạt để components share a
chạy pulse generator
They operate at the
same frequency.
37
Timing of
Synchronou
s Bus
Operations
Synchronous bus:
Bus in which all
components share a
pulse generator
They operate at the
same frequency.
38
Timing of Asynchronous Bus
Operations
Bus
Component Component
1 2 Pulse
Pulse
Digital logic- mạch Each component has
số: Buộc phải có it’s own pulse
xung kích hoạt để generator
chạy
39
Timing of
Asynchronous
Bus
Operations
Asynchronous bus:
Bus in which each
component has a
individual pulse
generator They
operate at different
frequencies.
+ 40
Building Block
Read by yourself
3.5- Point-to-Point Interconnect:
Two interconnect approaches:
(1) Point-to-point interconnections
(2) Bus interconnections.
3.6- PCI Express
+ A Top-Level View of
Summary
41
Computer Function
and
Chapter 3 Interconnection
Computer components
Computer function
Instruction fetch and
execute
Interrupts
I/O function
Interconnection structures
Bus interconnection
Bus structure
Multiple bus hierarchies
Elements of bus design
