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Outline
HDL Languages and Design Flow Introduction to Verilog HDL Basic Language Concepts Connectivity in Verilog Modeling using Verilog Race conditions UDPs Coding FSMs in Verilog
Outline
Verilog Logic Synthesis Verilog Coding Guidelines Electrical Properties Macros, Conditional Compilation & Naming Conventions Verilog for Logic Simulation Introduction to PLI
HDLs WHAT-WHY-HOW
WHAT is a HDL? HDLs A class of programming/computer languages used for formal description of electronic circuits. A Hardware Description Language is one that can describe circuits operation, conceptual design & organization and can test it by means of simulation. Usually deal with the design of digital logic circuits and systems.
HDLs WHAT-WHY-HOW
WHY were HDLs required? It is impractical to verify large circuits on breadboards or large chips after manufacturing. Highly important to find potential functional bugs in the early stages of design. These needs led to a the use of CAD techniques for digital design. The designers felt need for a flexible language that may help the design process by giving a complete framework for design.
HDLs WHAT-WHY-HOW
WHY were HDLs required? (contd..) Software Programming languages Sequential in nature. (C, Pascal, FORTRAN, etc.) Digital logic circuits involve Concurrency of operations. Traditional programming languages lack the capability for explicitly expressing time. Using s/w programming languages to represent hardware is Inconvenient, Time consuming & Costlier.
HDLs WHAT-WHY-HOW
HOW are HDLs advantageous? Allows designer to talk about what the hardware should do without actually designing the hardware itself. Designers can develop an executable functional specification that documents the exact behavior of all the components and their interfaces. Designers can make decisions about cost, performance, power, and area earlier in the design process. Designers can create tools which automatically manipulate the design for verification, synthesis, and optimization.
Design Hierarchy
Design Specification & Requirements Behavioral/Architectural Design Register Transfer Level (RTL) Design Logic Design Circuit Design Physical Design Manufacturing
System Specification Functional (Architectural Design) Behavioral Representation Functional Verification Logic Design Logic (Gate-level) Representation Logic Verification Circuit Design Circuit Representation Circuit Verification Physical Design Layout Representation Layout Verification Fabrication & Testing
...
Implementation
CPU
SubSystem
RTL Gate level Treansistor level
adder
subtr
Levels of Abstraction
Verilog supports a design at 4 different levels of abstraction. Behavioral Level Dataflow Level Gate Level Switch level Behavioral Dataflow Gate Level Switch level
Lowest Abstraction Level Highest Abstraction Level
Register Transfer Level (RTL) A combination of both Behavioral & Dataflow constructs. Acceptable to logic synthesis tool.
Design Methodologies
There are 2 types of design methodologies: Top-down design methodology, and Bottom-up design methodology. In a top-down design methodology, we define the top-level block and identify the sub-blocks necessary to build the top-level block. In a bottom-up design methodology, we first identify the building blocks that are available to us. We build bigger cells, using these building blocks.
Subblock1
Subblock2
Subblock3
Leaf Cell
Leaf Cell
Leaf Cell
Leaf Cell
Leaf Cell
Leaf Cell
Macro Cell1
Macro Cell 2
Macro Cell 3
Leaf Cell
Leaf Cell
Leaf Cell
Leaf Cell
Leaf Cell
Leaf Cell
Modules
A module is the basic building block in Verilog. Elements are grouped into modules to provide the common functionality that is used at many places in the design. A module provides the necessary functionality to the higher-level block through its port interface (inputs and outputs). In Verilog a module is declared by the keyword module. A corresponding keyword endmodule must appear at the end of the module definition.
Modules (Contd..)
Modules CANNOT be nested. Rather, one module can instantiate another module. Module instantiation is like creating actual objects (Instances) from the common template (module definition). Each instance of module has all the properties of that module. Module instantiations are used for: connecting different parts of the designs, and connecting test bench to the design.
Design Hierarchy
One top level module In which zero or more lower level modules can be instantiated. Each low level module can further instantiate still lower level modules. Verilog modules are like modules in schematics or classes in C++. Use them to make your design more readable and manageable. Debugging individual module is a lot easier than debugging the whole system together.
Structure of module
module <mod name> (<port list>); <declarations>; // input, output, inout // wire, register, etc. <statements>; // initial, begin, end, always // dataflow statements endmodule
Lexical Conventions
Keywords In lower case Case sensitive Delimit tokens, space String with double quotes Identifier A letter or _ can be followed by letters, digits, $ and _ Max 1024 characters Numbers [<sign>] [<size>] <base> <num> e.g.- 549, h8ff, o765, 4b11,3b10x, -4b11
Verilog Comments
Verilog supports 2 type of comment syntaxes Single line comment start with //, and end with newline. Block comment, start with /*, and end with */. Block comment cannot be nested.
Example
/* Copyright Kacper Technologies Pvt Ltd, 2009 No unauthorized copying is allowed. */ input status; // 0:ready, 1:not ready output data; // sync with clock mClock
Bit length in decimal. This is an optional value & if not specified, default is host machine word size. (usually 32 bits) b, B, d, D, o, O, h, H. Default is decimal 0-9, a-f, A-F, X, Z, ?, _
// Num = 6b00100x // 32 bit no with all x bits // Num = 6bzzzz01 // Num = 6b011zz1 // data = 32hX5f32693
// 8b0001_0000 // twos complement of 4 // 8bxxxx_xxxx // 8b0000_000x // 8b0000_010x // status == 32h0001 // status == 1b1
Data Types
reg: Register Integer & Real Data Types Declaration wire: Wire/net integer i, k; real r; Possible Values: 0, 1, x, z Use as registers (inside procedures) i = 1; Default: 1-bit (Scalar) r = 2.9; reg A, B, C; k = r; // k is rounded to 3 Integers are not initialized in Vector: Verilog!! Reg[0:7] A; Reals are initialized to 0.0 Reg[7:0] B;
Nets Nets represent the connections between hardware elements. They are always driven by some source. Default value for any net type variable is z. Usually, declared by the keyword wire. Different types: wire, wand, wor, tri, triand, trior, trireg, etc. wire is the most common of all.
Registers These correspond to variables in the C language. Register data types always retain their value until another value is placed on them. DO NOT confuse with hardware registers built with flip-flops. A reg type variable is the one that can hold a value. Unlike nets, registers do not need any drivers.
Registers (Contd..) In synthesis, the compiler will generate latches or flip-flops for them. However, if it can be sure their output does not need to be stored it will synthesize them into wires. It can be sure they do not have to store if their outputs is based only on their present inputs.
Rules for reg and wire The common rule in Verilog: A variable on the Left Hand Side (LHS) of a procedural block assignment is always declared as a register data type.All other variables are of net type. Verilog register data types: reg / time / integer / real / realtime / event (reg is the most common of all.) So, reg is assigned within always or initial blocks. A variable is declared of type wire if it appears on the left side of an continuous assignment statement. Structural code continuous assignment statements start with the keyword assign.
Integers A general purpose register data type with default value having all x bits. Declared with keyword integer. Usually preferred for arithmetic manipulations over reg. Default width: host machine word size (minimum 32 bits). Differs from reg type as it stores signed quantities as opposed to reg storing unsigned quantities.
Real Numbers Real number constants declared with a keyword real. Real constants have default value of 0. Real numbers CANNOT have a range declaration. Two notations: Decimal & Scientific notation. When a real value is assigned to an integer, the real number is rounded off to the nearest integer.
Time & Realtime Data types time A special register data type used mainly to store simulation time. time is an unsigned 64-bit by default. Usually, it is used to store the simulation time. realtime is similar to time except that it has initial value of 0. Depending upon the timescale specified, realtime provides the simulation time with the fractional part with given precision.
Logical Operators
Operator
~& | ~| ^ ~^ or ^~ == or === != or !== > >= < <= ?:
Operation
Reduction NAND Reduction OR Reduction NOR Reduction XOR Reduction XNOR Logical Inequality Logical Inequality Relational Conditional
Operator Operation
! && || ~ & | ^ ^~ or ~^ & Logical Negation Logical AND Logical OR Bit-wise Negation Bit-wise AND Bit-wise OR Bit-wise Exclusive OR Bit-wise Ex- NOR Reduction AND
1 2 3 4 5 6 7 8 && A B C D E F G H
True (1), False (0) or Unknown (X) Examples 1b1 && 1b0 2b11 && 2b10 2b1X && 2b11 0 0 X 1b1 || 1b0 2b11 || 2b10 2b1X || 2b11 1 1 1
Bitwise Operators
& | ~ bitwise AND bitwise OR bitwise NOT ^ bitwise XOR ~^ or ^~ bitwise XNOR Operation on bit by bit basis 8 & A B C D E F G H
1 & A
2 & B
3 & C
4 & D
5 & E
6 & F
7 & G
8 & H
Reduction operators
Key symbols: &, ~&, |, ~|, ^, ~^, ^~. The reduction operators are and, nand, or, nor, xor, xnor and an alternative xnor. They take one operand and perform a bit-bynext-bit operation, starting with the two leftmost bits, giving a 1bit result. initial begin a = 4'b1111; b = 4'b0101; c = 4'b0011; $displayb(& a); $displayb(| b); end
Reduction operation
& 1 2 3 4 5 6 7 8
1 &
3 & &
5 &
7 & &
&
Shift operators
Key symbols: >>, <<. The shift operators are shift left and shift right. The shift operator takes a vector and a number indicating the shift. The empty bits caused by shifting are filled with zeros. module shiftTest; reg [3:0] a; initial begin a = 4'b1010; $displayb(a << 1); $displayb(a >> 2); end endmodule // shiftTest
Conditional Operator
cond_expr ? true_expr : false_expr A ternary operator Acts like a 2-to-1 mux.
A B
1 0 sel
Concatenation Operator
{op1, op2, ..} concatenates op1, op2, .. to single number. Operands must be sized !! reg a; reg [2:0] b,c; a = 1b1,b = 3b 010, c = 3b 101; catx = {a, b, c}; // catx = 1_010_101 caty = {b, 2b11, a}; // caty = 010_11_1 catz = {b, 1}; // WRONG !!
Replication Operator
<no> { <variable/sized_number> } <no> is an integer. reg a; reg [2:0] b,c; a = 1b1,b = 3b 010, c = 3b 101; catr = {4{a}, b, 2{c}}; // catr = 1111_010_101101
Operator precedence
Operators Unary Multiply, Divide, Modulus Add, Subtract Shift Relational Equality Reduction Operator Symbols + - ! ~ * / % + >> << < <= >= > == != === !== & ~& ^ ^~ | ~| && || ?: Lowest Precedence Highest
Logical Conditional
Vectors
Vectors have multiple bits and are often used to represent buses. The left most number is an MSB (Most Significant Bit). There are 2 representations for vectors: A little-endian notation: [high# : low#] A big-endian notation: [low# : high#] wire [3:0] busA; reg [0:15] busC; reg [1:4] busB; // little-endian notation // big-endian notation
Vectors (Contd..)
Vector Part Select data[15:8] = 8h_12; inter_carry = carry[1:3]; Slice management reg [63:0] out; reg [3:0] dest_addr; initial begin dest_addr = out[63:60]; end // Accessing only bits 16 to 9 of data
Vectors (Contd..)
Vector assignment ( by position!! ) reg [2:0] bus_A; reg [0:2] bus_B; initial begin bus_A = bus_B; end
Vectors (Contd..)
Variable Vector Part Select [<starting_bit>+ : <width>] [<starting_bit>- : <width>] reg [31:0] data1; reg [0:31] data2; reg [7:0] byte1; reg [3:0] nibble1; reg [0:7] byte2; reg [0:3] nibble2; nibble1 = data1[31-:4]; // selects 4 bits from 31 to down, i.e. [31:28] byte1 = data1[24-:8]; // selects data1[24:17] byte2 = data2[10+:8]; // selects data2[10:17] nibble2 = data2[28+:4]; // selects data2[28:31]
Strings
Implemented with regs. Escaped chars: \n for newline \\ for \ \t for tab %% for % \ for \ooo characters as octal
reg [8*13:1] string_val; // can hold up to 13 chars ... string_val = Hello Verilog; string_val = hello; // MS Bytes are filled with 0 string_val = I am overflowed; // I is truncated
Arrays
Declaration: <type> <vector_size> <ary_name> <ary_size>; <ary_size> is declared as a range. Verilog supports multi-dimensional arrays. Elements are accessed by: <ary_name> [<index>]. reg array1 [99:0]; // array1 is an array with 100 elements // each element is of 1 bit. integer ary1 [19:0]; // array of integers with 20 elements wire [3:0] y [10:1]; // array of buses reg [31:0] payload [34:0]; // array of vectors time checkpoints [1:50]; // array of check-points real results [39:0]; // array of real numbers
Arrays (Contd..)
//Multi-dimensional arrays reg [7:0] sonet_frame [89:0][8:0]; // a 2-dimentional array representing the SONET frame. reg [7:0] matrix3d [9:0] [24:0] [3:0]; // 3-dimentional array of integers
Memories
Declaration: reg <vector_width> <ary_name> <no_of_locations>; reg [7:0] string_val [99:0]; reg [7:0] ray2d [4:0] [49:0]; // a memory with 100 elements // each of 1 byte // 2-dimentional array
Connectivity in Verilog
Port assignments
Modules contain functional descriptions and have input, output, and inout (bidirectional ports) for interfaces. The following are true of module interfaces: An input or inout port is a wire type within its module. An output port must be a wire if it is generated by a submodule. An output port must be a wire if it is generated declaratively. An output port must be a reg if it is assigned to procedurally. A wire if it is assigned through continuous assignment.
Module Instantiations
As we saw earlier, module instantiation is used to make connections between different parts of the design. There are two methods of making connections between signals specified in the modules and their input/output ports. Port ordered instantiation lists signal connections in the same order as the port list in the module definition. Unconnected ports are designated by two commas with no signal listed. Port named instantiation lists the port name and signal connected to it, in any order.
Hierarchical Naming
As modules instantiate one another, there forms a hierarchy of them. And them and their internal variables, etc. can be accessed from higher levels using hierarchical naming.
TB_TOP dff
nand1
nand2
nand1
nand2
Signals of the dff may be accessed using hierarchical naming as shown below: TB_TOP TB_TOP.dff1.Q TB_TOP.nand1 TB_TOP.nand1.o1 TB_TOP.dff1.QB
Gate Delays
Rise Delay: associated with a gate output transition to 1 from another value. Fall Delay: associated with a gate output transition to 0 from another value. Turn-off Delay: associated with a gate output transition to z from another value. If the output of gate changes to x, the minimum of the three delays is considered.
*/
Dataflow Modeling
The data flow between registers and the way that data gets processes is modeled using dataflow modeling. Dataflow modeling involves continuous assignments, that is driving values to the net. assign is used to drive value on the net by continuos assignment. Syntax: assign <drive_strength> #<delay> <list_of_assignments>;
Delays
A delay control expression specifies the time duration between initially encountering the statement and when the statement actually executes. e.g.#10 A = A + 1; The delay is represented using #. A number followed by # shows the delay value. In real circuits , logic gates have delays associated with them. Verilog provides the mechanism to associate delays with gates. There are different ways to specify delays in continuous assignments.
Delays (Cont..)
Regular Assignment Delay: This is the most commonly used method. e.g.assign #10 q = x + y; Implicit Continuous Assignment Delay: Similar to implicit assignment statement with delay added. e.g. wire #10 q = a ^ b; // which is equivalent to the following: // wire out; // assign #10 out = a ^ b;
Delays (Cont..)
Net Declaration Delay: The delay can be put on the net in declaration itself. e.g. wire #10 out; assign out = a & b; // which is equivalent to the following: // wire out; // assign #10 out = a & b;
Behavioral Modeling
In RTL and Gate level implementation, the details of the handshake mechanism between different processes are implied. The states are cycle-to-cycle accurate.
input data
received data
data ready
request data
overflow
acknowledge data
input data
received data
data ready
request data
Procedural Blocks
Procedural blocks are the basic components for behavioral modeling. initial begin imperative statements end Runs when simulation starts Terminates when control reaches the end Good for providing stimulus always begin imperative statements end Runs when simulation starts Restarts when control reaches the end Good for modeling / specifying hardware
Procedural Assignment
Procedural statements are statements inside a procedure. (they execute sequentially) This can be expressed in two types of blocks: initial they execute only once always they execute for ever The RHS expression is evaluated and assigned to LHS variable before next statement executes. RHS expression may contain wires and regs Two possible sources for data LHS must be a reg (rooy) type data type. Primitives or cont. assignment may set wire values
Blocking Assignments
The blocking assignment operator is an equal sign (=). The blocking assignment with timing delays on the RHS of the blocking operator, which is considered to be a poor coding style. A problem with blocking assignments occurs when the RHS variable of one assignment in one procedural block is also the LHS variable of another assignment in another procedural block, and both equations are scheduled to execute in the same simulation time step, such as on the same clock edge.
Non-blocking Assignments
The non-blocking assignment operator is the same as the lessthan-or-equal-to operator ("<="). They are called non-blocking because the assignment evaluates the RHS expression of a it at the beginning of a time step, and schedules the LHS update to take place at the end of the time step. Between evaluation of the RHS expression and update of the LHS expression, other Verilog statements can be evaluated and updated.
a 1
1
a <= 1; b <= a; c <= b;
a b c
// example of repeat loop i = 0; repeat (`MEMSIZE) begin mem[i] = 8b0; i = i + 1; end // example of forever loop i = 0; forever begin : mem_init mem[i] = 8b0; i = i + 1; if (i == `MEMSIZE) disable mem_init; end
Example of a task
task task_example; input [1:0] in1, in2; output [1:0] out1, out2; #1 out1 = in1 & in2; #1 out2 = in1 | in2; endtask
Example of a function
function [1:0] function_example; input [1:0] in1, in2; function_example = in1 & in2; endfunction
System Tasks
Verilog has some of the inbuilt task as part of the language itself. $display : This system task is used to display the text and formatted data on the screen. It inserts a newline at end of display text automatically. $monitor : It continuously monitors the changes in any of the variable/signal specified in the parameter list. Whenever, any one of them changes, it displays the formatted string specified within double quotes. $stop: It stops /suspends the simulation.
Compiler Directives
All compiler directives are preceded by a back tick ( ` ). `define : It is used to define a text macro in Verilog. `include: It is used to include content of some other file inside a Verilog code. `timescale: It is used to specify the timescale for simulation. It has two parts: reference time unit & time precision. First one specifies the time unit and the later determines the minimum unit that is considered for any round off. `timescale <ref_time_unit>/<precision>
Synchronization
Verilog support the following type of process synchronization event fork and join disable
Synchronization - Event
# <expression> suspends execution of the process for a fixed time period @event-expression suspends the execution of the process until the specified event occurs wait (expression) suspends the execution of the process until the expression become true
Synchronization (Contd..)
Verilog supports event data type. module event_example; event e1, e2; endmodule Trigger an event using ->event_variable
<statement S> is executed only when <statement 1> to <statement N> are completed
Synchronization disable
disable <block_name> remove pending events from <block_name> will not continue to execute the rest of the <block_name> if <block_name> is in the always block, execution continues from the start of the always block always begin : write_block <statement 1>; if ( write_through ) disable write_block; out = #10 ram[index]; end
if write_throughis true, all pending events (e.g. out=#10 ram[index] from the previous cycle) will be removed. Execution start from <statement 1>
Forever Statement
This loop executes continuously and never completes. An infinite loop that continuously executes the statement or statement group. Infinite loops in Verilog use the keyword forever. You must break up an infinite loop with an @(posedge clock) or @(negedge clock). expression to prevent combinational feedback, as shown in an example: Syntax; forever<execution statement> initial begin clock=0; forever #50 clock=~clock; end
Generate Statements
Generate statements are used when the same operation or module instance is repeated for multiple bits of vector. Generate statements allow control over the declaration of variables, functions and tasks as well as control over instantiations. All generate instantiations are coded with a module scope and require keywords generate endgenerate. There are three methods to create generate statements: Generate loop. Generate conditional. Generate case.
Parameters
A parameter is defined by Verilog as a constant value declared within the module structure. The value can be used to define a set of attributes for the module which can characterize its behavior as well as its physical representation. parameter <identifier> = constant; parameter byte_size = 8; reg[byte_size-1:0] A; Used to pass information globally.
Race Conditions
It is very common to have race conditions near latches or flipflops. The following is the example of it in which an intermediate node a between two Flip-flops is set and sampled at the same time. The solution for this is to use the non-blocking assignment in the flip-flop to guarantee the ordering of assignment to the output of the flip-flop and sampling of that output. always @(posedge clk) q <= d; always @(posedge clk) q = #1 d;
UDPs
Combinational UDP-Example
primitive mux4_to_1 ( output out, input i0, i1, i2, i3, s1, s0); table // i0 i1 i2 i3, s1 s0 : out 1 ? ? ? 0 0 : 1; 0 ? ? ? 0 0 : 0; ? 1 ? ? 0 1 : 1; ? 0 ? ? 0 1 : 0; ? ? 1 ? 1 0 : 1; ? ? 0 ? 1 0 : 0; ? ? ? 1 1 1 : 1; ? ? ? 0 1 1 : 0; ? ? ? ? x ? : x; ? ? ? ? ? x : x; endtable endprimitive I0 I1 I2 I3 S0
Out
Mux
S1
//Define an edge-sensitive sequential UDP; primitive edge_dff(output reg q = 0, input d, clock, clear); table // d clock clear : q : q+ ; ? ? 1 : ? : 0 ; //output = 0 if clear = 1 ? ? (10) : ? : - ; //ignore negative transition of clear 1 (10) 0 : ? : 1 ; //latch data on negative transition of 0 (10) 0 : ? : 0 ; //clock ? (1x) 0 : ? : - ; //hold q if clock transitions to unknown //state ? (0?) 0 : ? : - ; //ignore positive transitions of clock ? (x1) 0 : ? : - ; //ignore positive transitions of clock (??) ? 0 : ? : - ; //ignore any change in d when clock //is steady endtable endprimitive (10) Negative edge transition from 1 to 0
(1x) Transition from 1 to unknown (0?) Transition from 0 to 0,1,x.potential +ve edge transition (??) Transition in signal value 0,1, or x to 0, 1, or x
FSM Classification
Mealy:
Output is a function of present state and inputs. Output may change if inputs change during clock period, due to this the outputs may have momentary false values because of the delay encountered from the time the input change and the time that the FF output change.
Input
Memory
Output Decoder
Output
Clock
FSM Classification
Moore:
Output is a function of present state only that are synchronized with the clock. Input Next state Decoder Output Decoder Output
Memory
Memory
Clock
FSM encoding
Encoding the states is assigning unique binary numbers to the states State Initial S1 S2 S3 S4 Binary 000 001 010 011 100 Gray 000 001 011 010 110 One-hot 00001 00010 00100 01000 10000
FSM encoding
Binary The number of storage devices (Flip-flops) is minimum. Gray If it is gray encoded, there will be only one switching between adjacent states. This reduces glitches at the outputs due to unequal delays of storage devices.
FSM encoding
One-hot
only one of the state variables will be 1 and all others will be 0s for a state. Complexity of Next state Decoder and Output Decoder is reduced Due to reduced complexity of Decoders , the speed of the FSM (Max.clock frequency) is not limited by the combinational logic. Hence Faster FSM. Use casex for output and next state decoder
RTL Synthesis
What is RTL Register Transfer Level : storage element, like flip-flop, latches : transfer between input, output and register : level of abstraction
RTL Synthesis
RTL
synthesis
RTL Synthesis is a process to transform design description from RTL abstraction to the gate abstraction.
RTL Synthesis
VHDL/Verilog RTL level Optimization Structural representation, Control-Data Flow Graph Gate level Optimization Cell from a technology specific library.
Logic Level Optimization Fixed Synchronous logic. Boolean equation representation of combinational logic
Netlist
Operating Condition
Cell Name Cell Type Cell Function Cell Area Cell Timing Cell Power Cell Pin Cell Pin Loading Cell design rule Wire Load Table
Gate
Synthesis Process
Not all Verilog commands synthesize easily. For example initial initializing variables is easy to do in a program where all variables are stored. However in hardware only variables stored in flip-flops are easy to initialize. For this reason only a subset of Verilog is synthesizable. These presentation will concentrate on that subset.
Technology Library
A Technology Library contains a set of primitive cells which can be used by synthesis tools to build a circuit. Technology libraries are created by the silicon vendor. Not by the synthesis tools. A library may contain: The timing and electrical characteristics of the cells Net delay and net parasitic information Definition of capacitance, time and resistance units. Most libraries are compiled before delivery. They can be understood by the tools, but are unreadable to you.
Verilog Procedure
initial is not synthesizable and is used for test benches. always without @ condition, is normally only used in test benches Variables on the left-hand side should be of type reg in a procedural code , or at least not of type wire. In a structural code the LHS variable should be of type wire
Method 1:
Method 2
Be sure every branch of every if and case generate every output. always @(. . . begin if (a) begin x=2; y=0; z=0; end elseif (b) begin x=0; y=3; z=0; end else begin x=0; y=0; z=4; end end end
Procedural synthesis
Logic Inference Deciding what logic to synthesize from code is called inference. always @ Can infer: flip-flops, latches, and/or combinational logic. always @(posedge Clk) This is the statement that tells the logic compiler to generate flip flops. Latches and Combinational always @(C or D) :- This may generate a latch. It may just result in combinational logic.
Latch Inference
Inserting Latches With or Without Your Asking Latches form if //Latch Inference form if reg Q; always @(Clk or D) begin if (Clk) Q <= D; end //No Latch Inference from if reg Z; always @(Ck or D) begin Z<=1b0; //Initialize if (Ck) Z <= D; end
CDFG format
The control data flow graph is often used by synthesis tools for highest internal representation. If (S == 1b0) begin L <= A + B; M <= L + L; N <= A - C; end; else N <= A + C; end if; L=A+B M=L+L FORK N=A-C JOIN MERGE CDFG level optimization techniques will be used. N=A+C SELECT
Electrical Properties
Signal Types
0 : Logical 0, or false condition 1 : Logical 1, or false condition Z : High impedance state X : Unknown logic condition. Can be 0, 1 or Z
Signal Types(cont)
0 0 X Z
0 1 1
1 X X
Signals (cont)
0 X 1 X 1 X 0 X 0 S0 S1 SEL X S0 1 X X 0 X 1 S1 X X 0 1 SEL 0 1 X X Z S0 S1 0 1 Z
7 6 5 4 3
Su0 St 0 Pu0 La0 We0
2 1 0
Me0 Sm 0 HiZ 0
0
HiZ 1
1
Sm1
2 3 4 5 6 7
Me1 We 1 La1 Pu1 St 1 Su1
Note: Valid strength keywords are supply1, strong1, pull1, weak1, highz1, supply0, strong0, pull0, weak0, highz0.
A1 to Z delay
A1 Z A2
A2 to Z delay
Verilog
Delay Calculation
SDF
Physical Information
Delay Load
Cell Library
Table Look-up
Skew
SDF
Note: $sdf_annotate() can be placed anywhere in the HDL code. However, it make no sense to put it after time 0
Macro
Macro names and the names used in the design are different Macro definition is global. There is not scope restriction. Macro can be re-define. The last definition read is used. Keyword cannot be used as macro name. (It does not make sense). One line comment (//) will be excluded in the text substituted. Macro can also be defined in the command line. These macro has the highest priority. (e.g. verilog design.v +define+regressionSuit=4 )
Macro Cont..
define WORD 8 //word size define CLOCKMUX ssmux8 module register() reg [WORD-1 : 0] cpu_reg; CLOCKMUX hand_clockMux (); endmodule
Conditional Compilation
ifdef, else and endif can be nested Syntax for the ignored Verilog texts are not checked. Verilog simulator does not keep record of the ignored text. Thus any output (e.g. profiling and encryption) from the simulation does not retain the full Verilog input. module adder(a, b, c); output [8:0] a; input [7:0] b, c; reg [8:0] a; always @ (b or c) begin ifdef BEHAVIOURAL a = b + c; else gateAdder #(8, 7, 7)i0 (a, b, c); endif end endmodule
Introduction
Input command line
Simulation
Waveform
Testbench
Log
Design
Key Log
File Output
$display(), $write() and $monitor() have a counterpart to write to a specific file, beside the log file. integer fileID; initial begin fileID = $fopen(capture.dat); if (fileID == 0) $finish; $fdisplay(fileID, Start Simulation %s, $pli_currentDateTime() ); end
Test bench
The following things are essentially required to be provisioned a test bench. timing control input stimulus device under test reference model diagnostic logging assertion checking
Start/Stop dumping
$dumpon; / $dumpoff;
Interactive Debugging
Simulation control (depends on simulator) $finish() $stop() . ,; $reset : finish the simulation : stop simulation and enter interactive mode : continue simulation : step : restart the simulation
Some useful system tasks $showvars() : show unresolved values of specified variables $system() : execute a system command $showallinstance(): show number of instances of each module, gate and primitive in the design
Simulation Tips 1
Zero-delay loop
A common mistake in big design. Usually indicates a logic error. module top(reset); input reset; reg a; always begin if ( !reset ) begin // what happen when #10 a = 0; // reset is 1 #10 a = 1; end end endmodule
A more complicated zero delay loop module top; reg clk, reset, d; reg [3:0] a, b, c, res; initial begin clk = 0; forever #10 clk = !clk; end initial begin reset = 0; #10 reset = 1; #10 reset = 0; #1000 $finish; end always @(posedge clk or posedge reset) if(reset) {a,b,c,d}=13b0; else d = !d; always @(a or d) begin b = b + 1b1; if (d) res = b + d; end always @(b) c = c + 1b1; always @(c) a = a + 1b1; endmodule
Simulation Tips 2
Accelerated vs. Non-accelerated Construct
reg var; parameter delay=10 assign #delay a = b; assign #(delay + 1) c = d; assign e = f & g; assign #var h = i; assign j = k + m;
Simulation Tips 3
Timing violation in register when crossing timing domains
unSyncD
syncD
clk1 clk2
unSyncD clk2 syncD
The timing violation can kill the simulation. The Xstate get propagated to the rest of the circuit, and the simulation becomes meaningless.
Introduction to PLI
Uses Of PLI
PLI can be used to define additional system tasks and functions. Typical examples are monitoring tasks, stimulus tasks, debugging tasks, and complex operations that cannot be implemented with standard Verilog constructs. Application software like translators and delay calculators can be written with PLI. PLI can be used to extract design information such as hierarchy, connectivity, fanout, and number of logic elements of a certain type. PLI can be used to write special-purpose or customized output display routines. Waveform viewers can use this file to generate waveforms, logic connectivity, source level browsers, and hierarchy information.
Whenever the task $hello_verilog is invoked in the Verilog code, the C routine hello_verilog must be executed. The simulator needs to be aware that a new system task called $hello_verilog exists and is linked to the C routine hello_verilog. This process is called linking the PLI routines into the Verilog simulator.
At the end of the linking step, a special binary executable containing the new $hello_verilog system task is created. For example, instead of the usual simulator binary executable, a new binary executable hverilog is produced. To simulate, run hverilog instead of your usual simulator executable file. Once the user-defined task has been linked into the Verilog simulator, it can be invoked like any Verilog system task by the keyword $hello_verilog. A Verilog module hello_top, which calls the task $hello_verilog, is defined in file hello.v as shown below: module hello_top; initial $hello_verilog; //Invoke the user-defined task $hello_verilog endmodule Output of the simulation is as follows: Hello Verilog World
Summary
Summary of Verilog
Systems described hierarchically Modules with interfaces Modules contain instances of primitives, other modules Modules contain initial and always blocks Based on discrete-event simulation semantics Concurrent processes with sensitivity lists Scheduler runs parts of these processes in response to changes
Modeling Tools
Switch-level primitives CMOS transistors as switches that move around charge. Gate-level primitives Boolean logic gates User-defined primitives Gates and sequential elements defined with truth tables Continuous assignment Modeling combinational logic with expressions Initial and always blocks Procedural modeling of behavior
Language Features
Nets (wires) for modeling interconnection Non state-holding Values set continuously Regs for behavioral modeling Behave exactly like memory for imperative modeling. Do not always correspond to memory elements in synthesized netlist. Blocking vs. nonblocking assignment Blocking behaves like normal C-like assignment Nonblocking updates later for modeling synchronous behavior
Language Uses
Event-driven simulation Event queue containing things to do at particular simulated times. Evaluate and update events. Compiled-code event-driven simulation for speed. Logic synthesis Translating Verilog (structural and behavioral) into netlists. Register inference: whether output is always updated. Logic optimization for cleaning up the result.
References
http://www.asic-world.com/verilog/. Palnitkar, Samir, Verilog HDL: A Guide to Design and Synthesis www.sunburst-design.com. IEEE Standard Hardware Description Language Based on the Verilog Hardware Description Language, IEEE Computer Society, IEEE Std 1364-1995.
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