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MIPS Pipeline And Harvard Architecture

MIPS Pipeline And Harvard Architecture

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Published by BravoYusuf
Article includes Instruction Fetch(IF),Instruction Decode(ID),Execution Stage(EX),Memory Stage(MEM) and Write Back (WB) Stage.
Havard Architecture also includes.
Article includes Instruction Fetch(IF),Instruction Decode(ID),Execution Stage(EX),Memory Stage(MEM) and Write Back (WB) Stage.
Havard Architecture also includes.

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Published by: BravoYusuf on Jun 17, 2009
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CS-421 Parallel Processing BE (CIS) Batch 2004-05Handout_5.1
Page - 1 - of 3
MIPS Pipeline
1.
 
Instruction Fetch (IF) Stage
a.
 
 Instruction Fetch
Instruction’s address in PC is applied to instruction memory that causes the addressedinstruction to become available at the output lines of instruction memory. b.
 
Updating PC 
The address in PC is incremented by 4 but what is written in PC is determined by thecontrol signal
PCSrc
. Depending upon the status of control signal
PCSrc,
PC is either written by the branch target address (BTA) or the sequential address (PC + 4).
2.
 
Instruction Decode (ID) Stage
a.
 
Instruction is decoded by the control unit that takes 6-bit opcode and generates controlsignals. b.
 
The control signals are buffered in the pipeline registers until they are used in theconcerned stage by the corresponding instruction.c.
 
Registers are also read in this stage. Note that the first source register’s identifier in everyinstruction is at bit positions [25:21] and second source register’s identifier (if any) is at bit positions [20:16].d.
 
The destination register’s identifier is either at bit positions [15:11] (for R-type) or at[20:16] (for 
lw 
and
addi
). The correct destination register’s identifier is selected viamultiplexer controlled by the control signal
RegDst
.However, this multiplexer is placedin the EX stage because the instruction decoding is not finished until the second stage iscomplete. But this identifier is buffered until the WB stage because
an instruction writesa register in the WB stage.
3.
 
Execution (EX) Stage
a.
 
This stage is marked by the use of ALU that performs the desired operation on registers(R-type), calculates address (memory reference instructions), or compares registers(branch). b.
 
An
 ALU control 
accepts 6-bit
funct
field and 2-bit control signal
 ALUOp
to generatethe required control signal for the ALU.c.
 
BTA is also calculated in the EX stage by a separate adder.
4.
 
Memory (M) Stage
a.
 
Data memory is read (
lw 
) or written (
sw 
) using the address calculated by the ALU in EXstage. b.
 
ZERO
 
output of ALU and
BRANCH
signal generated by the control unit are ANDedto determine the fate of branch (taken or not taken).
 
 
CS-421 Parallel Processing BE (CIS) Batch 2004-05Handout_5.1
Page - 2 - of 3
5.
 
Write Back (WB) Stage
a.
 
Result produced by ALU in EX stage (R-type) or data read from data memory in M stage(lw) is written in destination register. The data to be written in destination register isselected via multiplexer controlled by the control signal
MemToReg.
 
Harvard Architecture
Separate memory units for instructions and data (Harvard Architecture) are required because in agiven pipeline cycle two instructions may need to use memory (one for instruction fetch andanother for data read/write) as shown below.
WB
I
1
I
2
I
3
I
4
I
5
I
6
 
MI
1
 
I
2
I
3
I
4
I
5
I
6
I
7
 
EX
I
1
I
2
I
3
I
4
I
5
I
6
I
7
I
8
 
ID
I
1
I
2
I
3
I
4
I
5
I
6
I
7
I
8
I
9
 
IF
I
1
I
2
I
3
 
I
4
 
I
5
I
6
I
7
I
8
I
9
I
10
 
cycles
1 2 3
4
5 6 7 8 9 10As indicated, in cycle 4
I
1
accesses memory for data read/write
and
I
4
 
is being fetchedaccessing instruction memory
.
 Harvard Architecture averts this problem
.
Exercise
1.
 
What are the sizes of pipeline registers IF/ID, ID/EX, EX/M and M/WB?2.
 
Why there is no pipeline register needed after WB stage?
Graphical Representation of MIPS Pipeline
Consider pipelined execution of following MIPS instructions:
lw $1, 0($2)add $3, $4, $5
The lw instruction uses all stages in the pipeline but add (like any other R-type instruction)doesn’t access data memory i.e. it doesn’t use M stage. Thus the progress of above instructionsthrough the MIPS pipeline is illustrated below:CC1 CC2 CC3 CC4 CC5
lw
IF ID EX M
WB
add
IF ID EX
WB
Did you notice any problem? In CC5 a
resource conflict 
is observed. That is, two differentinstructions attempt to use the same hardware in the same cycle. This can be averted by
ensuring uniformity
:
make all instructions pass through all the stages in the same order 
.

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/*********** DO NOT ALTER ANYTHING BELOW THIS LINE ! ************/ var s_code=s.t();if(s_code)document.write(s_code)//-->