CS-421 Parallel Processing BE (CIS) Batch 2004-05Handout_5.1
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Instruction Fetch (IF) Stage
Instruction’s address in PC is applied to instruction memory that causes the addressedinstruction to become available at the output lines of instruction memory. b.
The address in PC is incremented by 4 but what is written in PC is determined by thecontrol signal
. Depending upon the status of control signal
PC is either written by the branch target address (BTA) or the sequential address (PC + 4).
Instruction Decode (ID) Stage
Instruction is decoded by the control unit that takes 6-bit opcode and generates controlsignals. b.
The control signals are buffered in the pipeline registers until they are used in theconcerned stage by the corresponding instruction.c.
Registers are also read in this stage. Note that the first source register’s identifier in everyinstruction is at bit positions [25:21] and second source register’s identifier (if any) is at bit positions [20:16].d.
The destination register’s identifier is either at bit positions [15:11] (for R-type) or at[20:16] (for
). The correct destination register’s identifier is selected viamultiplexer controlled by the control signal
.However, this multiplexer is placedin the EX stage because the instruction decoding is not finished until the second stage iscomplete. But this identifier is buffered until the WB stage because
an instruction writesa register in the WB stage.
Execution (EX) Stage
This stage is marked by the use of ALU that performs the desired operation on registers(R-type), calculates address (memory reference instructions), or compares registers(branch). b.
field and 2-bit control signal
to generatethe required control signal for the ALU.c.
BTA is also calculated in the EX stage by a separate adder.
Memory (M) Stage
Data memory is read (
) or written (
) using the address calculated by the ALU in EXstage. b.
output of ALU and
signal generated by the control unit are ANDedto determine the fate of branch (taken or not taken).