Workshop on Fully Layout Technology

2002 / 03 / 23

THE ART OF ANALOG LAYOUT

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$%&'()*+ TEL/03-5101949
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Workshop on Fully Layout Technology

2002 / 03 / 23

01
23Analog4567 89analog matching guide :;'<=>?@ Design A layout >BC

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Workshop on Fully Layout Technology

2002 / 03 / 23

ANALOG LAYOUT
CMOS ANALOG LAYOUT BIPOLAR ANALOG LAYOUT BICMOS ANALOG LAYOUT

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Workshop on Fully Layout Technology

2002 / 03 / 23

CMOS ANALOG LAYOUT

CMOS Component Layout Guide CMOS Layout Application
Transistor Capacitor Resistor Bipolar Mos power transistor

CMOS Layout Case Study

4
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Workshop on Fully Layout Technology

2002 / 03 / 23

CMOS LAYOUT STRUCTURE

LV NMOS !(poly)&(active)&(nplus)&(psub) LV PMOS !(poly)&(active)&(pplus)&(nwell)

s
5

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Workshop on Fully Layout Technology

2002 / 03 / 23

CMOS LAYOUT STRUCTURE

Asymmetric HV12V Device Layout

N++ N+ POLY
DIFF

P+ N+ PDD

POLY

P+

NWELL

HV HV MT1

CONTACT

DIFF
DRAIN GATESOURCE DRAIN GATE SOURCE

NMOS
6

PMOS
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Workshop on Fully Layout Technology

2002 / 03 / 23

CMOS LAYOUT STRUCTURE

Asymmetric HVP30V Device Layout

NWELL+BL NWELL+HPF POLY N+

L
CO
DRAIN GATE SOURCE

HV DIFF P+
DRAIN

L
GATE SOURCE

HV DIFF

HPF+BL

POLY

PMOS
7

NMOS
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Workshop on Fully Layout Technology

2002 / 03 / 23

CMOS-RESISTOR LAYOUT STRUCTURE

>>Diff Resistor CONTACT

>>Poly register
POLY1

>>Nwell Resistor Ndiff

P+
DIFF
NWELL

NWELL DUMMY
8

DUMMY

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Workshop on Fully Layout Technology CO

2002 / 03 / 23

CMOS-CAPACITOR LAYOUT STRUCTURE

1"P1-P2 LAYOUT STRUCTURE M1

poly1

M2
2"MOS LAYOUT STRUCTURE CO

POLY2

N+
DIFF

P+

poly 1

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Workshop on Fully Layout Technology 3DMIN TOPMETAL A TOPMETAL-1EFG-MINLAYER

2002 / 03 / 23

CMOS-CAPACITOR LAYOUT STRUCTURE

M4 VIA4 M 5

MIM
4DMETAL POLY STRUCTURE
NWELL CONTACT

BOTTOM=POLY1+M2 TOP=M1+M3
10
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Workshop on Fully Layout Technology

2002 / 03 / 23

CMOS-PNP LAYOUT STRUCTURE

NWELL CONTACT

DIFF M1 P+

11

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Workshop on Fully Layout Technology

2002 / 03 / 23

CMOS-FUSE LAYOUT STRUCTURE

METAL FUSE POLY1 FUSE
CONTACT

POLY1 FUSE

M1

M1

CONTACT

POLY1

PASS

POL Y1
12

STYLE-1

STYLE-2

STYLE -3

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Workshop on Fully Layout Technology

2002 / 03 / 23

CMOS LAYOUT APPLICATION -TRANSISTOR >>MOS Matching Mirror

M2 VIA M1

P+

POLY
13

CONTACT DIFF
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Workshop on Fully Layout Technology

2002 / 03 / 23

CMOS LAYOUT APPLICATION -TRANSISTOR >>HIJK L1M

OUT P OUT N

14

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Workshop on Fully Layout Technology

2002 / 03 / 23

CMOS LAYOUT APPLICATION -TRANSISTOR >>HIJKL2M

DUMMY POLY

15

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Workshop on Fully Layout Technology

2002 / 03 / 23

CMOS LAYOUT APPLICATION-CAPACITOR

>>Unit Capacitor

DUMMY DUMMY

Well contact

16

poly

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Workshop on Fully Layout Technology

2002 / 03 / 23

CMOS LAYOUT APPLICATION-CAPACITOR >>Unit Capacitor Input Stage Matching

POLY2 POLY1

WELL CONTACT

M1

17

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Workshop on Fully Layout Technology

2002 / 03 / 23

CMOS LAYOUT APPLICATION-RESISTOR >> Normal Resistor-NOPQRS

18

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Workshop on Fully Layout Technology

2002 / 03 / 23

CMOS LAYOUT APPLICATION-RESISTOR >>Crocess Resistor

M2 VIA WELLCONTACT CONTACT

POLY M1

19

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Workshop on Fully Layout Technology

2002 / 03 / 23

CMOS LAYOUT APPLICATION -RESISTOR >>HIJK

DUMMY

DUMMY

20

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Workshop on Fully Layout Technology

2002 / 03 / 23

CMOS LAYOUT APPLICATION PNP X 10

P+

NWELL N+

P+

21

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Workshop on Fully Layout Technology

2002 / 03 / 23

CMOS LAYOUT APPLICATION PNP X 9

N+ NWELL P+ P+

22

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Workshop on Fully Layout Technology

2002 / 03 / 23

CMOS LAYOUT APPLICATION-Power MOS Transistor(1)

ESD PROTECTION 45TUVWXYZ YZ[\]^_ ESD PROTECTION `abcd

STYLE -1
23

STYLE -2
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Workshop on Fully Layout Technology

2002 / 03 / 23

CMOS LAYOUT APPLICATION Power MOS Transistor(2)

efghi"TYj^_
N+ DIFF NWELL

P+ DIFF

POLY

24

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Workshop on Fully Layout Technology

2002 / 03 / 23

CMOS LAYOUT APPLICATION- Power MOS Transistor#3$

N+DIFF P+DIFF
NDIFF POLY

25

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Workshop on Fully Layout Technology

2002 / 03 / 23

CMOS LAYOUT APPLICATION Power MOS Transistor#4$ >>M2 Finger Structure M2

M1

26

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Workshop on Fully Layout Technology

2002 / 03 / 23

CMOS LAYOUT CASE STUDY >>OP1

NW OD P+ N+ P1 P2 CO M1 M2 VIA

27

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Workshop on Fully Layout Technology

2002 / 03 / 23

CMOS LAYOUT CASE STUDY >>OP2 4 4 4 6

IP IN

5 1 4
NW OD P+ N+ P1 P2 CO M1 M2 VIA
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3 5 6

7 8
28

7 8

Workshop on Fully Layout Technology

2002 / 03 / 23

CMOS LAYOUT CASE STUDY-CIRCUIT

29

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Workshop on Fully Layout Technology

2002 / 03 / 23

BIPOLAR ANALOG LAYOUT

BIPOLAR Component Layout Guide BIPOLAR Layout Application

BIPOLAR Layout Case Study

30
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Workshop on Fully Layout Technology

2002 / 03 / 23

BIPOLAR LAYOUT STRUCTURE-VNPN

BL DC SP SN CO M1 VIA M2 TO CAP IR

STYLE-1

STYLE-2

31

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Workshop on Fully Layout Technology

2002 / 03 / 23

BIPOLAR LAYOUT STRUCTURE-LPNP

BL DC SP SN CO M1 VIA M2 TO CAP IR

STYLE-1

STYLE-2

STYLE-3

32

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Workshop on Fully Layout Technology

2002 / 03 / 23

BIPOLAR CAPACITOR LAYOUT STRUCTURE >>Sn-cap type SN

MT1

BL BIPOLAR-RISISTOR LAYOUT STRUCTURE

TO cap IR
33

SP
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Workshop on Fully Layout Technology

2002 / 03 / 23

BIPOLAR LAYOUT APPLICATION-VNPN

34

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Workshop on Fully Layout Technology

2002 / 03 / 23

BIPOLAR LAYOUT APPLICATION-LPNP

STYLE-1

STYLE-2

35

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Workshop on Fully Layout Technology

2002 / 03 / 23

BIPOLAR LAYOUT APPLICATION-LPNP

STYLE-3
36

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Workshop on Fully Layout Technology

2002 / 03 / 23

BIPOLAR LAYOUT APPLICATION-Power Transistor

EMIT YZ[k^l mnopqr stVuvw

xj
37

yzj

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Workshop on Fully Layout Technology

2002 / 03 / 23

BIPOLAR LAYOUT APPLICATION-VNPN {GEMIT>|}i~`a

38

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Workshop on Fully Layout Technology

2002 / 03 / 23

BIPOLAR LAYOUT CASE STUDY

39

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Workshop on Fully Layout Technology

2002 / 03 / 23

BIPOLAR LAYOUT CASE STUDY -CIRCUIT

40

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Workshop on Fully Layout Technology

2002 / 03 / 23

BIPOLAR LAYOUT CASE STUDY

41

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Workshop on Fully Layout Technology

2002 / 03 / 23

BICMOS ANALOG LAYOUT

BICMOS Component Layout Guide BICMOS Layout Application

BICMOS Layout Case Study

42

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Workshop on Fully Layout Technology

2002 / 03 / 23

BICMOS LAYOUT STURCTURE

43

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Workshop on Fully Layout Technology

2002 / 03 / 23

BICMOS LAYOUT STURCTURE-VPNP

>>Double Base
CONTACT DIFF PW P+

N+
NWELL

44

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Workshop on Fully Layout Technology

2002 / 03 / 23

BICMOS LAYOUT STURCTURE-LPNP

NWELL
NDIFF

N+BL
PDIFF

POLY
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45

Workshop on Fully Layout Technology

2002 / 03 / 23

BICMOS LAYOUT STURCTURE-VNPN

>>Double Base-Base ef

46

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Workshop on Fully Layout Technology

2002 / 03 / 23

BICMOS LAYOUT STURCTURE-RESISTOR

>>Base Resistor

%>P1 resistor

%>P2 resistor

47

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Workshop on Fully Layout Technology

2002 / 03 / 23

BICMOS LAYOUT STURCTURE

>>SNK Capasistor >>P1-P2 Capasistor
N+INP NWELL N+BL

48

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Workshop on Fully Layout Technology

2002 / 03 / 23

BICMOS LAYOUT APPLICATION-VNPN

>>HIJK

49

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Workshop on Fully Layout Technology

2002 / 03 / 23

BICMOS LAYOUT APPLICATION-VNPN

{GDriver `aiYZ

50

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Workshop on Fully Layout Technology

2002 / 03 / 23

BICMOS LAYOUT CASE STUDY-CASE 1 >>OP1

M1 M3 M4 M3 M4 M2 R2 R2

R2

R2

R2

R2 R2 R2

Q2

Q1

IN IP
Q1 Q2

DUMMY

DUMMY

R1 R1

R1

R1

R1

M5 M5

51

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Workshop on Fully Layout Technology

2002 / 03 / 23

BICMOS CASE STUDY OP CIRCUIT

52

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Workshop on Fully Layout Technology AMP

2002 / 03 / 23

BICMOS LAYOUT CASE STUDY-CASE 2

G1
DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY
COLLECT

M6 M6 M3 M2 M2 M1 M1 M2 M2 M3 M3

M5 M4

M1 M1

IN

M3

M4 M5

M6 M6

DUMMY

R1 R1

Q3
DUMMY
R2 R3

Q2
DUMMY

Q1
DUMMY

R1 R1 R1

DUMMY DUMMY

R1 R1 R1 R1 R1 R1 R1 R2

R4 R3 R4 R3 R3

DUMMY

DUMMY

R1 R1 R1 R1 R2 R2 R2 R2

M7

R3 R4 R3 R4

53

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Workshop on Fully Layout Technology

2002 / 03 / 23

BICMOS CASE STUDY AMP CIRCUIT

54

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