Analysis and Improvement of the Switching

Behaviour of Low Voltage Power MOSFETs with

High Current Ratings under Hard Switching
Conditions
Bjoern Wittig and Friedrich W. Fuchs
Christian-Albrechts-University of Kiel, Germany
Institute of Power Electronics and Electrical Drives
Kaiserstr. 2, 24143 Kiel, Germany
Email: bw@tf.uni-kiel.de
AbstractAn analysis and improvement of the switching be-
haviour of low voltage power MOSFETs with high current ratings
is presented. Different turn-off active gate control circuits are
described and their performance is analyzed with the focus on the
reduction of the overvoltage at turn-off under the precondition of
limited increasing of switching losses. The control methods are
experimentally compared to a basic gate drive circuit for two
different types of low voltage power MOSFETs.
I. INTRODUCTION
In battery fed power trains, like in cars and lift trucks,
power MOSFETs with high current ratings play a signicant
role. Typical applications are dc/ac converters for feeding
a three phase ac motor or dc/dc converters [1][3]. Due
to the high power and low voltages of i.e. 24 V in some
applications high currents are the consequence. Thus there
is a high demand for low voltage power MOSFETs with
a low drain-source on-state resistance R
DS(on)
and a low
temperature dependence on the market to achieve lower
conduction losses.
Due to the reduction of the drain-source on-state resistance
R
DS(on)
of modern automotive power MOSFETs and the
subsequently decreasing conduction losses, the switching
losses get a higher inuence of the total power losses
of the semiconductors. With higher switching frequencies
this effect rises and can play an important role in the
choice of a power MOSFET type and gate drive circuit
design has an inuence on the switching losses. Active gate
control of switch on and switch off via the gate drive could
be a chance to reduce the switching losses or the overvoltages.
In the literature many low cost and easy to implement
active gate control methods have been presented for
applications with IGBTs under hard switching conditions.
Only a few publications were made concerning the use for
power MOSFETs as the authors know [4][6].
In [4] a small inductance is used to measure the current
slope in the power MOSFET for decreasing or increasing
the switching speed. In addition a concept was presented by
measuring the drain source voltage slope of the MOSFET to
inuence the switching behaviour. Another method is the use
of a small transformer to control a signal mosfet at the gate
drive circuit and to inject an additional current during turn-on,
which leads to a decreasing turn-on switching energy [5]. In
[6] an EMI suppression driver is presented which only slows
down the gate-source voltage transition near the gate-source
threshold voltage, reducing the drain-source voltage slope.
An obvious way to increase or to decrease the voltage and
current slopes applied for an IGBT is to switch on or off an
additional gate resistor and current path to the available gate
resistor as described in [7][9]. In [10], [11] the transistor
is turned on again for a very short time after the end of
the switching process to decrease the current slope and
the overvoltage caused by the parasitic inductances in the
commutation path.
In this paper an analysis and improvement of the switching
behaviour of low voltage power MOSFETs with high current
ratings under hard switching conditions is presented. A
short explanation and analysis of the theoretical switching
behaviour and the effect of the stray inductance of the
commutation path on the drain-source voltage characteristic
is given at rst. Different turn-off active gate control methods
are presented and analysed. These methods are divided
into three types - the du/dt-control, the di/dt-control and
the two-stage-control - and their functionality is explained.
Experimental results for two different types of low voltage
power MOSFETs are presented. A comparison of the results
worked out for the different presented active gate control
methods is presented at the end of this paper.
II. SWITCHING BEHAVIOUR OF LOW VOLTAGE POWER
MOSFETS
A typical test circuit for the hard switching process
of power MOSFETs with an inductive load and with a
conventional gate drive circuit is illustrated in Fig. 1. Here
the MOSFET M
2
is the device under test and M
1
is used as a
978-1-4244-6391-6/10/$26.00 2010 644
Fig. 1. Typical test circuit for the hard switching process of power MOSFETs
with an inductive load and with a conventional gate drive circuit
freewheeling diode like in a typical half bridge conguration.
The stray inductance L

represents the sum of all stray

inductances in the commutation path. The theoretical current
and voltage characteristic at turn-on and turn-off of a power
MOSFET is displayed in Fig. 2 [12], [13]. The widely used
denitions of the current and voltage rise and fall times and
the turn-on and turn-off delay times for power MOSFETs are
depicted here also.
In Fig. 2 the dotted lines show the theoretical characteristic
considering the stray inductance L

. The drain current

overshoot, which results from the reverse recovery current
I
RRM
of the body-diode of M
1
, is indicated also.
At turn-on during the current rise time the induced positive
voltages at the stray inductances in the commutation path lead
to a lower voltage stress of the power MOSFET M
2
[12], [15].
In this phase the voltage decrease is:
V
ind
= L

di
D
dt
(1)
During the turn-off process and the current fall time the
induced voltages at the stray inductances are negative. Consid-
ering the turn-on overvoltage V
FRM
of the inverse body-diode
of M
1
leads to the following overvoltage peak at turn-off [12]:
V
pk
= L

di
D
dt
+V
FRM
(2)
For lower current slopes the turn-on overvoltage V
FRM
of
the body diode can be neglected but at higher values V
FRM
increases and can lead to an additional overvoltage of a few
volts for a short time.
In Fig. 2 the principle characteristic of the switching
losses is illustrated also. There the conduction losses and
the normally negligible blocking losses are indicated as
E
cond
respectively E
block
. Considering the parasitic stray
inductances in the commutation path and the described
voltage characteristic as mentioned above, this induced
voltages are responsible for a lower turn-on energy E
s(on)
and a higher turn-off energy E
s(off)
. Because of the very low
resulting turn-on energy and the relative low amplitude of
drain current overshoot, turn-on active gate control methods
Fig. 2. Theoretical current and voltage characteristic at turn-on and turn-
off of a power MOSFET, without (continuous line) and with (dotted line)
consideration of the stray inductance L in the commutation path
Fig. 3. Experimental turn-on and turn-off process of the power MOSFET
NP110N055PUG from NEC [14]: V
GS
5V/div (blue line), V
DS
10V/div
(green line), I
D
50A/div (red line), t 200ns/div; V
DD
= 24 V, R
G
= 3.9 ,
T
J
= 20

C
are not mandatory. Therefore the following analysis of
active gate drive concepts deals only with the inuence and
improvement of the turn-off switching characteristic of low
voltage power MOSFETs. In Fig. 3 an exemplary turn-on
and turn-off process of a low voltage power MOSFET is
shown. The reduction of the voltage stress at turn-on and the
overvoltage at turn-off is obvious.
III. ACTIVE GATE TURN-OFF CONTROL CIRCUITS
A. du/dt-control
A widely used method to inuence the switching behaviour
is the so called du/dt-control, which can be seen in Fig. 4
645
Fig. 4. du/dt-control methods a) du/dt-control by means of an external
gate-drain-capacitance, b) du/dt-control by means of an external gate-drain-
capacitance and a zener diode in series
(a) [16], [17]. There the voltage slope is fed back i.e. by
a small capacitance between the gate and the drain of the
power MOSFET.
The current through the external gate-drain-capacitance
C
GD
, which is proportional to the voltage slope dv
DS
/dt of
the transistor, is directly coupled into the gate of the power
MOSFET. This leads to an increase of the voltage rise time
and the current fall time. An expansion of this switching
control method is shown in Fig. 4 (b), where an additional
zener diode D
z
is used in series to the external capacitance
C
GD
, well known as an active clamping concept. This induces
a faster voltage rise at the beginning of the turn-off process
and a slower voltage rise at higher drain-source-voltage. By
the way the current slope is reduced. Thus it is possible only
to react at too high overvoltages.
B. di/dt-control
Another way to inuence the switching speed is to measure
the current slope di
D
/dt with a feedback circuit at the
gate, which is called di/dt-control. This can be done by an
additional inductance at the source pin of the power MOSFET
or by using the parasitic inductance L
S2
of the copper wire
or track. If a too high current falling slope is detected by
means of the induced voltage at the inductance, a positive
current is fed back via R
S
and D
1
into the gate of the power
MOSFET during the current fall time, which is controlled
towards on state.
In Fig. 5 two ways of realization of the control method
are displayed [17]. The rst method in Fig. 5 (a) leads to no
satisfying results because of the slow response time and the
relative high on-state resistance of the zener diode. Using a
signal transistor T
S
instead of a zener diode as shown in Fig.
5 (b) leads to better results. Thus it is possible to control
the current slope without to inuence the voltage slope at
turn-off.
C. Two-stage-control
A more complex active gate control method is the two-
stage-control, where a low ohmic current path for switch
off is in parallel to the conventional gate resistor during
Fig. 5. di/dt-control methods a) di/dt-control by means of a zener diode , b)
di/dt-control by means of a signal mosfet in the current feedback path
Fig. 6. Two-stage-control gate drive circuit
the voltage rise time. In Fig. 6 the principle circuit of the
two-stage-control circuit is presented. The low ohmic current
path is realized by the transistor T
2
, the low ohmic resistance
R
Goff,2
and the diode D
Goff,2
. At the beginning of the
turn-off process, T
2
is turned on via the gate voltage V
gg
.
Additionally a small current is injected through R
1
and D
1
into the power stage and leads to a voltage drop across R
2
and R
3
. This voltage drop is nearly the drain-source voltage
of the power MOSFET plus the forward voltage of the diode
D
1
. At a dened measured drain-source voltage the transistor
T
1
is turned on and hence T
2
is turned-off. During the current
fall time the low ohmic current path is switched off by this
way.
Although this leads to nearly the same current fall time
and therefore nearly the same induced V
DS
voltage peak
compared to the conventional gate drive circuit, the voltage
rise time can be reduced. Furthermore the turn-off delay time
t
d(off)
is kept low and nearly constant for increasing gate
resistance R
Goff,1
. These method has been also presented
in the literature with IGBTs instead of low voltage power
MOSFETs [18].
IV. EXPERIMENTAL RESULTS
For experimental analysis two different low voltage power
MOSFETs are used, which are described shortly in Ta-
ble I [14], [19]. Both power MOSFETs offer nearly the
646
Fig. 7. Experimental turn-on and turn-off characteristics of the two-stage-control method in comparison with the conventional gate drive @ R
G
= 7.5 ,
T
J
= 20

C: a) NP110N055PUG from NEC, b) IRFS3306PbF from International Rectier

Fig. 8. Experimental turn-on and turn-off characteristics of the du/dt-control by means of an external gate-drain-capacitance in comparison with the
conventional gate drive @ R
G
= 10 , T
J
= 20

C: a) NP110N055PUG from NEC, b) IRFS3306PbF from International Rectier

same breakdown voltage V
DSS
and continuous drain cur-
rent rating I
D,cont.
. The typical input capacitance C
iss
of
the NP110N055PUG, selected from the datasheet table, is
almost four times higher than the input capacitance of the
IRFS3306PbF. Therefore a signicant longer turn-off delay
time t
d(off)
and voltage rise time t
ru
is expected in case of
the NP110N055PUG.
The stray inductance L

of the whole current commutation

path in this laboratory setup is measured to about 36 nH. The
DC link voltage V
DD
is chosen to 24 V. All control methods
have been tested at the same working point. Additional analy-
ses at junction temperatures of T
J
= 100

C have been made,

which have not led to an essential temperature dependence of
the switching process with and without the proposed control
methods and will be therefore not presented here.
NP110N055 IRFS3306
PUG PbF
Breakdown voltage VDSS 55 V 60 V
Drain current ID,cont. 110 A 120 A
Drain-source resist. R
DS(on)
1.9 m 3.3 m
Input capacitance Ciss 17100 pF 4520 pF
TABLE I
DATASHEET PARAMETERS OF THE USED POWER MOSFETS IN THE
LABORATORY SETUP, [14], [19]
In Fig. 7 the experimental turn-on and turn-off characteristic
of both used power MOSFETs in case of the conventional and
647
Fig. 9. Experimental results of the presented active gate control methods with the NP110N055PUG from NEC @ V
DD
= 24 V, I
D
= 150 A, T
J
= 20

C
the two-stage gate drive circuit are shown. Due to the stray
inductance L

of the commutation path, the drain-source

voltage is very low during the current rise time. It is clearly
to be recognized, that the two-stage control method leads to
a faster voltage rise time and therefore to considerable lower
turn-off losses. The turn-on behaviour is not inuenced by
the two-stage-control method.
Comparing the turn-on and turn-off characteristic of both
power MOSFETs, it is cognoscible, that at same gate
resistance the drain-source voltage slope of the IRFS3306PbF
is higher than the voltage slope of the NP110N055PUG.
This is caused by the lower input capacitance C
iss
of the
IRFS3306PbF as mentioned before.
The du/dt-control by means of an external gate-drain-
capacitance is compared with the conventional gate drive
circuit in Fig. 8. At turn-on the current and voltage
characteristics are not different to each other. In contrast at
turn-off the du/dt-control provides a less steep current slope
and therefore a lower induced overvoltage V
ind
, resulting in
a higher turn-off energy E
s(off)
.
For comparison the results of the proposed active gate
drive circuits are illustrated in Fig. 9 for the NP110N055PUG
from NEC. In Fig. 9 (a) the induced overvoltage V
pk
in
dependence on the turn-off energy E
s(off)
is illustrated. It
can be seen, that the two-stage active gate control leads to the
most satisfying results concerning the induced overvoltage
and turn-off losses. For lower gate resistances a reduction
of 10 to 20 % of the turn-off energy E
s(off)
at the same
induced overvoltage was achieved. The du/dt-control method
by the means of an external gate-drain-capacitance with
and without a zener diode also delivers good results. The
di/dt-control does not provide satisfying results at higher
gate-resistances because of the lower voltage drop at the
source stray inductance L
s2
during turn-off.
In Fig. 9 (b)-(c) the induced overvoltage V
ind
and the
turn-on and turn-off switching energy E
s
depending on the
gate-resistance are shown. With higher gate resistance the
overvoltage decreases and the switching energy increases.
In case of the two-stage-control there is a much lower
switching energy rise with higher gate-resistance due to the
reduced voltage rise time, which can also be seen in Fig. 9 (f).
Another effect of the two-stage-control is the short turn-off
delay time t
d(off)
, which is nearly constant with increasing
gate-resistance and much lower compared to the other active
gate drive methods. This can lead indirectly to lower power
losses of a converter with half bridge topology due to a
possible reduction of the deadtimes. In Fig. 10 (a)-(f) the
experimental results for the IRFS3306PbF from International
Rectier are presented, where similar results are depicted as
described before.
V. CONCLUSION
Different turn-off active gate control methods for low volt-
age power MOSFETs with high current ratings have been pre-
sented and analysed. First the theoretical switching behaviour
of a power MOSFET is explained. Different gate control
methods of the du/dt-control and of the di/dt-control and one
two-stage-control concept have been presented. The proposed
gate drive circuits have been realized and measured in the
laboratory. The two-stage-control concept delivers the best
648
Fig. 10. Experimental results of the presented active gate control methods with the IRFS3306PbF from International Rectier @ V
DD
= 24 V, I
D
= 150 A,
T
J
= 20

C
results of the analysed active gate drive circuits considering
the turn-off losses in dependence with the turn-off overvoltage.
The turn-off delay time can be reduced by the two-stage
control in comparison to a conventional gate drive circuit
also. With minor additional components needed a remarkable
reduction of power losses is achieved. Thus this method can
be judged well to be used in industrial applications.
ACKNOWLEDGMENT
The authors would like to thank the Fraunhofer-Gesellschaft
and the state of Schleswig-Holstein, which partly founded this
project. The work was carried out in a combined project of
the Centre of Competence for Power Electronics Schleswig-
Holstein.
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