Power MOSFET Transistor Data PDF

TMOS Power MOSFET Transistor Device Data
Alphanumeric Index of Part Numbers 1
Selector Guide 2
Introduction to Power MOSFETs

Basic Characteristics of Power MOSFETs 3
Data Sheets 4
Surface Mount Package Information and

5
Tape and Reel Specifications
Package Outline Dimensions and Footprints 6
Distributors and Sales Offices 7

Designer’s, SENSEFET, E–FETs, ICePAK, HDTMOS, MiniMOS, SMARTDISCRETES,
Thermopad and Thermowatt are trademarks of Motorola, Inc.
Burst Mode is a trademark of Linear Technology Corp.
Cho–Therm is a registered trademark of Chromerics, Inc.
Grafoil is a registered trademark of Union Carbide
ISOTOP is a trademark of SGS–THOMSON Microelectronics
Kapton is a registered trademark of E.I. Dupont
Rubber–Duc is a trademark of AAVID Engineering
Sil Pad and Thermal Clad are trademarks of the Bergquist Company
Sync–Nut is a trademark of ITW Shakeproof
Thermal Clad is a trademark of the Bergquist Company
Thermasil is a registered trademark and Thermafilm is a trademark of Thermalloy, Inc.
Bourns Knobpot is a registered trademark of Bourns Inc.

TMOS and are registered trademarks of Motorola, Inc.
ii
TMOS Power MOSFET Transistor Device Data
The information in this book has been carefully reviewed and is believed to be accurate; however, no responsibility is assumed
for inaccuracies. Furthermore, this information does not convey to the purchaser of semiconductor devices any license under the
patent rights to the manufacturer.
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty,
representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any
liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without
limitation consequential or incidental damages. “Typical” parameters which may be provided in Motorola data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters,
including “Typicals” must be validated for each customer application by customer’s technical experts. Motorola does not convey
any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as
components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for
any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur.
Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and
hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and
expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with
such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture
of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action
Employer.
 Motorola, Inc. 1996

Previous Edition  1994
“All Rights Reserved”
Printed in U.S.A.
iii
MOTDIST
Three Ways To Receive

Motorola Semiconductor Technical Information
Literature Centers
Printed literature can be obtained from the Literature Centers upon request. For those items that incur a cost, the U.S.
Literature Center will accept Master Card and Visa.
How to reach us:
USA/EUROPE/Locations Not Listed: Motorola Literature Center
P.O. Box 20912
Phoenix, Arizona 85036
Phone: 1–800–441–2447 or 602–303–5454
JAPAN: Nippon Motorola Ltd.
6F Seibu–Butsuryu–Center
3–14–2 Tatsumi Koto–Ku
Tokyo 135, Japan
Phone: 03–81–3521–8315
ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.
2 Dai King Street
Tai Po Industrial Estate
Tai Po N.T. Hong Kong
Phone: 852–2–666–8333
Mfax - Touch–Tone Fax

Mfax offers access to over 30,000 Motorola documents for faxing to customers worldwide. With menus and voice instruc-
tion, customers can request the documents needed, using their own touch–tone telephones from any location, 7 days a
week and 24 hours a day. A number of features are offered within the Mfax system, including product data sheets, applica-
tion notes, engineering bulletins, article reprints, selector guides, Literature Order Forms, Technical Training Information,
and HOT DOCS (4–digit code identifiers for currently referenced promotional or advertising material).
INSTRUCTIONS
You will be asked to enter various pieces of information. To enter phone numbers, fax numbers, or hot document numbers
simply enter numbers from your touch-tone keypad followed by the pound sign. For example, to enter a fax number, you
might enter 6025551212#. (Numeric Input)
To enter combinations of letters and numbers (such as a part number, your first initial, your last name or company name),
you must use sequences of two-digit codes to represent all of the letters and numbers. The telephone keypad groups
three letters on each key. Numbers are prefixed with a “0”. The number “7” would be entered as 07.
Example of Text Input:
The part number MC6530, would be translated as follows:
Text to be entered: M C 6 5 3 0
Two-digit codes: 61 23 06 05 03 00
When prompted for a part number, you would enter 61 23 06 05 03 00 #
“Q” is the fourth letter on the “7” key, “Z” is the fourth letter on the “9” key, 1 2 3 1 2 3 1 2 3
and special characters “–”, “ .” and “/” are on the “1” key. – . / A B C D E F
We suggest that you translate and write out the required information 1 2 3
before starting your call. Then simply enter the pre-translated informa- 1 2 3 1 2 3 1 2 3
tion. G H I J K L MN O
4 5 6
NOTE: The system will repeat each letter as you enter two-digit codes.
Should you make an error, you can reject the entire entry and start over 1 2 3 4 1 2 3 1 2 3 4
when asked to verify. Entering an “✱” will provide you with verbal instruc- P R S Q T U V WX Y Z
tions on entering letters and numbers. During this help information, you 7 8 9
may press any key to skip the remaining message and proceed with
ordering your fax. ✱ 0 #
Should you encounter any problems with this system please contact the system administrator at 602-244-6591.
How to reach us:
Mfax: RMFAX0@email.sps.mot.com –TOUCH–TONE (602) 244–6609
or via the http://Design–NET.com home page, select the Mfax Icon.
iv
Motorola SPS World Marketing Internet Server
Motorola SPS’s Electronic Data Delivery organization has set up a World Wide Web Server to deliver Motorola SPS’s technical
data to the global Internet community. Technical data such as the complete Master Selection Guide along with the OEM North
American price book are available on the Internet server with full search capabilities. Other data on the server include abstracts
of data books, application notes, selector guides, and textbooks. All have easy text search capability. Ordering literature from
the Literature Center is available on line. Other features of Motorola SPS’s Internet server include the availability of a searchable
press release database, technical training information, with on–line registration capabilities, complete on–line access to the
Mfax system for ordering faxes, an on–line technical support form to send technical questions and receive answers through
email, information on product groups, full search capabilities of device models, a listing of the Domestic and International sales
offices, and links directly to other Motorola world wide web servers. For more information on Motorola SPS’s Internet server you
can request BR1307/D from Mfax or the Literature Center.
How to reach us:

After accessing the Internet, use the following URL:
http://Design—NET.com
REV 1
v
Table of Contents
SECTION ONE — MMDF2C01HD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–106
Alphanumeric Index of Part Numbers MMDF2C02E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–115
Alphanumeric Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–2 MMDF2C02HD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–123
Obsolete Part Numbers Cross Reference . . . . . . . . . . . . 1–3 MMDF2C03HD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–132
MMDF2N02E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–141
SECTION TWO — MMDF2P01HD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–147
Selector Guide MMDF2P02E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–154
MMDF2P02HD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–160
TMOS Power MOSFETs . . . . . . . . . . . . . . . . . . . . . . . . . . 2–1
MMDF2P03HD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–167
TMOS Power MOSFETs Numbering System . . . . . . 2–2
MMDF3N02HD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–174
SO–8 (MiniMOS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–3
MMDF3N03HD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–181
Micro8 HDTMOS Products . . . . . . . . . . . . . . . . . . . . 2–3
MMDF4N01HD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–187
EZFET — Power MOSFETs with Zener Gate
MMDF4N01Z . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–194
Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–4
MMFT1N10E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–196
SOT–223 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–4
MMFT2N02EL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–202
DPAK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–4 MMFT2955E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–208
D2PAK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–5 MMFT3055V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–214
D3PAK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–6 MMFT3055VL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–216
TO–220AB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–7 MMSF2P02E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–218
TO–247 (Isolated Mounting Hole) . . . . . . . . . . . . . . . . 2–8 MMSF3P02HD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–224
TO–264 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–8 MMSF3P02Z . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–231
SOT–227B (ISOTOP) . . . . . . . . . . . . . . . . . . . . . . . . . 2–9 MMSF3P03HD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–238
SMARTDISCRETES . . . . . . . . . . . . . . . . . . . . . . . . . . 2–9 MMSF4P01HD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–245
IGBT — Insulated Gate Bipolar Transistor . . . . . . . . 2–10 MMSF4P01Z . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–252
Power MOS Gate Drivers . . . . . . . . . . . . . . . . . . . . . . 2–10 MMSF5N02HD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–259
MMSF5N03HD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–266
SECTION THREE — MMSF5N03Z . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–273
Introduction to Power MOSFETs MMSF7N03HD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–280
Chapter 1: Introduction to Power MOSFETs MPIC2111 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–287
Symbols, Terms and Definitions . . . . . . . . . . . . . . . . . . 3–2 MPIC2112 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–291
Basic TMOS Structure, Operation and Physics . . . . . 3–7 MPIC2113 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–295
Distinct Advantages of Power MOSFETs . . . . . . . . . 3–10 MPIC2117 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–299
Chapter 2: Basic Characteristics of Power MOSFETs MPIC2130 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–303
Output Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 3–13 MPIC2131 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–308
Basic MOSFET Parameters . . . . . . . . . . . . . . . . . . . . . 3–13 MPIC2151 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–313
Temperature Dependent Characteristics . . . . . . . . . . 3–14 MTB1N100E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–317
Drain-Source Diode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–15 MTB2N40E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–323
Chapter 3: The Data Sheet . . . . . . . . . . . . . . . . . . . . . . . 3–17 MTB2N60E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–329
MTB2P50E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–335
SECTION FOUR — Data Sheets MTB3N100E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–341
MC33153 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–2 MTB3N120E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–347
MGP20N14CL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–13 MTB4N80E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–354
MGP20N35CL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–15 MTB6N60E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–360
MGP20N40CL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–20 MTB8N50E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–366
MGW12N120 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–25 MTB9N25E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–368
MGW12N120D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–30 MTB10N40E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–374
MGW20N60D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–35 MTB15N06V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–380
MGW20N120 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–40 MTB16N25E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–386
MGW30N60 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–45 MTB20N20E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–392
MGY20N120D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–49 MTB23P06V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–398
MGY25N120 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–54 MTB30N06VL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–404
MGY25N120D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–59 MTB30P06V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–410
MGY30N60D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–64 MTB33N10E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–416
MGY40N60 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–69 MTB35N06ZL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–422
MGY40N60D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–73 MTB36N06V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–424
MLD1N06CL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–78 MTB50P03HDL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–430
MLD2N06CL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–84 MTB52N06V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–437
MLP1N06CL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–90 MTB52N06VL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–439
MLP2N06CL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–96 MTB55N06Z . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–441
MMDF1N05E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–102 MTB60N06HD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–443
vi
Table of Contents (continued)
SECTION FOUR — Data Sheets (continued) MTP9N25E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–783
MTP10N10E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–789
MTB75N03HDL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–450 MTP10N10EL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–795
MTB75N05HD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–457 MTP10N40E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–801
MTD1N50E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–464 MTP12N10E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–807
MTD1N60E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–470 MTP12P10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–813
MTD1N80E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–476 MTP15N06V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–818
MTD1P50E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–482 MTP15N06VL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–824
MTD2N40E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–484 MTP16N25E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–826
MTD2N50E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–490 MTP20N06V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–832
MTD3N25E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–496 MTP20N20E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–834
MTD4N20E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–502 MTP23P06V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–840
MTD5N25E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–508 MTP27N10E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–846
MTD5P06V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–514 MTP30N06VL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–852
MTD6N10E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–520 MTP30P06V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–858
MTD6N15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–526 MTP33N10E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–864
MTD6N20E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–531 MTP35N06ZL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–870
MTD6P10E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–537 MTP36N06V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–872
MTD9N10E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–543 MTP50P03HDL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–878
MTD10N10EL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–549 MTP52N06V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–885
MTD12N06EZL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–555 MTP52N06VL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–887
MTD15N06V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–561 MTP55N06Z . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–889
MTD15N06VL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–567 MTP60N06HD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–891
MTD20N03HDL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–569 MTP75N03HDL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–898
MTD20N06HD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–576 MTP75N05HD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–905
MTD20N06HDL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–583 MTP75N06HD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–911
MTD20N06V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–590 MTP2955V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–918
MTD20P03HDL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–592 MTP3055V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–920
MTD20P06HDL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–599 MTP3055VL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–926
MTD2955V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–606 MTSF1P02HD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–932
MTD3055V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–608 MTSF2P02HD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–940
MTD3055VL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–614 MTSF3N02HD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–943
MTDF1N02HD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–620 MTSF3N03HD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–951
MTDF1N03HD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–628 MTV6N100E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–959
MTE30N50E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–636 MTV10N100E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–965
MTE53N50E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–642 MTV16N50E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–971
MTE125N20E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–648 MTV20N50E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–977
MTE215N10E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–654 MTV25N50E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–983
MTP1N50E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–660 MTV32N20E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–989
MTP1N60E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–666 MTV32N25E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–995
MTP1N80E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–672 MTW6N100E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–1001
MTP1N100E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–678 MTW7N80E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–1007
MTP2N40E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–684 MTW8N60E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–1013
MTP2N50E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–690 MTW10N100E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–1019
MTP2N60E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–696 MTW14N50E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–1025
MTP2P50E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–702 MTW16N40E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–1031
MTP3N50E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–708 MTW20N50E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–1037
MTP3N60E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–714 MTW24N40E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–1043
MTP3N100E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–720 MTW32N20E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–1049
MTP3N120E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–726 MTW32N25E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–1055
MTP4N40E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–733 MTW35N15E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–1061
MTP4N50E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–735 MTW45N10E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–1067
MTP4N80E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–741 MTY14N100E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–1073
MTP5N40E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–747 MTY16N80E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–1079
MTP5P06V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–753 MTY20N50E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–1085
MTP6N60E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–759 MTY25N60E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–1091
MTP6P20E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–765 MTY30N50E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–1097
MTP7N20E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–771 MTY55N20E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–1103
MTP8N50E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–777 MTY100N10E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4–1109
vii
SECTION FIVE — SECTION SIX —
Surface Mount Package Information Package Outline Dimensions and Footprints
and Tape and Reel Specifications Package Outline Dimensions and Footprints . . . . . . . . . 6–2
Surface Mount Package Information . . . . . . . . . . . . . . . . 5–2
Power Dissipation for a Surface Mount Device . . . . . 5–2 SECTION SEVEN —
Solder Stencil Guidelines . . . . . . . . . . . . . . . . . . . . . . . 5–3 Distributors and Sales Offices
Soldering Precautions . . . . . . . . . . . . . . . . . . . . . . . . . . 5–3
Distributors and Sales Offices . . . . . . . . . . . . . . . . . . . . . . 7–2
Typical Solder Heating Profile . . . . . . . . . . . . . . . . . . . 5–4
Footprints for Soldering . . . . . . . . . . . . . . . . . . . . . . . . . 5–5
Tape and Reel Specifications . . . . . . . . . . . . . . . . . . . . . . 5–6
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–6
Embossed Tape and Reel Data . . . . . . . . . . . . . . . . . . 5–7
viii
Section One
Alphanumeric Index of Part Numbers
Alphanumeric Index of Part Numbers . . . . . . . . . . . . . . . 1–2

Obsolete Part Numbers Cross Reference . . . . . . . . . . . . 1–3
Motorola TMOS Power MOSFET Transistors Device Data Alphanumeric Index of Part Numbers
1–1

Alphanumeric Index of Part Numbers
The following index provides you with a quick page number reference for complete data sheets. Contact your local Motorola
Sales Office for data sheets not referenced in this index.
Motorola Data Sheet Motorola Data Sheet Motorola Data Sheet

Part Number Page Number Part Number Page Number Part Number Page Number
MC33153 4–2 MTB1N100E 4–317 MTDF1N02HD 4–620

MGP20N14CL 4–13 MTB2N40E 4–323 MTDF1N03HD 4–628
MGP20N35CL 4–15 MTB2N60E 4–329 MTE30N50E 4–636
MGP20N40CL 4–20 MTB2P50E 4–335 MTE53N50E 4–642
MGW12N120 4–25 MTB3N100E 4–341 MTE125N20E 4–648
MGW12N120D 4–30 MTB3N120E 4–347 MTE215N10E 4–654
MGW20N60D 4–35 MTB4N80E 4–354 MTP1N50E 4–660
MGW20N120 4–40 MTB6N60E 4–360 MTP1N60E 4–666
MGW30N60 4–45 MTB8N50E 4–366 MTP1N80E 4–672
MGY20N120D 4–49 MTB9N25E 4–368 MTP1N100E 4–678
MGY25N120 4–54 MTB10N40E 4–374 MTP2N40E 4–684
MGY25N120D 4–59 MTB15N06V 4–380 MTP2N50E 4–690
MGY30N60D 4–64 MTB16N25E 4–386 MTP2N60E 4–696
MGY40N60 4–69 MTB20N20E 4–392 MTP2P50E 4–702
MGY40N60D 4–73 MTB23P06V 4–398 MTP3N50E 4–708
MLD1N06CL 4–78 MTB30N06VL 4–404 MTP3N60E 4–714
MLD2N06CL 4–84 MTB30P06V 4–410 MTP3N100E 4–720
MLP1N06CL 4–90 MTB33N10E 4–416 MTP3N120E 4–726
MLP2N06CL 4–96 MTB35N06ZL 4–422 MTP4N40E 4–733
MMDF1N05E 4–102 MTB36N06V 4–424 MTP4N50E 4–735
MMDF2C01HD 4–106 MTB50P03HDL 4–430 MTP4N80E 4–741
MMDF2C02E 4–115 MTB52N06V 4–437 MTP5N40E 4–747
MMDF2C02HD 4–123 MTB52N06VL 4–439 MTP5P06V 4–753
MMDF2C03HD 4–132 MTB55N06Z 4–441 MTP6N60E 4–759
MMDF2N02E 4–141 MTB60N06HD 4–443 MTP6P20E 4–765
MMDF2P01HD 4–147 MTB75N03HDL 4–450 MTP7N20E 4–771
MMDF2P02E 4–154 MTB75N05HD 4–457 MTP8N50E 4–777
MMDF2P02HD 4–160 MTD1N50E 4–464 MTP9N25E 4–783
MMDF2P03HD 4–167 MTD1N60E 4–470 MTP10N10E 4–789
MMDF3N02HD 4–174 MTD1N80E 4–476 MTP10N10EL 4–795
MMDF3N03HD 4–181 MTD1P50E 4–482 MTP10N40E 4–801
MMDF4N01HD 4–187 MTD2N40E 4–484 MTP12N10E 4–807
MMDF4N01Z 4–194 MTD2N50E 4–490 MTP12P10 4–813
MMFT1N10E 4–196 MTD3N25E 4–496 MTP15N06V 4–818
MMFT2N02EL 4–202 MTD4N20E 4–502 MTP15N06VL 4–824
MMFT2955E 4–208 MTD5N25E 4–508 MTP16N25E 4–826
MMFT3055V 4–214 MTD5P06V 4–514 MTP20N06V 4–832
MMFT3055VL 4–216 MTD6N10E 4–520 MTP20N20E 4–834
MMSF2P02E 4–218 MTD6N15 4–526 MTP23P06V 4–840
MMSF3P02HD 4–224 MTD6N20E 4–531 MTP27N10E 4–846
MMSF3P02Z 4–231 MTD6P10E 4–537 MTP30N06VL 4–852
MMSF3P03HD 4–238 MTD9N10E 4–543 MTP30P06V 4–858
MMSF4P01HD 4–245 MTD10N10EL 4–549 MTP33N10E 4–864
MMSF4P01Z 4–252 MTD12N06EZL 4–555 MTP35N06ZL 4–870
MMSF5N02HD 4–259 MTD15N06V 4–561 MTP36N06V 4–872
MMSF5N03HD 4–266 MTD15N06VL 4–567 MTP50P03HDL 4–878
MMSF5N03Z 4–273 MTD20N03HDL 4–569 MTP52N06V 4–885
MMSF7N03HD 4–280 MTD20N06HD 4–576 MTP52N06VL 4–887
MPIC2111 4–287 MTD20N06HDL 4–583 MTP55N06Z 4–889
MPIC2112 4–291 MTD20N06V 4–590 MTP60N06HD 4–891
MPIC2113 4–295 MTD20P03HDL 4–592 MTP75N03HDL 4–898
MPIC2117 4–299 MTD20P06HDL 4–599 MTP75N05HD 4–905
MPIC2130 4–303 MTD2955V 4–606 MTP75N06HD 4–911
MPIC2131 4–308 MTD3055V 4–608 MTP2955V 4–918
MPIC2151 4–313 MTD3055VL 4–614 MTP3055V 4–920
Alphanumeric Index of Part Numbers Motorola TMOS Power MOSFET Transistor Device Data
1–2
ALPHANUMERIC INDEX OF PART NUMBERS (continued)
Motorola Data Sheet Motorola Data Sheet Motorola Data Sheet

Part Number Page Number Part Number Page Number Part Number Page Number
MTP3055VL 4–926 MTV32N25E 4–995 MTW32N25E 4–1055

MTSF1P02HD 4–932 MTW6N100E 4–1001 MTW35N15E 4–1061
MTSF2P02HD 4–940 MTW7N80E 4–1007 MTW45N10E 4–1067
MTSF3N02HD 4–943 MTW8N60E 4–1013 MTY14N100E 4–1073
MTSF3N03HD 4–951 MTW10N100E 4–1019 MTY16N80E 4–1079
MTV6N100E 4–959 MTW14N50E 4–1025 MTY20N50E 4–1085
MTV32N20E 4–989
Obsolete Part Numbers Cross Reference

Old Part New Part Old Part New Part Old Part New Part
Number Number Number Number Number Number
BUZ11 MTP36N06V IRFZ20 MTP15N06V MTP8N06E MTP15N06V

BUZ71 MTP15N06V MMFT3055E MMFT3055V MTP15N05E MTP15N06V
BUZ71A MTP15N06V MMFT3055EL MMFT3055VL MTP15N05EL MTP15N06VL
IRF510 MTP10N10E MTB15N06E MTB15N06V MTP15N06E MTP15N06V
IRF520 MTP10N10E MTB23P06E MTB23P06V MTP23P06 MTP23P06V
IRF530 MTP12N10E MTB30N06EL MTB30N06VL MTP30N06EL MTP30N06VL
MTP36N06E MTP36N06V
IRF540 MTP27N10E MTB36N06E MTB36N06V
MTP50N05E MTP50N06V
IRF610 MTP7N20E MTB50N06E MTB50N06V
MTP50N05EL MTP50N06VL
IRF620 MTP7N20E MTB50N06EL MTB50N06VL
MTP50N06E MTP50N06V
IRF630 MTP20N20E MTD5P06E MTD5P06V MTP2955E MTP2955V
IRF640 MTP20N20E MTD8N06E MTD15N06V MTP3055E MTP3055V
IRF720 MTP4N40E MTD10N05E MTD15N06V MTP3055EL MTP3055VL
IRF730 MTP5N40E MTD2955E MTD2955V MTW20P10 MTP12P10
IRF740 MTP10N40E MTD3055E MTD3055V MTW23N25E MTW32N25E
IRF820 MTP3N50E MTD3055EL MTD3055VL MTW26N15E MTW35N15E
IRF840 MTP8N50E MTP3N25E MTP9N25E MTW54N05E MTP50N06V
Motorola TMOS Power MOSFET Transistors Device Data Alphanumeric Index of Part Numbers
1–3
Alphanumeric Index of Part Numbers Motorola TMOS Power MOSFET Transistor Device Data
1–4
Section Two
TMOS Power MOSFETs
Products Selector Guide
In Brief . . . Table of Contents

Motorola continues to build a world class portfolio of Page
TMOS Power MOSFETs with new advances in silicon and TMOS Power MOSFETs . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–1
packaging technology. The following new advances have TMOS Power MOSFETs Numbering System . . . . . . . 2–2
been made in the area of silicon technology. SO–8 (MiniMOS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–3
Micro8 HDTMOS Products . . . . . . . . . . . . . . . . . . . . . 2–3
• Additional high voltage devices with voltages up to
EZFET — Power MOSFETs with Zener Gate
1200 volts.
Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–4
• The new High Cell Density (HDTMOS) Family of standard
SOT–223 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–4
and Logic Level devices in both N and P-channel are
DPAK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–4
available in SO–8, DPAK and D2PAK surface mount
D2PAK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–5
packages and in the industry standard TO-220 package.
D3PAK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–6
The following new advances have been made in the area TO–220AB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–7
of packaging technology. TO–247 (Isolated Mounting Hole) . . . . . . . . . . . . . . . . . 2–8
• Motorola has added Micro8, SO-8 (MiniMOS) and TO–264 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–8
SOT-223 packages to the surface mount portfolio. SOT–227B (ISOTOP) . . . . . . . . . . . . . . . . . . . . . . . . . . 2–9
• New High Power packages capable of housing very large SMARTDISCRETES . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–9
die and higher power dissipation are now available in the IGBT — Insulated Gate Bipolar Transistor . . . . . . . . 2–10
TO-264 (TO-3PBL) and SOT-227B (ISOTOP) packages. Power MOS Gate Drivers . . . . . . . . . . . . . . . . . . . . . . 2–10
Motorola TMOS Power MOSFET Transistors Device Data Selector Guide

2–1
TMOS

Power MOSFETs
TMOS Power MOSFETs Numbering System

Wherever possible, Motorola has used the following numbering systems for TMOS power MOSFET products.
MTP75N06HD
MOTOROLA OPTIONAL SUFFIX:
X FOR ENGINEERING SAMPLES L FOR LOGIC LEVEL
TMOS E FOR ENERGY RATED
T FOR TMOS T4 FOR TAPE & REEL (DPAK/D2PAK)
L FOR SMARTDISCRETES RL FOR TAPE & REEL (DPAK/D3PAK)
G FOR IGBT HD FOR HIGH CELL DENSITY
P FOR MULTIPLE CHIP PRODUCTS V FOR TMOS V (FIVE)
PACKAGE TYPE
VOLTAGE RATING DIVIDED BY 10
P FOR PLASTIC TO–220
D FOR DPAK
A FOR TO–220 ISOLATED CHANNEL POLARITY, N OR P
W FOR TO–247
B FOR D2PAK
Y FOR TO–264
E FOR SOT–227B
Example of exceptions: MTD/MTP3055E
V FOR D3PAK Example of exceptions: MTD/MTP2955E
CURRENT
SO–8 (MiniMOS), Micro8 and SOT–223 Power MOSFETs

MMSF4P01HDR1
MOTOROLA R2 FOR TAPE & REEL MiniMOS, Micro8
T1 AND T3 FOR TAPE & REEL SOT–223
PACKAGE TYPE
OPTIONAL SUFFIX:
MMDF — DUAL FET (SO–8)
E FOR ENERGY RATED
MMSF — SINGLE FET (SO–8)
HD FOR HIGH CELL DENSITY
MMFT — FET TRANSISTOR (SOT–223)
L FOR LOGIC LEVEL
MTSF — SINGLE FET (Micro8)
Z FOR ESD GATE PROTECTION
MTDF — DUAL FET (Micro8)
CURRENT
CHANNEL POLARITY, N OR P
C FOR COMPLEMENTARY
Selector Guide Motorola TMOS Power MOSFET Transistor Device Data

2–2
 
TM
SO–8 (MiniMOS)
V(BR)DSS RDS(on) @ VGS ID
(3)PD (3)
(V) 10 V 4.5 V 2.7 V (A) Package (Watts)
(mΩ) (mΩ) (mΩ) Device (5) Type Max
Table 1. SO–8 — N–Channel
50 300 500 — 1.5 MMDF1N05E SO–8 2.0
40 80 100 — 3.4 MMDF3N04HD SO–8 2.0
30 28 40 — 8 MMSF7N03HD SO–8 2.5
40 50 — 5 MMSF5N03HD SO–8 2.5
70 75 — 2.8 MMDF3N03HD SO–8 2.0
70/200(11) 75/300 — 2 MMDF2C03HD SO–8 2.0
20 25 40 — 5 MMSF5N02HD SO–8 2.5
90 100 — 3 MMDF3N02HD SO–8 2.0
100 200 — 2 MMDF2N02E SO–8 2.0
90/160(11) 100/180(11) — 2 MMDF2C02HD SO–8 2.0
100/250(11) 200/400(11) — 2 MMDF2C02E SO–8 2.0
12 — 45 55 4 MMDF4N01HD SO–8 2.0
— 45/180 55/220(11) 2 MMDF2C01HD SO–8 2.0
Table 2. SO–8 — P–Channel
30 100 110 — 3 MMSF3P03HD SO–8 2.5
200 300 — 2 MMDF2P03HD SO–8 2.0
20 75 95 — 3 MMSF3P02HD SO–8 2.5
160 180 — 2 MMDF2P02HD SO–8 2.0
250 400 — 2 MMDF2P02E SO–8 2.0
250 400 — 2 MMSF2P02E SO–8 2.0
12 — 100 110 4 MMSF4P01HD SO–8 2.5
— 180 220 2 MMDF2P01HD SO–8 2.0
1(3) Power rating when mounted on an FR–4 glass epoxy printed circuit board with the minimum recommended footprint.
1(5) Available in tape and reel only — R1 suffix = 500/reel, R2 suffix = 2500/reel.
(11) N–Channel/P–Channel R
DS(on)
Micro8 HDTMOS Products

V(BR)DSS RDS(on) VGS ID
(Volts) (mW) @ (Volts) (cont) Product
Min Max Amps Device Description
Table 3. N – Channel and P– Channel

20 190 2.7 2 MTSF1P02HD Single P– Channel
200 1.5 MTDF1N02HD Dual N – Channel
30 75 4.5 3 MTSF3N03HD Single N – Channel
225 1.5 MTDF1N03HD Dual N – Channel
Devices listed in bold, italic are Motorola preferred devices.

2–3
EZFET — Power MOSFETs with Zener Gate Protection
RDS(on) VGS
(mW) @ (Volts)
V(BR)DSS ID VGS PD(3)
Max
(Volts) (cont) (Volts) (Watts)
Min Description 10 V 4.5 V 2.7 V Amps Device Max Package Max
Table 4. SO – 8 — N – Channel
20 Single N–Channel — 22 27 6 MMSF6N02Z "10 SO–8 1.6
30 Single N–Channel 35 30 — 5 MMSF5N03Z "15
50 Dual N–Channel 300 500 — 2 MMDF2N05Z
60 N–Channel 18 — — 55 MTP55N06Z "20 TO–220 136
MTB55N06Z D2PAK 3
26 28 — 35 MTP35N06ZL "15 TO–220 94
MTB35N06ZL D2PAK 3
SOT–223
V(BR)DSS RDS(on) ID ID PD(1)
(Volts) (Ohms) @ (Amps) (cont) (Watts)
Min Max Device (12) Amps Max
Table 5. SOT–223 — N–Channel
100 0.30 0.5 MMFT1N10E 1 0.8(3)
60 0.14 0.75 MMFT3055VL(2) 1.5
0.13 0.85 MMFT3055V 1.7

20 0.15 1 MMFT2N02EL(2) 2
Table 6. SOT–223 — P–Channel

60 0.30 0.6 MMFT2955E 1.2 0.8(3)
1(1) T = 25°C
C
1(2) Indicates logic level
1(3) Power rating when mounted on an FR–4 glass epoxy printed circuit board with the minimum recommended footprint.
(12) Available in tape and reel only — T1 suffix = 1000/reel, T3 suffix = 4000/reel.
DPAK
Table 7. DPAK — N–Channel

800 12 0.5 MTD1N80E 1 1.75(3)
600 8 0.5 MTD1N60E 1
500 5 0.5 MTD1N50E 1
3.60 1 MTD2N50E 2
400 3.50 1 MTD2N40E 2
250 1.40 1.5 MTD3N25E 3
1 2.5 MTD5N25E 5
200 1.5 1.5 MTD3N20E 3
1.20 2 MTD4N20E 4
0.70 3 MTD6N20E 6
150 0.30 3 MTD6N15 6
(1) T = 25°C (continued)
C
(3) Power rating when mounted on an FR–4 glass epoxy printed circuit board with the minimum recommended footprint.
(4) Available in tape and reel — add T4 suffix to part number.

2–4
DPAK (continued)
Table 7. DPAK — N–Channel (continued)

100 0.40 3 MTD6N10E 6 1.75(3)
0.25 4.5 MTD9N10E 9
0.22 5 MTD10N10EL 10
7 MTD14N10E 14
60 0.15 4 MTD3055V 8
0.18 6 MTD3055VL(2) 12
0.18 6 MTD12N06EZL(2)(13) 12
0.12 7.5 MTD15N06V 15
0.085 7.5 MTD15N06VL(2) 15
0.045 10 MTD20N06HD 20
0.045 10 MTD20N06HDL(2) 20
0.080 10 MTD20N06V 20
30 0.035 10 MTD20N03HDL(2) 20
Table 8. DPAK — P–Channel
500 15.0 0.5 MTD1P50E 1 1.75(3)
100 0.66 3 MTD6P10E 6
60 0.45 2.5 MTD5P06V 5
0.30 6 MTD2955V 12
0.15 10 MTD20P06HDL(2) 20
30 0.099 10 MTD20P03HDL(2) 19
(1) T = 25°C
C
(2) Indicates logic level
(13) ESD protected to 4 kV.
D2PAK
Table 9. D2PAK — N–Channel

1200 5.0 1.5 MTB3N120E 3 2.5(3)
1000 9 0.5 MTB1N100E 1
4 1.5 MTB3N100E 3
800 3 2 MTB4N80E 4
600 1.20 3 MTB6N60E 6
4.16 1 MTB2N60E 2
500 0.80 4 MTB8N50E 8
400 3.50 1 MTB2N40E 2
0.55 5 MTB10N40E 10
250 0.50 4.5 MTB9N25E 9
0.25 8 MTB16N25E 16
C

2–5
D2PAK (continued)
Table 9. D2PAK — N–Channel (continued)

200 0.16 10 MTB20N20E 20 2.5(3)
100 0.060 16.5 MTB33N10E 33
60 0.12 7.5 MTB15N06V 15
0.05 15 MTB30N06VL(2) 30
0.026 17.5 MTB35N06ZL 35
0.04 18 MTB36N06V 32
0.032 21 MTB50N06VL(2) 42
0.028 21 MTB50N06V 42
0.024 26 MTB52N06VL(2) 52
0.018 27.5 MTB55N06Z (13) 55
0.022 26 MTB56N06V 52
0.014 30 MTB60N06HD 60
0.01 37.5 MTB75N06HD 75
50 0.0095 37.5 MTB75N05HD 75
25 0.009 37.5 MTB75N03HDL(2) 75
Table 10. D2PAK — P–Channel
500 6 1 MTB2P50E 2 2.5(3)
60 0.12 11.5 MTB23P06V 23
0.080 15 MTB30P06V 30
30 0.025 25 MTB50P03HDL(2) 50
(1) T = 25°C
C
(13) ESD protected to 4 kV.
D3PAK
Table 11. D3PAK — N–Channel
1000 1.50 3 MTV6N100E 6 178
1.30 5 MTV10N100E 10 250
500 0.400 8 MTV16N50E 16 250
0.240 10 MTV20N50E 20 250
0.200 12.5 MTV25N50E 25 250
250 0.080 16 MTV32N25E 32 250
200 0.075 16 MTV32N20E 32 180
(1) T = 25°C
C

2–6
TO–220AB
Min Max Device Amps Max
Table 12. TO–220AB — N–Channel
1200 5.0 1.5 MTP3N120E 3 125
1000 9 0.5 MTP1N100E 1 75
4.0 1.5 MTP3N100E 3 125
800 12 1 MTP1N80E 1 48
3 2 MTP4N80E 4 125
600 8 0.5 MTP1N60E 1 50
3.80 1 MTP2N60E 2
2.20 1.5 MTP3N60E 3 75
1.20 3 MTP6N60E 6 125
500 5 0.5 MTP1N50E 1 50
3.60 1 MTP2N50E 2 75
3 1.5 MTP3N50E 3 50
1.50 2 MTP4N50E 4 75
0.80 4 MTP8N50E 8 125
400 3.50 1 MTP2N40E 2 50
1.80 2 MTP4N40E 4
1 2.5 MTP5N40E 5 75
0.55 5 MTP10N40E 10 125
250 0.5 4.5 MTP9N25E 9 75
0.25 8 MTP16N25E 16 125
200 0.70 3.5 MTP7N20E 7 75
0.16 10 MTP20N20E 20 125
100 0.25 5 MTP10N10E 10 75
0.22 5 MTP10N10EL 10 40
0.16 6 MTP12N10E 12 75
0.070 13.5 MTP27N10E 27 125
0.060 16.5 MTP33N10E 33 150
60 0.18 6 MTP3055VL(2) 12 48
0.15 6 MTP3055V 12
0.12 7.5 MTP15N06V 15 60
0.085 7.5 MTP15N06VL 15
0.080 10 MTP20N06V 20 90
0.05 15 MTP30N06VL(2) 30
0.026 17.5 MTP35N06ZL 35 94
0.04 18 MTP36N06V 32 90
0.032 21 MTP50N06VL(2) 42 150
0.028 21 MTP50N06V 42
0.022 26 MTP52N06V 52
0.024 26 MTP52N06VL 52
0.018 22.5 MTP55N06Z 55
0.014 30 MTP60N06HD 60
0.01 37.5 MTP75N06HD 75
50 0.0095 37.5 MTP75N05HD 75
25 0.009 37.5 MTP75N03HDL(2) 75
C

2–7
TO–220AB (continued)
Table 13. TO–220AB — P–Channel

500 6 1 MTP2P50E 2 75
200 1 3 MTP6P20E 6
100 0.30 6 MTP12P10 12 88
60 0.45 2.5 MTP5P06V 5 40
0.30 6 MTP2955V 12 60
0.12 11.5 MTP23P06V 23 125
0.08 15 MTP30P06V 30 125
30 0.025 25 MTP50P03HDL (2) 50 150
(1) T = 25°C
C
TO–247 (Isolated Mounting Hole)

Table 14. TO–247 — N–Channel

1000 1.50 3 MTW6N100E 6 180
1.30 5 MTW10N100E 10 250
800 1 3.5 MTW7N80E 7 180
600 0.55 4 MTW8N60E 8 180
500 0.40 7 MTW14N50E 14 180
0.24 10 MTW20N50E 20 250
400 0.24 8 MTW16N40E 16 180
0.16 12 MTW24N40E 24 250
250 0.08 16 MTW32N25E 32 250
200 0.075 16 MTW32N20E 32 180
150 0.05 17.5 MTW35N15E 35 180
100 0.035 22.5 MTW45N10E 45 180
(1) T = 25°C
C
TO–264
Table 15. TO–264 — N–Channel
1000 0.80 7 MTY14N100E 14 568
800 0.50 8 MTY16N80E 16 568
600 0.21 12.5 MTY25N60E 25 568
500 0.26 10 MTY20N50E 20 300
0.15 15 MTY30N50E 30 568
200 0.028 27.5 MTY55N20E 55 568
100 0.011 50 MTY100N10E 100 568
(1) T = 25°C
C

2–8
SOT–227B (ISOTOP)
Table 16. SOT–227B (ISOTOP)
500 0.15 15 MTE30N50E 30 250
0.08 26.5 MTE53N50E 53 460
200 0.015 62.5 MTE125N20E 125 460
100 0.0055 107 MTE215N10E 215 460
(1) T = 25°C
C
Indicates UL Recognition — File #E69369
SMARTDISCRETES
Table 17. Ignition IGBTs
BVCES (Volts) VCE(on) PD(1)
Clamped @ 10 A Device (Watts) Max Package
140 V 1.8 MGP20N14CL 150 TO–220AB
350 V 1.8 MGP20N35CL 150 TO–220AB
MGB20N35CL 2.5(3)(4) D2PAK
400 V 1.8 MGP20N40CL 150 TO–220AB
MGB20N40CL 2.5(3)(4) D2PAK
Table 18. TO–220AB
V(BR)DSS RDS(on) ID ID (cont) PD(1)
(Volts) Min (Ohms) Max (Amps) Device Amps (Watts) Max
60 Clamped Voltage 0.75 1 MLP1N06CL Current Limited 40
62 Clamped Voltage 0.4 2 MLP2N06CL Current Limited 40
Table 19. DPAK
V(BR)DSS RDS(on) ID ID (cont) PD(1)
(Volts) Min (Ohms) Max (Amps) Device Amps (Watts) Max
60 Clamped Voltage 0.75 1 MLD1N06CL Current Limited 1.75
62 Clamped Voltage 0.4 2 MLD2N06CL Current Limited 1.75
(1) T = 25°C
C

2–9
IGBT — Insulated Gate Bipolar Transistor
BVCES IC90 IC VCE(on) @ IC90 Eoff @ IC90
@ 25°C (V) (mJ)
Device (V) (A) (A) typ typ @ 125°C Package
Table 20. IGBT — N–Channel
MGP20N60 600 20 32 2.90 1.20 TO–220
MGW20N60D TO–247
MGW30N60 30 50 2.60 1.80 TO–247
MGY30N60D TO–264
MGY40N60 40 66 2.60 2.40 TO–264
MGY40N60D
MGW10N120 1200 12 20 3.10 1.43 TO–247
MGW10N120D
MGY25N120 25 38 2.90 4.29 TO–264
MGY25N120D
IC90 = Collector current rating at 90°C case temperature
Power MOS Gate Drivers

Device Description Package
Table 21.
MC33153D VCC–VEE = 23 V, 1 A Source, 2 A Sink Low Side Driver 8 Pin SOIC
MC33153P (Can be used as High Side Driver with Opto–coupler) 8 Pin PDIP
MPIC2111D 600 V, 420 mA, Half Bridge Driver 8 Pin SOIC
MPIC2111P 8 Pin PDIP
MPIC2112DW 600 V, 420 mA, Half Bridge Driver 16 Pin SOIC–Wide
MPIC2113DW 600 V, 2 A, Half Bridge Driver 16 Pin SOIC–Wide
MPIC2117D 600 V, 420 mA, High Side Driver 8 Pin SOIC
MPIC2130P 600 V, 420 mA, Three Phase Driver 28 Pin PDIP
MPIC2130FN 44 Pin PLCC (modified)
MPIC2131P 600 V, 420 mA, Three Phase Driver 28 Pin PDIP
MPIC2131FN 44 Pin PLCC (modified)
MPIC2151D 600 V, 210 mA, Self Oscillating, Half Bridge Driver 8 Pin SOIC

2–10
Section Three
Introduction to Power MOSFETs
Basic Characteristics of Power MOSFETs
Table of Contents
Chapter 1: Introduction to Power MOSFETs
Symbols, Terms and Definitions . . . . . . . . . . . . . . . . . . 3–2
Basic TMOS Structure, Operation and Physics . . . . . 3–7
Distinct Advantages of Power MOSFETs . . . . . . . . . 3–10
Chapter 2: Basic Characteristics of Power MOSFETs
Output Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 3–13
Basic MOSFET Parameters . . . . . . . . . . . . . . . . . . . . . 3–13
Temperature Dependent Characteristics . . . . . . . . . . 3–14
Drain-Source Diode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–15
Chapter 3: The Data Sheet . . . . . . . . . . . . . . . . . . . . . . 3–17
Motorola TMOS Power MOSFET Transistors Device Data Introduction and Basic Characteristics
3–1
Chapter 1: Introduction to Power MOSFETs
Symbols, Terms and Definitions
The following are the most commonly used letter symbols, terms and definitions associated with Power MOSFETs.
Symbol Term Definition
Cds drain–source capacitance The capacitance between the drain and source terminals
with the gate terminal connected to the guard terminal of
a three–terminal bridge.
Cdg drain–gate capacitance The same as Crss – See Crss.
Cgs gate–source capacitance The capacitance between the gate and source terminals
with the drain terminal connected to the guard terminal of
a three–terminal bridge.
Ciss short–circuit input capacitance, The capacitance between the input terminals (gate and
common–source source) with the drain short–circuited to the source for
alternating current. (Ref. IEEE No. 255)
Coss short–circuit output capacitance, The capacitance between the output terminals (drain and
common–source source) with the gate short–circuited to the source for
alternating current. (Ref. IEEE No. 255)
Crss short–circuit reverse transfer The capacitance between the drain and gate terminals
capacitance, common–source with the source connected to the guard terminal of a
three–terminal bridge.
gFS common–source large–signal The ratio of the change in drain current due to a change in
transconductance gate–to–source voltage.
ID drain current, dc The direct current into the drain terminal.
ID(on) on–state drain current The direct current into the drain terminal with a specified
forward gate–source voltage applied to bias the device to
the on–state.
IDSS zero–gate–voltage drain current The direct current into the drain terminal when the
gate–source voltage is zero. This is an on–state current in
a depletion–type device, an off–state in an enhancement–
type device.
IG gate current, dc The direct current into the gate terminal.
IGSS reverse gate current, drain short–circuited The direct current into the gate terminal of a junction–gate
to source field–effect transistor when the gate terminal is reverse
biased with respect to the source terminal and the drain
terminal is short–circuited to the source terminal.
IGSSF forward gate current, drain short–circuited The direct current into the gate terminal of an insulated–
to source gate field–effect transistor with a forward gate–source
voltage applied and the drain terminal short–circuited to
the source terminal.
IGSSR reverse gate current, drain short–circuited The direct current into the gate terminal of an insulated–
to source gate field–effect transistor with a reverse gate–source
voltage applied and the drain terminal short–circuited to
the source terminal.
Introduction and Basic Characteristics Motorola TMOS Power MOSFET Transistor Device Data
3–2
IS source current, dc The direct current into the source terminal.

PT, PD total nonreactive power input to all The sum of the products of the dc input currents and
terminals voltages.
Qg total gate charge The total gate charge required to charge the MOSFETs
input capacitance to VGS(on).
RDS(on) static drain–source on–state resistance The dc resistance between the drain and source terminals
with a specified gate–source voltage applied to bias the
device to the on state.
RθCA thermal resistance, case–to–ambient The thermal resistance (steady–state) from the device
case to the ambient.
RθJA thermal resistance, junction–to–ambient The thermal resistance (steady–state) from the semicon-
ductor junction(s) to the ambient.
RθJC thermal resistance, junction–to–case The thermal resistance (steady–state) from the semicon-
ductor junction(s) to a stated location on the case.
RθJM thermal resistance, junction–to–mounting The thermal resistance (steady–state) from the semicon-
surface ductor junction(s) to a stated location on the mounting
surface.
TA ambient temperature or free–air The air temperature measured below a device, in an
temperature environment of substantially uniform temperature, cooled
only by natural air convection and not materially affected
by reflective and radiant surfaces.
TC case temperature The temperature measured at a specified location on the
case of a device.
tc turn–off crossover time The time interval during which drain voltage rises from
10% of its peak off–state value and drain current falls to
10% of its peak on–state value, in both cases ignoring
spikes that are not charge–carrier induced.
TJ channel temperature The temperature of the channel of a field–effect transistor.
Tstg storage temperature The temperature at which the device, without any power
applied, may be stored.
td(off) turn–off delay time Synonym for current turn–off delay time (see Note 1)*.
td(off)i current turn–off delay time The interval during which an input pulse that is switching
the transistor from a conducting to a nonconducting state
falls from 90% of its peak amplitude and the drain current
waveform falls to 90% of its on–state amplitude, ignoring
td(off)v voltage turn–off delay time The time interval during which an input pulse that is
switching the transistor from a conducting to a noncon-
ducting state falls from 90% of its peak amplitude and the
drain voltage waveform rises to 10% of its off–state
amplitude, ignoring spikes that are not charge–carrier
induced.
td(on) turn–on delay time Synonym for current turn–on delay time (see Note 1)*.
td(on)i current turn–on delay time The time interval during which can input pulse that is
switching the transistor from a nonconducting to a
conducting state rises from 10% of its peak amplitude and
the drain current waveform rises to 10% of its on–state
induced.
3–3
td(on)v voltage turn–on delay time The time interval during which an input pulse that is
switching the transistor from a nonconducting to a
conducting state rises from 10% of its peak amplitude and
the drain voltage waveform falls to 90% of its off–state
induced.
tf fall time Synonym for current fall time (see Note 1)*.
tfi current fall time The time interval during which the drain current changes
from 90% to 10% of its peak off–state value, ignoring
tfv voltage fall time The time interval during which the drain voltage changes
toff turn–off time Synonym for current turn–off time (see Note 1)*.
toff(i) current turn–off time The sum of current turn–off delay time and current fall time,
i.e., td(off)i + tfi.
toff(v) voltage turn–off time The sum of voltage turn–off delay time and voltage rise
time, i.e., td(off)v + trv.
ton turn–on time Synonym for current turn–on time (see Note 1)*.
ton(i) current turn–on time The sum of current turn–on delay time and current rise
time, i.e., td(on)i + tri.
ton(v) voltage turn–on time The sum of voltage turn–on delay time and voltage fall
time, i.e., td(on)v + tfv.
tp pulse duration The time interval between a reference point on the leading
edge of a pulse waveform and a reference point on the
trailing edge of the same waveform.
Note: The two reference points are usually 90% of the
steady–state amplitude of the waveform existing after the leading
edge, measured with respect to the steady–state amplitude
existing before the leading edge. If the reference points are 50%
points, the symbol tw and term average pulse duration should be
used.
tr rise time Synonym for current rise time (see Note 1)*.
tri current rise time The time interval during which the drain current changes
from 10% to 90% of its peak on–state value, ignoring
trv voltage rise time The time interval during which the drain voltage changes
tti current fall time The time interval following current fall time during which
the drain current changes from 10% to 2% of its peak
on–state value, ignoring spikes that are not charge–carrier
induced.
tw average pulse duration The time interval between a reference point on the leading
edge of a pulse waveform and a reference point on the
trailing edge of the same waveform, with both reference
points being 50% of the steady–state amplitude of the
waveform existing after the leading edge, measured with
respect to the steady–state amplitude existing before the
leading edge.
Note: If the reference points are not 50% points, the symbol tp
and term pulse duration should be used.
3–4
V(BR)DSR drain–source breakdown voltage with The breakdown voltage between the drain terminal and the
(resistance between gate and source) source terminal when the gate terminal is (as indicated by
the last subscript letter) as follows:
R = returned to the source terminal through a specified
resistance.
V(BR)DSS gate short–circuited to source S = short–circuited to the source terminal.
V(BR)DSV voltage between gate and source V = returned to the source terminal through a specified
voltage.
V(BR)DSX circuit between gate and source X = returned to the source terminal through a specified
circuit.
V(BR)GSSF forward gate–source breakdown voltage The breakdown voltage between the gate and source
terminals with a forward gate–source voltage applied and
the drain terminal short–circuited to the source terminal.
V(BR)GSSR reverse gate–source breakdown voltage The breakdown voltage between the gate and source
terminals with a reverse gate–source voltage applied and
the drain terminal short–circuited to the source terminal.
VDD, VGG supply voltage, dc (drain, gate, source) The dc supply voltage applied to a circuit or connected to
VSS voltage the reference terminal.
VDG drain–to–gate The dc voltage between the terminal indicated by the first
VDS drain–to–source subscript and the reference terminal indicated by the
VGD gate–to–drain second subscript (stated in terms of the polarity at the
VGS gate–to–source terminal indicated by the first subscript).
VSD source–to–drain
VSG source–to–gate
VDS(on) drain–source on–state voltage The voltage between the drain and source terminals with
a specified forward gate–source voltage applied to bias the
device to the on state.
VGS(th) gate–source threshold voltage The forward gate–source voltage at which the magnitude
of the drain current of an enhancement–type field–effect
transistor has been increased to a specified low value.
ZθJA(t) transient thermal impedance, The transient thermal impedance from the semiconductor
junction–to–ambient junction(s) to the ambient.
ZθJC(t) transient thermal impedance, The transient thermal impedance from the semiconductor
junction–to–case junction(s) to a stated location on the case.
Note 1: As names of time intervals for characterizing switching transistors, the terms “fall time” and “rise time” always refer to the change that is
taking place in the magnitude of the output current even though measurements may be made using voltage waveforms. In a purely resistive
circuit, the (current) rise time may be considered equal and coincident to the voltage fall time and the (current) fall time may be considered equal
and coincident to the voltage rise time. The delay times for current and voltage will be equal and coincident. When significant amounts of
inductance are present in a circuit, these equalities and coincidences no longer exist, and use of the unmodified terms delay time, fall time, and
rise time must be avoided.
3–5
90% 100%
Input Voltage Pulse

(Idealized wave shape) amplitude
10%
toff ≅ ton(i)
toff ≅ toff(i)
td(on) = td(on)i td(off) = td(off)i Drain
tf ≅ tfi Current
tr ≅ tri (Practical wave shape
ID(on)
90% including spikes caused
Drain by currents that are
Current not charge–carrier
(Idealized wave shape) induced)
10%
toff(v) ID(off)
ton(v)
td(on)v td(off)v
tfv trv
[VDD
90%
Drain
Voltage
(Idealized wave shape)
10%
VDS(on)
Figure 1–1. Waveforms for Resistive–Load Switching
90%
Input
Voltage
toff(i)
tfi
IDM
90%
Drain
Current td(off)i
10%
2% ID(off)
tc (or txo)
tti
trv VDSM
Vclamp or V(BR)DSX
90%
(See Note)
td(off)v
Drain
Voltage
VDS(on)
10% [VDD
toff(v)
NOTE: Vclamp (in a clamped inductive–load switching circuit) or V(BR)DSX (in an unclamped circuit) is the peak off–state voltage
excluding spikes.
Figure 1–2. Waveforms for Inductive Load Switching, Turn–Off
3–6
Basic TMOS Structure, Operation and Physics
Structures: GATE + VG
Motorola’s TMOS Power MOSFET family is a matrix of dif- CURRENT

fused channel, vertical, metal–oxide–semiconductor power
field–effect transistors which offer an exceptionally wide
range of voltages and currents with low RDS(on). The inherent
advantages of Motorola’s power MOSFETs include:
• Nearly infinite static input impedance featuring:
— Voltage driven input DEPLETION
— Low input power REGION
— Few driver circuit components N–CHANNEL
• Very fast switching times (CURRENT PATH)
— No minority carriers P–SUBSTRATE
— Minimal turn–off delay time AND BODY
— Large reversed biased safe operating area SOURCE METAL
— High gain bandwidth product
DRAIN METAL + VDD
• Positive temperature coefficient of on–resistance
— Large forward biased safe operating area Figure 1–3. Conventional Small–Signal MOSFET has
— Ease in paralleling Long Lateral Channel Resulting in Relatively High
• Almost constant transconductance Drain–to–Source Resistance
• High dv/dt immunity
Motorola’s TMOS power MOSFET line is the latest step in S G D
an evolutionary progression that began with the conventional
small–signal MOSFET and superseded the intermediate lat- SiO2
eral double diffused MOSFET (LDMOSFET) and the vertical
V–groove MOSFET (VMOSFET).
The conventional small–signal lateral N–channel N+ N+
MOSFET consists of a lightly doped P–type substrate into P
which two highly doped N+ regions are diffused, as shown in
Channel Current
Figure 1–3. The N+ regions act as source and drain which
are separated by a channel whose length is determined by N–
photolithographic constraints. This configuration resulted in
long channel lengths, low current capability, low reverse
blocking voltage and high RDS(on). Figure 1–4. Lateral Double Diffused MOSFET
Two major changes in the small–signal MOSFET structure Structure Featuring Short Channel Lengths and High
were responsible for the evolution of the power MOSFET. Packing Densities for Lower On Resistance
One was the use of self aligned, double diffusion techniques
to achieve very short channel lengths, which allowed higher The next step in the evolutionary process was a vertical
channel packing densities, resulting in higher current capa- structure in which the drain contact was on the back of the
bility and lower RDS(on). The other was the incorporation of a die, further increasing the channel packing density. The initial
lightly doped N+ region between the channel and the N+ concept used a V–groove MOSFET power transistor as
drain allowing high reverse blocking voltages. shown in Figure 1–5. The channels in this device are defined
These changes resulted in the lateral double diffused by preferentially etching V–grooves through double diffused
MOSFET power transistor (LDMOS) structure shown in N+ and P– regions. The requirements of adequate packing
Figure 1–4, in which all the device terminals are still on the density, efficient silicon usage and adequate reverse block-
top surface of the die. The major disadvantage of this config- ing voltage are all met by this configuration. However, due to
uration is its inefficient use of silicon area due to the area its non–planar structure, process consistency and cleanli-
needed for the top drain contact. ness requirements resulted in higher die costs.
3–7
The cell structure chosen for Motorola’s TMOS power As the drain voltage is increased, the drain current satu-
MOSFET’s is shown in Figure 1–6. This structure is similar to rates and becomes proportional to the square of the applied
that of Figure 1–4 except that the drain contact is dropped gate–to–source voltage, VGS, as indicated in Equation (2).
through the N– substrate to the back of the die. The gate
structure is now made with polysilicon sandwiched between
two oxide layers and the source metal applied continuously (2) ID [ 2LZ mCo [VGS–VGS(th)]2
over the entire active area. This two layer electrical contact
gives the optimum in packing density and maintains the Where µ = Carrier Mobility
processing advantages of planar LDMOS. This results in a Co = Gate Oxide Capacitance per unit area
highly manufacturable process which yields low RDS(on) and Z = Channel Width
high voltage product. L = Channel Length
S G S
ÏÏÏ
ÏÏÏÏÏÏÏÏ
X of These values are selected by the device design engineer
A1
SiO2 to meet design requirements and may be used in modeling
ÏÏÏ
ÏÏÏÏÏÏÏÏ and circuit simulations. They explain the shape of the output
ÏÏÏÏÏ
n+ characteristics discussed in Chapter 2.
ÏÏÏÏÏ
p
Transconductance, gFS:
n–
The transconductance or gain of the TMOS power
MOSFET is defined as the ratio of the change in drain cur-
ÏÏÏÏÏÏÏÏÏÏÏÏÏ
n+ rent and an accompanying small change in applied gate–to–
source voltage and is represented by Equation (3).
+ DDID(sat) + ZL
D
Figure 1–5. V–Groove MOSFET Structure Has (3) gFS
VGS
mCo [VGS–VGS(th)]
Short Vertical Channels with Low
Drain–to–Source Resistance The parameters are the same as above and demonstrate
SOURCE SITE SOURCE that drain current and transconductance are directly related
METALIZATION and are a function of the die design. Note that transconduc-
tance is a linear function of the gate voltage, an important
feature in amplifier design.
SILICON
GATE
N–CHANNEL
Threshold Voltage, VGS(th)
Threshold voltage is the gate–to–source voltage required
DRAIN CURRENT to achieve surface inversion of the diffused channel region,
INSULATING OXIDE, SiO2 (r CH in Figure 1–7) and as a result, conduction in the
channel.
N–Epi LAYER DRAIN As the gate voltage increases the more the channel is
METALIZATION “enhanced,” or the lower its resistance (rCH) is made, the
N–SUBSTRATE
more current will flow. Threshold voltage is measured at a
Figure 1–6. TMOS Power MOSFET Structure Offers specified value of current to maintain measurement correla-
Vertical Current Flow, Low Resistance Paths and tions. A value of 1.0 mA is common throughout the industry.
Permits Compact Metalization on Top and Bottom This value is primarily a function of the gate oxide thickness
Surfaces to Reduce Chip Size and channel doping level which are chosen during the die
design to give a high enough value to keep the device off with
Operation: no bias on the gate at high temperatures. A minimum value
Transistor action and the primary electrical parameters of of 1.5 volts at room temperature will guarantee the transistor
Motorola’s TMOS power MOSFET can be defined as follows: remains an enhancement mode device at junction tempera-
tures up to 150°C.
Drain Current, ID:
When a gate voltage of appropriate polarity and magnitude
On–Resistance, RDS(on):
is applied to the gate terminal, the polysilicon gate induces
an inversion layer at the surface of the diffused channel On–resistance is defined as the total resistance encoun-
region represented by rCH in Figure 1–7 (page A–8). This tered by the drain current as it flows from the drain terminal to
inversion layer or channel connects the source to the lightly the source terminal. Referring to Figure 1–7, RDS(on) is com-
doped region of the drain and current begins to flow. For posed primarily of four resistive components associated with:
small values of applied drain–to–source voltage, VDS, drain The Inversion channel, rCH; the Gate–Drain Accumulation
current increases linearly and can be represented by Equa- Region, rACC; the junction FET Pinch region, rJFET; and the
tion (1). lightly doped Drain Region, rD, as indicated in Equation (4).
(1) ID [ ZL mCo [VGS–VGS(th)] VDS (4) RDS(on) + rCH ) rACC ) rJFET ) rD

3–8
S G resistance continues to decrease as VGS is increased toward
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
the maximum rating of the device.
ÌÌÌÌÌÌ
Note: RDS(on) is inversely proportional to the carrier mobility. This
ÌÌÌÌÌÌ
means that the RDS(on) of the P–Channel MOSFET is approximately
POLY 2.5 to 3.0 times that of a similar N–Channel MOSFET. Therefore, in
order to have matched complementary on characteristics, the Z/L ratio
N+ N+ of the P–Channel device must be 2.5–3.0 times that of the N–Channel
rJFET
rCH device. This means larger die are required for P–Channel MOSFET’s
rACC
P+ P+ with the same RDS(on) and same breakdown voltage as an N–Channel
device and thus device capacitances and costs will be
N– rD correspondingly higher.
N+ Breakdown Voltage, V(BR)DSS:

Breakdown voltage or reverse blocking voltage of the
D TMOS power MOSFET is defined in the same manner as
V(BR)CES in the bipolar transistor and occurs as an avalanche
Figure 1–7. TMOS Device On–Resistance
breakdown. This voltage limit is reached when the carriers
S G within the depletion region of the reverse biased P–N junc-
tion acquire sufficient kinetic energy to cause ionization or
ÌÌÌÌÌÌ
Cgs when the critical electric field is reached. The magnitude of
A this voltage is determined mainly by the characteristics of the
ÌÌÌÌÌÌ
Cgs
POLY lightly doped drain region and the type of termination of the
die’s surface electric field.
N+ N+ n+ Figure 1–9 shows a schematic representation of the
Cgd cross–section in Figure 1–8 and depicts the bipolar transistor
P+ P+ built in the epi layer. Point A shows where the emitter and
base of the bipolar is shorted together. This is why V(BR)DSS
Cds
N– of the power FET is equal to V(BR)CES of the bipolar. Also
note the short brings the base in contact with the source met-
N+
al allowing the use of the base–collector junction. This is the
diode across the TMOS power MOSFET.
D
Figure 1–8. TMOS Device Parasitic Capacitances
D D
Whereas the channel resistance increases with channel
length, the accumulation resistance increases with poly
width and the JFET pinch resistance increases with epi
resistivity and all three are inversely proportional to the chan-
nel width and gate–to–source voltage. The drain resistance
is proportional to the epi resistivity, poly width and inversely
proportional to channel width. This says that the on–resis- G G
tance of TMOS power FETs with the thick and high resistivity
epi required for high voltage parts will be dominated by rD.
Low voltage devices have thin, low resistivity epi and rCH S S
will be a large portion of the total on–resistance. This is
why high voltage devices are “full on” with moderate voltages Figure 1–9. Schematic Diagram of all the Components
on the gate, whereas with low voltage devices the on– of the Cross Section of Figure 1–7
3–9
TMOS Power MOSFET Capacitances: gate, breakdown will occur through the glass, creating a re-
sistive path and destroying MOSFET operation.
Two types of intrinsic capacitances occur in the TMOS
power MOSFET – those associated with the MOS structure Optimizing TMOS Geometry:
and those associated with the P–N junction.
The geometry and packing density of Motorola’s
The two MOS capacitances associated with the MOSFET
MOSFETs vary according to the magnitude of the reverse
cell are:
blocking voltage.
Gate–Source Capacitance, Cgs
The geometry of the source site, as well as the spacing be-
Gate–Drain Capacitance, Cgd
tween source sites, represents important factors in efficient
The magnitude of each is determined by the die geometry power MOSFET design. Both parameters determine the
and the oxides associated with the silicon gate. channel packing density, i.e.: ratio of channel width per cell to
The P–N junction formed during fabrication of the power cell area.
MOSFET results in the drain–to–source capacitance, Cds. For low voltage devices, channel width is crucial for mini-
This capacitance is defined the same as any other planar mizing RDS(on), since the major contributing component of
junction capacitance and is a direct function of the channel RDS(on) is rCH. However, at high voltages, the major contrib-
drain area and the width of the reverse biased junction deple- uting component of resistance is rD and thus minimizing
tion region. RDS(on) is dependent on maximizing the ratio of active drain
The dielectric insulator of Cgs and Cgd is basically a glass. area per cell to cell area. These two conditions for minimizing
Thus these are very stable capacitors and will not vary with RDS(on) cannot be met by a single geometry pattern for both
voltage or temperature. If excessive voltage is placed on the low and high voltage devices.
Distinct Advantages of Power MOSFETs

Power MOSFETs offer unique characteristics and capabili- The phenomena of second breakdown does not occur within
ties that are not available with bipolar power transistors. By the ratings of the device. Depending on the application,
taking advantage of these differences, overall systems cost snubber circuits may be eliminated or a smaller capacitance
savings can result without sacrificing reliability. value may be used in the snubber circuit. The safe operating
boundaries are limited by the peak current ratings, break-
Speed down voltages and the power capabilities of the devices.
Power MOSFETs are majority carrier devices, therefore
their switching speeds are inherently faster. Without the
minority carrier stored base charge common in bipolar tran- On–Voltage
sistors, storage time is eliminated. The high switching The minimum on–voltage of a power MOSFET is deter-
speeds allow efficient switching at higher frequencies which mined by the device on–resistance RDS(on). For low voltage
reduces the cost, size and weight of reactive components. devices the value of RDS(on) is extremely low, but with high
MOSFET switching speeds are primarily dependent on voltage devices the value increases. RDS(on) has a positive
charging and discharging the device capacitances and are temperature coefficient which aids in paralleling devices.
essentially independent of operating temperature.
Input Characteristics Examples of Advantages Offered by
The gate of a power MOSFET is electrically isolated from MOSFETs
the source by an oxide layer that represents a dc resistance
greater than 40 megohms. The devices are fully biased–on High Voltage Flyback Converter
with a gate voltage of 10 volts. This significantly simplifies the An obvious way of showing the advantages of power
drive circuits and in many instances the gate may be driven MOSFETs over bipolars is to compare the two devices in the
directly from logic integrated circuits such as CMOS and TTL same system. Since the drive requirements are not the
to control high power circuits directly. same, it is not a question of simply replacing the bipolar with
Since the gate is isolated from the source, the drive the FET, but one of designing the respective drive circuits to
requirements are nearly independent of the load current. produce an equivalent output, as described in Figures 1–10
This reduces the complexity of the drive circuit and results in and 1–11.
overall system cost reduction. For this application, a peak output voltage of about 700 V
driving a 30 kΩ load (PO(pk) ≈ 16 W) was required. With the
Safe Operating Area component values and timing shown, the inductor/device
Power MOSFETs, unlike bipolars, do not require derating current required to generate this flyback voltage would have
of power handling capability as a function of applied voltage. to ramp up to about 3.0 A.
3–10
+VDD ≤ 36 V
1.6 mH L
1N4725 Vo ≤ 800 V
MTP4N80E RL
Q1 30 k CL
15 V
68 0.5 µF
0
PW ≤ 350 µs
f = 1.7 kHz 1.0 k
Figure 1–10. TMOS Output Stage
+V +VCC ≤ 32 V
2.2 Ω
150 pF 2.0 W
VI
MJE200
0
Q1 D1 Vo ≤ 700 V
82
0.01 µF 180
D2 0.5 µF
30 k
Q4
270 47
27
Q3 D3
Q2 MJE200 MJ8505
100
1N914
1.0 k
2N2905
–V
Figure 1–11. Bipolar Driver and Output Stage
Figures 1–10 and 1–11. Circuit Configurations for a TMOS and

Bipolar Output Stage of a High Voltage Flyback Converter
Figure 1–10 shows the TMOS version. Because of its high Compare this circuit with the bipolar version of Figure
input impedance, the FET, an MTP4N80E, can be directly 1–11.
driven from the pulse width modulator. However, the PWM To achieve the output voltage, using a high voltage Switch-
output should be about 15 volts in amplitude and for relative- mode MJ8505 power transistor, requires a rather complex
ly fast FET switching be capable of sourcing and sinking drive circuit for generating the proper IB1 and IB2. This circuit
100 mA. Thus, all that is required to drive the FET is a resis- uses three additional transistors (two of which are power
tor or two. The peak drain current of 3.2 A is within the transistors), three Baker clamp diodes, eleven passive com-
MTP4N80E pulsed current rating of 18.0 A (4.0 A continu-
ponents and a negative power supply for generating an off–
ous), and the turn–off load line of 3.2 A, 700 V is well within
bias voltage. Also, the RBSOA capability of this device is
the Switching SOA (18.0 A/800 V) of the device. Thus, the
only 3.0 A at 900 V and 4.7 A at 800 V, values below the
circuit demonstrates the advantages of TMOS:
18.0 A/800 V rating of the MOSFET. A detailed description of
• High input impedance
these circuits is shown in Chapter 8, Switching Power
• Fast Switching Supplies.
• No Second breakdown
3–11
+170 V +170 V
VCC 1N4933 +10 µF
MC34060
Q1 10 µH
MC3406 Q1
PWM MTP4N50E Q2
200
47 MJE13005
56
MPSA55
Figure 1–12. TMOS Version Figure 1–13. Bipolar Version
Figures 1–12 and 1–13. Comparison of Power MOSFET and Bipolar

in the Power Output Stage of a 20 kHz Switcher
20 kHz Switcher
An example of MOSFET advantage over bipolar that illus- MJE13005 bipolar transistor. Although the saturation losses
trates its superior switching speed is shown in the power out- were greater for the TMOS, its lower switching losses pre-
put section of Figures 1–12 and 1–13. In addition to the drive dominated, resulting in a more efficient switching device.
simplicity and reduced component count, the faster switching In general, at low switching frequencies, where static
speed offers better circuit efficiency. For this 35 W switching losses predominate, bipolars are more efficient. At higher
regulator, using the same small heatsink for either device, a frequencies, above 50 kHz, the power MOSFETs are more
case temperature rise of only 18°C was measured for the efficient.
MTP4N50E power MOSFET compared to a 46°C rise for the
3–12
Chapter 2: Basic Characteristics of Power MOSFETs
Output Characteristics
Perhaps the most direct way to become familiar with the One of the three obvious differences between Figures 2–1
basic operation of a device is to study its output characteris- and 2–2 is the family of curves for the power MOSFET is
tics. In this case, a comparison of the MOSFET characteris- generated by changes in gate voltage and not by base cur-
tics with those of a bipolar transistor with similar ratings is in rent variations. A second difference is the slope of the curve
order, since the curves of a bipolar device are almost univer- in the bipolar saturation region is steeper than the slope in
sally familiar to power circuit design engineers. the ohmic region of the power MOSFET indicating that the
As indicated in Figures 2–1 and 2–2, the output character- on–resistance of the MOSFET is higher than the effective
istics of the power MOSFET and the bipolar transistor can be on–resistance of the bipolar.
divided similarly into two basic regions. The figures also The third major difference between the output characteris-
show the numerous and often confusing terms assigned to tics is that in the active regions the slope of the bipolar curve
those regions. To avoid possible confusion, this section will is steeper than the slope of the TMOS curve, making the
refer to the MOSFET regions as the “on” (or “ohmic”) and MOSFET a better constant current source. The limiting of ID
“active” regions and bipolar regions as the “saturation” and is due to pinch–off occurring in the MOSFET channel.
“active” regions.
POWER MOSFET Basic MOSFET Parameters

10 On–Resistance
10 V
9.0 The on–resistance, or RDS(on), of a power MOSFET is an
REGION A
8.0 important figure of merit because it determines the amount of
I D, DRAIN CURRENT (AMPS)
9.0 V
REGION B current the device can handle without excessive power dis-
7.0
sipation. When switching the MOSFET from off to on, the
6.0 drain–source resistance falls from a very high value to
5.0 8.0 V RDS(on), which is a relatively low value. To minimize RDS(on)
4.0
the gate voltage should be large enough for a given drain
current to maintain operation in the ohmic region. Data
3.0 sheets usually include a graph, such as Figure 2–3, which
7.0 V
2.0 relates this information. As Figure 2–4 indicates, increasing
6.0 V the gate voltage above 12 volts has a diminishing effect on
1.0
VGS = 5.0 V lowering on–resistance (especially in high voltage devices)
0 and increases the possibility of spurious gate–source voltage
0 4.0 8.0 12 16
VDS, DRAIN–SOURCE VOLTAGE (VOLTS) spikes exceeding the maximum gate voltage rating of
20 volts. Somewhat like driving a bipolar transistor deep into
Figure 2–1. ID–VDS Output Characteristics of a Power saturation, unnecessarily high gate voltages will increase
MOSFET. Region A is Called the Ohmic, On, Constant turn–off time because of the excess charge stored in the in-
Resistance or Linear Region. Region B is Called the put capacitance. All Motorola TMOS FETs will conduct the
Active, Constant Current, or Saturation Region. rated continuous drain current with a gate voltage of 10 volts.
BIPOLAR POWER TRANSISTOR As the drain current rises, especially above the continuous
10 rating, the on–resistance also increases. Another important
100 mA relationship, which is addressed later with the other tempera-
9.0 REGION A
ture dependent parameters, is the effect that temperature
8.0
REGION B has on the on–resistance. Increasing TJ and ID both effect an
7.0 increase in RDS(on) as shown in Figure 2–5.
6.0
5.0 Transconductance
4.0 Since the transconductance, or gFS, denotes the gain of
IB = 20 mA the MOSFET, much like beta represents the gain of the bipo-
3.0 lar transistor, it is an important parameter when the device is
2.0 operated in the active, or constant current, region. Defined
IB = 10 mA
1.0
as the ratio of the change in drain current corresponding to a
change in gate voltage (gFS = dID/dVGS), the transconduc-
0
0 4.0 8.0 12 16 tance varies with operating conditions as seen in Figure 2–6.
VCE, COLLECTOR–EMITTER VOLTAGE (VOLTS) The value of gFS is determined from the active portion of the
VDS–ID transfer characteristics where a change in VDS no
Figure 2–2. IC–VCE Output Characteristics of a Bipolar longer significantly influences gFS. Typically the transcon-
Power Transistor. Region A is the Saturation Region. ductance rating is specified at half the rated continuous drain
Region B is the Linear or Active Region. current and at a VDS of 15 V.
3–13
8.0 1.25
1.20
NORMALIZED ON–RESISTANCE
VDS = 30 V 1.15
6.0
1.10
HIGH VOLTAGE
1.05
MOSFET
4.0 1.00
0.95
TJ = 100°C 25°C 0.90
2.0 LOW
–55°C 0.85
VOLTAGE
0.80 MOSFET
0 0.75
0 2.0 4.0 6.0 8.0 10 4.0 6.0 8.0 10 12 14 16 18 20
VGS, GATE–TO–SOURCE VOLTAGE (VOLTS) VGS, GATE–TO–SOURCE VOLTAGE (VOLTS)
Figure 2–3. Transfer Characteristics Figure 2–4. The Effect of Gate–to–Source

Voltage on On–Resistance Varies with a
Device’s Voltage Rating
RDS(on), DRAIN–TO–SOURCE RESISTANCE (OHMS)
0.5 3.0
gFS , FORWARD TRANSCONDUCTANCE

TJ = 100°C
0.4 VDS = 15 V
TC = 25°C
TJ = 25°C 2.0
CURVE FALLS AS
(SIEMENS)
0.3
DEVICE ENTERS
TJ = 55°C OHMIC REGION
0.2 (VDS DEPENDENT)
1.0
0.1
0 0
0 5.0 10 15 20 25 4.0 5.0 6.0 7.0 8.0 9.0 10 11 12
ID, DRAIN CURRENT (AMPS) VGS, GATE–TO–SOURCE VOLTAGE (VOLTS)
Figure 2–5. Variation of RDS(on) with Drain Figure 2–6. Small–Signal Transconductance
Current and Temperature versus VGS
For designers interested only in switching the power

MOSFET between the on and off states, the transconduc- Temperature Dependent Characteristics RDS(on)
tance is often an unused parameter. Obviously when the de- Junction temperature variations and their effect on the on–
vice is switched fully on, the transistor will be operating in its resistance, RDS(on), should be considered when designing
ohmic region where the gate voltage will be high. In that re- with power MOSFETs. Since RDS(on) varies approximately
gion, a change in an already high gate voltage will do little to linearly with temperature, power MOSFETs can be assigned
increase the drain current; therefore, gFS is almost zero. temperature coefficients that describe this relationship.
Figure 2–7 shows that the temperature coefficient of
Threshold Voltage RDS(on) is greater for high voltage devices than for low
Threshold Voltage, VGS(th), is the lowest gate voltage at voltage MOSFETs. A graph showing the variation of RDS(on)
which a specified small amount of drain current begins to with junction temperature is shown on most data sheets, Fig-
flow. Motorola normally specifies VGS(th) at an ID of one ure 2–5.
milliampere. Device designers can control the value of the
threshold voltage and target VGS(th) to optimize device per- Switching Speeds are Constant with Temperature
formance and practicality. A low threshold voltage is desired High junction temperatures emphasize one of the most de-
so the TMOS FET can be controlled by low voltage chips sirable characteristics of the MOSFET, that of low dynamic or
such as CMOS and TTL. A low value also speeds switching switching losses. In the bipolar transistor, temperature in-
because less current needs to be transferred to charge the creases will increase switching times, causing greater dy-
parasitic input capacitances. But the threshold voltage can namic losses. On the other hand, thermal variations have
be too low if noise can trigger the device. Also, a positive– little effect on the switching speeds of the power MOSFET.
going voltage transient on the drain can be coupled to the These speeds depend on how rapidly the parasitic input ca-
gate by the gate–to–drain parasitic capacitances and can pacitances can be charged and discharged. Since the mag-
cause spurious turn–on of a device with a low VGS(th). nitudes of these capacitances are essentially temperature
3–14
invariant, so are the switching speeds. Therefore, as temper- Importance of TJ(max) and Heat Sinking
ature increases, the dynamic losses in a MOSFET are low Two of the packages that commonly house the TMOS die
and remain constant, while in the bipolar transistors the are the TO–220AB and the TO–204. The power ratings of
switching losses are higher and increase with junction tem- these packages range from 40 to 250 watts depending on
perature. the die size and the type of materials used in construction.
These ratings are nearly meaningless, however, unless
Drain–To–Source Breakdown Voltage some heat sinking is provided. Without heat sinking the
The drain–to–source breakdown voltage is a function of TO–204 and the TO–220 can dissipate only about 4.0 and
the thickness and resistivity of a device’s N–epitaxial region. 2.0 watts respectively, regardless of the die size.
Since that resistivity varies with temperature, so does Because long term reliability decreases with increasing
V(BR)DSS. As Figure 2–8 indicates, a 100°C rise in junction junction temperature, TJ should not exceed the maximum
temperature causes a V(BR)DSS to increase by about 10%. rating of 150°C. Steady–state operation above 150°C also
However, it should also be remembered that the actual invites abrupt and catastrophic failure if the transistor experi-
V(BR)DSS falls at the same rate as TJ decreases. ences additional transient thermal stresses. Excluding the
possibility of thermal transients, operating below the rated
2.0 junction temperature can enhance reliability. A TJ(max) of
150°C is normally chosen as a safe compromise between
NORMALIZED ON–RESISTANCE
1.8 long term reliability and maximum power dissipation.

In addition to increasing the reliability, proper heat sinking
can reduce static losses in the power MOSFET by decreas-
1.6 ing the on–resistance. RDS(on), with its positive temperature
coefficient, can vary significantly with the quality of the heat
400 V MOSFET sink. Good heat sinking will decrease the junction tempera-
1.4
ture, which further decreases RDS(on) and the static losses.
60 V MOSFET
1.2
Drain–Source Diode
Inherent in most power MOSFETs, and all TMOS transis-
1.0 tors, is a “parasitic” drain–source diode. Figure 2–9, the
25 50 75 100 125 150
illustration of cross section of the TMOS die, shows the P–N
TJ, JUNCTION TEMPERATURE
junction formed by the P–well and the N–Epi layer. Because
Figure 2–7. The Influence of Junction of its extensive junction area, the current ratings of the diode
Temperature on On–Resistance Varies with are the same as the MOSFET’s continuous and pulsed cur-
Breakdown Voltage rent ratings. For the N–Channel TMOS FET shown in Figure
2–10, this diode is forward biased when the source is at a
positive potential with respect to the drain. Since the diode
Threshold Voltage
may be an important circuit element, Motorola Designer’s
The gate voltage at which the MOSFET begins to conduct,
Data Sheets specify typical values of the forward on–voltage,
the gate–threshold voltage, is temperature dependent. The
forward turn–on and reverse recovery time. The forward
variation with TJ is linear as shown on most data sheets.
characteristic of the drain–source diode of a TMOS power
Having a negative temperature coefficient, the threshold
MOSFET is shown in Figure 2–11.
voltage falls about 10% for each 45°C rise in the junction
temperature.
1.20
SOURCE SITE SOURCE
1.15 METALIZATION
NORMALIZED DRAIN–TO–SOURCE
BREAKDOWN VOLTAGE
1.10
1.05 SILICON
GATE
1.00
N–CHANNEL
0.95
DRAIN CURRENT
0.90 INSULATING OXIDE, SiO2
0.85 N–Epi LAYER DRAIN
0.80 METALIZATION
N–SUBSTRATE
–50 –25 0 25 50 75 100 125 150
TJ, JUNCTION TEMPERATURE
Figure 2–8. Typical Variation of

Drain–to–Source Breakdown Voltage with Figure 2–9. Cross Section of TMOS Cell
Junction Temperature
3–15
DRAIN In many applications, the drain–source diode is never
forward biased and does not influence circuit operation.
However, in multi–transistor configurations, such as the
totem pole network of Figure 2–13, the parasitic diodes play
GATE an important and useful role. Each transistor is protected
from excessive flyback voltages, not by its own drain–source
diode, but by the diode of the opposite transistor. As an
SOURCE
illustration, assume that Q2 of Figure 2–13 is turned on, Q1
is off and current is flowing up from ground, through the load
and into Q2. When Q2 turns off, current is diverted into the
Figure 2–10. N–Channel Power MOSFET Symbol drain–source diode of Q1 which clamps the load’s inductive
Including Drain–Source Diode kick to V+. By similar reasoning, one can see that D2 protects
Q1 during its turn–off.
Most rectifiers, a notable exception being the Schottky As a note of caution, it should be realized that diode recov-
diode, exhibit a “reverse recovery” characteristic as depicted ery problems may arise when using MOSFETs in multiple
in Figure 2–12. When forward current flows in a standard transistor configurations. A treatment of the subject in Chap-
diode, a carrier gradient is formed in the high resistivity side ter 5 gives greater details.
of the junction resulting in an apparent storage of charge. TMOS power MOSFET intrinsic diodes also have forward
Upon sudden application of a reverse bias, the stored charge recovery times, meaning that they do not instantaneously
temporarily produces a negative current flow during the re- conduct when they are forward biased. However, since those
verse recovery time, or trr, until the charge is depleted. The times are so brief, typically less than 10 ns, their effect on cir-
circuit conditions that influence trr and the stored charge are cuit operation can almost always be ignored. Package, lead
the forward current magnitude and the rate of change of cur- and wiring inductance are often at least as great a factor in
rent from the forward current magnitude to the reverse cur- limiting current rise time.
rent peak. When tested under the same circuit conditions,
the parasitic drain–source diode of a TMOS transistor has a
trr similar to that of a fast recovery rectifier.
100 Is = 0.5 A/div
0
50
t = 50 ns/div
I s , D–S DIODE FORWARD CURRENT (AMPS)
10
Figure 2–12. Typical Reverse Recovery
Characteristics of a Drain–Source Diode
5.0
TC + 25°C
+V
300 µS Pulse 60 pps
1.0
0.5 Q1
RL
0.1 Q2
0 1.0 2.0 3.0 4.0 5.0 6.0
VSD, D–D DIODE FORWARD ON–VOLTAGE (VOLTS)
–V
Figure 2–11. Forward Characteristics of Power Figure 2–13. TMOS Totem Pole Network with
MOSFETs D–S Diodes Integral Drain–Source Diodes
3–16
Chapter 3: The Data Sheet
Introduction
Motorola prides itself in having one of the most complete reduction in new product introduction cycle time as well as
and accurate Power MOSFET data sheets in the industry. providing more accurate and repeatable data.
For consistency, data sheet templates have been estab-
lished for each technology and or application grouping. This Headline Information
insures that the best approach is used in describing the per- Motorola’s TMOS Power MOSFET numbering system
formance characteristics of each device for the applications contains coded information describing technology, package,
they are used in. Additionally, this allows for the automation current and voltage information. A complete explanation of
of the data sheet generation process which has lead to a the nomenclature used is contained in Figure 3–1.
MTP75N06HD
MOTOROLA OPTIONAL SUFFIX:
X FOR ENGINEERING SAMPLES L FOR LOGIC LEVEL
TMOS E FOR ENERGY RATED
T FOR TMOS T4 FOR TAPE & REEL (DPAK/D2PAK)
L FOR SMARTDISCRETES RL FOR TAPE & REEL (DPAK)
G FOR IGBT HD FOR HIGH CELL DENSITY
P FOR MULTIPLE CHIP PRODUCTS V FOR TMOS V (FIVE)
PACKAGE TYPE
P FOR PLASTIC TO–220
M FOR METAL TO–204 (TO–3)/ICePAK
D FOR DPAK
A FOR TO–220 ISOLATED
W FOR TO–247
B FOR D2PAK
Y FOR TO–264 Example of exceptions: MTD/MTP3055E
E FOR SOT–227B Example of exceptions: MTD/MTP2955E
CURRENT
SO–8 (MiniMOS) and SOT–223 Power MOSFETs

MMSF4P01HDR1
MOTOROLA R1 AND R2 FOR TAPE & REEL
MiniMOS
TMOS
OPTIONAL SUFFIX:
M FOR MINIATURE
E FOR ENERGY RATED
PACKAGE TYPE HD FOR HIGH CELL DENSITY
DF — DUAL FET L FOR LOGIC LEVEL
SF — SINGLE FET
FT — FET TRANSISTOR
CURRENT C FOR COMPLEMENTARY
Figure 3–1. TMOS Power MOSFET Numbering System
3–17
Absolute Maximum Ratings
Absolute maximum ratings represent the extreme capabili- Junction Temperature (TJ ) – This value represents the
ties of the device. They can best be described as device maximum allowable junction temperature of the device. It is
characterization boundaries and are given to facilitate “worst derived and based off of long term Reliability data. Exceed-
case” design. ing this value will only serve to shorten the device’s long term
operating life.
Drain–to–Source Voltage (VDSS , VDGR ) – This represents
the lower limit of the devices blocking voltage capability from Thermal Resistance (Rthjc , Rthja ) – The quantity that resists
drain–to–source when either the gate is shorted to the or impedes the flow of heat energy in a device is called ther-
source (VDSS), or when a 1 MΩ gate–to–source resistor is mal resistance. Thermal resistance values are needed for
present (VDGR). It is measured at a specific leakage current proper thermal design. These values are measured as de-
and has a positive temperature coefficient. The voltage tailed in Motorola Application Note AN1083.
across the Power MOSFET should never exceed this rating
in order to prevent breakdown of the drain–to–source Electrical Characteristics
junction. The intent of this section in the data sheet is to provide de-
Maximum Gate–to–Source Voltage (VGS , VGSM ) – The tailed device characterization so that the designer can pre-
maximum allowable gate–to–source voltage as either a con- dict with a high degree of accuracy the behavior of the device
tinuous condition (VGS), or as a single pulse non–repetitive in a specific application.
condition (VGSM). Exceeding this limit may result in perma- Drain–to–Source Breakdown Voltage (V(BR)DSS ) – As de-
nent device degradation. scribed earlier, this represents the lower limit of the devices
Continuous Drain Current (ID ) – The dc current level that blocking voltage capability from drain–to–source with the
will raise the devices junction temperature to it’s rated maxi- gate shorted to the source. It is measured at a specific leak-
mum while it’s reference temperature is held at 25°C. This age current and has a positive temperature coefficient.
can be calculated by the equation: Zero Gate Voltage Drain Current (IDSS ) – The direct current
into the drain terminal of the device when the gate–to–source
ID = SQRT (PD/RDS(on) @ MAX TJ) voltage is zero and the drain terminal is reversed biased with
where, respect to the source terminal. This parameter generally in-
SQRT = Square root creases with temperature as shown in the “Drain–to–Source
PD = Device’s maximum power dissipation Leakage Current versus Voltage” figure found in the device’s
RDS(on) = Device’s “on” resistance data sheet.
MAX TJ = Device’s maximum rated junction temperature Gate–Body Leakage Current (IGSS ) – The direct current
into the gate terminal of the device when the gate terminal is
Pulsed Drain Current (IDM ) – The maximum allowable peak biased with either a positive or negative voltage with respect
drain current the device can safely handle under a 10 µs to the source terminal and the drain terminal is short–
pulsed condition. This rating takes into consideration the de- circuited to the source terminal.
vices thermal limitation as well as RDS(on), wire bond and Gate Threshold Voltage (VGS(th) ) – The forward gate–to–
source metal limitations. source voltage at which the magnitude of drain current has
Drain–to–Source Avalanche Energy (EAS) – This specifi- been increased to some low threshold value, usually
cation defines the maximum allowable energy that the device specified as 250 µA or 1 mA. This parameter has a negative
can safely handle in avalanche due to an inductive current temperature coefficient.
spike. It is tested at the ID of the device as a single pulse Drain–to–Source On–Resistance (RDS(on) ) – The dc resis-
non–repetitive condition. This value has a negative tempera- tance between the drain–to–source terminals with a speci-
ture coefficient as shown by the “Maximum Avalanche Ener- fied gate–to–source voltage applied to bias the device into
gy versus Starting Junction Temperature” figure shown in the the on–state. This parameter has a positive temperature
data sheet. For repetitive avalanche conditions, this value coefficient.
should be derated using the “Thermal Response” figure Drain–to–Source On–Voltage (VDS(on) ) – The dc voltage
shown in the data sheet for calculating the junction tempera- between the drain–to–source terminals with a specified
ture and the “Maximum Avalanche Energy versus Starting gate–to–source voltage applied to bias the device into the
Junction Temperature” figure also shown in the data sheet. on–state. This parameter has a positive temperature coeffi-
Maximum Power Dissipation (PD ) – Specifies the power cient.
dissipation limit which takes the junction temperature to it’s Forward Transconductance (gFS ) – The ratio of the
maximum rating while the reference temperature is being change in drain current due to a change in gate–to–source
held at 25°C. It is calculated by the following equation: voltage (i.e., ∆ ID/∆ VGS).
PD = (TJ – Tr)/Rthjr Device Capacitance (Ciss , Coss , Crss ) – Power MOSFET
devices have internal parasitic capacitance from terminal–
where,
to–terminal. This capacitance is voltage dependent as
PD = Maximum power dissipation shown by the “Capacitance Variation” figure on the device’s
TJ = Maximum allowable junction temperature data sheet. Ciss is the capacitance between the gate–to–
Tr = Reference (case and or ambient) temperature source terminals with the drain terminal short–circuited to the
Rthjr = Thermal resistance junction–to–reference source terminal for alternating current. Coss is the capaci-
= (case or ambient) tance between the drain–to–source terminals with the gate
3–18
short–circuited to the source terminal for alternating current. VGS(on)
Crss is the capacitance between the drain–to–gate terminals RL
with the source terminal connected to the guard terminal of a PULSE VDD
three–terminal bridge (Ref. IEEE No. 255). Figures 3–2, 3–3 GENERATOR MTP
LOW RG 3055V
and 3–4 show test circuits used for Power MOSFET capaci- IMPEDANCE
tance measurements. DRIVER +VR–
IM
L
D
B M L
I CAP. E O Figure 3–5. Switching Test Circuit
Cgd 0.1
A METER A O
S S. P Cds µF
G ton toff
H C1
IM Cgs
td(off) tr td(off) tf
GUARD
90% 90%
S OUTPUT, Vout
INVERTED
10%
L = 2.5 mH 90%
INPUT, Vin 50% 50%
10%
+ –
VDS PULSE WIDTH
Figure 3–2. Ciss Test Configuration Figure 3–6. Switching Waveforms
IM D
L
M L Gate Charge (QT, Q1 , Q2 ) – Gate charge values are used to
B
I
E O size the gate drive circuit and to estimate switching speeds
CAP. A O Cgd
A and switching losses. QT is defined as the total gate charge
METER S. P
S Cds required to charge the device’s input capacitance to the ap-
IM plied gate voltage. Q1 is defined as the charge required to
H
G Cgs charge the devices input capacitance to the VGS(on) required
GUARD to maintain the test current ID. The time required to deliver
this charge is called turn–on delay time. Q2 is defined as the
S
charge time required for the drain–to–source voltage to drop
to VDS(on).
+ –
Forward On–Voltage (VSD ) – The dc voltage between the
VDS source–to–drain terminals when the power MOSFET’s intrin-
Figure 3–3. Coss Test Configuration sic body diode is forward biased.
Reverse Recovery Time (trr , ta , tb , QRR ) – The intrinsic
IM D body diode of a power MOSFET is a minority carrier device
L and thus has a finite reverse recovery time. Ta is defined as
M L
B the time between the dropping IS current’s zero crossing
E O
I CAP. point to the peak IRM. Tb is defined as the time between the
A O Cgd
A METER peak IRM to a projected IRM zero current crossing point
S. P IM Cds
S
through a 25% IRM projection as shown in Figure 3–7. Total
H
G Cgs reverse recovery time, trr, is defined as the sum of ta and tb.
GUARD QRR is defined as the integral of the area made up by the IRM
waveform and VR, the reapplied blocking voltage which
S forces reverse recovery.
+ – di/dt
VDS IS
Figure 3–4. Crss Test Configuration trr
ta tb
Resistive Switching (td(on) , tr , td(off) , tf ) – MOSFET switch-
ing speeds are very fast, relative to comparably sized bipolar TIME
transistors. They are tested and measured using a resistive tp 0.25 IS
switching test circuit as shown in Figure 3–5. A typical
switching waveform showing parameter measurement points IS
is shown in Figure 3–6. Figure 3–7. Diode Reverse Recovery Waveform
3–19
3–20
Section Four
Data Sheets
Motorola TMOS Power MOSFET Transistor Device Data 4–1

MC33153
Advance Information
Single IGBT Gate Driver
The MC33153 is specifcally designed as an IGBT driver for high power
applications that include ac induction motor control, brushless dc motor con- SINGLE IGBT
trol and uninterruptable power supplies. Although designed for driving dis- GATE DRIVER
crete and module IGBTs, this device offers a cost effective solution for
driving power MOSFETs and Bipolar Transistors. Device protection features
include the choice of desaturation or overcurrent sensing and undervoltage SEMICONDUCTOR
detection. These devices are available in dual–in–line and surface mount TECHNICAL DATA
packages and include the following features:
• High Current Output Stage: 1.0 A Source/2.0 A Sink

• Protection Circuits for Both Conventional and Sense IGBT’s
• Programmable Fault Blanking Time
• Protection against Overcurrent and Short Circuit
• Undervoltage Lockout Optimzed for IGBT’s 8
• Negative Gate Drive Capability 1
• Cost Effectively Drives Power MOSFETs and Bipolar Transistors
P SUFFIX
PLASTIC PACKAGE
CASE 626
Representative Block Diagram

VCC
6 8
1
VCC VCC Short Circuit
Short Circuit Comparator
D SUFFIX
Latch
Fault S VCC PLASTIC PACKAGE
Output 7 Q CASE 751
R Overcurrent
Comparator
Current (SO–8)
Overcurrent Sense
VEE Latch 130 mV 1 Input
S
Q
R 65 mV
VEE
VCC Kelvin
VCC Gnd PIN CONNECTIONS
2
270 mA
Fault
8 Blanking/ Current Sense
Desaturation 1 8 Fault Blanking/
6.5 V Input Input Desaturation Input
Fault Blanking/ VEE
Desaturation
Comparator Kelvin Gnd 2 7 Fault Output
VCC
VEE 3 6 VCC
VCC Output
Stage
Input 4 5 Drive Output
Input Drive
4 VCC 5 Output
Under
Voltage (Top View)
VEE Lockout
VEE
ORDERING INFORMATION
12 V/
11 V Operating
3 VEE Device Temperature Range Package
This device contains 133 active transistors. MC33153D SO–8

TA = –40° to +105°C
MC33153P DIP–8
4–2 Motorola TMOS Power MOSFET Transistor Device Data

MC33153
MAXIMUM RATINGS
Rating Symbol Value Unit
Power Supply Voltage V
VCC to VEE VCC – VEE 23
Kelvin Ground to VEE KGnd – VEE 23
Logic Input Vin VEE –0.3 to VCC V
Current Sense Input VS –0.3 to VCC V
Blanking/Desaturation Input VBD –0.3 to VCC V
Gate Drive Output IO A
Source Current 1.0
Sink Current 2.0
Diode Clamp Current 1.0
Fault Output IFO mA
Source Current 25
Sink Curent 10
Power Dissipation and Thermal Characteristics
D Suffix SO–8 Package, Case 751
Maximum Power Dissipation @ TA = 50°C PD 0.56 W
Thermal Resistance, Junction–to–Air RθJA 180 °C/W
P Suffix DIP–8 Package, Case 626
Maximum Power Dissipation @ TA = 50°C PD 1.0 W
Thermal Resistance, Junction–to–Air RθJA 100 °C/W
Operating Junction Temperature TJ +150 °C
Operating Ambient Temperature TA –40 to +105 °C
Storage Temperature Range Tstg –65 to +150 °C
ELECTRICAL CHARACTERISTICS (VCC = 15 V, VEE = 0 V, Kelvin Gnd connected to VEE. For typical values
TA = 25°C, for min/max values TA is the operating ambient temperature range that applies (Note 1), unless otherwise noted.)
Characteristic Symbol Min Typ Max Unit
LOGIC INPUT
Input Threshold Voltage V
High State (Logic 1) VIH – 2.70 3.2
Low State (Logic 0) VIL 1.2 2.30 –
Input Current µA
High State (VIH = 3.0 V) IIH – 130 500
Low State (VIL = 1.2 V) IIL – 50 100
DRIVE OUTPUT
Output Voltage V
Low State (ISink = 1.0 A) VOL – 2.0 2.5
High State (ISource = 500 mA) VOH 12 13.9 –
Output Pull–Down Resistor RPD – – 200 kΩ
FAULT OUTPUT
Output voltage V
Low State (ISink = 5.0 mA) VFL – 0.2 1.0
High State (ISource = 20 mA) VFH 12 13.3 –
SWITCHING CHARACTERISTICS
Propagation Delay (50% Input to 50% Output CL = 1.0 nF) ns
Logic Input to Drive Output Rise tPLH(in/out) – 80 300
Logic Input to Drive Output Fall tPHL (in/out) – 120 300
Drive Output Rise Time (10% to 90%) CL = 1.0 nF tr – 17 55 ns
Drive Output Fall Time (90% to 10%) CL = 1.0 nF tf – 17 55 ns
Propagation Delay µs
Current Sense Input to Drive Output tP(OC) – 0.3 1.0
NOTE: 1. Low duty cycle pulse techniques are used during test to maintain the junction temperature as close to ambient as possible.
Tlow = –40°C for MC33153 Thigh = +105°C for MC33153

MC33153
ELECTRICAL CHARACTERISTICS (continued) (VCC = 15 V, VEE = 0 V, Kelvin Gnd connected to VEE. For typical values
TA = 25°C, for min/max values TA is the operating ambient temperature range that applies (Note 1), unless otherwise noted.)
SWITCHING CHARACTERISTICS (continued)

Fault Blanking/Desaturation Input to Drive Output tP(FLT) – 0.3 1.0
UVLO
Startup Voltage VCC start – 12 12.6 V
Disable Voltage VCC dis 10.4 11 – V
COMPARATORS
Overcurrent Threshold Voltage (VPin8 > 7.0 V) VSOC 50 65 80 mV
Short Circuit Threshold Voltage (VPin8 > 7.0 V) VSSC 100 130 160 mV
Fault Blanking/Desaturation Threshold (VPin1 > 100 mV) Vth(FLT) 6.0 6.5 7.0 V
Current Sense Input Current (VSI = 0 V) ISI – –1.4 –10 µA
FAULT BLANKING/DESATURATION INPUT
Current Source (VPin8 = 0 V, VPin4 = 0 V) Ichg –200 –270 –300 µA
Discharge Current (VPin8 = 15 V, VPin4 = 5.0 V) Idschg 1.0 2.5 – mA
TOTAL DEVICE
Power Supply Current ICC mA
Standby (VPin 4 = VCC, Output Open) – 7.2 14
Operating (CL = 1.0 nF, f = 20 kHz) – 7.9 20
NOTE: 1. Low duty cycle pulse techniques are used during test to maintain the junction temperature as close to ambient as possible.
Tlow = –40°C for MC33153 Thigh = +105°C for MC33153
Figure 1. Input Current versus Input Voltage Figure 2. Output Voltage versus Input Voltage
1.5 16
14 VCC = 15 V
TA = 25°C
I in , INPUT CURRENT (mA)
VO , OUTPUT VOLTAGE (V)
12
1.0
10
8.0
6.0
0.5
4.0
VCC = 15 V
TA = 25°C 2.0
0 0
0 2.0 4.0 6.0 8.0 10 12 14 16 0 1.0 2.0 3.0 4.0 5.0
Vin, INPUT VOLTAGE (V) Vin, INPUT VOLTAGE (V)

MC33153
Figure 3. Input Threshold Voltage Figure 4. Input Threshold Voltage

versus Temperature versus Supply Voltage
3.2 2.8
V IH – V IL , INPUT THRESHOLD VOLTAGE (V)

V IH – V IL , INPUT THRESHOLD VOLTAGE (V)
VCC = 15 V VIH TA = 25°C

3.0 2.7
2.8 VIH 2.6
2.6 2.5
2.4 2.4
VIL
2.2 VIL 2.3
2.0 2.2
–60 –40 –20 0 20 40 60 80 100 120 140 12 13 14 15 16 17 18 19 20
TA, AMBIENT TEMPERATURE (°C) VCC, SUPPLY VOLTAGE (V)
Figure 5. Drive Output Low State Voltage Figure 6. Drive Output Low State Voltage
versus Temperature versus Sink Current
2.5 2.0
V OL, OUTPUT LOW STATE VOLTAGE (V)
2.0
ISink = 1.0 A V OL, OUTPUT LOW STATE VOLTAGE (V) 1.6
= 500 mA
1.5 1.2
= 250 mA
1.0 0.8
0.5 0.4
TA = 25°C
VCC = 15 V
VCC = 15 V
0 0
–60 –40 –20 0 20 40 60 80 100 120 140 0 0.2 0.4 0.6 0.8 1.0
TA, AMBIENT TEMPERATURE (°C) ISink, OUTPUT SINK CURRENT (A)
Figure 7. Drive Output High State Voltage Figure 8. Drive Output High State Voltage
versus Temperature versus Source Current
VOH , DRIVE OUTPUT HIGH STATE VOLTAGE (V)
VOH , DRIVE OUTPUT HIGH STATE VOLTAGE (V)
14.0 15.0
VCC = 15 V
13.9 14.6 TA = 25°C
13.8 14.2
13.7 13.8
13.6 VCC = 15 V 13.4

ISource = 500 mA
13.5 13.0
–60 –40 –20 0 20 40 60 80 100 120 140 0 0.1 0.2 0.3 0.4 0.5
TA, AMBIENT TEMPERATURE (°C) ISource, OUTPUT SOURCE CURRENT (A)

MC33153
Figure 9. Drive Output Voltage Figure 10. Fault Output Voltage

versus Current Sense Input Voltage versus Current Sense Input Voltage
16 14
V Pin 7, FAULT OUTPUT VOLTAGE (V)

14 VCC = 15 V 12 VCC = 15 V
VO , DRIVE OUTPUT VOLTAGE (V)
VPin 4 = 0 V VPin 4 = 0 V
12 VPin 8 > 7.0 V VPin 8 > 7.0 V
10
TA = 25°C TA = 25°C
10
8.0
8.0
6.0
6.0
4.0
4.0
2.0 2.0
0 0
50 55 60 65 70 75 80 100 110 120 130 140 150 160
VPin 1, CURRENT SENSE INPUT VOLTAGE (mV) VPin 1, CURRENT SENSE INPUT VOLTAGE (V)
Figure 11. Overcurrent Protection Threshold Figure 12. Overcurrent Protection Threshold
V SOC , OVERCURRENT THRESHOLD VOLTAGE (mV)
V SOC , OVERCURRENT THRESHOLD VOLTAGE (mV)

Voltage versus Temperature Voltage versus Supply Voltage
70 70
VCC = 15 V TA = 25°C
68 68
66 66
64 64
62 62
60 60
–60 –40 –20 0 20 40 60 80 100 120 140 12 14 16 18 20
Figure 13. Short Circuit Comparator Threshold Figure 14. Short Circuit Comparator Threshold
VSSC, SHORT CIRCUIT THRESHOLD VOLTAGE (mV)
VSSC, SHORT CIRCUIT THRESHOLD VOLTAGE (mV)
Voltage versus Temperature Voltage versus Supply Voltage

135 135
VCC = 15 V TA = 25°C
130 130
125 125
–60 –40 –20 0 20 40 60 80 100 120 140 12 14 16 18 20

MC33153
Figure 15. Current Sense Input Current Figure 16. Drive Output Voltage versus Fault
ISI , CURRENT SENSE INPUT CURRENT (µ A) versus Voltage Blanking/Desaturation Input Voltage
0 16
14

VCC = 15 V VCC = 15 V
TA = 25°C VPin 4 = 0 V
12
VPin 1 > 100 mV
–0.5 TA = 25°C
10
8.0
6.0
–1.0
4.0
2.0
–1.5 0
0 2.0 4.0 6.0 8.0 10 12 14 16 6.0 6.2 6.4 6.6 6.8 7.0
VPin 1, CURRENT SENSE INPUT VOLTAGE (V) VPin 8, FAULT BLANKING/DESATURATION INPUT VOLTAGE (V)
Figure 17. Fault Blanking/Desaturation Comparator Figure 18. Fault Blanking/Desaturation Comparator
Threshold Voltage versus Temperature Threshold Voltage versus Supply Voltage
6.6 6.6
V BDT , FAULT BLANKING/DESATURATION
VCC = 15 V V BDT , FAULT BLANKING/DESATURATION VPin 4 = 0 V

THRESHOLD VOLTAGE (V)
VPin 4 = 0 V THRESHOLD VOLTAGE (V) VPin 1 > 100 mV

VPin 1 > 100 mV TA = 25°C
6.5 6.5
6.4 6.4
–60 –40 –20 0 20 40 60 80 100 120 140 12 14 16 18 20
Figure 19. Fault Blanking/Desaturation Current Figure 20. Fault Blanking/Desaturation Current
Source versus Temperature Source versus Supply Voltage
–200 –200
VCC = 15 V
Ichg, CURRENT SOURCE ( µ A)
Ichg, CURRENT SOURCE ( µ A)
–220 –220 VPin 4 = 0 V

VPin 8 = 0 V VPin 8 = 0 V
TA = 25°C
–240 –240
–260 –260
–280 –280
–300 –300
–60 –40 –20 0 20 40 60 80 100 120 140 5.0 10 15 20

MC33153
Figure 21. Fault Blanking/Desaturation Figure 22. Fault Blanking/Desaturation Discharge

Current Source versus Input Voltage Current versus Input Voltage
–200 2.5
I dscg, DISCHARGE CURRENT (mA)

2.0
I chg, CURRENT SOURCE ( µ A)
–220 VCC = 15 V
VPin 4 = 0 V
TA = 25°C 1.5
–240
1.0
–260
0.5
–280 VCC = 15 V
0 VPin 4 = 5.0 V
TA = 25°C
–300 –0.5
0 2.0 4.0 6.0 8.0 10 12 14 16 0 4.0 8.0 12 16
VPin 8, INPUT VOLTAGE (V) VPin 8, INPUT VOLTAGE (V)
Figure 23. Fault Output Low State Voltage Figure 24. Fault Output High State Voltage
versus Sink Current versus Source Current
1.0 14.0
VPin 7 , FAULT OUTPUT VOLTAGE (V)
0.8 VCC = 15 V VPin 7 , FAULT OUTPUT VOLTAGE (V) 13.8

VCC = 15 V
VPin 4 = 0 V
VPin 4 = 5.0 V
VPin 1 = 1.0 V
TA = 25°C
Pin 8 = Open
0.6 13.6 TA = 25°C
0.4 13.4
0.2 13.2
0 13.0
0 2.0 4.0 6.0 8.0 10 0 2.0 4.0 6.0 8.0 10 12 14 16 18 20
ISink, OUTPUT SINK CURRENT (mA) ISource, OUTPUT SOURCE CURRENT (mA)
Figure 25. Drive Output Voltage Figure 26. UVLO Thresholds

versus Supply Voltage versus Temperature
16 12.5
14 Startup Threshold
VCC Increasing
Vth(UVLO), UNDERVOLTAGE
LOCKOUT THRESHOLD (V)
12 12.0
10
Turn–Off
8.0 Threshold 11.5
6.0 Turn–Off Threshold

VCC Decreasing
4.0 Startup 11.0
Threshold VPin 4 = 0 V
2.0 TA = 25°C
0 10.5
10 11 12 13 14 15 –60 –40 –20 0 20 40 60 80 100 120 140
VCC, SUPPLY VOLTAGE (V) TA, AMBIENT TEMPERATURE (°C)

MC33153
Figure 27. Supply Current versus

Supply Voltage Figure 28. Supply Current versus Temperature
10 10
Output High
8.0
ICC, SUPPLY CURRENT (mA)

8.0
Output Low
6.0 6.0
4.0 4.0
2.0 TA = 25°C 2.0 VCC = 15 V

VPin 4 = VCC
Drive Output Open
0 0
5.0 10 15 20 –60 –40 –20 0 20 40 60 80 100 120 140
VCC, SUPPLY VOLTAGE (V) TA, AMBIENT TEMPERATURE (°C)
Figure 29. Supply Current versus Input Frequency

80
CL = 10 nF
VCC = 15 V
TA = 25°C
60 = 5.0 nF
40
= 2.0 nF
20
= 1.0 nF
0
1.0 10 100 1000
f, INPUT FREQUENCY (Hz)
OPERATING DESCRIPTION
GATE DRIVE
Controlling Switching Times
The most important design aspect of an IGBT gate drive is The turn–off resistor, Roff, controls the turn–off speed and
optimization of the switching characteristics. The switching ensures that the IGBT remains off under commutation
characteristics are especially important in motor control stresses. Turn–off is critical to obtain low switching losses.
applications in which PWM transistors are used in a bridge While IGBTs exhibit a fixed minimum loss due to minority car-
configuration. In these applications, the gate drive circuit rier recombination, a slow gate drive will dominate the turn–
components should be selected to optimize turn–on, turn–off off losses. This is particularly true for fast IGBTs. It is also
and off–state impedance. A single resistor may be used to possible to turn–off an IGBT too fast. Excessive turn–off
control both turn–on and turn–off as shown in Figure 30. speed will result in large overshoot voltages. Normally, the
However, the resistor value selected must be a compromise turn–off resistor is a small fraction of the turn–on resistor.
in turn–on abruptness and turn–off losses. Using a single The MC33153 contains a bipolar totem pole output stage
resistor is normally suitable only for very low frequency that is capable of sourcing 1.0 amp and sinking 2.0 amps
PWM. An optimized gate drive output stage is shown in Fig- peak. This output also contains a pull down resistor to ensure
ure 31. This circuit allows turn–on and turn–off to be opti- that the IGBT is off whenever there is insufficient VCC to the
mized separately. The turn–on resistor, Ron, provides control MC33153.
over the IGBT turn–on speed. In motor control circuits, the In a PWM inverter, IGBTs are used in a half–bridge config-
resistor sets the turn–on di/dt that controls how fast the free– uration. Thus, at least one device is always off. While the
wheel diode is cleared. The interaction of the IGBT and free– IGBT is in the off–state, it will be subjected to changes in volt-
wheeling diode determines the turn–on dv/dt. Excessive age caused by the other devices. This is particularly a prob-
turn–on dv/dt is a common problem in half–bridge circuits. lem when the opposite transistor turns on.

MC33153
When the lower device is turned on, clearing the upper The MC33153 may be used with an optically isolated
diode, the turn–on dv/dt of the lower device appears across input. The optoisolator can be used to provide level shifting,
the collector emitter of the upper device. To eliminate shoot– and if desired, isolation from ac line voltages. An optoisolator
through currents, it is necessary to provide a low sink imped- with a very high dv/dt capability should be used, such as the
ance to the device that is in the off–state. In most applications Hewlett Packard HCPL4053. The IGBT gate turn–on resistor
the turn–off resistor can be made small enough to hold off the should be set large enough to ensure that the opto’s dv/dt
device that is under commutation without causing exces- capability is not exceeded. Like most optoisolators, the
sively fast turn–off speeds. HCPL4053 has an active low open–collector output. Thus,
when the LED is on, the output will be low. The MC33153 has
an inverting input pin to interface directly with an optoisolator
using a pull up resistor. The input may also be interfaced
Figure 30. Using a Single Gate Resistor directly to 5.0 V CMOS logic or a microcontroller.
VCC
IGBT Optoisolator Output Fault
The MC33153 has an active high fault output. The fault
Rg
Output output may be easily interfaced to an optoisolator. While it is
5 important that all faults are properly reported, it is equally
important that no false signals are propagated. Again, a high
dv/dt optoisolator should be used.
VEE VEE The LED drive provides a resistor programmable current
3 of 10 to 20 mA when on, and provides a low impedance path
VEE when off. An active high output, resistor, and small signal
diode provide an excellent LED driver. This circuit is shown in
Figure 32.
Figure 31. Using Separate Resistors Figure 32. Output Fault Optoisolator
for Turn–On and Turn–Off
VCC Short Circuit

IGBT Latch Output VCC
Ron
Output Q
Doff Roff
5
7
VEE VEE
VEE VEE
3
VEE
UNDERVOLTAGE LOCKOUT
A negative bias voltage can be used to drive the IGBT into
It is desirable to protect an IGBT from insufficient gate volt-
the off–state. This is a practice carried over from bipolar Dar-
age. IGBTs require 15 V on the gate to achieve the rated on–
lington drives and is generally not required for IGBTs. How-
voltage. At gate voltages below 13 V, the on–voltage
ever, a negative bias will reduce the possibility of
increases dramatically, especially at higher currents. At very
shoot–through. The MC33153 has separate pins for VEE and
low gate voltages, below 10 V, the IGBT may operate in the
Kelvin Ground. This permits operation using a +15/–5.0 V
linear region and quickly overheat. Many PWM motor drives
supply.
use a bootstrap supply for the upper gate drive. The UVLO
provides protection for the IGBT in case the bootstrap capac-
itor discharges.
INTERFACING WITH OPTOISOLATORS The MC33153 will typically start up at about 12 V. The
Isolated Input UVLO circuit has about 1.0 V of hysteresis and will disable
the output if the supply voltage falls below about 11V.

MC33153
PROTECTION CIRCUITRY The MC33153 also features a programmable fault blank-
Desaturation Protection ing time. During turn–on, the IGBT must clear the opposing
free–wheeling diode. The collector voltage will remain high
Bipolar Power circuits have commonly used what is known
until the diode is cleared. Once the diode has been cleared,
as “Desaturation Detection”. This involves monitoring the col-
lector voltage and turning off the device if this voltage rises the voltage will come down quickly to the VCE(sat) of the
above a certain limit. A bipolar transistor will only conduct a device. Following turn–on, there is normally considerable
certain amount of current for a given base drive. When the ringing on the collector due to the COSS capacitance of the
base is overdriven, the device is in saturation. When the col- IGBTs and the parasitic wiring inductance. The fault signal
lector current rises above the knee, the device pulls out of from the Desaturation Comparator must be blanked suffi-
saturation. The maximum current the device will conduct in ciently to allow the diode to be cleared and the ringing to
the linear region is a function of the base current and the dc settle out.
current gain (hFE) of the transistor. The blanking function uses an NPN transistor to clamp the
The output characteristics of an IGBT are similar to a Bipo- comparator input when the gate input is low. When the input
lar device. However, the output current is a function of gate is switched high, the clamp transistor will turn “off”, allowing
voltage instead of current. The maximum current depends on the internal current source to charge the blanking capacitor.
the gate voltage and the device type. IGBTs tend to have a The time required for the blanking capacitor to charge up
very high transconductance and a much higher current den-
from the on–voltage of the internal NPN transistor to the trip
sity under a short circuit than a bipolar device. Motor control
voltage of the comparator is the blanking time.
IGBTs are designed for a lower current density under shorted
If a short circuit occurs after the IGBT is turned on and sat-
conditions and a longer short circuit survival time.
The best method for detecting desaturation is the use of a urated, the delay time will be the time required for the current
high voltage clamp diode and a comparator. The MC33153 source to charge up the blanking capacitor from the VCE(sat)
has a Fault Blanking/Desaturation Comparator which senses level of the IGBT to the trip voltage of the comparator. Fault
the collector voltage and provides an output indicating when blanking can be disabled by leaving Pin 8 unconnected.
the device is not fully saturated. Diode D1 is an external high
Sense IGBT Protection
voltage diode with a rated voltage comparable to the power
device. When the IGBT is “on” and saturated, D1 will pull Another approach to protecting the IGBTs is to sense the
down the voltage on the Fault Blanking/Desaturation Input. emitter current using a current shunt or Sense IGBTs. This
When the IGBT pulls out of saturation or is “off”, the current method has the advantage of being able to use high gain
source will pull up the input and trip the comparator. The IGBTs which do not have any inherent short circuit capability.
comparator threshold is 6.5 V, allowing a maximum on–volt- Current sense IGBTs work as well as current sense MOS-
age of about 5.8 V. FETs in most circumstances. However, the basic problem of
A fault exists when the gate input is high and VCE is working with very low sense voltages still exists. Sense
greater than the maximum allowable VCE(sat). The output of
IGBTs sense current through the channel and are therefore
the Desaturation Comparator is ANDed with the gate input
linear with respect to the collector current. Because IGBTs
signal and fed into the Short Circuit and Overcurrent Latches.
The Overcurrent Latch will turn–off the IGBT for the remain- have a very low incremental on–resistance, sense IGBTs
der of the cycle when a fault is detected. When input goes behave much like low–on resistance current sense MOS-
high, both latches are reset. The reference voltage is tied to FETs. The output voltage of a properly terminated sense
the Kelvin Ground instead of the VEE to make the threshold IGBT is very low, normally less than 100 mV.
independent of negative gate bias. Note that for proper The sense IGBT approach requires fault blanking to pre-
operation of the Desaturation Comparator and the Fault Out- vent false tripping during turn–on. The sense IGBT also
put, the Current Sense Input must be biased above the Over- requires that the sense signal is ignored while the gate is low.
current and Short Circuit Comparator thresholds. This can be This is because the mirror output normally produces large
accomplished by connecting Pin 1 to VCC. transient voltages during both turn–on and turn–off due to the
collector to mirror capacitance. With non–sensing types of
IGBTs, a low resistance current shunt (5.0 to 50 mΩ) can be
Figure 33. Desaturation Detection used to sense the emitter current. When the output is an
actual short circuit, the inductance will be very low. Since the
VCC blanking circuit provides a fixed minimum on–time, the peak
Desaturation VCC
Comparator current under a short circuit can be very high. A short circuit
270 µA D1 discern function is implemented by the second comparator
which has a higher trip voltage. The short circuit signal is
8
Vref
latched and appears at the Fault Output. When a short circuit
Kelvin 6.5 V VEE is detected, the IGBT should be turned–off for several milli-
Gnd seconds allowing it to cool down before it is turned back on.
The sense circuit is very similar to the desaturation circuit. It
is possible to build a combination circuit that provides protec-
tion for both Short Circuit capable IGBTs and Sense IGBTs.

MC33153
APPLICATION INFORMATION
Figure 34 shows a basic IGBT driver application. When If desaturation protection is desired, a high voltage diode
driven from an optoisolator, an input pull up resistor is is connected to the Fault Blanking/Desaturation pin. The
required. This resistor value should be set to bias the output blanking capacitor should be connected from the Desatura-
transistor at the desired current. A decoupling capacitor tion pin to the VEE pin. If a dual supply is used, the blanking
should be placed close to the IC to minimize switching noise. capacitor should be connected to the Kelvin Ground. The
A bootstrap diode may be used for a floating supply. If the Current Sense Input should be tied high because the two
protection features are not required, then both the Fault comparator outputs are ANDed together. Although the
Blanking/Desaturation and Current Sense Inputs should both reverse voltage on collector of the IGBT is clamped to the
be connected to the Kelvin Ground (Pin 2). When used with a emitter by the free–wheeling diode, there is normally consid-
single supply, the Kelvin Ground and VEE pins should be con- erable inductance within the package itself. A small resistor
nected together. Separate gate resistors are recommended in series with the diode can be used to protect the IC from
to optimize the turn–on and turn–off drive. reverse voltage transients.
Figure 34. Basic Application Figure 36. Desaturation Application

+18 V +18 V
B+
Bootstrap
6 6
VCC Desat/ 8 7 VCC Desat/ 8
Fault Blank
7 Blank
Fault 5 CBlank
Output MC33153
5
MC33153 Output
1 1
4 Sense Sense
Input 4
2 Input 2
VEE Gnd VEE Gnd
3 3
When using sense IGBTs or a sense resistor, the sense

Figure 35. Dual Supply Application voltage is applied to the Current Sense Input. The sense trip
voltages are referenced to the Kelvin Ground pin. The sense
+15 V
voltage is very small, typically about 65 mV, and sensitive to
noise. Therefore, the sense and ground return conductors
should be routed as a differential pair. An RC filter is useful in
6 filtering any high frequency noise. A blanking capacitor is
VCC Desat/ 8
connected from the blanking pin to VEE. The stray capaci-
7 Blank
Fault 5 tance on the blanking pin provides a very small level of blank-
Output
ing if left open. The blanking pin should not be grounded
MC33153 when using current sensing, that would disable the sense.
1
4 Sense The blanking pin should never be tied high, that would short
Input
2 out the clamp transistor.
VEE Gnd
3
Figure 37. Sense IGBT Application
+18 V
–5.0 V
6
When used in a dual supply application as in Figure 35, the 7 VCC Desat/ 8
Fault Blank
Kelvin Ground should be connected to the emitter of the 5
Output
IGBT. If the protection features are not used, then both the
Fault Blanking/Desaturation and the Current Sense Inputs MC33153
1
should be connected to Ground. The input optoisolator Sense
should always be referenced to VEE. 4
Input 2
VEE Gnd
3

MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Product Preview
MGP20N14CL
SMARTDISCRETES
Internally Clamped, N-Channel
IGBT 20 AMPERES
This Logic Level Insulated Gate Bipolar Transistor (IGBT) VOLTAGE CLAMPED
features Gate–Emitter ESD protection, Gate–Collector overvoltage N–CHANNEL IGBT
protection from SMARTDISCRETES monolithic circuitry for Vce(on) = 1.9 VOLTS
usage as an Ignition Coil Driver. 135 VOLTS (CLAMPED)
• Temperature Compensated Gate–Drain Clamp Limits Stress
Applied to Load 
• Integrated ESD Diode Protection
• Low Threshold Voltage to Interface Power Loads to Logic or
C
Microprocessors
• Low Saturation Voltage
• High Pulsed Current Capability
G
G
C
Rge E
CASE 221A–06, Style 9

TO–220AB
E
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)

Collector–Emitter Voltage VCES CLAMPED Vdc
Collector–Gate Voltage VCGR CLAMPED Vdc
Gate–Emitter Voltage VGE CLAMPED Vdc
Collector Current — Continuous @ TC = 25°C IC 20 Adc
Collector Current — Single Pulsed (tp = 10 ms)" ICM 60 Apk
Total Power Dissipation @ TC = 25°C (TO–220) PD 150 Watts

Derate Above 25°C 1.0 W/°C
Operating and Storage Temperature Range TJ, Tstg – 55 to 175 °C

Single Pulse Collector–Emitter Avalanche Energy @ Starting TJ = 25°C EAS mJ
(VCC = 80 V, VGE = 5 V, Peak IL = 10 A, L = 10 mH) 500
THERMAL CHARACTERISTICS
Thermal Resistance — Junction to Case – (TO–220) RqJC 1.0 °C/W
Thermal Resistance — Junction to Ambient RqJA 62.5
Maximum Lead Temperature for Soldering Purposes, 1/8″ from case for 5 seconds TL 275 °C
Mounting Torque, 6–32 or M3 screw 10 lbfin (1.13 Nm)
This document contains information on a new product. Specifications and information herein are subject to change without notice.

MGP20N14CL
ELECTRICAL CHARACTERISTICS (TC = 25°C unless otherwise noted)
OFF CHARACTERISTICS
Clamp Voltage BVCES Vdc
(IClamp = 10 mA, TJ = –40 to 150°C) 135
Zero Gate Voltage Collector Current ICES mA
(VCE = 100 V, VGE = 0 V) — — 10
(VCE = 100 V, VGE = 0 V, TJ = 150°C) — — 100
Gate–Emitter Clamp Voltage (IG = 1 mA) BVGES 10 Vdc
Gate–Emitter Leakage Current (VGE = "5 V, VCE = 0 V) IGES — — 1.0 mA
ON CHARACTERISTICS (1)
Gate Threshold Voltage VCE(th) V
(VCE = VGE, IC = 1 mA) 1.0 1.5 2.0
Threshold Temperature Coefficient (Negative) 4.4 mV/°C
Collector–Emitter On–Voltage VCE(on) V
(VGE = 5 V, IC = 10 A) — 1.9
(VGE = 5 V, IC = 10 Adc, TJ = 175°C) — 1.8
Forward Transconductance (VCE u 15 V, IC = 10 A) gfs 8.0 15 — Mhos
DYNAMIC CHARACTERISTICS
Input Capacitance Ciss — 430 600 pF
Output Capacitance (VCE = 25 Vdc,
Vd VGE = 0 Vdc,
Vd
Coss — 182 250
f = 1.0 MHz)
Transfer Capacitance Crss — 48 100
SWITCHING CHARACTERISTICS (1)

Turn–On Delay Time td(on) — TBD TBD ns
Rise Time ((VCC = 68 V, IC = 20 A, tr — TBD TBD
Turn–Off Delay Time VGE = 5 V, RG = 9.1 W) td(off) — TBD TBD
Fall Time tf — TBD TBD
Total Gate Charge Qg — 14 20 nC
(VCC = 108 V,
V IC = 20 A,
A
Gate–Emitter Charge Qgs — 3.0 —
VGE = 5 V)
Gate–Collector Charge Qgd — 6.0 —
(1) Pulse Test: Pulse Width ≤ 300 µs, Duty Cycle ≤ 2%.

MOTOROLA
Advanced Information MGP20N35CL

SMARTDISCRETES
IGBT 20 AMPERES
Applied to Load 
C
Microprocessors
G
G
C
Rge E

TO–220AB
E

Reversed Collector Current – pulse width t 100 ms ICR 12 Apk
Electrostatic Voltage — Gate–Emitter ESD 3.5 kV
Thermal Resistance — Junction to Ambient RqJA 62.5
UNCLAMPED INDUCTIVE SWITCHING CHARACTERISTICS

Single Pulse Collector–Emitter Avalanche Energy EAS mJ
@ Starting TJ = 25°C 550

MGP20N35CL
OFF CHARACTERISTICS
Collector–to–Emitter Breakdown Voltage BVCES Vdc
(IClamp = 10 mA, TJ = –40 to 150°C) 320 350 380
Zero Gate Voltage Collector Current ICES
(VCE = 250 V, VGE = 0 V, TJ = 125°C) — — 1.0 mA
(VCE = 15 V, VGE = 0 V, TJ = 125°C) — — 200 mA
Resistance Gate–Emitter (TJ = –40 to 150°C) RGE 10k 16k 30k W
Gate–Emitter Breakdown Voltage (IG = 2 mA) BVGES 11 13 15 "V
Collector–Emitter Reverse Leakage (VCE = –15 V, TJ = –40 to 150°C) ICES — 8 100 mA
Collector–Emitter Reversed Breakdown Voltage (IE = 75 mA) BVCER 26 40 120 V
Gate Threshold Voltage VGE(th) V
(VCE = VGE, IC = 1 mA) 1.0 1.7 2.4
(VCE = VGE, IC = 1 mA, TJ = 150°C) 0.75 — 1.8
(VGE = 5 V, IC = 5 A) — 1.1 1.4
(VGE = 5 V, IC = 10 A) — 1.4 1.9
(VGE = 5 V, IC = 10 Adc, TJ = 150°C) — 1.4 1.8
Forward Transconductance (VCE u 50 V, IC = 10 A) gfs 10 16 — S
Input Capacitance Ciss — 2800 — pF
Vd VGE = 0 Vdc,
Vd
Coss — 200 —
f = 1.0 MHz)
Transfer Capacitance Crss — 25 —

Gate–Emitter Charge (VCC = 280 V,
V IC = 20 A,
A
Qgs — 8.0 —
VGE = 5 V)
Gate–Collector Charge Qgd — 20 —
Turn–Off Delay Time ( CC = 320 V, IC = 20 A,
(V td(off) — TBD TBD µs
Fall Time L = 200 mH, RG = 1 KW) tf — TBD TBD
Turn–On Delay Time ((VCC = 14 V, IC = 20 A, td(on) — TBD TBD µs
Rise Time L = 200 mH, RG = 1 KW) tr — TBD TBD

MGP20N35CL
TYPICAL ELECTRICAL CHARACTERISTICS
40 40
VGE = 10 V 5V TJ = 25°C VGE = 10 V 5V TJ = 125°C
I C , COLLECTOR CURRENT (AMPS)

30 30
4V
4V
20 20
10 10 3V
3V
0 0
0 2 4 6 8 10 0 1 2 3 4 5 6 7 8 9 10
VCE, COLLECTOR–TO–EMITTER VOLTAGE (VOLTS) VCE, COLLECTOR–TO–EMITTER VOLTAGE (VOLTS)
Figure 1. Output Characteristics, TJ = 25°C Figure 2. Output Characteristics, TJ = 125°C
VCE , COLLECTOR–TO–EMITTER VOLTAGE (VOLTS)

40 2.2
VGE = 5 V
VCE = 10 V
2.0 IC = 20 A
30
1.8
15 A
20 1.6
TJ = 125°C 25°C 1.4 10 A

10
1.2
0 1.0
1 2 3 4 5 –50 0 50 100 150
VGE, GATE–TO–EMITTER VOLTAGE (VOLTS) TJ, JUNCTION TEMPERATURE (°C)
Figure 3. Transfer Characteristics Figure 4. Collector–to–Emitter Saturation

Voltage versus Junction Temperature
10000 1000
VCE = 0 V TJ = 25°C VCE = 0 V TJ = 25°C
Ciss
1000
C, CAPACITANCE (pF)
C, CAPACITANCE (pF)
100 Ciss
Coss
100
Crss 10
Coss
10
Crss
1.0 1.0
0 25 50 75 100 125 150 175 200 10 100 1000
COLLECTOR–TO–EMITTER VOLTAGE (VOLTS) DRAIN–TO–SOURCE VOLTAGE (VOLTS)
Figure 5. Capacitance Variation Figure 6. High Voltage Capacitance Variation

MGP20N35CL
8 60 60
TOTAL SWITCHING ENERGY LOSSES (mJ)

VGE, GATE–TO–EMITTER VOLTAGE (VOLTS)
Qg VDD = 320 V
VGE = 5 V
50 TJ = 125°C 50
6 IC = 20 A Eoff
SWITCHING TIME ( mS)

40 Td(off) 40
Qgs Qgd
4 30 30
20 20
2 TJ = 25°C
IC = 20 A 10 TF 10
0 0 0
0 10 20 30 40 0 1000 2000 3000 4000 5000
Qg, TOTAL GATE CHARGE (nC) RG, GATE RESISTANCE (OHMS)
Figure 7. Gate–to–Emitter and Figure 8. Total Switching Losses

Collector–to–Emitter Voltage vs Total Charge versus Gate Temperature
50 6 26 6

VCC = 320 V
24 VGE = 5 V
40 Eoff
5 RG = 1000 W
22 L = 200 mH
SWITCHING TIME ( m S)
4 IC = 20 A Td(off)
30
20
Td(off) Eoff
3
20 VDD = 320 V 18
TF VGE = 5 V 2
TJ = 25°C 16
10 IC = 20 A
1 14 TF
0 0 12 4
0 1000 2000 3000 4000 5000 25 50 75 100 125
RG, GATE RESISTANCE (OHMS) TC, CASE TEMPERATURE (°C)
Figure 9. Total Switching Losses Figure 10. Total Switching Losses

versus Gate Resistance versus Case Temperature
25 25 20
VCC = 320 V
VGE = 5 V
RG = 1000 W Eoff 16 3 mH
L = 200 mH
LATCH CURRENT (AMPS)
20 20
TJ = 125°C
12
15 Td(off) 15
10 mH
8.0
10 10
4.0
TF
5 5 0
5 10 15 20 0 25 50 75 100 125
IC, COLLECTOR–TO–EMITTER CURRENT (AMPS) TEMPERATURE (°C)
Figure 11. Total Switching Losses Figure 12. Latch Current versus Temperature
versus Collector Current

MGP20N35CL
1.0
D = 0.5
TRANSIENT THERMAL RESISTANCE

r(t), NORMALIZED EFFECTIVE
0.2
0.1
0.1 P(pk)
0.05 RθJC(t) = r(t) RθJC
D CURVES APPLY FOR POWER
0.02
PULSE TRAIN SHOWN
t1 READ TIME AT t1
0.01 t2 TJ(pk) – TC = P(pk) RθJC(t)
DUTY CYCLE, D = t1/t2
SINGLE PULSE
0.01
1.0E – 05 1.0E – 04 1.0E – 03 1.0E – 02 1.0E – 01 1.0E+00 1.0E+01
t, TIME (s)
Figure 13. Thermal Response

MOTOROLA
Advanced Information MGP20N40CL

SMARTDISCRETES
IGBT 20 AMPERES
Applied to Load 
C
Microprocessors
G
G
C
Rge E

TO–220AB
E

Reversed Collector Current – pulse width t 100 ms ICR 12 Apk
Electrostatic Voltage — Gate–Emitter ESD 3.5 kV
— Junction to Ambient RqJA 62.5
UNCLAMPED INDUCTIVE SWITCHING CHARACTERISTICS

Single Pulse Collector–Emitter Avalanche Energy EAS mJ

MGP20N40CL
OFF CHARACTERISTICS
(IClamp = 10 mA, TJ = –40 to 150°C) 380 405 440
Zero Gate Voltage Collector Current ICES
(VCE = 300 V, VGE = 0 V, TJ = 125°C) — — 1.0 mA
(VCE = 15 V, VGE = 0 V, TJ = 125°C) — — 200 mA
Resistance Gate–Emitter (TJ = –40 to 150°C) RGE 10k 16k 30k W
Gate–Emitter Breakdown Voltage (IG = 2 mA) BVGES 11 13 15 "V
Collector–Emitter Reverse Leakage (VCE = –15 V, TJ = –40 to 150°C) ICES — — — mA
Collector–Emitter Reversed Breakdown Voltage (IE = 75 mA) BVCER 26 40 120 V
Gate Threshold Voltage VGE(th) V
(VCE = VGE, IC = 1 mA) 1.0 1.7 2.4
(VCE = VGE, IC = 1 mA, TJ = 150°C) 0.75 — 1.8
(VGE = 5 V, IC = 5 A) — 1.1 1.4
(VGE = 5 V, IC = 10 A) — 1.4 1.9
(VGE = 5 V, IC = 10 Adc, TJ = 150°C) — 1.4 1.8
Forward Transconductance (VCE u 50 V, IC = 10 A) gfs 10 16 — S
Vd VGE = 0 Vdc,
Vd
Coss — 200 —
f = 1.0 MHz)

Gate–Emitter Charge (VCC = 280 V,
V IC = 20 A,
A
Qgs — 8.0 —
VGE = 5 V)
Gate–Collector Charge Qgd — 20 —
Turn–Off Delay Time ( CC = 320 V, IC = 20 A,
(V td(off) — TBD TBD µs
Fall Time L = 200 mH, RG = 1 KW) tf — TBD TBD
Turn–On Delay Time ((VCC = 14 V, IC = 20 A, td(on) — TBD TBD µs
Rise Time L = 200 mH, RG = 1 KW) tr — TBD TBD

MGP20N40CL
40 40
VGE = 10 V 5V TJ = 25°C VGE = 10 V 5V TJ = 125°C

30 30
4V
4V
20 20
10 10 3V
3V
0 0
0 2 4 6 8 10 0 1 2 3 4 5 6 7 8 9 10

40 2.2
VGE = 5 V
VCE = 10 V
2.0 IC = 20 A
30
1.8
15 A
20 1.6
TJ = 125°C 25°C 1.4 10 A

10
1.2
0 1.0
1 2 3 4 5 –50 0 50 100 150

10000 1000
VCE = 0 V TJ = 25°C VGS = 0 V TJ = 25°C
Ciss
1000
C, CAPACITANCE (pF)
C, CAPACITANCE (pF)
100 Ciss
Coss
100
Crss 10
Coss
10
Crss
1.0 1.0
0 25 50 75 100 125 150 175 200 10 100 1000
COLLECTOR–TO–EMITTER VOLTAGE (VOLTS) DRAIN–TO–SOURCE VOLTAGE (VOLTS)
Figure 5. Capacitance Variation Figure 6. High Voltage Capacitance Variation

MGP20N40CL
8 60 60

Qg VDD = 320 V
VGE = 5 V
50 TJ = 125°C 50
6 IC = 20 A Eoff
SWITCHING TIME ( mS)

40 Td(off) 40
Qgs Qgd
4 30 30
20 20
2 TJ = 25°C
IC = 20 A 10 TF 10
0 0 0
0 10 20 30 40 0 1000 2000 3000 4000 5000
Figure 7. Gate–to–Emitter and Figure 8. Total Switching Losses

Collector–to–Emitter Voltage vs Total Charge versus Gate Temperature
50 6 26 6

VCC = 320 V
24 VGE = 5 V
40 Eoff
5 RG = 1000 W
22 L = 200 mH
4 IC = 20 A Td(off)
30
20
Td(off) Eoff
3
20 VDD = 320 V 18
TF VGE = 5 V 2
TJ = 25°C 16
10 IC = 20 A
1 14 TF
0 0 12 4
0 1000 2000 3000 4000 5000 25 50 75 100 125
Figure 9. Total Switching Losses Figure 10. Total Switching Losses

versus Gate Resistance versus Case Temperature
25 25 20
VCC = 320 V
VGE = 5 V
RG = 1000 W Eoff 16 3 mH
L = 200 mH
LATCH CURRENT (AMPS)
20 20
TJ = 125°C
12
15 Td(off) 15
10 mH
8.0
10 10
4.0
TF
5 5 0
5 10 15 20 0 25 50 75 100 125
IC, COLLECTOR–TO–EMITTER CURRENT (AMPS) TEMPERATURE (°C)
Figure 11. Total Switching Losses Figure 12. Latch Current versus Temperature
versus Collector Current

MGP20N40CL
1.0
D = 0.5

0.2
0.1
0.1 P(pk)
0.02
PULSE TRAIN SHOWN
t1 READ TIME AT t1
SINGLE PULSE
0.01
1.0E – 05 1.0E – 04 1.0E – 03 1.0E – 02 1.0E – 01 1.0E+00 1.0E+01
t, TIME (s)

MOTOROLA
Designer's  Data Sheet MGW12N120

Insulated Gate Bipolar Transistor Motorola Preferred Device
N–Channel Enhancement–Mode Silicon Gate
This Insulated Gate Bipolar Transistor (IGBT) uses an advanced IGBT IN TO–247
termination scheme to provide an enhanced and reliable high 12 A @ 90°C
voltage–blocking capability. Short circuit rated IGBT’s are specifi- 20 A @ 25°C
cally suited for applications requiring a guaranteed short circuit 1200 VOLTS
withstand time such as Motor Control Drives. Fast switching SHORT CIRCUIT RATED
characteristics result in efficient operation at high frequencies.
• Industry Standard High Power TO–247 Package with
Isolated Mounting Hole
• High Speed Eoff: 160 mJ/A typical at 125°C
• High Short Circuit Capability – 10 ms minimum
• Robust High Voltage Termination
C
G
C
G E
CASE 340F–03, Style 4

TO–247AE

Collector–Emitter Voltage VCES 1200 Vdc
Collector–Gate Voltage (RGE = 1.0 MΩ) VCGR 1200 Vdc
Gate–Emitter Voltage — Continuous VGE ± 20 Vdc
Collector Current — Continuous @ TC = 25°C IC25 20 Adc
Collector Current — Continuous @ TC = 90°C IC90 12
Collector Current — Repetitive Pulsed Current (1) ICM 40 Apk
Total Power Dissipation @ TC = 25°C PD 123 Watts
Derate above 25°C 0.98 W/°C
Operating and Storage Junction Temperature Range TJ, Tstg – 55 to 150 °C

Short Circuit Withstand Time tsc 10 ms
(VCC = 720 Vdc, VGE = 15 Vdc, TJ = 125°C, RG = 20 Ω)
Thermal Resistance — Junction to Case – IGBT RθJC 1.0 °C/W
Thermal Resistance — Junction to Ambient RθJA 45
Mounting Torque, 6–32 or M3 screw 10 lbfSin (1.13 NSm)
(1) Pulse width is limited by maximum junction temperature. Repetitive rating.
Designer’s Data for “Worst Case” Conditions — The Designer’s Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves — representing boundaries on device characteristics — are given to facilitate “worst case” design.
Preferred devices are Motorola recommended choices for future use and best overall value.
REV 1

MGW12N120
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted)
OFF CHARACTERISTICS
(VGE = 0 Vdc, IC = 25 µAdc) 1200 — —
Temperature Coefficient (Positive) — 870 — mV/°C
Emitter–to–Collector Breakdown Voltage (VGE = 0 Vdc, IEC = 100 mAdc) BVECS 25 — — Vdc
Zero Gate Voltage Collector Current ICES µAdc
(VCE = 1200 Vdc, VGE = 0 Vdc) — — 100
(VCE = 1200 Vdc, VGE = 0 Vdc, TJ = 125°C) — — 2500
Gate–Body Leakage Current (VGE = ± 20 Vdc, VCE = 0 Vdc) IGES — — 250 nAdc
Collector–to–Emitter On–State Voltage VCE(on) Vdc
(VGE = 15 Vdc, IC = 5.0 Adc) — 2.51 3.37
(VGE = 15 Vdc, IC = 5.0 Adc, TJ = 125°C) — 2.36 —
(VGE = 15 Vdc, IC = 10 Adc) — 3.21 4.42
Gate Threshold Voltage VGE(th) Vdc
(VCE = VGE, IC = 1.0 mAdc) 4.0 6.0 8.0
Threshold Temperature Coefficient (Negative) — 10 — mV/°C
Forward Transconductance (VCE = 10 Vdc, IC = 10 Adc) gfe — 12 — Mhos
Input Capacitance Cies — 930 — pF
Vd VGE = 0 Vdc,
Vd
Coes — 126 —
f = 1.0 MHz)
Transfer Capacitance Cres — 16 —

Turn–On Delay Time td(on) — 74 — ns
Rise Time (VCC = 720 Vdc, IC = 10 Adc, tr — 83 —
Vd L = 300 mH
VGE = 15 Vdc,
Turn–Off Delay Time td(off) — 76 —
RG = 20 Ω, TJ = 2525°C)
C)
Fall Time Energy losses include “tail” tf — 231 —
Turn–Off Switching Loss Eoff — 0.55 1.33 mJ
Vd L = 300 mH
VGE = 15 Vdc,
RG = 20 Ω, TJ = 125°C)
125 C)
Turn–Off Switching Loss Eoff — 1.49 — mJ
Gate Charge QT — 31 — nC
(VCC = 720 Vdc,
Vd IC = 10 Adc,
Ad
Q1 — 13 —
VGE = 15 Vdc)
Q2 — 14 —
INTERNAL PACKAGE INDUCTANCE
Internal Emitter Inductance LE nH
(Measured from the emitter lead 0.25″ from package to emitter bond pad) — 13 —

MGW12N120
40 40
TJ = 25°C VGE = 20 V TJ = 125°C VGE = 20 V
IC, COLLECTOR CURRENT (AMPS)

30 30
17.5 V
17.5 V
20 15 V 20
15 V
12.5 V 12.5 V
10 10
7.5 V 10 V
0 0
0 1 2 3 4 5 6 7 8 0 1 2 3 4 5 6 7 8

24 3.8
VCE = 10 V
250 µs PULSE WIDTH 3.6 IC = 10 A
20
3.4
16 3.2
7.5 A
3.0
12 TJ = 125°C
2.8
8 25°C 2.6 5A
2.4
4 VGE = 15 V
2.2
250 µs PULSE WIDTH
0 2
5 7 9 11 13 15 – 50 0 50 100 150

1600 16
VCE = 0 V QT
1200 12
C, CAPACITANCE (pF)
Cies Q1 Q2
800 8
400 4
Coes TJ = 25°C
IC = 10 A
Cres
VGE = 15 V
0 0
0 5 10 15 20 25 0 5 10 15 20 25 30 35
GATE–TO–EMITTER OR COLLECTOR–TO–EMITTER VOLTAGE (VOLTS) Qg, TOTAL GATE CHARGE (nC)
Figure 5. Capacitance Variation Figure 6. Gate–to–Emitter Voltage versus

Total Charge

MGW12N120
3 3

VCC = 720 V 2.8 VCC = 720 V
VGE = 15 V 2.6 VGE = 15 V
IC = 10 A
TJ = 125°C 2.4 RG = 20 Ω
2.5 2.2 IC = 10 A
2
1.8
1.6
2 7.5 A
7.5 A 1.4
1.2
1 5A
1.5 0.8
0.6
5A
0.4
0.2
1 0
10 20 30 40 50 25 50 75 100 125 150
Figure 7. Total Switching Losses versus Figure 8. Total Switching Losses versus
Gate Resistance Case Temperature
I , INSTANTANEOUS FORWARD CURRENT (AMPS)

2.4 25
VCC = 720 V
2.2 VGE = 15 V
RG = 20 Ω 20
2 TJ = 125°C
15 TJ = 125°C
1.8
1.6 10
TJ = 25°C
1.4
5
1.2
1 0
F
5 6 7 8 9 10 0 1 2 3 4
IC, COLLECTOR–TO–EMITTER CURRENT (AMPS) VFM, FORWARD VOLTAGE DROP (VOLTS)
Figure 9. Total Switching Losses versus Figure 10. Maximum Forward Drop versus
Collector–to–Emitter Current Instantaneous Forward Current
100
IC, COLLECTOR–TO–EMITTER CURRENT (A)
10
VGE = 15 V
RGE = 20 Ω
TJ ≤ 125°C
0.1
1 10 100 1000 10000
VCE, COLLECTOR–TO–EMITTER VOLTAGE (VOLTS)
Figure 11. Reverse Biased

Safe Operating Area

MGW12N120
1.0
D = 0.5
0.2
0.1
0.05
0.1 P(pk)
0.01 PULSE TRAIN SHOWN
SINGLE PULSE t1 READ TIME AT t1
t2 TJ(pk) – TC = P(pk) RθJC(t)
0.01
1.0E–05 1.0E–04 1.0E–03 1.0E–02 1.0E–01 1.0E+00 1.0E+01
t, TIME (s)

MOTOROLA
 Data Sheet
Designer's
MGW12N120D
with Anti-Parallel Diode

N–Channel Enhancement–Mode Silicon Gate IGBT & DIODE IN TO–247
12 A @ 90°C
This Insulated Gate Bipolar Transistor (IGBT) is co–packaged
20 A @ 25°C
with a soft recovery ultra–fast rectifier and uses an advanced
1200 VOLTS
termination scheme to provide an enhanced and reliable high
SHORT CIRCUIT RATED
voltage–blocking capability. Short circuit rated IGBT’s are specifi-
cally suited for applications requiring a guaranteed short circuit
withstand time such as Motor Control Drives. Fast switching
Co–packaged IGBT’s save space, reduce assembly time and cost.
C
• High Speed Eoff: 160 mJ per Amp typical at 125°C
• Soft Recovery Free Wheeling Diode is included in the package
G
• Robust High Voltage Termination G
• Robust RBSOA C
E
E

TO–247AE

— Continuous @ TC = 90°C IC90 12
— Repetitive Pulsed Current (1) ICM 40 Apk

— Junction to Case – Diode RθJC 1.4
— Junction to Ambient RθJA 45
REV 1

MGW12N120D
OFF CHARACTERISTICS
(VGE = 0 Vdc, IC = 25 µAdc) 1200 — —
(VCE = 1200 Vdc, VGE = 0 Vdc) — — 100
(VGE = 15 Vdc, IC = 5.0 Adc) — 2.71 3.37
(VGE = 15 Vdc, IC = 5.0 Adc, TJ = 125°C) — 3.78 —
(VGE = 15 Vdc, IC = 10 Adc) — 3.72 4.42
(VCE = VGE, IC = 1.0 mAdc) 4.0 6.0 8.0
Vd VGE = 0 Vdc,
Vd
Coes — 126 —
f = 1.0 MHz)

(VCC = 720 Vdc
Vdc, IC = 10 Adc
Adc,
Rise Time VGE = 15 Vdc,, L = 300 mH tr — 83 —
Turn–Off Delay Time RG = 20 Ω, TJ = 25°C) td(off) — 76 —
Energy losses include “tail”
tail
Fall Time tf — 231 —
Turn–On Switching Loss Eon — 1.21 1.88
Total Switching Loss Ets — 1.76 3.21
(VCC = 720 Vdc
Vdc, IC = 10 Adc
Adc,
tail
Turn–On Switching Loss Eon — 2.37 —
Total Switching Loss Ets — 3.86 —
(VCC = 720 Vdc,
Vd IC = 10 Adc,
Ad
Q1 — 13 —
VGE = 15 Vdc)
Q2 — 12 —
DIODE CHARACTERISTICS
Diode Forward Voltage Drop VFEC Vdc
(IEC = 5.0 Adc) — 2.26 3.32
(IEC = 5.0 Adc, TJ = 125°C) — 1.37 —
(IEC = 10 Adc) — 2.86 4.18
(1) Pulse Test: Pulse Width ≤ 300 µs, Duty Cycle ≤ 2%. (continued)

MGW12N120D
ELECTRICAL CHARACTERISTICS — continued (TJ = 25°C unless otherwise noted)
DIODE CHARACTERISTICS — continued
Reverse Recovery Time trr — 116 — ns
((IF = 10 Adc, VR = 720 Vdc, ta — 69 —

dIF/dt = 100 A/µs) tb — 47 —
Reverse Recovery Stored Charge QRR — 0.36 — µC
((IF = 10 Adc, VR = 720 Vdc, ta — 149 —

dIF/dt = 100 A/µs, TJ = 125°C) tb — 85 —
40 40
TJ = 25°C VGE = 20 V TJ = 125°C VGE = 20 V

30 30
17.5 V
17.5 V
20 15 V 20
15 V
12.5 V 12.5 V
10 10
7.5 V 10 V
0 0
0 1 2 3 4 5 6 7 8 0 1 2 3 4 5 6 7 8

24 3.8
VCE = 10 V
250 µs PULSE WIDTH 3.6 IC = 10 A
20
3.4
16 3.2
7.5 A
3.0
12 TJ = 125°C
2.8
8 25°C 2.6 5A
2.4
4 VGE = 15 V
2.2
250 µs PULSE WIDTH
0 2
5 7 9 11 13 15 – 50 0 50 100 150


MGW12N120D
10000 1000
TJ = 25°C Cies
VGE = 0 V
Cies
C, CAPACITANCE (pF)
C, CAPACITANCE (pF)
1000
Coes 100
Coes
100 Cres
Cres
TJ = 25°C
10 10
0 5 10 15 20 25 50 100 150 200
GATE–TO–EMITTER OR COLLECTOR–TO–EMITTER VOLTAGE (VOLTS) COLLECTOR–TO–EMITTER VOLTAGE (VOLTS)
Figure 5. Capacitance Variation Figure 5b. High Voltage Capacitance

Variation
16 3

QT VCC = 720 V
VGE = 15 V
IC = 10 A
TJ = 125°C
12 2.5
Q1 Q2
8 2
7.5 A
TJ = 25°C
4 1.5
IC = 20 A
5A
0 1
0 20 40 60 80 10 20 30 40 50
Figure 6. Gate–to–Emitter and Figure 7. Total Switching Losses versus

Collector–to–Emitter Voltage versus Total Charge Gate Resistance
3 2.4
2.8 VCC = 720 V VCC = 720 V

2.6 VGE = 15 V 2.2 VGE = 15 V
2.4 RG = 20 Ω RG = 20 Ω
2.2 IC = 10 A 2 TJ = 125°C
2
1.8 1.8
1.6
1.4 7.5 A
1.6
1.2
1 5A
0.8 1.4
0.6
0.4 1.2
0.2
0 1
25 50 75 100 125 150 5 6 7 8 9 10
TC, CASE TEMPERATURE (°C) IC, COLLECTOR–TO–EMITTER CURRENT (AMPS)
Case Temperature Collector–to–Emitter Current

MGW12N120D

25 100

20
10
15 TJ = 125°C
10
TJ = 25°C 1
5 VGE = 15 V
RGE = 20 Ω
TJ = 125°C
0 0.1
F
0 1 2 3 4 1 10 100 1000
VFM, FORWARD VOLTAGE DROP (VOLTS) VCE, COLLECTOR–TO–EMITTER VOLTAGE (VOLTS)
Figure 10. Maximum Forward Drop versus Figure 11. Reverse Biased
Instantaneous Forward Current Safe Operating Area
1.0
D = 0.5
0.2
0.1
0.05
0.1 P(pk)
0.01
1.0E–05 1.0E–04 1.0E–03 1.0E–02 1.0E–01 1.0E+00 1.0E+01
t, TIME (s)

MOTOROLA
 Data Sheet
Designer's
MGW20N60D

20 A @ 90°C
32 A @ 25°C
600 VOLTS
SHORT CIRCUIT RATED
characteristics result in efficient operations at high frequencies.
C
G
• Robust RBSOA C
E
E

TO–247AE
MAXIMUM RATINGS (TC = 25°C unless otherwise noted)


(1) Pulse width is limited by maximum junction temperature.

MGW20N60D
OFF CHARACTERISTICS
(VGE = 0 Vdc, IC = 250 µAdc) 600 — —
(VCE = 600 Vdc, VGE = 0 Vdc) — — 100
(VGE = 15 Vdc, IC = 10 Adc) — 2.30 2.85
(VGE = 15 Vdc, IC = 10 Adc, TJ = 125°C) — 2.20 —
(VGE = 15 Vdc, IC = 20 Adc) — 2.85 3.65
(VCE = VGE, IC = 1 mAdc) 4.0 6.0 8.0
Vd VGE = 0 Vdc,
Vd
Coes — 165 —
f = 1.0 MHz)

(VCC = 360 Vdc
Vdc, IC = 20 Adc
Adc,
tail
(VCC = 360 Vdc
Vdc, IC = 20 Adc
Adc,
tail
(VCC = 360 Vdc,
Vd IC = 20 Adc,
Ad
Q1 — 19 —
VGE = 15 Vdc)
Q2 — 27 —
(IEC = 10 Adc) — 1.50 1.90
(IEC = 10 Adc, TJ = 125°C) — 1.30 —
(IEC = 20 Adc) — 1.70 2.15

MGW20N60D
((IF = 20 Adc, VR = 360 Vdc, ta — 70 —

dIF/dt = 200 A/µs) tb — 47 —
((IF = 20 Adc, VR = 360 Vdc, ta — 98 —

dIF/dt = 200 A/µs, TJ = 125°C) tb — 68 —
60 60
TJ = 25°C VGE = 20 V 12.5 V TJ = 125°C VGE = 20 V 12.5 V
17.5 V IC, COLLECTOR CURRENT (AMPS) 17.5 V

15 V 15 V
40 40
10 V
10 V
20 20
0 0
0 2 4 6 8 0 2 4 6 8

40 3.2
VGE = 15 V
VCE = 100 V
80 µs PULSE WIDTH IC = 20 A
5 µs PULSE WIDTH
30
2.8
TJ = 125°C
15 A
20
25°C
2.4
10 A
10
0 2
5 6 7 8 9 10 11 – 50 0 50 100 150


MGW20N60D
4000 16

VCE = 0 V TJ = 25°C QT
3200
12
C, CAPACITANCE (pF)
Cies
2400 Q1 Q2
8
1600
TJ = 25°C
4
800 Coes IC = 20 A
Cres
0 0
0 5 10 15 20 25 0 20 40 60 80

Total Charge
4 4

VCC = 360 V VCC = 360 V
VGE = 15 V 3.5 VGE = 15 V
IC = 20 A
3.2 TJ = 125°C RG = 20 Ω
3
2.4 15 A 2.5
IC = 20 A
1.6 10 A 2
15 A
1.5
0.8 10 A
1
0 0.5
10 20 30 40 50 0 25 50 75 100 125 150
RG, GATE RESISTANCE (OHMS) TJ, JUNCTION TEMPERATURE (°C)
Gate Resistance Junction Temperature
3 1.6
VCC = 360 V VCC = 360 V

VGE = 15 V
TURN–OFF ENERGY LOSSES (mJ)
VGE = 15 V
2.5
RG = 20 Ω TJ = 125°C IC = 20 A
TJ = 125°C
2 1.2
1.5 15 A
1 0.8
10 A
0.5
0 0.4
0 5 10 15 20 10 20 30 40 50
IC, COLLECTOR–TO–EMITTER CURRENT (AMPS) RG, GATE RESISTANCE (OHMS)
Figure 9. Total Switching Losses versus Figure 10. Turn–Off Losses versus
Collector–to–Emitter Current Gate Resistance

MGW20N60D
2 1.2
VCC = 360 V VCC = 360 V
TURN–OFF ENERGY LOSSES (mJ) VGE = 15 V

VGE = 15 V
RG = 20 Ω RG = 20 Ω
1.5 TJ = 125°C
0.8
1
IC = 20 A
15 A
0.4
10 A
0.5
0 0
0 25 50 75 100 125 150 0 5 10 15 20
TJ, JUNCTION TEMPERATURE (°C) IC, COLLECTOR–TO–EMITTER CURRENT (AMPS)
Figure 11. Turn–Off Losses versus Figure 12. Turn–Off Losses versus
Junction Temperature Collector–to–Emitter Current
i F, INSTANTANEOUS FORWARD CURRENT (AMPS)
100 100

10 10
TJ = 125°C
TJ = 25°C
1 1
VGE = 15 V
RGE = 20 Ω
TJ = 125°C
0.1 0.1
0 0.4 0.8 1.2 1.6 2 1 10 100 1000
Figure 13. Typical Diode Forward Drop versus Figure 14. Reverse Biased Safe
Instantaneous Forward Current Operating Area

MOTOROLA
Designer's  Data Sheet MGW20N120

withstand time. Fast switching characteristics result in efficient SHORT CIRCUIT RATED
operation at high frequencies.
C
G G
C
E

TO–247AE

Gate–Emitter Voltage — Continuous VGE ±20 Vdc


MGW20N120
OFF CHARACTERISTICS
(VGE = 0 Vdc, IC = 25 µAdc) 1200 — —
(VCE = 1200 Vdc, VGE = 0 Vdc) — — 100
(VGE = 15 Vdc, IC = 10 Adc) — 3.00 3.54
(VGE = 15 Vdc, IC = 10 Adc, TJ = 125°C) — 2.36 —
(VGE = 15 Vdc, IC = 20 Adc) — 2.90 4.99
(VCE = VGE, IC = 1.0 mAdc) 4.0 6.0 8.0
Vd VGE = 0 Vdc,
Vd
Coes — 122 —
f = 1.0 MHz)

Vd L = 300 mH
VGE = 15 Vdc,
RG = 20 Ω, TJ = 2525°C)
C)
Vd L = 300 mH
VGE = 15 Vdc,
RG = 20 Ω, TJ = 125°C)
125 C)
(VCC = 720 Vdc,
Vd IC = 20 Adc,
Ad
Q1 — 21 —
VGE = 15 Vdc)
Q2 — 25 —

MGW20N120
60 60
TJ = 25°C VGE = 20 V TJ = 125°C VGE = 20 V 15 V
15 V

50 17.5 V 50
17.5 V
40 40
12.5 V 12.5 V
30 30
20 20 10 V
10 10 V 10
0 0
0 2 4 6 8 0 2 4 6 8

60 4
VCE = 10 V VGE = 15 V
250 µs PULSE WIDTH 250 µs PULSE WIDTH
TJ = 125°C
IC = 20 A
40 3
15 A
10 A
20 2
25°C
0 1
5 6 7 8 9 10 11 12 13 14 15 – 50 0 50 100 150

10000 16
14
Cies
12
C, CAPACITANCE (pF)
1000
10
Coes Q1 Q2
8
100 Cres 6
TJ = 25°C
4
IC = 20 A
2
10 0
0 5 10 15 20 25 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70

Total Charge

MGW20N120
6 5

VCC = 720 V VCC = 720 V
VGE = 15 V VGE = 15 V
5 IC = 25 A
TJ = 25°C 4 RG = 20 Ω IC = 20 A
4
15 A
3 15 A
3
10 A 2
2
10 A
1 1
0 0
10 15 20 25 30 35 40 45 50 25 50 75 100 125 150

5 40
VCC = 720 V
VGE = 15 V
RG = 20 Ω
4 TJ = 125°C 30
TJ = 125°C
3 20
TJ = 25°C
2 10
1 0
10 12 14 16 18 20
F
0 1 2 3 4 5
Figure 9. Turn–Off Losses versus Figure 10. Maximum Forward Drop versus
100
10
VGE = 15 V
RGE = 20 Ω
TJ = 125°C
0.1
1 10 100 1000

Safe Operating Area

MGW20N120
1.0
D = 0.5
0.2
0.1
0.05
0.1 P(pk)
0.01
1.0E–05 1.0E–04 1.0E–03 1.0E–02 1.0E–01 1.0E+00 1.0E+01
t, TIME (s)

MOTOROLA
 Data Sheet
Designer's
Insulated Gate Bipolar Transistor MGW30N60

Motorola Preferred Device
• Robust RBSOA C
G G
C
E

TO–247AE



MGW30N60
OFF CHARACTERISTICS
(VGE = 0 Vdc, IC = 250 µAdc) 600 — —
(VCE = 600 Vdc, VGE = 0 Vdc) — — 100
(VGE = 15 Vdc, IC = 15 Adc) — 2.20 2.90
(VGE = 15 Vdc, IC = 15 Adc, TJ = 125°C) — 2.10 —
(VGE = 15 Vdc, IC = 30 Adc) — 2.60 3.45
(VCE = VGE, IC = 1 mAdc) 4.0 6.0 8.0
Vd VGE = 0 Vdc,
Vd
Coes — 275 —
f = 1.0 MHz)

Vd L = 300 mH
VGE = 15 Vdc,
RG = 20 Ω, TJ = 2525°C)
C)
Vd L = 300 mH
VGE = 15 Vdc,
RG = 20 Ω, TJ = 125°C)
125 C)
(VCC = 360 Vdc,
Vd IC = 30 Adc,
Ad
Q1 — 30 —
VGE = 15 Vdc)
Q2 — 45 —

MGW30N60
60 60

17.5 V 17.5 V
10 V 10 V
40 15 V 40 15 V
20 20
0 0
0 1 2 3 4 5 0 1 2 3 4 5

60 3
VCE = 100 V VGE = 15 V
IC = 30 A
TJ = 125°C
40 2.6 22.5 A
25°C 15 A
20 2.2
0 1.8
5 6 7 8 9 10 11 – 50 0 50 100 150

7200 16
TJ = 25°C QT
6400
VCE = 0 V
5600 12
C, CAPACITANCE (pF)
4800 Cies
4000
8 Q1 Q2
3200
2400
4 TJ = 25°C
1600 Coes IC = 30 A
800
Cres
0 0
0 5 10 15 20 25 0 20 40 60 80 100 120 140

Total Charge

MGW30N60
3 3
VCC = 360 V VCC = 360 V

2.5 VGE = 15 V 2.5 VGE = 15 V
TJ = 125°C RG = 20 Ω
IC = 30 A
2 2
1.5 20 A 1.5 IC = 30 A
1 1 20 A
10 A
0.5 0.5 10 A
0 0
10 20 30 40 50 0 25 50 75 100 125 150

2 100

VCC = 360 V
VGE = 15 V
1.6 RG = 20 Ω
TJ = 125°C
10
1.2
0.8
1
0.4 VGE = 15 V
RGE = 20 Ω
TJ = 125°C
0 0.1
0 5 10 15 20 25 30 1 10 100 1000
IC, COLLECTOR–TO–EMITTER CURRENT (AMPS) VCE, COLLECTOR–TO–EMITTER VOLTAGE (VOLTS)
Figure 9. Turn–Off Losses versus Figure 10. Reverse Biased Safe

Collector–to–Emitter Current Operating Area

MOTOROLA
 Data Sheet
Designer's
MGY20N120D

20 A @ 90°C
28 A @ 25°C
1200 VOLTS
SHORT CIRCUIT RATED
• Industry Standard High Power TO–264 Package (TO–3PBL) C
• Robust RBSOA
G
C
E E
CASE 340G–02, Style 5

TO–264



MGY20N120D
OFF CHARACTERISTICS
(VGE = 0 Vdc, IC = 25 µAdc) 1200 — —
(VCE = 1200 Vdc, VGE = 0 Vdc) — — 100
(VGE = 15 Vdc, IC = 10 Adc) — 3.00 3.54
(VGE = 15 Vdc, IC = 10 Adc, TJ = 125°C) — 2.36 —
(VGE = 15 Vdc, IC = 20 Adc) — 2.90 4.99
(VCE = VGE, IC = 1.0 mAdc) 4.0 6.0 8.0
Vd VGE = 0 Vdc,
Vd
Coes — 208 —
f = 1.0 MHz)

(VCC = 720 Vdc
Vdc, IC = 20 Adc
Adc,
Rise Time VGE = 15 Vdc, L = 300 mH tr — 103 —
tail
(VCC = 720 Vdc
Vdc, IC = 20 Adc
Adc,
tail
Vd IC = 20 Adc,
(VCC = 720 Vdc, Ad
Q1 — 20 —
VGE = 15 Vdc)
Q2 — 27 —
(IEC = 10 Adc) — 2.92 3.59
(IEC = 10 Adc, TJ = 125°C) — 1.73 —
(IEC = 20 Adc) — 3.67 4.57

MGY20N120D
((IF = 20 Adc, VR = 720 Vdc, ta — 74 —

dIF/dt = 150 A/µs) tb — 40 —
((IF = 20 Adc, VR = 720 Vdc, ta — 149 —

dIF/dt = 150 A/µs, TJ = 125°C) tb — 75 —
60 60
TJ = 25°C VGE = 20 V TJ = 125°C VGE = 20 V 15 V
15 V
50 IC, COLLECTOR CURRENT (AMPS) 50

17.5 V 17.5 V
40 40
12.5 V 12.5 V
30 30
20 20 10 V
10 10 V 10
0 0
0 2 4 6 8 0 2 4 6 8

60 4
VCE = 10 V VGE = 15 V
TJ = 125°C
IC = 20 A
40 3
15 A
10 A
20 2
25°C
0 1
5 6 7 8 9 10 11 12 13 14 15 – 50 0 50 100 150


MGY20N120D
10000 10000
TJ = 25°C VGE = 0 V TJ = 25°C
Cies Cies
C, CAPACITANCE (pF)
C, CAPACITANCE (pF)
1000 1000
Coes
Coes
100 Cres 100
Cres
10 10
0 5 10 15 20 25 50 100 150 200

Variation
16 6

QT VCC = 720 V
14 VGE = 15 V
5 IC = 25 A
TJ = 25°C
12
4
10 15 A
Q1 Q2
8 3
10 A
6
2
TJ = 25°C
4
IC = 20 A
1
2
0 0
0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 10 15 20 25 30 35 40 45 50
Figure 6. Gate–to–Emitter and Collector–to–Emitter Figure 7. Total Switching Losses versus

Voltage versus Total Charge Gate Resistance
5 5
VCC = 720 V VCC = 720 V

VGE = 15 V VGE = 15 V
4 RG = 20 Ω IC = 20 A RG = 20 Ω
4 TJ = 125°C
3 15 A
3
2
10 A
2
1
0 1
25 50 75 100 125 150 10 12 14 16 18 20

MGY20N120D

40 100

30
TJ = 125°C 10
20
TJ = 25°C
1
10
VGE = 15 V
RGE = 20 Ω
TJ = 125°C
0 0.1
F
0 1 2 3 4 5 1 10 100 1000
1.0
D = 0.5
0.2
0.1
0.05
0.1 P(pk)
0.01
1.0E–05 1.0E–04 1.0E–03 1.0E–02 1.0E–01 1.0E+00 1.0E+01
t, TIME (s)

MOTOROLA
Designer's  Data Sheet MGY25N120

withstand time. Fast switching characteristics result in efficient SHORT CIRCUIT RATED
operation at high frequencies.
• Industry Standard High Power TO–264 Package (TO–3PBL)
G
C
G E
E
TO–264


REV 1

MGY25N120
OFF CHARACTERISTICS
(VGE = 0 Vdc, IC = 25 µAdc) 1200 — —
(VCE = 1200 Vdc, VGE = 0 Vdc) — — 100
(VGE = 15 Vdc, IC = 12.5 Adc) — 2.37 3.24
(VGE = 15 Vdc, IC = 12.5 Adc, TJ = 125°C) — 2.15 —
(VGE = 15 Vdc, IC = 25 Adc) — 2.98 4.19
(VCE = VGE, IC = 1.0 mAdc) 4.0 6.0 8.0
Vd VGE = 0 Vdc,
Vd
Coes — 181 —
f = 1.0 MHz)

Vd L = 300 mH
VGE = 15 Vdc,
RG = 20 Ω, TJ = 2525°C)
C)
Vd L = 300 mH
VGE = 15 Vdc,
RG = 20 Ω, TJ = 125°C)
125 C)
(VCC = 720 Vdc,
Vd IC = 25 Adc,
Ad
Q1 — 31 —
VGE = 15 Vdc)
Q2 — 40 —

MGY25N120
75 75

15 V
60 60 15 V
45 12.5 V 45 12.5 V
30 30
10 V 10 V
15 15
0 0
0 1 2 3 4 5 6 7 8 0 1 2 3 4 5 6 7 8

70 4
VCE = 10 V VGE = 15 V
60
TJ = 125°C IC = 20 A
50
3 15 A
40
10 A
30
2
20
25°C
10
0 1
4 6 8 10 12 14 16 – 50 0 50 100 150

10000 16
14
Cies
12
C, CAPACITANCE (pF)
1000
10 Q1 Q2
Coes
8
100 6
Cres
TJ = 25°C
4
IC = 25 A
2
10 0
0 5 10 15 20 25 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70

Total Charge

MGY25N120
6 7

IC = 25 A VCC = 720 V
5.5 6 VGE = 15 V
RG = 20 Ω
5 VCC = 720 V
VGE = 15 V 5 IC = 25 A
4.5 TJ = 125°C
IC = 25 A 4
4 15 A
3 15 A
3.5
2
3
10 A 10 A
2.5 1
2 0
10 20 30 40 50 25 50 75 100 125 150

7 50
VCC = 720 V
6 VGE = 15 V
RG = 20 Ω 40
5 TJ = 125°C
TJ = 125°C
4 30
TJ = 25°C
3 20
2
10
1
0 0
F
0 5 10 15 20 25 0 1 2 3 4 5
Figure 9. Turn–Off Losses versus Figure 10. Maximum Forward Drop versus
100
10
VGE = 15 V
RGE = 20 Ω
TJ = 125°C
0.1
1 10 100 1000

Safe Operating Area

MGY25N120
1.0
D = 0.5
0.2
0.1
0.05
0.1 P(pk)
0.01
1.0E–05 1.0E–04 1.0E–03 1.0E–02 1.0E–01 1.0E+00 1.0E+01
t, TIME (s)

MOTOROLA
 Data Sheet
Designer's
MGY25N120D

25 A @ 90°C
38 A @ 25°C
1200 VOLTS
SHORT CIRCUIT RATED
C
G
• Robust RBSOA
G
E C
E

TO–264


REV 1

MGY25N120D
OFF CHARACTERISTICS
(VGE = 0 Vdc, IC = 25 µAdc) 1200 — —
(VCE = 1200 Vdc, VGE = 0 Vdc) — — 100
(VGE = 15 Vdc, IC = 12.5 Adc) — 2.37 3.24
(VGE = 15 Vdc, IC = 12.5 Adc, TJ = 125°C) — 2.15 —
(VGE = 15 Vdc, IC = 25 Adc) — 2.98 4.19
(VCE = VGE, IC = 1.0 mAdc) 4.0 6.0 8.0
Vd VGE = 0 Vdc,
Vd
Coes — 198 —
f = 1.0 MHz)

(VCC = 720 Vdc
Vdc, IC = 25 Adc
Adc,
tail
(VCC = 720 Vdc
Vdc, IC = 25 Adc
Adc,
tail
Vd IC = 25 Adc,
(VCC = 720 Vdc, Ad
Q1 — 22 —
VGE = 15 Vdc)
Q2 — 25 —
(IEC = 12.5 Adc) — 2.89 3.50
(IEC = 12.5 Adc, TJ = 125°C) — 1.75 —
(IEC = 25 Adc) — 3.65 4.45

MGY25N120D
((IF = 25 Adc, VR = 720 Vdc, ta — 71 —

dIF/dt = 150 A/µs) tb — 43 —
((IF = 25 Adc, VR = 720 Vdc, ta — 165 —

dIF/dt = 150 A/µs, TJ = 125°C) tb — 61 —
75 75
15 V
60 60 15 V
45 12.5 V 45 12.5 V
30 30
10 V 10 V
15 15
0 0
0 1 2 3 4 5 6 7 8 0 1 2 3 4 5 6 7 8

70 4
VCE = 10 V VGE = 15 V
60
TJ = 125°C IC = 20 A
50
3 15 A
40
10 A
30
2
20
25°C
10
0 1
4 6 8 10 12 14 16 – 50 0 50 100 150


MGY25N120D
10000 10000
TJ = 25°C VGE = 0 V TJ = 25°C
Cies Cies
C, CAPACITANCE (pF)
C, CAPACITANCE (pF)
1000 1000
Coes
Coes
100 Cres 100
Cres
10 10
0 5 10 15 20 25 50 100 150 200

Variation
16 6

QT IC = 25 A
14 5.5
12 5 VCC = 720 V
VGE = 15 V
10 Q1 Q2 4.5 TJ = 125°C
IC = 25 A
8 4 15 A
6 3.5
TJ = 25°C
4 3
IC = 25 A 10 A
2 2.5
0 2
0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 10 20 30 40 50
Figure 6. Gate–to–Emitter and Collector–to–Emitter Figure 7. Total Switching Losses versus

Voltage versus Total Charge Gate Resistance
7 7
VCC = 720 V VCC = 720 V

6 VGE = 15 V 6 VGE = 15 V
RG = 20 Ω RG = 20 Ω
5 5 TJ = 125°C
IC = 25 A
4 4
3 15 A 3
2 2
10 A
1 1
0 0
25 50 75 100 125 150 0 5 10 15 20 25


MGY25N120D

50 100

40
10
TJ = 125°C
30
TJ = 25°C
20
1
10 VGE = 15 V
RGE = 20 Ω
TJ = 125°C
0 0.1
F
0 1 2 3 4 5 1 10 100 1000
1.0
D = 0.5
0.2
0.1
0.05
0.1 P(pk)
0.01
1.0E–05 1.0E–04 1.0E–03 1.0E–02 1.0E–01 1.0E+00 1.0E+01
t, TIME (s)

MOTOROLA
 Data Sheet
Designer's
MGY30N60D

30 A @ 90°C
50 A @ 25°C
600 VOLTS
SHORT CIRCUIT RATED
• Industry Standard High Power TO–264 Package (TO–3PBL) C
• Robust RBSOA
G
C
E E

TO–264



MGY30N60D
OFF CHARACTERISTICS
(VGE = 0 Vdc, IC = 250 µAdc) 600 — —
(VCE = 600 Vdc, VGE = 0 Vdc) — — 100
(VGE = 15 Vdc, IC = 15 Adc) — 2.20 2.90
(VGE = 15 Vdc, IC = 15 Adc, TJ = 125°C) — 2.10 —
(VGE = 15 Vdc, IC = 30 Adc) — 2.60 3.45
(VCE = VGE, IC = 1 mAdc) 4.0 6.0 8.0
Vd VGE = 0 Vdc,
Vd
Coes — 225 —
f = 1.0 MHz)

Rise Time tr — 80 —
Turn–Off Delay Time (VCC = 360 Vdc, IC = 30 Adc, td(off) — 348 —
Vd L = 300 mH
VGE = 15 Vdc,
RG = 20 Ω, TJ = 2525°C)
C)
Turn–Off Switching Loss Energy losses include “tail” Eoff — 0.98 1.28 mJ
Vd L = 300 mH
VGE = 15 Vdc,
RG = 20 Ω, TJ = 125°C)
125 C)
Turn–Off Switching Loss Energy losses include “tail” Eoff — 1.90 — mJ
(VCC = 360 Vdc,
Vd IC = 30 Adc,
Ad
Q1 — 30 —
VGE = 15 Vdc)
Q2 — 45 —
(IEC = 15 Adc) — 1.30 1.80
(IEC = 15 Adc, TJ = 125°C) — 1.10 —
(IEC = 30 Adc) — 1.45 2.05

MGY30N60D
((IF = 30 Adc, VR = 360 Vdc, ta — 82 —

dIF/dt = 200 A/µs) tb — 71 —
((IF = 30 Adc, VR = 360 Vdc, ta — 117 —

dIF/dt = 200 A/µs, TJ = 125°C) tb — 91 —
60 60
17.5 V IC, COLLECTOR CURRENT (AMPS) 17.5 V

10 V 10 V
40 15 V 40 15 V
20 20
0 0
0 1 2 3 4 5 0 1 2 3 4 5

60 3
VCE = 100 V VGE = 15 V
IC = 30 A
TJ = 125°C
40 2.6 22.5 A
25°C 15 A
20 2.2
0 1.8
5 6 7 8 9 10 11 – 50 0 50 100 150


MGY30N60D
8000 20

VCE = 0 V TJ = 25°C
QT
6000 15
C, CAPACITANCE (pF)
Cies
4000 10 Q1 Q2
2000 5 TJ = 25°C
Coes IC = 30 A
Cres
0 0
0 5 10 15 20 25 0 30 60 90 120 150

Total Charge
6.4 6.5

VCC = 360 V
VGE = 15 V VCC = 360 V
5.6
TJ = 125°C 5.5 VGE = 15 V
IC = 30 A
4.8 RG = 20 Ω
4.5
4 IC = 30 A
3.2 20 A 3.5
20 A
2.4
2.5
1.6 10 A
1.5 10 A
0.8
0 0.5
10 20 30 40 50 0 25 50 75 100 125 150
5 3
VCC = 360 V VCC = 360 V

VGE = 15 V VGE = 15 V
4
RG = 20 Ω TJ = 125°C
IC = 30 A
TJ = 125°C 2
3
20 A
2
1
10 A
1
0 0
0 5 10 15 20 25 30 10 20 30 40 50

MGY30N60D
3 2
VCC = 360 V VCC = 360 V

VGE = 15 V VGE = 15 V
RG = 20 Ω RG = 20 Ω
1.5
TJ = 125°C
2
IC = 30 A 1
1 20 A
0.5
10 A
0 0
0 25 50 75 100 125 150 0 5 10 15 20 25 30
100 100

10 10
TJ = 125°C
TJ = 25°C
1 1
VGE = 15 V
RGE = 20 Ω
TJ = 125°C
0.1 0.1
0 0.4 0.8 1.2 1.6 1 10 100 1000

MOTOROLA
 Data Sheet
Designer's
Insulated Gate Bipolar Transistor MGY40N60

• Robust RBSOA
G
C
G E
E
TO–264



MGY40N60
OFF CHARACTERISTICS
(VGE = 0 Vdc, IC = 250 µAdc) 600 — —
(VCE = 600 Vdc, VGE = 0 Vdc) — — 100
(VGE = 15 Vdc, IC = 20 Adc) — 2.20 2.80
(VGE = 15 Vdc, IC = 20 Adc, TJ = 125°C) — 2.10 —
(VGE = 15 Vdc, IC = 40 Adc) — 2.60 3.25
(VCE = VGE, IC = 1 mAdc) 4.0 6.0 8.0
Vd VGE = 0 Vdc,
Vd
Coes — 464 —
f = 1.0 MHz)

Vd L = 300 mH
VGE = 15 Vdc,
RG = 20 Ω, TJ = 2525°C)
C)
Vd L = 300 mH
VGE = 15 Vdc,
RG = 20 Ω, TJ = 125°C)
125 C)
(VCC = 360 Vdc,
Vd IC = 40 Adc,
Ad
Q1 — 49 —
VGE = 15 Vdc)
Q2 — 81 —

MGY40N60
80 80

17.5 V 10 V 17.5 V 15 V
15 V
60 60 10 V
40 40
20 20
0 0
0 1 2 3 4 5 0 1 2 3 4 5

80 3
VCE = 100 V VGE = 15 V
IC = 40 A
60 TJ = 125°C
2.6
30 A
40
25°C
2.2 20 A
20
0 1.8
5 6 7 8 9 10 – 50 0 50 100 150

12000 20
VCE = 0 V TJ = 25°C
QT
15
C, CAPACITANCE (pF)
8000
Cies
10 Q1 Q2
4000
5 TJ = 25°C
Coes IC = 40 A
Cres
0 0
0 5 10 15 20 25 0 50 100 150 200 250

Total Charge

MGY40N60
4 4
VCC = 360 V VCC = 360 V
TURN–OFF ENERGY LOSSES (mJ) VGE = 15 V VGE = 15 V

TJ = 125°C RG = 20 Ω
3 IC = 40 A 3
IC = 40 A
2 30 A 2
30 A
20 A
1 1 20 A
0 0
10 20 30 40 50 0 25 50 75 100 125 150

3 100

VCC = 360 V
VGE = 15 V
RG = 20 Ω
TJ = 125°C
2 10
1 1
VGE = 15 V
RGE = 20 Ω
TJ = 125°C
0 0.1
0 5 10 15 20 25 30 35 40 1 10 100 1000
IC, COLLECTOR–TO–EMITTER CURRENT (AMPS) VCE, COLLECTOR–TO–EMITTER VOLTAGE (VOLTS)
Figure 9. Turn–Off Losses versus Figure 10. Reverse Biased Safe

Collector–to–Emitter Current Operating Area

MOTOROLA
 Data Sheet
Designer's
MGY40N60D

40 A @ 90°C
66 A @ 25°C
600 VOLTS
SHORT CIRCUIT RATED
C
G
• Robust RBSOA
G
E C
E

TO–264


Thermal Resistance — Junction to Case – Diode RθJC 1.13

MGY40N60D
OFF CHARACTERISTICS
(VGE = 0 Vdc, IC = 250 µAdc) 600 — —
(VCE = 600 Vdc, VGE = 0 Vdc) — — 100
(VGE = 15 Vdc, IC = 20 Adc) — 2.20 2.80
(VGE = 15 Vdc, IC = 20 Adc, TJ = 125°C) — 2.10 —
(VGE = 15 Vdc, IC = 40 Adc) — 2.60 3.25
(VCE = VGE, IC = 1 mAdc) 4.0 6.0 8.0
Vd VGE = 0 Vdc,
Vd
Coes — 464 —
f = 1.0 MHz)

Vd L = 300 mH
VGE = 15 Vdc,
RG = 20 Ω, TJ = 2525°C)
C)
Turn–Off Switching Loss Energy losses include “tail” Eoff — 1.50 2.10 mJ
Vd L = 300 mH
VGE = 15 Vdc,
RG = 20 Ω, TJ = 125°C)
125 C)
Turn–Off Switching Loss Energy losses include “tail” Eoff — 2.70 — mJ
(VCC = 360 Vdc,
Vd IC = 40 Adc,
Ad
Q1 — 49 —
VGE = 15 Vdc)
Q2 — 81 —
(IEC = 20 Adc) — 1.19 1.70
(IEC = 20 Adc, TJ = 125°C) — 1.04 —
(IEC = 40 Adc) — 1.36 2.00

MGY40N60D
((IF = 40 Adc, VR = 360 Vdc, ta — 78 —

dIF/dt = 200 A/µs) tb — 60 —
((IF = 40 Adc, VR = 360 Vdc, ta — 122 —

dIF/dt = 200 A/µs, TJ = 125°C) tb — 91 —
80 80
17.5 V 10 V IC, COLLECTOR CURRENT (AMPS) 17.5 V 15 V

15 V
60 60 10 V
40 40
20 20
0 0
0 1 2 3 4 5 0 1 2 3 4 5

80 3
VCE = 100 V VGE = 15 V
IC = 40 A
60 TJ = 125°C
2.6
30 A
40
25°C
2.2 20 A
20
0 1.8
5 6 7 8 9 10 – 50 0 50 100 150


MGY40N60D
12000 20

VCE = 0 V TJ = 25°C
QT
15
C, CAPACITANCE (pF)
8000
Cies
10 Q1 Q2
4000
5 TJ = 25°C
Coes IC = 40 A
Cres
0 0
0 5 10 15 20 25 0 50 100 150 200 250

Total Charge
8.5

VCC = 360 V VCC = 360 V
VGE = 15 V 7 VGE = 15 V
7.5 IC = 40 A
TJ = 125°C RG = 20 Ω
6.5
IC = 40 A
5
5.5 30 A
30 A
4.5
3
20 A
20 A
3.5
2.5 1
10 20 30 40 50 0 25 50 75 100 125 150
7 4
VCC = 360 V VCC = 360 V

VGE = 15 V
6 VGE = 15 V
RG = 20 Ω TJ = 125°C IC = 40 A
TJ = 125°C 3
5
4 30 A
2
3
20 A
2
1
1
0 0
0 5 10 15 20 25 30 35 40 10 20 30 40 50

MGY40N60D
4 3
VCC = 360 V VCC = 360 V
TURN–OFF ENERGY LOSSES (mJ) VGE = 15 V

VGE = 15 V
RG = 20 Ω RG = 20 Ω
3 TJ = 125°C
2
2 IC = 40 A
30 A 1
1 20 A
0 0
0 25 50 75 100 125 150 0 5 10 15 20 25 30 35 40
100 100

10 10
TJ = 125°C
TJ = 25°C
1 1
VGE = 15 V
RGE = 20 Ω
TJ = 125°C
0.1 0.1
0 0.4 0.8 1.2 1 10 100 1000

MOTOROLA
 Data Sheet
Designer's
SMARTDISCRETES 
MLD1N06CL
Internally Clamped, Current Limited

N–Channel Logic Level Power MOSFET VOLTAGE CLAMPED
The MLD1N06CL is designed for applications that require a rugged power switching CURRENT LIMITING
device with short circuit protection that can be directly interfaced to a microcontrol unit MOSFET
(MCU). Ideal applications include automotive fuel injector driver, incandescent lamp 62 VOLTS (CLAMPED)
driver or other applications where a high in–rush current or a shorted load condition could RDS(on) = 0.75 OHMS
occur.
This logic level power MOSFET features current limiting for short circuit protection,
integrated Gate–Source clamping for ESD protection and integral Gate–Drain clamping D
for over–voltage protection and Sensefet technology for low on–resistance. No additional
gate series resistance is required when interfacing to the output of a MCU, but a 40 kΩ
gate pulldown resistor is recommended to avoid a floating gate condition.
The internal Gate–Source and Gate–Drain clamps allow the device to be applied
without use of external transient suppression components. The Gate–Source clamp
R1
protects the MOSFET input from electrostatic voltage stress up to 2.0 kV. The
G
Gate–Drain clamp protects the MOSFET drain from the avalanche stress that occurs
with inductive loads. Their unique design provides voltage clamping that is essentially
independent of operating temperature.
The MLD1N06CL is fabricated using Motorola’s SMARTDISCRETES technology which R2
combines the advantages of a power MOSFET output device with the on–chip protective
circuitry that can be obtained from a standard MOSFET process. This approach offers an
economical means of providing protection to power MOSFETs from harsh automotive and S
industrial environments. SMARTDISCRETES devices are specified over a wide tempera-
ture range from –50°C to 150°C.

Drain–to–Source Voltage VDSS Clamped Vdc
Drain–to–Gate Voltage (RGS = 1.0 MΩ) VDGR Clamped Vdc
Gate–to–Source Voltage — Continuous VGS ±10 Vdc
Drain Current — Continuous ID Self–limited Adc
— Single Pulse IDM 1.8 Apk
Total Power Dissipation PD 40 Watts
Operating and Storage Temperature Range TJ, Tstg –50 to 150 °C
Electrostatic Discharge Voltage (Human Model) ESD 2.0 kV
Thermal Resistance — Junction to Case RθJC 3.12 °C/W
— Junction to Ambient (1) RθJA 71.4
Maximum Lead Temperature for Soldering Purposes, TL 260 °C DPAK Surface Mount
1/8″ from case for 5 sec.
UNCLAMPED DRAIN–TO–SOURCE AVALANCHE CHARACTERISTICS

Single Pulse Drain–to–Source Avalanche Energy EAS 80 mJ
Starting TJ = 25°C
(1) When surface mounted to an FR4 board using the minimum recommended pad size.

MLD1N06CL
OFF CHARACTERISTICS
Drain–to–Source Breakdown Voltage (Internally Clamped) V(BR)DSS Vdc
(ID = 20 mAdc, VGS = 0 Vdc) 59 62 65
(ID = 20 mAdc, VGS = 0 Vdc, TJ = 150°C) 59 62 65
Zero Gate Voltage Drain Current IDSS µAdc
(VDS = 45 Vdc, VGS = 0 Vdc) — 0.6 5.0
(VDS = 45 Vdc, VGS = 0 Vdc, TJ = 150°C) — 6.0 20
Gate–Source Leakage Current IGSS µAdc
(VG = 5.0 Vdc, VDS = 0 Vdc) — 0.5 5.0
(VG = 5.0 Vdc, VDS = 0 Vdc, TJ = 150°C) — 1.0 20
ON CHARACTERISTICS(1)
Gate Threshold Voltage VGS(th) Vdc
(ID = 250 µAdc, VDS = VGS) 1.0 1.5 2.0
(ID = 250 µAdc, VDS = VGS, TJ = 150°C) 0.6 — 1.6
Static Drain–to–Source On–Resistance RDS(on) Ohms
(ID = 1.0 Adc, VGS = 4.0 Vdc) — 0.63 0.75
(ID = 1.0 Adc, VGS = 5.0 Vdc) — 0.59 0.75
(ID = 1.0 Adc, VGS = 4.0 Vdc, TJ = 150°C) — 1.1 1.9
(ID = 1.0 Adc, VGS = 5.0 Vdc, TJ = 150°C) — 1.0 1.8
Static Source–to–Drain Diode Voltage (IS = 1.0 Adc, VGS = 0 Vdc) VSD — 1.1 1.5 Vdc
Static Drain Current Limit ID(lim) Adc
(VGS = 5.0 Vdc, VDS = 10 Vdc) 2.0 2.3 2.75
(VGS = 5.0 Vdc, VDS = 10 Vdc, TJ = 150°C) 1.1 1.3 1.8
Forward Transconductance (ID = 1.0 Adc, VDS = 10 Vdc) gFS 1.0 1.4 — mhos
RESISTIVE SWITCHING CHARACTERISTICS(2)
Turn–On Delay Time td(on) — 1.2 2.0 ns
Rise Time ((VDD = 25 Vdc, ID = 1.0 Adc, tr — 4.0 6.0
Turn–Off Delay Time VGS(on) = 5.0 Vdc, RGS = 50 Ohms) td(off) — 4.0 6.0
Fall Time tf — 3.0 5.0
Internal Drain Inductance LD nH
(Measured from drain lead 0.25” from package to center of die) — 4.5 —
Internal Source Inductance LS nH
(Measured from the source lead 0.25” from package to source bond pad) — 7.5 —
(2) Switching characteristics are independent of operating junction temperature.
4
TJ = 25°C VDS ≥ 7.5 V
4 –50°C
ID , DRAIN CURRENT (AMPS)
3
10 V
6V 8V 3
4V 25°C
2
2
1 VGS = 3 V TJ = 150°C
1
0 0
0 2 4 6 8 0 2 4 6 8
VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS) VGS, GATE–TO–SOURCE VOLTAGE (VOLTS)
Figure 1. Output Characteristics Figure 2. Transfer Function

MLD1N06CL
THE SMARTDISCRETES CONCEPT 4
From a standard power MOSFET process, several active VGS = 5 V
VDS = 7.5 V
ID(lim) , DRAIN CURRENT (AMPS)

and passive elements can be obtained that provide on–chip
protection to the basic power device. Such elements require 3
only a small increase in silicon area and/or the addition of one
masking layer to the process. The resulting device exhibits
significant improvements in ruggedness and reliability as well
2
as system cost reduction. The SMARTDISCRETES device
functions can now provide an economical alternative to smart
power ICs for power applications requiring low on–resistance,
high voltage and high current. 1
These devices are designed for applications that require a
rugged power switching device with short circuit protection
that can be directly interfaced to a microcontroller unit (MCU). 0
–50 0 50 100 150
Ideal applications include automotive fuel injector driver,
TJ, JUNCTION TEMPERATURE (°C)
incandescent lamp driver or other applications where a high
in–rush current or a shorted load condition could occur.
Figure 3. ID(lim) Variation
OPERATION IN THE CURRENT LIMIT MODE
With Temperature
The amount of time that an unprotected device can with-
stand the current stress resulting from a shorted load before
its maximum junction temperature is exceeded is dependent
upon a number of factors that include the amount
4
of heatsinking that is provided, the size or rating of the device, ID = 1 A
R DS(on), ON–RESISTANCE (OHMS)

its initial junction temperature, and the supply voltage. Without
some form of current limiting, a shorted load can raise a de-
3
vice’s junction temperature beyond the maximum rated oper-
ating temperature in only a few milliseconds.
Even with no heatsink, the MLD1N06CL can withstand a
shorted load powered by an automotive battery (10 to 14 2
150°C
Volts) for almost a second if its initial operating temperature is TJ = –50°C
25°C
under 100°C. For longer periods of operation in the current–
limited mode, device heatsinking can extend operation from 1
several seconds to indefinitely depending on the amount of
heatsinking provided.
SHORT CIRCUIT PROTECTION AND THE EFFECT OF 0
0 2 4 6 8 10
TEMPERATURE VGS, GATE–TO–SOURCE VOLTAGE (VOLTS)
The on–chip circuitry of the MLD1N06CL offers an integrated
means of protecting the MOSFET component from high in–rush Figure 4. RDS(on) Variation With
current or a shorted load. As shown in the schematic diagram, Gate–To–Source Voltage
the current limiting feature is provided by an NPN transistor and
integral resistors R1 and R2. R2 senses the current through the
MOSFET and forward biases the NPN transistor’s base as the
current increases. As the NPN turns on, it begins to pull gate
drive current through R1, dropping the gate drive voltage across 1.25
it, and thus lowering the voltage across the gate–to–source of ID = 1 A
the power MOSFET and limiting the current. The current limit is
RDS(on), ON–RESISTANCE (OHMS)
temperature dependent as shown in Figure 3, and decreases 1

from about 2.3 Amps at 25°C to about 1.3 Amps at 150°C.
Since the MLD1N06CL continues to conduct current and dis- VGS = 4 V
sipate power during a shorted load condition, it is important to 0.75
provide sufficient heatsinking to limit the device junction tempera-
VGS = 5 V
ture to a maximum of 150°C.
The metal current sense resistor R2 adds about 0.4 ohms to 0.5
the power MOSFET’s on–resistance, but the effect of tempera-
ture on the combination is less than on a standard MOSFET due
to the lower temperature coefficient of R2. The on–resistance 0.25
variation with temperature for gate voltages of 4 and 5 Volts is –50 0 50 100 150
shown in Figure 5. TJ, JUNCTION TEMPERATURE (°C)
Back–to–back polysilicon diodes between gate and source Figure 5. On–Resistance Variation With
provide ESD protection to greater than 2 kV, HBM. This on–chip Temperature
protection feature eliminates the need for an external Zener
diode for systems with potentially heavy line transients.

MLD1N06CL
BV(DSS) , DRAIN–SOURCE SUSTAINING VOLTAGE (VOLTS)

WAS , SINGLE PULSE AVALANCHE ENERGY (mJ)
100 64
80
63
60
62
40
61
20
0 60
25 50 75 100 125 150 –50 0 50 100 150
TJ, JUNCTION TEMPERATURE (°C) TJ, JUNCTION TEMPERATURE (°C)
Figure 6. Single Pulse Avalanche Energy Figure 7. Drain–Source Sustaining

versus Junction Temperature Voltage Variation With Temperature
FORWARD BIASED SAFE OPERATING AREA DUTY CYCLE OPERATION

The FBSOA curves define the maximum drain–to–source When operating in the duty cycle mode, the maximum
voltage and drain current that a device can safely handle drain voltage can be increased. The maximum operating
when it is forward biased, or when it is on, or being turned on. temperature is related to the duty cycle (DC) by the following
Because these curves include the limitations of simultaneous equation:
high voltage and high current, up to the rating of the device, TC = (VDS x ID x DC x RθCA) + TA
they are especially useful to designers of linear systems. The
The maximum value of VDS applied when operating in a
curves are based on a case temperature of 25°C and a maxi-
duty cycle mode can be approximated by:
mum junction temperature of 150°C. Limitations for repetitive
pulses at various case temperatures can be determined by 150 – TC
VDS =
using the thermal response curves. Motorola Application ID(lim) x DC x RθJC
Note, AN569, “Transient Thermal Resistance — General
Data and Its Use” provides detailed instructions. 10
VGS = 10 V
SINGLE PULSE
TC = 25°C
MAXIMUM DC VOLTAGE CONSIDERATIONS
10 µs
The maximum drain–to–source voltage that can be contin-
uously applied across the MLD1N06CL when it is in current
1.0 100 µs
limit is a function of the power that must be dissipated. This
power is determined by the maximum current limit at maxi- 1 ms
mum rated operating temperature (1.8 A at 150°C) and not 10 ms
the RDS(on). The maximum voltage can be calculated by the RDS(on) LIMIT
following equation: THERMAL LIMIT
PACKAGE LIMIT dc
(150 – TA) 0.1
Vsupply = 0.1 1.0 10 100
ID(lim) (RθJC + RθCA)
VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
where the value of RθCA is determined by the heatsink that is Figure 8. Maximum Rated Forward Bias
being used in the application. Safe Operating Area (MLD1N06CL)

MLD1N06CL
1.0
D = 0.5

0.2
0.1
0.1 0.05 P(pk)

RθJC(t) = r(t) RθJC
PULSE TRAIN SHOWN
0.02
t1 READ TIME AT t1
SINGLE PULSE
0.01
1.0E – 05 1.0E – 04 1.0E – 03 1.0E – 02 1.0E – 01 1.0E+00 1.0E+01
t, TIME (s)
Figure 9. Thermal Response (MLD1N06CL)
VDD ton toff
RL Vout td(on) tr td(off) tf

90% 90%
Vin DUT
PULSE GENERATOR OUTPUT, Vout
z = 50 Ω 10%
Rgen INVERTED
50Ω
90%
50 Ω
50% 50%
INPUT, Vin PULSE WIDTH
10%
Figure 10. Switching Test Circuit Figure 11. Switching Waveforms
ACTIVE CLAMPING
SMARTDISCRETES technology can provide on–chip real- elements provide greater than 2.0 kV electrostatic voltage
ization of the popular gate–to–source and gate–to–drain protection.
Zener diode clamp elements. Until recently, such features The avalanche voltage of the gate–to–drain voltage clamp
have been implemented only with discrete components is set less than that of the power MOSFET device. As soon
which consume board space and add system cost. The as the drain–to–source voltage exceeds this avalanche volt-
SMARTDISCRETES technology approach economically age, the resulting gate–to–drain Zener current builds a gate
melds these features and the power chip with only a slight voltage across the gate–to–source impedance, turning on
increase in chip area. the power device which then conducts the current. Since vir-
In practice, back–to–back diode elements are formed in a tually all of the current is carried by the power device, the
polysilicon region monolithicly integrated with, but electrically
gate–to–drain voltage clamp element may be small in size.
isolated from, the main device structure. Each back–to–back
This technique of establishing a temperature compensated
diode element provides a temperature compensated voltage
drain–to–source sustaining voltage (Figure 7) effectively re-
element of about 7.2 volts. As the polysilicon region is
formed on top of silicon dioxide, the diode elements are free moves the possibility of drain–to–source avalanche in the
from direct interaction with the conduction regions of the power device.
power device, thus eliminating parasitic electrical effects The gate–to–drain voltage clamp technique is particularly
while maintaining excellent thermal coupling. useful for snubbing loads where the inductive energy would
To achieve high gate–to–drain clamp voltages, several otherwise avalanche the power device. An improvement in
voltage elements are strung together; the MLD1N06CL uses ruggedness of at least four times has been observed when
8 such elements. Customarily, two voltage elements are inductive energy is dissipated in the gate–to–drain clamped
used to provide a 14.4 volt gate–to–source voltage clamp. conduction mode rather than in the more stressful gate–to–
For the MLD1N06CL, the integrated gate–to–source voltage source avalanche mode.

MLD1N06CL
TYPICAL APPLICATIONS: INJECTOR DRIVER, SOLENOIDS, LAMPS, RELAY COILS
The MLD1N06CL has been designed to allow direct inter- VBAT

face to the output of a microcontrol unit to control an isolated
load. No additional series gate resistance is required, but a VDD
40 kΩ gate pulldown resistor is recommended to avoid a
floating gate condition in the event of an MCU failure. The in-
ternal clamps allow the device to be used without any exter- D
nal transistent suppressing components.
G
MCU MLD1N06CL

MOTOROLA
 Data Sheet
Designer's
SMARTDISCRETES 
MLD2N06CL

The MLD2N06CL is designed for applications that require a rugged power switching CURRENT LIMITING
occur.
R1
G
The MLD2N06CL is fabricated using Motorola’s SMARTDISCRETES technology which R2

Drain Current — Continuous @ TC = 25°C ID Self–limited Adc
Electrostatic Voltage ESD 2.0 kV
Operating and Storage Temperature Range TJ, Tstg –50 to 150 °C
Maximum Junction Temperature TJ(max) 150 °C
Thermal Resistance – Junction to Case RθJC 3.12 °C/W
Maximum Lead Temperature for Soldering Purposes, TL 260 °C CASE 369A–13, Style 2
1/8″ from case for 5 sec. DPAK Surface Mount
DRAIN–TO–SOURCE AVALANCHE CHARACTERISTICS

(Starting TJ = 25°C, ID = 2.0 A, L = 40 mH)

MLD2N06CL
OFF CHARACTERISTICS
Drain–to–Source Breakdown Voltage V(BR)DSS Vdc
(ID = 20 mAdc, VGS = 0 Vdc) 58 62 66
(VDS = 40 Vdc, VGS = 0 Vdc) — 0.6 5.0
(VG = 5.0 Vdc, VDS = 0 Vdc) — 0.5 5.0
(VG = 5.0 Vdc, VDS = 0 Vdc, TJ = 150°C) — 1.0 20
(ID = 250 µAdc, VDS = VGS) 1.0 1.5 2.0
(ID = 250 µAdc, VDS = VGS, TJ = 150°C) 0.6 1 1.6
(VGS = 5.0 Vdc, VDS = 10 Vdc) 3.8 4.4 5.2
(ID = 1.0 Adc, VGS = 5.0 Vdc) — 0.3 0.4
(ID = 1.0 Adc, VGS = 5.0 Vdc, TJ = 150°C) — 0.53 0.7
Static Source–to–Drain Diode Voltage VSD Vdc
(IS = 1.0 Adc, VGS = 0 Vdc) — 1.1 1.5
SWITCHING CHARACTERISTICS(2)
Turn–On Delay Time td(on) — 1.0 1.5 µs
5 4.0
TJ = 25°C 6.0 V VDS ≥ 7.5 V – 55°C 25°C
5.5 V 3.5
I D , DRAIN CURRENT (AMPS)
4 5.0 V TJ = 150°C
4.5 V 3.0
4.0 V
3 2.5
3.5 V
2.0
3.0 V
2 1.5
1.0
1
2.5 V
0.5
2.0 V
0 0
0 2 4 6 8 0 1 2 3 4 5 6 7 8

MLD2N06CL
and passive elements can be obtained that provide on–chip VDS = 10 V
I D(lim) , DRAIN CURRENT (AMPS)

5
protection to the basic power device. Such elements require
only a small increase in silicon area and/or the addition of one 4
3
power ICs for power applications requiring low on–resistance, 2
high voltage and high current.
These devices are designed for applications that require a 1
– 50 0 50 100 150
incandescent lamp driver or other applications where a high TJ, JUNCTION TEMPERATURE (°C)
in–rush current or a shorted load condition could occur.
Figure 3. ID(lim) Variation
With Temperature
upon a number of factors that include the amount 1.0
RDS(on) , ON–RESISTANCE (OHMS)

its initial junction temperature, and the supply voltage. Without 0.8
ating temperature in only a few milliseconds. 0.6
Even with no heatsink, the MLD2N06CL can withstand a
shorted load powered by an automotive battery (10 to 14 100°C
Volts) for almost a second if its initial operating temperature is 0.4
under 100°C. For longer periods of operation in the current– 25°C
limited mode, device heatsinking can extend operation from 0.2
several seconds to indefinitely depending on the amount of TJ = – 50°C
0 1 2 3 4 5 6 7 8 9 10
The on–chip circuitry of the MLD2N06CL offers an integrated
current increases. As the NPN turns on, it begins to pull gate 0.6
drive current through R1, dropping the gate drive voltage across ID = 1 A
it, and thus lowering the voltage across the gate–to–source of 0.5
VGS = 4 V
temperature dependent as shown in Figure 3, and decreases 0.4
Since the MLD2N06CL continues to conduct current and dis- VGS = 5 V
0.3
sipate power during a shorted load condition, it is important to
provide sufficient heatsinking to limit the device junction tempera-
0.2
ture to a maximum of 150°C.
The metal current sense resistor R2 adds about 0.4 ohms to
the power MOSFET’s on–resistance, but the effect of tempera- 0.1
to the lower temperature coefficient of R2. The on–resistance 0
– 50 0 50 100 150
variation with temperature for gate voltages of 4 and 5 Volts is
shown in Figure 5.

MLD2N06CL
100 64.0
BV(DSS) , DRAIN–TO–SOURCE SUSTAINING

EAS , SINGLE PULSE DRAIN–TO–SOURCE
ID = 2 A ID = 20 mA
63.5
AVALANCHE ENERGY (mJ) 80
63.0
VOLTAGE (VOLTS)
60 62.5
62.0
40 61.5
61.0
20
60.5
0 60.0
25 50 75 100 125 150 – 50 0 50 100 150
TJ, STARTING JUNCTION TEMPERATURE (°C) TJ = JUNCTION TEMPERATURE
Figure 6. Maximum Avalanche Energy Figure 7. Drain–Source Sustaining

versus Starting Junction Temperature Voltage Variation With Temperature

VDS =
VGS = 10 V
SINGLE PULSE
TC = 25°C
The maximum drain–to–source voltage that can be contin- dc
uously applied across the MLD2N06CL when it is in current 10 ms
limit is a function of the power that must be dissipated. This 1.0 1 ms
power is determined by the maximum current limit at maxi-
mum rated operating temperature (1.8 A at 150°C) and not
PACKAGE LIMIT
(150 – TA) 0.1
Vsupply = 0.1 1.0 10 100
being used in the application. Safe Operating Area (MLD2N06CL)

MLD2N06CL
1.0
D = 0.5

0.2
0.1
0.1 0.05 P(pk)

PULSE TRAIN SHOWN
0.02
t1 READ TIME AT t1
SINGLE PULSE
0.01
1.0E – 05 1.0E – 04 1.0E – 03 1.0E – 02 1.0E – 01 1.0E+00 1.0E+01
t, TIME (s)
Figure 9. Thermal Response (MLD2N06CL)
VDD ton toff

90% 90%
Vin DUT
z = 50 Ω 10%
Rgen INVERTED
50Ω
90%
50 Ω
50% 50%
10%
ACTIVE CLAMPING
voltage elements are strung together; the MLD2N06CL uses ruggedness of at least four times has been observed when
For the MLD2N06CL, the integrated gate–to–source voltage source avalanche mode.

MLD2N06CL
The MLD2N06CL has been designed to allow direct inter- VBAT

G
MCU MLD2N06CL

MOTOROLA
SMARTDISCRETES 
MLP1N06CL
N–Channel Logic Level Power MOSFET

These SMARTDISCRETES devices feature current limiting for short circuit
VOLTAGE CLAMPED
protection, an integral gate–to–source clamp for ESD protection and gate–to–drain
CURRENT LIMITING
clamp for over–voltage protection. No additional gate series resistance is required
MOSFET
when interfacing to the output of a MCU, but a 40 kΩ gate pulldown resistor is
62 VOLTS (CLAMPED)
recommended to avoid a floating gate condition.
RDS(on) = 0.75 OHMS
The internal gate–to–source and gate–to–drain clamps allow the devices to be
applied without use of external transient suppression components. The gate–to–
source clamp protects the MOSFET input from electrostatic gate voltage stresses
up to 2.0 kV. The gate–to–drain clamp protects the MOSFET drain from drain D
avalanche stresses that occur with inductive loads. This unique design provides
voltage clamping that is essentially independent of operating temperature.
The MLP1N06CL is fabricated using Motorola’s SMARTDISCRETES technolo-
gy which combines the advantages of a power MOSFET output device with
on–chip protective circuitry. This approach offers an economical means for
R1
providing additional functions that protect a power MOSFET in harsh automotive
G
and industrial environments. SMARTDISCRETES devices are specified over a
wide temperature range from –50°C to 150°C.
• Temperature Compensated Gate–to–Drain Clamp Limits Voltage Stress
Applied to the Device and Protects the Load From Overvoltage R2
• Controlled Switching Minimizes RFI
S
• Low Threshold Voltage Enables Interfacing Power Loads to Microprocessors

Drain Current — Continuous ID Self–limited Adc
Drain Current — Single Pulse IDM 1.8
Electrostatic Discharge Voltage (Human Body Model) ESD 2.0 kV
G
Operating and Storage Junction Temperature Range TJ, Tstg –50 to 150 °C D
S
Thermal Resistance, Junction to Case RθJC 3.12 °C/W
Thermal Resistance, Junction to Ambient RθJA 62.5
Maximum Lead Temperature for Soldering Purposes, TL 260 °C
1/8″ from case CASE 221A–06, Style 5
TO–220AB
UNCLAMPED DRAIN–TO–SOURCE AVALANCHE CHARACTERISTICS
(Starting TJ = 25°C, ID = 2.0 A, L = 40 mH) (Figure 6)
REV 1

MLP1N06CL
OFF CHARACTERISTICS
Drain–to–Source Sustaining Voltage (Internally Clamped) V(BR)DSS Vdc
(ID = 20 mA, VGS = 0) 59 62 65
(ID = 20 mA, VGS = 0, TJ = 150°C) 59 62 65
(VDS = 45 V, VGS = 0) — 0.6 5.0
(VDS = 45 V, VGS = 0, TJ = 150°C) — 6.0 20
Gate–Body Leakage Current IGSS µAdc
(VG = 5.0 V, VDS = 0) — 0.5 5.0
(VG = 5.0 V, VDS = 0, TJ = 150°C) — 1.0 20
ON CHARACTERISTICS*
(ID = 250 µA, VDS = VGS) 1.0 1.5 2.0
(ID = 250 µA, VDS = VGS, TJ = 150°C) 0.6 — 1.6
(ID = 1.0 A, VGS = 4.0 V) — 0.63 0.75
(ID = 1.0 A, VGS = 5.0 V) — 0.59 0.75
(ID = 1.0 A, VGS = 4.0 V, TJ = 150°C) — 1.1 1.9
(ID = 1.0 A, VGS = 5.0 V, TJ = 150°C) — 1.0 1.8
Forward Transconductance (ID = 1.0 A, VDS = 10 V) gFS 1.0 1.4 — mhos
Static Source–to–Drain Diode Voltage (IS = 1.0 A, VGS = 0) VSD — 1.1 1.5 Vdc
Static Drain Current Limit ID(lim) A
(VGS = 5.0 V, VDS = 10 V) 2.0 2.3 2.75
(VGS = 5.0 V, VDS = 10 V, TJ = 150°C) 1.1 1.3 1.8
RESISTIVE SWITCHING CHARACTERISTICS*

Rise Time ((VDD = 25 V, ID = 1.0 A, tr — 4.0 6.0
Turn–Off Delay Time VGS = 5.0 V, RG = 50 Ohms) td(off) — 4.0 6.0
* Indicates Pulse Test: Pulse Width ≤ 300 µs, Duty Cycle ≤ 2.0%.
4
TJ = 25°C VDS ≥ 7.5 V
4 –50°C
3
10 V
6V 8V 3
4V 25°C
2
2
1 VGS = 3 V TJ = 150°C
1
0 0
0 2 4 6 8 0 2 4 6 8

MLP1N06CL
THE SMARTDISCRETES CONCEPT
From a standard power MOSFET process, several active 4
and passive elements can be obtained that provide on–chip VGS = 5 V
VDS = 7.5 V
ID(lim) , DRAIN CURRENT (AMPS)

2
power ICs for power applications requiring low on–resistance,
that can be directly interfaced to a microcontroller unit
(MCU). Ideal applications include automotive fuel injector 0
–50 0 50 100 150
driver, incandescent lamp driver or other applications where
a high in–rush current or a shorted load condition could occur.
OPERATION IN THE CURRENT LIMIT MODE Figure 3. ID(lim) Variation With Temperature
upon a number of factors that include the amount
of heatsinking that is provided, the size or rating of the de- 4
vice, its initial junction temperature, and the supply voltage. ID = 1 A
R DS(on), ON–RESISTANCE (OHMS)

Without some form of current limiting, a shorted load can
raise a device’s junction temperature beyond the maximum
3
rated operating temperature in only a few milliseconds.
Even with no heatsink, the MLP1N06CL can withstand a
shorted load powered by an automotive battery (10 to 14
Volts) for almost a second if its initial operating temperature 2
150°C
is under 100°C. For longer periods of operation in the cur- 25°C
TJ = –50°C
rent–limited mode, device heatsinking can extend operation
from several seconds to indefinitely depending on the 1
amount of heatsinking provided.
SHORT CIRCUIT PROTECTION AND THE EFFECT OF
0
TEMPERATURE 0 2 4 6 8 10
The on–chip circuitry of the MLP1N06CL offers an inte- VGS, GATE–TO–SOURCE VOLTAGE (VOLTS)
grated means of protecting the MOSFET component from
high in–rush current or a shorted load. As shown in the sche- Figure 4. RDS(on) Variation With
matic diagram, the current limiting feature is provided by an Gate–To–Source Voltage
NPN transistor and integral resistors R1 and R2. R2 senses
the current through the MOSFET and forward biases the
NPN transistor’s base as the current increases. As the NPN
turns on, it begins to pull gate drive current through R1, drop-
ping the gate drive voltage across it, and thus lowering the 1.25
voltage across the gate–to–source of the power MOSFET ID = 1 A
and limiting the current. The current limit is temperature de-
RDS(on), ON–RESISTANCE (OHMS)
pendent as shown in Figure 3, and decreases from about 2.3 1

Amps at 25°C to about 1.3 Amps at 150°C.
Since the MLP1N06CL continues to conduct current and VGS = 4 V
dissipate power during a shorted load condition, it is impor- 0.75
tant to provide sufficient heatsinking to limit the device junc-
VGS = 5 V
tion temperature to a maximum of 150°C.
The metal current sense resistor R2 adds about 0.4 ohms 0.5
to the power MOSFET’s on–resistance, but the effect of tem-
perature on the combination is less than on a standard
MOSFET due to the lower temperature coefficient of R2. The 0.25
on–resistance variation with temperature for gate voltages of –50 0 50 100 150
4 and 5 Volts is shown in Figure 5. TJ, JUNCTION TEMPERATURE (°C)
provide ESD protection to greater than 2 kV, HBM. This on– Temperature
chip protection feature eliminates the need for an external
Zener diode for systems with potentially heavy line transients.

MLP1N06CL
BV(DSS) , DRAIN–SOURCE SUSTAINING VOLTAGE (VOLTS)

WAS , SINGLE PULSE AVALANCHE ENERGY (mJ) 100 64
80
63
60
62
40
61
20
0 60
25 50 75 100 125 150 –50 0 50 100 150
Figure 6. Single Pulse Avalanche Energy Figure 7. Drain–Source Sustaining

versus Junction Temperature Voltage Variation With Temperature

VDS =
6
3 ID(lim) – MAX 1 ms
MAXIMUM DC VOLTAGE CONSIDERATIONS 1.5
2 ms
The maximum drain–to–source voltage that can be contin- ID(lim) – MIN 5 ms
uously applied across the MLP1N06CL when it is in current dc
1
limit is a function of the power that must be dissipated. This
power is determined by the maximum current limit at maxi- 0.6
DEVICE/POWER LIMITED
mum rated operating temperature (1.8 A at 150°C) and not RDS(on) LIMITED
0.3
the RDS(on). The maximum voltage can be calculated by the VGS = 5 V
0.2
following equation: SINGLE PULSE
TC = 25°C
0.1
(150 – TA) 1 2 3 6 10 20 30 60 100
Vsupply =
ID(lim) (RθJC + RθCA) VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
being used in the application. Safe Operating Area (MLP1N06CL)

MLP1N06CL
1.0
0.7 D = 0.5
r(t), EFFECTIVE TRANSIENT THERMAL 0.5 RθJC(t) = 3.12°C/W Max
RESISTANCE (NORMALIZED)
0.3 0.2 D Curves Apply for Power
0.2 Pulse Train Shown
0.1 Read Time at t1
TJ(pk) – TC = P(pk) RθJC(t)
0.1 0.05
0.07 0.02
0.05 P(pk)
0.03
0.01 t1
0.02 t2
SINGLE PULSE DUTY CYCLE, D =t1/t2
0.01
0.01 0.02 0.03 0.05 0.1 0.2 0.3 0.5 1.0 2.0 3.0 5.0 10 20 30 50 100 200 300 500 1000
t, TIME (ms)
Figure 9. Thermal Response (MLP1N06CL)
VDD ton toff

90% 90%
Vin DUT
z = 50 Ω 10%
Rgen INVERTED
50Ω
90%
50 Ω
50% 50%
10%
ACTIVE CLAMPING
voltage elements are strung together; the MLP1N06CL uses ruggedness of at least four times has been observed when
For the MLP1N06CL, the integrated gate–to–source voltage source avalanche mode.

MLP1N06CL
The MLP1N06CL has been designed to allow direct inter- VBAT

G
MCU MLP1N06CL

MOTOROLA
 Data Sheet
Designer's
SMARTDISCRETES 
MLP2N06CL

The MLP2N06CL is designed for applications that require a rugged power switching CURRENT LIMITING
occur.
R1
G
The MLP2N06CL is fabricated using Motorola’s SMARTDISCRETES technology which R2

Drain Current — Continuous @ TC = 25°C ID Self–limited Adc
Electrostatic Voltage ESD 2.0 kV G
D
Operating and Storage Temperature Range TJ, Tstg –50 to 150 °C S
Maximum Junction Temperature TJ(max) 150 °C
Maximum Lead Temperature for Soldering Purposes, TL 260 °C CASE 221A–06, Style 5
1/8″ from case for 5 sec. TO–220AB
DRAIN–TO–SOURCE AVALANCHE CHARACTERISTICS

(Starting TJ = 25°C, ID = 2.0 A, L = 40 mH)

MLP2N06CL
OFF CHARACTERISTICS
(ID = 20 mAdc, VGS = 0 Vdc) 58 62 66
(VDS = 40 Vdc, VGS = 0 Vdc) — 0.6 5.0
(VG = 5.0 Vdc, VDS = 0 Vdc) — 0.5 5.0
(VG = 5.0 Vdc, VDS = 0 Vdc, TJ = 150°C) — 1.0 20
(ID = 250 µAdc, VDS = VGS) 1.0 1.5 2.0
(ID = 250 µAdc, VDS = VGS, TJ = 150°C) 0.6 1 1.6
(VGS = 5.0 Vdc, VDS = 10 Vdc) 3.8 4.4 5.2
(ID = 1.0 Adc, VGS = 5.0 Vdc) — 0.3 0.4
(ID = 1.0 Adc, VGS = 5.0 Vdc, TJ = 150°C) — 0.53 0.7
Static Source–to–Drain Diode Voltage VSD Vdc
(IS = 1.0 Adc, VGS = 0 Vdc) — 1.1 1.5
5 4.0
TJ = 25°C 6.0 V VDS ≥ 7.5 V – 55°C 25°C
5.5 V 3.5
4 5.0 V TJ = 150°C
4.5 V 3.0
4.0 V
3 2.5
3.5 V
2.0
3.0 V
2 1.5
1.0
1
2.5 V
0.5
2.0 V
0 0
0 2 4 6 8 0 1 2 3 4 5 6 7 8

MLP2N06CL
and passive elements can be obtained that provide on–chip VDS = 10 V
I D(lim) , DRAIN CURRENT (AMPS)

5
3
power ICs for power applications requiring low on–resistance, 2
– 50 0 50 100 150
incandescent lamp driver or other applications where a high TJ, JUNCTION TEMPERATURE (°C)
in–rush current or a shorted load condition could occur. Figure 3. ID(lim) Variation With Temperature
upon a number of factors that include the amount 1.0

its initial junction temperature, and the supply voltage. Without 0.8
ating temperature in only a few milliseconds. 0.6
Even with no heatsink, the MLP2N06CL can withstand a
shorted load powered by an automotive battery (10 to 14 100°C
Volts) for almost a second if its initial operating temperature is 0.4
under 100°C. For longer periods of operation in the current– 25°C
limited mode, device heatsinking can extend operation from 0.2
several seconds to indefinitely depending on the amount of TJ = – 50°C
0 1 2 3 4 5 6 7 8 9 10
The on–chip circuitry of the MLP2N06CL offers an integrated
current increases. As the NPN turns on, it begins to pull gate 0.6
drive current through R1, dropping the gate drive voltage across ID = 1 A
it, and thus lowering the voltage across the gate–to–source of 0.5
VGS = 4 V
temperature dependent as shown in Figure 3, and decreases 0.4
Since the MLP2N06CL continues to conduct current and dissi- VGS = 5 V
0.3
pate power during a shorted load condition, it is important to pro-
vide sufficient heatsinking to limit the device junction temperature
0.2
to a maximum of 150°C.
The metal current sense resistor R2 adds about 0.4 ohms to
the power MOSFET’s on–resistance, but the effect of tempera- 0.1
to the lower temperature coefficient of R2. The on–resistance 0
– 50 0 50 100 150
variation with temperature for gate voltages of 4 and 5 Volts is
shown in Figure 5.

MLP2N06CL
100 64.0
BV(DSS) , DRAIN–TO–SOURCE SUSTAINING

EAS , SINGLE PULSE DRAIN–TO–SOURCE
ID = 2 A ID = 20 mA
63.5
AVALANCHE ENERGY (mJ) 80
63.0
VOLTAGE (VOLTS)
60 62.5
62.0
40 61.5
61.0
20
60.5
0 60.0
25 50 75 100 125 150 – 50 0 50 100 150
TJ, STARTING JUNCTION TEMPERATURE (°C) TJ = JUNCTION TEMPERATURE
Figure 6. Maximum Avalanche Energy Figure 7. Drain–Source Sustaining

versus Starting Junction Temperature Voltage Variation With Temperature

VDS =
VGS = 10 V
SINGLE PULSE
TC = 25°C
The maximum drain–to–source voltage that can be contin- dc
uously applied across the MLP2N06CL when it is in current 10 ms
limit is a function of the power that must be dissipated. This 1.0 1 ms
power is determined by the maximum current limit at maxi-
mum rated operating temperature (1.8 A at 150°C) and not
PACKAGE LIMIT
(150 – TA) 0.1
Vsupply = 0.1 1.0 10 100
being used in the application. Safe Operating Area (MLP2N06CL)

MLP2N06CL
1.0
D = 0.5

0.2
0.1
0.05 P(pk)
0.02
PULSE TRAIN SHOWN
0.01 t1 READ TIME AT t1
SINGLE PULSE DUTY CYCLE, D = t1/t2
0.01
1.0E – 05 1.0E – 04 1.0E – 03 1.0E – 02 1.0E – 01 1.0E+00 1.0E+01
t, TIME (s)
Figure 9. Thermal Response (MLP2N06CL)
VDD ton toff

90% 90%
Vin DUT
z = 50 Ω 10%
Rgen INVERTED
50Ω
90%
50 Ω
50% 50%
10%
ACTIVE CLAMPING
voltage elements are strung together; the MLP2N06CL uses ruggedness of at least four times has been observed when
For the MLP2N06CL, the integrated gate–to–source voltage source avalanche mode.

MLP2N06CL
The MLP2N06CL has been designed to allow direct inter- VBAT

G
MCU MLP2N06CL

MOTOROLA
Medium Power Surface Mount Products

TMOS Dual N-Channel MMDF1N05E
Field Effect Transistors
MiniMOS devices are an advanced series of power MOSFETs
which utilize Motorola’s TMOS process. These miniature surface DUAL TMOS MOSFET
mount MOSFETs feature ultra low RDS(on) and true logic level 50 VOLTS
performance. They are capable of withstanding high energy in the 1.5 AMPERE
avalanche and commutation modes and the drain–to–source diode  RDS(on) = 0.30 OHM
has a low reverse recovery time. MiniMOS devices are designed
for use in low voltage, high speed switching applications where
power efficiency is important. Typical applications are dc–dc
converters, and power management in portable and battery D
powered products such as computers, printers, cellular and
cordless phones. They can also be used for low voltage motor
controls in mass storage products such as disk drives and tape
drives. The avalanche energy is specified to eliminate the G
guesswork in designs where inductive loads are switched and offer CASE 751–05, Style 11
additional safety margin against unexpected voltage transients. SO–8
S
• Ultra Low RDS(on) Provides Higher Efficiency and Extends Battery Life
• Logic Level Gate Drive — Can Be Driven by Logic ICs
• Miniature SO–8 Surface Mount Package — Saves Board Space
• Diode Is Characterized for Use In Bridge Circuits Source–1 1 8 Drain–1
• Diode Exhibits High Speed Gate–1 2 7 Drain–1
• Avalanche Energy Specified Source–2 3 6 Drain–2
• Mounting Information for SO–8 Package Provided
Gate–2 4 5 Drain–2
• IDSS Specified at Elevated Temperature
Top View

Drain–to–Source Voltage VDS 50 Volts
Gate–to–Source Voltage — Continuous VGS ± 20 Volts
Drain Current — Continuous ID 2.0 Amps
Drain Current — Pulsed IDM 10
Single Pulse Drain–to–Source Avalanche Energy — Starting TJ = 25°C EAS 300 mJ

(VDD = 25 V, VGS = 10 V, IL = 2 Apk)

Total Power Dissipation @ TA = 25°C PD 2.0 Watts
Thermal Resistance – Junction to Ambient (1) RθJA 62.5 °C/W
Maximum Temperature for Soldering, TL 260 °C
Time in Solder Bath 10 Sec
DEVICE MARKING
F1N05
(1) Mounted on 2” square FR4 board (1” sq. 2 oz. Cu 0.06” thick single sided) with one die operating, 10 sec. max.
Device Reel Size Tape Width Quantity
MMDF1N05ER2 13″ 12 mm embossed tape 2500
REV 4

MMDF1N05E
ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted)
OFF CHARACTERISTICS
Drain–to–Source Breakdown Voltage V(BR)DSS 50 — — Vdc
(VGS = 0, ID = 250 µA)
Zero Gate Voltage Drain Current IDSS — — 250 µAdc
(VDS = 50 V, VGS = 0)
Gate–Body Leakage Current IGSS — — 100 nAdc
(VGS = 20 Vdc, VDS = 0)
Gate Threshold Voltage VGS(th) 1.0 — 3.0 Vdc
(VDS = VGS, ID = 250 µAdc)
Drain–to–Source On–Resistance Ohms
(VGS = 10 Vdc, ID = 1.5 Adc) RDS(on) — — 0.30
(VGS = 4.5 Vdc, ID = 0.6 Adc) RDS(on) — — 0.50
Forward Transconductance (VDS = 15 V, ID = 1.5 A) gFS — 1.5 — mhos
(VDS = 25 VV, VGS = 0,
0
Output Capacitance Coss — 160 —
f = 1.0 MHz)
Reverse Transfer Capacitance Crss — 50 —
Turn–On Delay Time td(on) — — 20 ns
Rise Time ((VDD = 10 V, ID = 1.5 A, RL = 10 Ω, tr — — 30
Turn–Off Delay Time VG = 10 V, RG = 50 Ω) td(off) — — 40
Fall Time tf — — 25
Total Gate Charge Qg — 12.5 — nC
(VDS = 10 V,
V ID = 1.5
1 5 A,
A
Gate–Source Charge Qgs — 1.9 —
VGS = 10 V)
Gate–Drain Charge Qgd — 3.0 —
SOURCE–DRAIN DIODE CHARACTERISTICS (TC = 25°C)

Forward Voltage(1) ((IS = 1.5 A, VGS = 0 V)) VSD — — 1.6 V
Reverse Recovery Time (dIS/dt = 100 A/µs) trr — 45 — ns
(1) Pulse Test: Pulse Width ≤ 300 µs, Duty Cycle ≤ 2.0%.

MMDF1N05E
10 10
10 V 6V TJ = 25°C – 55°C
8V 5V VDS ≥ 10 V 25°C
8

100°C
4.5 V
6 6
4V
4 4
25°C
VGS = 3.5 V
2 2
100°C
– 55°C
0 0
0 2 4 6 8 10 0 1 2 3 4 5 6 7 8
Figure 1. On–Region Characteristics Figure 2. Transfer Characteristics

RDS(on) , DRAIN–TO–SOURCE ON–RESISTANCE (OHMS)
RDS(on) , DRAIN–TO–SOURCE ON–RESISTANCE

0.5 1.8
VGS = 10 V 1.6 VGS = 10 V
0.4
1.4 ID = 1.5 A
(NORMALIZED) 1.2
0.3
1
0.8
0.2 100°C
0.6
25°C
0.1 0.4
– 55°C 0.2
0 0
0 2 4 6 8 – 50 – 25 0 25 50 75 100 125 150
ID, DRAIN CURRENT (AMPS) TJ, JUNCTION TEMPERATURE (°C)
Figure 3. On–Resistance versus Drain Current Figure 4. On–Resistance Variation with Temperature
V GS(th), GATE THRESHOLD VOLTAGE (NORMALIZED)
RDS(on) , DRAIN–TO–SOURCE RESISTANCE (OHMS)
0.5 1.2
ID = 1.5 A VDS = VGS

0.4 1.1
VGS = 0 ID = 1 mA
0.3 1
0.2 0.9
0.1 0.8
0 0.7
2 3 4 5 6 7 8 9 10 – 50 – 25 0 25 50 75 100 125 150
TJ, JUNCTION TEMPERATURE TJ, JUNCTION TEMPERATURE (°C)
Figure 5. On Resistance versus Figure 6. Gate Threshold Voltage Variation

Gate–To–Source Voltage with Temperature

MMDF1N05E
VGS 0 VDS
1200 12
Ciss
VGS , GATE–TO–SOURCE VOLTAGE (VOLTS)

1000 Crss TJ = 25°C 10 VDS = 25 V
ID = 1.2 A
C, CAPACITANCE (pF)
800 8
VDS = 0 VGS = 0
600 6
400 Ciss 4
Coss
200 2
Crss
0 0
20 15 10 5 0 5 10 15 20 25 0 2 4 6 8 10 12 14 16
GATE–TO–SOURCE OR DRAIN–TO–SOURCE VOLTAGE (VOLTS) Qg, TOTAL GATE CHARGE (nC)
Figure 7. Capacitance Variation Figure 8. Gate Charge versus

Gate–To–Source Voltage
SAFE OPERATING AREA INFORMATION 100
VGS = 20 V Mounted on 2” sq. FR4 board (1” sq. 2 oz. Cu 0.06”
thick single sided) with one die operating, 10s max.
SINGLE PULSE
Forward Biased Safe Operating Area TC = 25°C

The FBSOA curves define the maximum drain–to–source 10
10 µs
voltage and drain current that a device can safely handle 100 µs
when it is forward biased, or when it is on, or being turned on. 10 ms
Because these curves include the limitations of simultaneous 1
dc
high voltage and high current, up to the rating of the device,
curves are based on a case temperature of 25°C and a maxi- 0.1
mum junction temperature of 150°C. Limitations for repetitive RDS(on) LIMIT
pulses at various case temperatures can be determined by THERMAL LIMIT
using the thermal response curves. Motorola Application PACKAGE LIMIT
0.01
Note, AN569, “Transient Thermal Resistance — General 0.1 1 10 100
Data and Its Use” provides detailed instructions. VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
Figure 9. Maximum Rated Forward Biased

Safe Operating Area
10
Rthja(t), EFFECTIVE TRANSIENT
THERMAL RESISTANCE
1 D = 0.5
0.2
0.1
0.1
0.05 Normalized to θja at 10s.
0.02 Chip 0.0175 Ω 0.0710 Ω 0.2706 Ω 0.5776 Ω 0.7086 Ω
0.01
0.01
0.0154 F 0.0854 F 0.3074 F 1.7891 F 107.55 F
Ambient
SINGLE PULSE
0.001
1.0E–05 1.0E–04 1.0E–03 1.0E–02 1.0E–01 1.0E+00 1.0E+01 1.0E+02 1.0E+03
t, TIME (s)

MOTOROLA
 Data Sheet
Designer's
Medium Power Surface Mount Products MMDF2C01HD

Complementary TMOS Motorola Preferred Device
Field Effect Transistors COMPLEMENTARY

MiniMOS devices are an advanced series of power MOSFETs DUAL TMOS POWER FET
which utilize Motorola’s High Cell Density HDTMOS process. 2.0 AMPERES
These miniature surface mount MOSFETs feature ultra low RDS(on) 12 VOLTS
and true logic level performance. They are capable of withstanding RDS(on) = 0.045 OHM
(N–CHANNEL)
high energy in the avalanche and commutation modes and the 
drain–to–source diode has a very low reverse recovery time. RDS(on) = 0.18 OHM
MiniMOS devices are designed for use in low voltage, high speed (P–CHANNEL)
switching applications where power efficiency is important. Typical
applications are dc–dc converters, and power management in D
portable and battery powered products such as computers, N–Channel
printers, cellular and cordless phones. They can also be used for
low voltage motor controls in mass storage products such as disk
drives and tape drives.
G CASE 751–05, Style 14
• Ultra Low RDS(on) Provides Higher Efficiency and Extends SO–8
Battery Life
• Logic Level Gate Drive — Can Be Driven by Logic ICs S
• Miniature SO–8 Surface Mount Package — Saves Board Space D
• Diode Is Characterized for Use In Bridge Circuits P–Channel
• Diode Exhibits High Speed, With Soft Recovery N–Source 1 8 N–Drain
• IDSS Specified at Elevated Temperature N–Gate 2 7 N–Drain
• Mounting Information for SO–8 Package Provided P–Source 3 6 P–Drain
G
P–Gate 4 5 P–Drain
S Top View
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)(1)
Drain–to–Source Voltage N–Channel VDSS 20 Vdc
P–Channel 12
Gate–to–Source Voltage VGS ± 8.0 Vdc
Drain Current — Continuous N–Channel ID 5.2 A
P–Channel 3.4
— Pulsed N–Channel IDM 48
P–Channel 17
Operating and Storage Temperature Range TJ and Tstg – 55 to 150 °C
Total Power Dissipation @ TA= 25°C (2) PD 2.0 Watts
Thermal Resistance — Junction to Ambient (2) RθJA 62.5 °C/W
Maximum Lead Temperature for Soldering Purposes, 1/8″ from case for 10 seconds. TL 260 °C
DEVICE MARKING
D2C01
(1) Negative signs for P–Channel device omitted for clarity.
MMDF2C01HDR2 13″ 12 mm embossed tape 2500 units
REV 4

MMDF2C01HD
ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted)(1)
Characteristic Symbol Polarity Min Typ Max Unit
OFF CHARACTERISTICS
Drain–Source Breakdown Voltage V(BR)DSS (N) 20 — — Vdc
(VGS = 0 Vdc, ID = 250 µAdc) (P) 12 — —
(VGS = 0 Vdc, VDS = 20 Vdc) (N) — — 1.0
(VGS = 0 Vdc, VDS = 12 Vdc) (P) — — 1.0
Gate–Body Leakage Current IGSS nAdc
(VGS = ± 8.0 Vdc, VDS = 0) — — — 100
Gate Threshold Voltage VGS(th) (N) 0.7 0.8 1.1 Vdc
(VDS = VGS, ID = 250 µAdc) (P) 0.7 1.0 1.1
Drain–to–Source On–Resistance RDS(on) Ohm
(VGS = 4.5 Vdc, ID = 4.0 Adc) (N) — 0.035 0.045
(VGS = 4.5 Vdc, ID = 2.0 Adc) (P) — 0.16 0.18
(VGS = 2.7 Vdc, ID = 2.0 Adc) (N) — 0.043 0.055
(VGS = 2.7 Vdc, ID = 1.0 Adc) (P) — 0.2 0.22
Forward Transconductance gFS mhos
(VDS = 2.5 Adc, ID = 2.0 Adc) (N) 3.0 6.0 —
(VDS = 2.5 Adc, ID = 1.0 Adc) (P) 3.0 4.75 —
Input Capacitance Ciss (N) — 425 595 pF
(P) — 530 740
Output Capacitance (VDS = 10 Vdc, VGS = 0 Vdc, Coss (N) — 270 378
f = 1.0 MHz) (P) — 410 570
Transfer Capacitance Crss (N) — 115 230
(P) — 177 250
Turn–On Delay Time td(on) (N) — 13 26 ns
((VDD = 6.0 Vdc, ID = 4.0 Adc, (P) — 21 45
Rise Time VGS = 2.7 Vdc, tr (N) — 60 120
RG = 2.3 Ω) (P) — 156 315
Turn–Off Delay Time (VDD = 6.0 Vdc, ID = 2.0 Adc, td(off) (N) — 20 40
VGS = 2.7 Vdc,
dc, (P) — 38 75
Fall Time RG = 6.0 Ω) tf (N) — 29 58
(P) — 68 135
Turn–On Delay Time td(on) (N) — 10 20
((VDS = 6.0 Vdc, ID = 4.0 Adc, (P) — 16 35
RG = 2.3 Ω) (P) — 44 90
Turn–Off Delay Time (VDS = 6.0 Vdc, ID = 2.0 Adc, td(off) (N) — 24 48
VGS = 4.55 Vdc,
dc, (P) — 68 135
Fall Time RG = 6.0 Ω) tf (N) — 28 56
(P) — 54 110
Total Gate Charge QT (N) — 9.2 13 nC
(P) — 9.3 13
Gate–Source Charge (VDS = 10 Vdc, ID = 4.0 Adc, Q1 (N) — 1.3 —
VGS = 4.5 Vdc) (P) — 0.8 —
Gate–Drain Charge (VDS = 6.0 Vdc, ID = 2.0 Adc, Q2 (N) — 3.5 —
VGS = 4.5 Vdc)) (P) — 4.0 —
Q3 (N) — 3.0 —
(P) — 3.0 —
(1) Negative signs for P–Channel device omitted for clarity. (continued)

MMDF2C01HD
ELECTRICAL CHARACTERISTICS — continued (TA = 25°C unless otherwise noted)(1)
Forward Voltage(2) (IS = 4.0 Adc, VGS = 0 Vdc) VSD (N) — 0.95 1.1 Vdc
(IS = 2.0 Adc, VGS = 0 Vdc) (P) — 1.69 2.0
Reverse Recovery Time trr (N) — 38 — ns
(P) — 48 —
ta (N) — 17 —
( F = IS,
(I (P) — 23 —
dIS/dt = 100 A/µs) tb (N) — 22 —
(P) — 25 —
Reverse Recovery Stored Charge QRR (N) — 0.028 — µC
(P) — 0.05 —
N–Channel P–Channel
8 4
VGS = 8 V TJ = 25°C VGS = 8 V 2.5 V TJ = 25°C
4.5 V
2.3 V
3.1 V 4.5 V

2.5 V 2.1 V 3.1 V 2.3 V
6 2.7 V 3
2.7 V
2.1 V
4 1.9 V 2
1.7 V 1.9 V
2 1
1.7 V
1.5 V
1.3 V 1.5 V
0 0
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS) VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
Figure 1. On–Region Characteristics Figure 1. On–Region Characteristics
8 4
VDS ≥ 10 V VDS ≥ 10 V
6 3
4 100°C 2
25°C
100°C 25°C
2 TJ = – 55°C 1
TJ = – 55°C
0 0
1 1.2 1.4 1.6 1.8 2 2.2 1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 2.8
Figure 2. Transfer Characteristics Figure 2. Transfer Characteristics

MMDF2C01HD
RDS(on) , DRAIN–TO–SOURCE RESISTANCE (OHMS) N–Channel P–Channel

0.07 0.35
TJ = 25°C TJ = 25°C
ID = 2 A ID = 1 A
0.30
0.06
0.25
0.05
0.20
0.04
0.15
0.03 0.1
0 2 4 6 8 0 2 4 6 8
Figure 3. On–Resistance versus Figure 3. On–Resistance versus

Gate–To–Source Voltage Gate–To–Source Voltage

0.050 0.30
TJ = 25°C TJ = 25°C
0.045 VGS = 2.7 V 0.25
0.040 0.20 VGS = 2.7 V
4.5 V 4.5 V
0.035 0.15
0.030 0.10
0 2 4 6 8 0 0.8 1.6 2.4 3.2 4
ID, DRAIN CURRENT (AMPS) ID, DRAIN CURRENT (AMPS)
Figure 4. On–Resistance versus Drain Current Figure 4. On–Resistance versus Drain Current
and Gate Voltage and Gate Voltage
2 2
RDS(on) , DRAIN–TO–SOURCE RESISTANCE
VGS = 4.5 V VGS = 4.5 V

ID = 4 A ID = 2 A
1.5 1.5
(NORMALIZED)
(NORMALIZED)
1 1
0.5 0.5
0 0
– 50 – 25 0 25 50 75 100 125 150 – 50 – 25 0 25 50 75 100 125 150
Figure 5. On–Resistance Variation with Figure 5. On–Resistance Variation with

Temperature Temperature

MMDF2C01HD
100 1000
VGS = 0 V VGS = 0 V
TJ = 125°C
I DSS , LEAKAGE (nA)

TJ = 125°C
10 100
100°C
10
0 2 4 6 8 10 12 0 4 8 12
Figure 6. Drain–To–Source Leakage Figure 6. Drain–To–Source Leakage

Current versus Voltage Current versus Voltage
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted The capacitance (Ciss) is read from the capacitance curve at
by recognizing that the power MOSFET is charge controlled. a voltage corresponding to the off–state condition when cal-
The lengths of various switching intervals (∆t) are deter- culating td(on) and is read at a voltage corresponding to the
mined by how fast the FET input capacitance can be charged on–state when calculating td(off).
by current from the generator.
The published capacitance data is difficult to use for calculat- At high switching speeds, parasitic circuit elements com-
ing rise and fall because drain–gate capacitance varies plicate the analysis. The inductance of the MOSFET source
greatly with applied voltage. Accordingly, gate charge data is lead, inside the package and in the circuit wiring which is
used. In most cases, a satisfactory estimate of average input common to both the drain and gate current paths, produces a
current (IG(AV)) can be made from a rudimentary analysis of voltage at the source which reduces the gate drive current.
the drive circuit so that The voltage is determined by Ldi/dt, but since di/dt is a func-
t = Q/IG(AV) tion of drain current, the mathematical solution is complex.
The MOSFET output capacitance also complicates the
During the rise and fall time interval when switching a resis-
mathematics. And finally, MOSFETs have finite internal gate
tive load, VGS remains virtually constant at a level known as
resistance which effectively adds to the resistance of the
the plateau voltage, VSGP. Therefore, rise and fall times may
driving source, but the internal resistance is difficult to mea-
be approximated by the following:
sure and, consequently, is not specified.
tr = Q2 x RG/(VGG – VGSP) The resistive switching time variation versus gate resis-
tf = Q2 x RG/VGSP tance (Figure 9) shows how typical switching performance is
where affected by the parasitic circuit elements. If the parasitics
were not present, the slope of the curves would maintain a
VGG = the gate drive voltage, which varies from zero to VGG value of unity regardless of the switching speed. The circuit
RG = the gate drive resistance used to obtain the data is constructed to minimize common
and Q2 and VGSP are read from the gate charge curve. inductance in the drain and gate circuit loops and is believed
readily achievable with board mounted components. Most
During the turn–on and turn–off delay times, gate current is
power electronic loads are inductive; the data in the figure is
not constant. The simplest calculation uses appropriate val-
taken with a resistive load, which approximates an optimally
ues from the capacitance curves in a standard equation for
snubbed inductive load. Power MOSFETs may be safely op-
voltage change in an RC network. The equations are:
erated into an inductive load; however, snubbing reduces
td(on) = RG Ciss In [VGG/(VGG – VGSP)] switching losses.
td(off) = RG Ciss In (VGG/VGSP)

MMDF2C01HD
2000 2000
VDS = 0 V VGS = 0 V TJ = 25°C VDS = 0 V VGS = 0 V TJ = 25°C
Ciss
1600 Ciss 1600
C, CAPACITANCE (pF)
C, CAPACITANCE (pF)
1200 1200
Crss
800 Crss 800
Ciss Ciss
400 Coss 400 Coss

Crss
Crss
0 0
8 4 0 4 8 12 8 4 0 4 8 12
VGS VDS VGS VDS
GATE–TO–SOURCE OR DRAIN–TO–SOURCE VOLTAGE (VOLTS) GATE–TO–SOURCE OR DRAIN–TO–SOURCE VOLTAGE (Volts)
Figure 7. Capacitance Variation Figure 7. Capacitance Variation
VGS, GATE–TO–SOURCE VOLTAGE (VOLTS)

5 10 5 10
VDS , DRAIN–TO–SOURCE VOLTAGE (VOLTS)

QT VDS , DRAIN–TO–SOURCE VOLTAGE (VOLTS)
QT
4 8 4 8
VGS VGS
VDS VDS
3 6 3 6
Q1 Q2
2 ID = 4 A 4 2 Q1 ID = 2 A 4
TJ = 25°C Q2 TJ = 25°C
1 2 1 2
Q3 Q3
0 0 0 0
0 2 4 6 8 10 0 2 4 6 8 10
QT, TOTAL CHARGE (nC) QT, TOTAL CHARGE (nC)
Figure 8. Gate–To–Source and Drain–To–Source Figure 8. Gate–To–Source and Drain–To–Source

Voltage versus Total Charge Voltage versus Total Charge
100 1000
VDD = 6 V VDD = 6 V
ID = 4 A tr ID = 2 A
VGS = 4.5 V VGS = 4.5 V
TJ = 25°C tf TJ = 25°C
td(off)
t, TIME (ns)
t, TIME (ns)
10 td(on) 100 td(off)

tf
tr
td(on)
1 10
0.1 1 10 100 1 10 100
RG, GATE RESISTANCE (OHMS) RG, GATE RESISTANCE (OHMS)
Figure 9. Resistive Switching Time Figure 9. Resistive Switching Time

Variation versus Gate Resistance Variation versus Gate Resistance

MMDF2C01HD
DRAIN–TO–SOURCE DIODE CHARACTERISTICS
The switching characteristics of a MOSFET body diode di/dts. The diode’s negative di/dt during ta is directly con-
are very important in systems using it as a freewheeling or trolled by the device clearing the stored charge. However,
commutating diode. Of particular interest are the reverse re- the positive di/dt during tb is an uncontrollable diode charac-
covery characteristics which play a major role in determining teristic and is usually the culprit that induces current ringing.
switching losses, radiated noise, EMI and RFI. Therefore, when comparing diodes, the ratio of tb/ta serves
System switching losses are largely due to the nature of as a good indicator of recovery abruptness and thus gives a
the body diode itself. The body diode is a minority carrier de- comparative estimate of probable noise generated. A ratio of
vice, therefore it has a finite reverse recovery time, trr, due to 1 is considered ideal and values less than 0.5 are considered
the storage of minority carrier charge, QRR, as shown in the
snappy.
typical reverse recovery wave form of Figure 14. It is this
Compared to Motorola standard cell density low voltage
stored charge that, when cleared from the diode, passes
MOSFETs, high cell density MOSFET diodes are faster
through a potential and defines an energy loss. Obviously,
repeatedly forcing the diode through reverse recovery further (shorter trr), have less stored charge and a softer reverse re-
increases switching losses. Therefore, one would like a covery characteristic. The softness advantage of the high
diode with short trr and low QRR specifications to minimize cell density diode means they can be forced through reverse
these losses. recovery at a higher di/dt than a standard cell MOSFET
The abruptness of diode reverse recovery effects the diode without increasing the current ringing or the noise gen-
amount of radiated noise, voltage spikes, and current ring- erated. In addition, power dissipation incurred from switching
ing. The mechanisms at work are finite irremovable circuit the diode will be less due to the shorter recovery time and
parasitic inductances and capacitances acted upon by high lower switching losses.
4 2
VV GS= =0 0VV
GS VGS = 0 V
TJTJ= =25°C
25°C TJ = 25°C
I S , SOURCE CURRENT (AMPS)
3 1.5
2 1
1 0.5
0 0
0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8
VSD, SOURCE–TO–DRAIN VOLTAGE (VOLTS) VSD, SOURCE–TO–DRAIN VOLTAGE (VOLTS)
Figure 10. Diode Forward Voltage versus Current Figure 10. Diode Forward Voltage versus Current

MMDF2C01HD
di/dt = 300 A/µs Standard Cell Density
trr
High Cell Density
I S , SOURCE CURRENT
trr
tb
ta
t, TIME
Figure 11. Reverse Recovery Time (trr)
SAFE OPERATING AREA
The Forward Biased Safe Operating Area curves define averaged over a complete switching cycle must not exceed
the maximum simultaneous drain–to–source voltage and (TJ(MAX) – TC)/(RθJC).
drain current that a transistor can handle safely when it is for- A power MOSFET designated E–FET can be safely used
ward biased. Curves are based upon maximum peak junc- in switching circuits with unclamped inductive loads. For reli-
tion temperature and a case temperature (TC) of 25°C. Peak able operation, the stored energy from circuit inductance dis-
repetitive pulsed power limits are determined by using the sipated in the transistor while in avalanche must be less than
thermal response data in conjunction with the procedures the rated limit and must be adjusted for operating conditions
discussed in AN569, “Transient Thermal Resistance – Gen- differing from those specified. Although industry practice is to
eral Data and Its Use.” rate in terms of energy, avalanche energy capability is not a
Switching between the off–state and the on–state may tra- constant. The energy rating decreases non–linearly with an
verse any load line provided neither rated peak current (IDM) increase of peak current in avalanche and peak junction tem-
nor rated voltage (VDSS) is exceeded, and that the transition perature.
time (tr, tf) does not exceed 10 µs. In addition the total power
100 100
VGS = 20 V
SINGLE PULSE 10 µs SINGLE PULSE
100 µs TC = 25°C
TC = 25°C
10 1 ms 10
1 ms
10 ms 10 ms
1 1
dc dc
RDS(on) LIMIT
THERMAL LIMIT 0.1
0.1
PACKAGE LIMIT RDS(on) LIMIT
THERMAL LIMIT
Mounted on 2” sq. FR4 board (1” sq. 2 oz. Cu 0.06”
thick single sided) with one die operating, 10s max. PACKAGE LIMIT
0.01 0.01
0.1 1 10 100 0.1 1 10 100
Figure 12. Maximum Rated Forward Biased Figure 12. Maximum Rated Forward Biased
Safe Operating Area Safe Operating Area

MMDF2C01HD
Rthja(t), EFFECTIVE TRANSIENT 10

THERMAL RESISTANCE
1 D = 0.5
0.2
0.1
0.1
0.02 Chip 0.0175 Ω 0.0710 Ω 0.2706 Ω 0.5776 Ω 0.7086 Ω
0.01
0.01
0.0154 F 0.0854 F 0.3074 F 1.7891 F 107.55 F
Ambient
SINGLE PULSE
0.001
1.0E–05 1.0E–04 1.0E–03 1.0E–02 1.0E–01 1.0E+00 1.0E+01 1.0E+02 1.0E+03
t, TIME (s)
di/dt
IS
trr
ta tb
TIME
tp 0.25 IS
IS
Figure 14. Diode Reverse Recovery Waveform

MOTOROLA
 Data Sheet
MMDF2C02E
Designer's

Complementary TMOS
which utilize Motorola’s TMOS process. These miniature surface 2.5 AMPERES
performance. They are capable of withstanding high energy in the RDS(on) = 0.100 OHM
avalanche and commutation modes and the drain–to–source diode (N–CHANNEL)
has a low reverse recovery time. MiniMOS devices are designed  RDS(on) = 0.25 OHM
for use in low voltage, high speed switching applications where (P–CHANNEL)
N–Channel
drives. The avalanche energy is specified to eliminate the G
guesswork in designs where inductive loads are switched and offer CASE 751–05, Style 14
additional safety margin against unexpected voltage transients. SO–8
S
• Ultra Low RDS(on) Provides Higher Efficiency and Extends
Battery Life D
P–Channel
• Logic Level Gate Drive — Can Be Driven by Logic ICs N–Source 1 8 N–Drain
• Miniature SO–8 Surface Mount Package — Saves Board Space N–Gate 2 7 N–Drain
• Diode Is Characterized for Use In Bridge Circuits
P–Source 3 6 P–Drain
• Diode Exhibits High Speed, with Soft Recovery G
P–Gate 4 5 P–Drain
• Avalanche Energy Specified
• Mounting Information for SO–8 Package Provided Top View
S
Drain–to–Source Voltage VDSS 25 Vdc
Gate–to–Source Voltage VGS ± 20 Vdc
Drain Current — Continuous N–Channel ID 3.6 Adc
P–Channel 2.5
P–Channel 13
Operating and Storage Temperature Range TJ and Tstg – 55 to 150 °C
Single Pulse Drain–to–Source Avalanche Energy — Starting TJ = 25°C EAS mJ
(VDD = 20 V, VGS = 10 V, Peak IL = 9.0 A, L = 6.0 mH, RG = 25 Ω) N–Channel 245
(VDD = 20 V, VGS = 10 V, Peak IL = 7.0 A, L = 10 mH, RG = 25 Ω) P–Channel 245
Maximum Lead Temperature for Soldering, 0.0625″ from case. Time in Solder Bath is 10 seconds. TL 260 °C
DEVICE MARKING
F2C02
MMDF2C02ER2 13″ 12 mm embossed tape 2500 units
REV 4

MMDF2C02E
OFF CHARACTERISTICS
Drain–Source Breakdown Voltage V(BR)DSS Vdc
(VGS = 0 Vdc, ID = 250 µAdc) — 25 — —
Zero Gate Voltage Drain Current IDSS (N) — — 1.0 µAdc
(VDS = 20 Vdc, VGS = 0 Vdc) (P) — — 1.0
Gate–Body Leakage Current (VGS = ± 20 Vdc, VDS = 0) IGSS — — — 100 nAdc
(VDS = VGS, ID = 250 µAdc) — 1.0 2.0 3.0
(VGS = 10 Vdc, ID = 2.2 Adc) (N) — — 0.100
(VGS = 10 Vdc, ID = 2.0 Adc) (P) — — 0.250
(VGS = 4.5 Vdc, ID = 1.0 Adc) (N) — — 0.200
(VGS = 4.5 Vdc, ID = 1.0 Adc) (P) — — 0.400
On–State Drain Current ID(on) (N) 2.0 — — Adc
(VDS = 5.0 Vdc, VGS = 4.5 Vdc) (P) 2.0 — —
(VDS = 3.0 Vdc, ID = 1.5 Adc) (N) 1.0 2.6 —
(VDS = 3.0 Vdc, ID = 1.0 Adc) (P) 1.0 2.8 —
(P) — 340 475
f = 1.0 MHz) (P) — 220 300
(P) — 75 150
((VDD = 10 Vdc, ID = 2.0 Adc, (P) — 20 40
RG = 9.1 Ω) (P) — 40 80
Turn–Off Delay Time (VDD = 10 Vdc, ID = 1.0 Adc, td(off) (N) — 19 38
VGS = 5
5.00 Vdc,
dc, (P) — 53 106
Fall Time RG = 25 Ω) tf (N) — 25 50
(P) — 41 82
Turn–On Delay Time td(on) (N) — 7.0 21
((VDD = 10 Vdc, ID = 2.0 Adc, (P) — 13 26
Rise Time VGS = 10 Vdc, tr (N) — 17 30
RG = 6.0 Ω) (P) — 29 58
VGS = 100 Vdc,
dc, (P) — 30 60
Fall Time RG = 6.0 Ω) tf (N) — 18 30
(P) — 28 56
(P) — 10 15
Gate–Source Charge Q1 (N) — 1.3 —
((VDS = 16 Vdc,, ID = 2.0 Adc,, (P) — 1.0 —
Gate–Drain Charge VGS = 10 Vdc) Q2 (N) — 2.9 —
(P) — 3.5 —
Q3 (N) — 2.7 —
(P) — 3.0 —

MMDF2C02E
(IS = 2.0 Adc, VGS = 0 Vdc) (P) — 1.5 2.0
Reverse Recovery Time trr (N) — 34 66 ns
see Figure 7 (P) — 32 64
ta (N) — 17 —
((IF = IS, (P) — 19 —
dIS/dt = 100 A/µs) tb (N) — 17 —
(P) — 12 —
QRR (N) — 0.025 — µC
(P) — 0.035 —

7 4
VGS = 10 V 3.7 V VGS = 10 7 V 5V TJ = 25°C
4.7 V
6 4.5 V 3.5 V 4.5 V

4.3 V 3.9 V
3
5 4.1 V
3.3 V 4.3 V
4
3.1 V 2 4.1 V
3
2.9 V 3.9 V
2
2.7 V 1
3.7 V
1 2.5 V 3.5 V
TJ = 25°C 3.3 V
0 0
0 0.25 0.5 0.75 1 1.25 1.5 1.75 2 0 0.4 0.8 1.2 1.6 2
7 4
VDS ≥ 10 V VDS ≥ 10 V
6 TJ = 25°C
3
5
4 100°C 100°C
2
3 25°C
25°C
TJ = –55°C
2
1
1
TJ = –55°C
0 0
1.5 2 2.5 3 3.5 4 2.5 3 3.5 4 4.5

MMDF2C02E

0.6 0.6
ID = 3.5 A ID = 1 A
TJ = 25°C TJ = 25°C
0.5 0.5
0.4 0.4
0.3 0.3
0.2 0.2
0.1 0.1
0 0
2 3 4 5 6 7 8 9 10 3 4 5 6 7 8 9 10

Gate–to–Source Voltage Gate–to–Source Voltage

0.15 0.6
TJ = 25°C
TJ = 25°C
VGS = 4.5 0.5
0.1
0.4
10 V
VGS = 4.5
0.3
0.05
0.2
10 V
0 0.1
0 1 2 3 4 5 6 7 0 0.5 1 1.5 2
RDS(on) , DRAIN–TO–SOURCE RESISTANCE (NORMALIZED)
RDS(on), DRAIN–TO–SOURCE RESISTANCE (NORMALIZED)
2.0 2.0
VGS = 10 V VGS = 10 V
ID = 3.5 A ID = 2 A
1.5 1.5
1.0 1.0
0.5 0.5
0 0
– 50 – 25 0 25 50 75 100 125 150 – 50 – 25 0 25 50 75 100 125 150
Figure 5. On–Resistance Variation Figure 5. On–Resistance Variation with

with Temperature Temperature

MMDF2C02E
10000 100
VGS = 0 V TJ = 125°C VGS = 0 V
1000 100°C

TJ = 125°C
100 10
25°C
10
100°C
1 1
5 10 15 20 25 0 4 8 12 16 20
Figure 6. Drain–to–Source Leakage Current Figure 6. Drain–to–Source Leakage Current

versus Voltage versus Voltage
Switching behavior is most easily modeled and predicted During the turn–on and turn–off delay times, gate current is
by recognizing that the power MOSFET is charge controlled. not constant. The simplest calculation uses appropriate val-
The lengths of various switching intervals (∆t) are deter- ues from the capacitance curves in a standard equation for
mined by how fast the FET input capacitance can be charged voltage change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG – VGSP)]
The published capacitance data is difficult to use for calculat-
ing rise and fall because drain–gate capacitance varies td(off) = RG Ciss In (VGG/VGSP)
greatly with applied voltage. Accordingly, gate charge data is
used. In most cases, a satisfactory estimate of average input The capacitance (Ciss) is read from the capacitance curve at
current (IG(AV)) can be made from a rudimentary analysis of a voltage corresponding to the off–state condition when cal-
the drive circuit so that culating td(on) and is read at a voltage corresponding to the
on–state when calculating td(off).
t = Q/IG(AV)
During the rise and fall time interval when switching a resis- At high switching speeds, parasitic circuit elements com-
tive load, VGS remains virtually constant at a level known as plicate the analysis. The inductance of the MOSFET source
the plateau voltage, VSGP. Therefore, rise and fall times may lead, inside the package and in the circuit wiring which is
be approximated by the following: common to both the drain and gate current paths, produces a
tr = Q2 x RG/(VGG – VGSP) voltage at the source which reduces the gate drive current.
The voltage is determined by Ldi/dt, but since di/dt is a func-
tf = Q2 x RG/VGSP tion of drain current, the mathematical solution is complex.
where The MOSFET output capacitance also complicates the
VGG = the gate drive voltage, which varies from zero to VGG mathematics. And finally, MOSFETs have finite internal gate
RG = the gate drive resistance driving source, but the internal resistance is difficult to mea-
and Q2 and VGSP are read from the gate charge curve. sure and, consequently, is not specified.

MMDF2C02E
snappy.

trr
High Cell Density
trr
tb
ta
t, TIME

MMDF2C02E
SAFE OPERATING AREA
The Forward Biased Safe Operating Area curves define able operation, the stored energy from circuit inductance dis-
the maximum simultaneous drain–to–source voltage and sipated in the transistor while in avalanche must be less than
drain current that a transistor can handle safely when it is for- the rated limit and must be adjusted for operating conditions
ward biased. Curves are based upon maximum peak junc- differing from those specified. Although industry practice is to
tion temperature and a case temperature (TC) of 25°C. Peak rate in terms of energy, avalanche energy capability is not a
repetitive pulsed power limits are determined by using the constant. The energy rating decreases non–linearly with an
thermal response data in conjunction with the procedures increase of peak current in avalanche and peak junction tem-
discussed in AN569, “Transient Thermal Resistance – Gen-
perature.
eral Data and Its Use.”
Although many E–FETs can withstand the stress of drain–
Switching between the off–state and the on–state may tra-
verse any load line provided neither rated peak current (IDM) to–source avalanche at currents up to rated pulsed current
nor rated voltage (VDSS) is exceeded, and that the transition (IDM), the energy rating is specified at rated continuous cur-
time (tr, tf) does not exceed 10 µs. In addition the total power rent (ID), in accordance with industry custom. The energy rat-
averaged over a complete switching cycle must not exceed ing must be derated for temperature as shown in the
(TJ(MAX) – TC)/(RθJC). accompanying graph (Figure 9). Maximum energy at cur-
A power MOSFET designated E–FET can be safely used rents below rated continuous ID can safely be assumed to
in switching circuits with unclamped inductive loads. For reli- equal the values indicated.
100 100
VGS = 20 V Mounted on 2” sq. FR4 board (1” sq. 2 oz. Cu 0.06” Mounted on 2” sq. FR4 board (1” sq. 2 oz. Cu 0.06”
VGS = 20 V
thick single sided) with one die operating, 10s max. thick single sided) with one die operating, 10s max.
SINGLE PULSE SINGLE PULSE
TC = 25°C
I D , DRAIN CURRENT (AMPS) TC = 25°C

10 10 µs 10 10 µs
100 µs 100 µs
10 ms 10 ms
1 dc 1 dc
0.1 0.1
RDS(on) LIMIT RDS(on) LIMIT
THERMAL LIMIT THERMAL LIMIT
PACKAGE LIMIT PACKAGE LIMIT
0.01 0.01
0.1 1 10 100 0.1 1 10 100
280 280
I pk = 9 A I pk = 7 A
EAS, SINGLE PULSE DRAIN-TO-SOURCE
240 240
AVALANCHE ENERGY (mJ)
200 200
160 160
120 120
80 80
40 40
0 0
25 50 75 100 125 150 25 50 75 100 125 150
TJ, STARTING JUNCTION TEMPERATURE (°C) TJ, STARTING JUNCTION TEMPERATURE (°C)
Figure 9. Maximum Avalanche Energy versus Figure 9. Maximum Avalanche Energy versus
Starting Junction Temperature Starting Junction Temperature

MMDF2C02E
10

THERMAL RESISTANCE
1 D = 0.5
0.2
0.1
0.1
0.02 Chip 0.0175 Ω 0.0710 Ω 0.2706 Ω 0.5776 Ω 0.7086 Ω
0.01
0.01
0.0154 F 0.0854 F 0.3074 F 1.7891 F 107.55 F
Ambient
SINGLE PULSE
0.001
1.0E–05 1.0E–04 1.0E–03 1.0E–02 1.0E–01 1.0E+00 1.0E+01 1.0E+02 1.0E+03
t, TIME (s)
di/dt
IS
trr
ta tb
TIME
tp 0.25 IS
IS

MOTOROLA
 Data Sheet
Designer's


high energy in the avalanche and commutation modes and the (N–CHANNEL)
drain–to–source diode has a very low reverse recovery time. 
RDS(on) = 0.160 OHM
MiniMOS devices are designed for use in low voltage, high speed (P–CHANNEL)
portable and battery powered products such as computers, N–Channel
drives and tape drives. The avalanche energy is specified to
G
eliminate the guesswork in designs where inductive loads are
CASE 751–05, Style 14
switched and offer additional safety margin against unexpected
SO–8
voltage transients. S
• Ultra Low RDS(on) Provides Higher Efficiency and Extends
Battery Life D
P–Channel
• Logic Level Gate Drive — Can Be Driven by Logic ICs N–Source 1 8 N–Drain
• Miniature SO–8 Surface Mount Package — Saves Board Space N–Gate 2 7 N–Drain
• Diode Is Characterized for Use In Bridge Circuits 3 6
P–Source P–Drain
• Diode Exhibits High Speed, With Soft Recovery G
• Avalanche Energy Specified P–Gate 4 5 P–Drain
Top View
S
Drain–to–Gate Voltage (RGS = 1.0 mΩ) VDGR 20 Vdc
P–Channel 3.3
P–Channel 20
(VDD = 20 V, VGS = 5.0 V, Peak IL = 9.0 A, L = 10 mH, RG = 25 Ω) N–Channel 405
(VDD = 20 V, VGS = 5.0 V, Peak IL = 6.0 A, L = 18 mH, RG = 25 Ω) P–Channel 324
DEVICE MARKING
D2C02
REV 4

MMDF2C02HD
OFF CHARACTERISTICS
(VGS = 0 Vdc, ID = 250 µAdc) — 20 — —
(VDS = 20 Vdc, VGS = 0 Vdc) (P) — — 1.0
(VDS = VGS, ID = 250 µAdc) — 1.0 1.5 2.0
(VGS = 4.5 Vdc, ID = 1.5 Adc) (N) — 0.074 0.100
(VGS = 4.5 Vdc, ID = 1.0 Adc) (P) — 0.152 0.180
(VGS = 10 Vdc, ID = 3.0 Adc) (N) — 0.058 0.090
(VGS = 10 Vdc, ID = 2.0 Adc) (P) — 0.118 0.160
(VDS = 3.0 Vdc, ID = 1.5 Adc) (N) 2.0 3.88 —
(VDS = 3.0 Vdc, ID = 1.0 Adc) (P) 2.0 3.0 —
(P) — 420 588
f = 1.0 MHz) (P) — 290 406
(P) — 116 232
((VDD = 10 Vdc, ID = 3.0 Adc, (P) — 19 38
RG = 6.0 Ω) (P) — 66 132
VGS = 4.5 Vdc, (P) — 25 50
Fall Time RG = 6.0 Ω) tf (N) — 20 40
(P) — 37 74
Turn–On Delay Time td(on) (N) — 7.0 21
((VDD = 10 Vdc,, ID = 3.0 Adc,, (P) — 11 22
RG = 6.0 Ω) (P) — 21 42
VGS = 10 Vdc,, (P) — 45 90
Fall Time RG = 6.0 Ω) tf (N) — 21 42
(P) — 36 72
(P) — 15 20
VGS = 10 Vdc) (P) — 1.2 —
Gate–Drain Charge (VDS = 16 Vdc, ID = 2.0 Adc, Q2 (N) — 2.8 —
VGS = 10 Vdc)) (P) — 5.0 —
Q3 (N) — 2.4 —
(P) — 4.0 —

MMDF2C02HD
(IS = 2.0 Adc, VGS = 0 Vdc) (P) — 1.5 2.1
(P) — 38 —
(IS = 3.0 Adc, VAS = 0 Vdc, ta (N) — 18 —
dIS/dt = 100 A/µs) (P) — 17 —
(IS = 2.0 Adc, VAS = 0 Vdc, tb (N) — 5.0 —

µ )
dIS/dt = 100 A/µs) (P) — 21 —
Reverse Recovery Stored Charge QRR (N) — 0.025 — µC
(P) — 0.034 —

6 4
VGS = 10 V 3.5 V TJ = 25°C VGS = 10 V 4.5 V 3.9 V 3.7 V TJ = 25°C
4.5 V 3.3 V
5 3.7 V

3.9 V 3.5 V
3
4
3.1 V
3.3 V
3 2
2.9 V 3.1 V
2
1 2.9 V
2.7 V
1 2.7 V
2.5 V
2.5 V
0 0
0 0.2 0.4 0.6 0.8 1 1.2 1.4
1.6 1.8 2 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
6 4
VDS ≥ 10 V VDS ≥ 10 V
3
4
TJ = 100°C
2
25°C
2
– 55°C 1
100°C 25°C
TJ = – 55°C
0 0
1 1.4 1.8 2.2 2.6 3 3.4 1.0 1.5 2.0 2.5 3.0 3.5

MMDF2C02HD

0.6 0.6
ID = 1.5 A ID = 1 A
TJ = 25°C TJ = 25°C
0.4 0.4
0.2 0.2
0 0
0 1 2 3 4 5 6 7 8 9 10 0 2 4 6 8 10


0.08 0.20
TJ = 25°C TJ = 25°C
VGS = 4.5 V
0.16 VGS = 4.5 V

0.07
0.12
10 V
0.06 10 V
0.08
0.05 0.04
0 1 2 3 4 5 6 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
1.6 1.6
VGS = 10 V
VGS = 10 V
ID = 2 A
ID = 1.5 A
1.4 1.4
(NORMALIZED)
(NORMALIZED)
1.2 1.2
1 1.0
0.8 0.8
0.6 0.6
– 50 – 25 0 25 50 75 100 125 150 – 50 – 25 0 25 50 75 100 125 150


MMDF2C02HD
1000 100
VGS = 0 V VGS = 0 V
TJ = 125°C
TJ = 125°C
I DSS, LEAKAGE (nA)

100
100°C 10
25°C 100°C
10
1 1
0 4 8 12 16 20 0 5 10 15 20

Switching behavior is most easily modeled and predicted td(off) = RG Ciss In (VGG/VGSP)
by recognizing that the power MOSFET is charge controlled.
The lengths of various switching intervals (∆t) are deter- The capacitance (Ciss) is read from the capacitance curve at
mined by how fast the FET input capacitance can be charged a voltage corresponding to the off–state condition when cal-
by current from the generator. culating td(on) and is read at a voltage corresponding to the
During the rise and fall time interval when switching a resis- The MOSFET output capacitance also complicates the
tive load, VGS remains virtually constant at a level known as mathematics. And finally, MOSFETs have finite internal gate
the plateau voltage, VSGP. Therefore, rise and fall times may resistance which effectively adds to the resistance of the
be approximated by the following: driving source, but the internal resistance is difficult to mea-
During the turn–on and turn–off delay times, gate current is power electronic loads are inductive; the data in the figure is
not constant. The simplest calculation uses appropriate val- taken with a resistive load, which approximates an optimally
ues from the capacitance curves in a standard equation for snubbed inductive load. Power MOSFETs may be safely op-
voltage change in an RC network. The equations are: erated into an inductive load; however, snubbing reduces

MMDF2C02HD
1400 1200
VDS = 0 V VGS = 0 V TJ = 25°C VDS = 0 V VGS = 0 V TJ = 25°C
1200 Ciss Ciss
1000
C, CAPACITANCE (pF)
C, CAPACITANCE (pF)
1000
800
800
Crss 600
600 Crss Ciss
Ciss
400
400
Coss Coss
200 200
Crss
Crss
0
10 5 0 5 10 15 20 10 5 0 5 10 15 20
VGS VDS VGS VDS
GATE–TO–SOURCE OR DRAIN–TO–SOURCE VOLTAGE (Volts) GATE–TO–SOURCE OR DRAIN–TO–SOURCE VOLTAGE (Volts)
12 18
12 24
VGS, GATE-TO-SOURCE VOLTAGE (VOLTS)

v DS , DRAIN–TO–SOURCE VOLTAGE (VOLTS)
, DRAIN-TO-SOURCE VOLTAGE (VOLTS)

QT QT
10 20 10 15
VGS VGS
8 16 8 VDS 12
6 ID = 3 A 12 6 9
TJ = 25°C
Q1
4 Q2 8 4 Q1 Q2 6
ID = 2 A
TJ = 25°C
2 4 2 3
Q3 VDS Q3
0 0 0
V
0
0 2 4 6 8 10 12 14 0 4 8 12 16
QT, TOTAL GATE CHARGE (nC) QT, TOTAL GATE CHARGE (nC)

100 1000
VDD = 10 V VDD = 10 V
ID = 3 A ID = 2 A
VGS = 10 V tr VGS = 10 V
TJ = 25°C t TJ = 25°C
d(off)
t, TIME (ns)
t, TIME (ns)
tf
10 100
td(on)
td(off)
tf
tr
td(on)
1 10
1 10 100 1 10 100


MMDF2C02HD
snappy.
3.0 2.0
VGS = 0 V VGS = 0 V
TJ = 25°C TJ = 25°C
2.5
1.6
2.0
1.2
1.5
0.8
1.0
0.5 0.4
0 0
0.50 0.55 0.60 0.65 0.70 0.75 0.80 0.5 0.7 0.9 1.1 1.3 1.5

MMDF2C02HD
trr
High Cell Density
trr
tb
ta
t, TIME
SAFE OPERATING AREA
perature.
100 100
Mounted on 2” sq. FR4 board (1” sq. 2 oz. Cu 0.06” VGS = 20 V Mounted on 2” sq. FR4 board (1” sq. 2 oz. Cu 0.06”
VGS = 20 V
thick single sided) with one die operating, 10s max. thick single sided) with one die operating, 10s max.
SINGLE PULSE SINGLE PULSE
TC = 25°C
TC = 25°C 100 µs
10 100 µs 10
1 ms 1 ms
10 ms 10 ms
1 1
dc dc
0.1 0.1
RDS(on) LIMIT RDS(on) LIMIT
THERMAL LIMIT THERMAL LIMIT
PACKAGE LIMIT PACKAGE LIMIT
0.01 0.01
0.1 1 10 100 0.1 1 10 100

MMDF2C02HD
450 350
ID = 9 A ID = 6 A
EAS, SINGLE PULSE DRAIN–TO–SOURCE

400
300
350

250
300
250 200
200 150
150
100
100
50
50
0 0
25 50 75 100 125 150 25 50 75 100 125 150
10
THERMAL RESISTANCE
1 D = 0.5
0.2
0.1
0.1
0.02 Chip 0.0175 Ω 0.0710 Ω 0.2706 Ω 0.5776 Ω 0.7086 Ω
0.01
0.01
0.0154 F 0.0854 F 0.3074 F 1.7891 F 107.55 F
Ambient
SINGLE PULSE
0.001
1.0E–05 1.0E–04 1.0E–03 1.0E–02 1.0E–01 1.0E+00 1.0E+01 1.0E+02 1.0E+03
t, TIME (s)
di/dt
IS
trr
ta tb
TIME
tp 0.25 IS
IS

MOTOROLA
 Data Sheet
Designer's


high energy in the avalanche and commutation modes and the (N-CHANNEL)
drain-to-source diode has a very low reverse recovery time.  RDS(on) = 0.200 OHM
MiniMOS devices are designed for use in low voltage, high speed (P-CHANNEL)
applications are dc-dc converters, and power management in
portable and battery powered products such as computers, D
printers, cellular and cordless phones. They can also be used for N–Channel
switched and offer additional safety margin against unexpected G CASE 751–05, Style 14
voltage transients. SO–8
• Ultra Low RDS(on) Provides Higher Efficiency and Extends S
Battery Life
• Logic Level Gate Drive — Can Be Driven by Logic ICs D
• Miniature SO-8 Surface Mount Package — Saves Board Space P–Channel
1 8 N–Drain
N–Source
• Diode Exhibits High Speed, With Soft Recovery N–Gate 2 7 N–Drain
• IDSS Specified at Elevated Temperature P–Source 3 6 P–Drain
G
• Avalanche Energy Specified P–Gate 4 5 P–Drain
• Mounting Information for SO-8 Package Provided
S Top View
P–Channel 3.0
Drain Current — Pulsed N–Channel IDM 21
P–Channel 15
(VDD = 30 V, VGS = 5.0 V, Peak IL = 9.0 Apk, L = 8.0 mH, RG = 25 Ω) N–Channel 324
(VDD = 30 V, VGS = 5.0 V, Peak IL = 6.0 Apk, L = 18 mH, RG = 25 Ω) P–Channel 324
DEVICE MARKING
D2C03
REV 4

MMDF2C03HD
OFF CHARACTERISTICS
(VGS = 0 Vdc, ID = 250 µAdc) — 30 — —
(VDS = 30 Vdc, VGS = 0 Vdc) (P) — — 1.0
Gate Threshold Voltage VGS(th) (N) 1.0 1.7 3.0 Vdc
(VDS = VGS, ID = 250 µAdc) (P) 1.0 1.5 2.0
(VGS = 10 Vdc, ID = 3.0 Adc) (N) — 0.06 0.070
(VGS = 10 Vdc, ID = 2.0 Adc) (P) — 0.17 0.200
(VGS = 4.5 Vdc, ID = 1.5 Adc) (N) — 0.065 0.075
(VGS = 4.5 Vdc, ID = 1.0 Adc) (P) — 0.225 0.300
(VDS = 3.0 Vdc, ID = 1.5 Adc) (N) 2.0 3.6 —
(VDS = 3.0 Vdc, ID = 1.0 Adc) (P) 2.0 3.4 —
(P) — 397 550
Output Capacitance Vd VGS = 0
(VDS = 24 Vdc,
Coss (N) — 160 225
Vdc,
(P) — 189 250
f = 1.0 MHz)
(P) — 64 126
Turn–On Delay Time (VDD = 15 Vdc, ID = 3.0 td(on) (N) — 12 24 ns
Adc, (P) — 16 32
RG = 9.1 Ω) (P) — 18 36
Turn–Off Delay Time (VDD = 15 Vdc, ID = 2.0 td(off) (N) — 16 32
Adc, (P) — 63 126
Fall Time VGS = 4.5 Vdc, tf (N) — 19 38
RG = 6.0 Ω) (P) — 194 390
Turn–On Delay Time (VDD = 15 Vdc, ID = 3.0 td(on) (N) — 8.0 16
Adc, (P) — 9.0 18
RG = 9.1 Ω) (P) — 10 20
Turn–Off Delay Time (VDD = 15 Vdc, ID = 2.0 td(off) (N) — 30 60
Adc, (P) — 81 162
Fall Time VGS = 10 Vdc, tf (N) — 23 46
RG = 6.0 Ω) (P) — 192 384
(P) — 14.2 19
VGS = 10 Vdc) (P) — 1.1 —
Gate–Drain Charge (VDS = 24 Vdc, ID = 2.0 Adc, Q2 (N) — 3.5 —
VGS = 10 Vdc)) (P) — 4.5 —
Q3 (N) — 2.8 —
(P) — 3.5 —

MMDF2C03HD
(IS = 2.0 Adc, VGS = 0 Vdc) (P) — 1.82 2.0
(P) — 42 —
ta (N) — 17 —
((IF = IS, (P) — 16 —
dIS/dt = 100 A/µs) tb (N) — 7.0 —
(P) — 26 —
Reverse Recovery Storage Charge QRR (N) — 0.025 — µC
(P) — 0.043 —

6 4
VGS = 10 V 3.9 V 3.5 V VGS = 10 V 4.5 V 3.7 V 3.5 V TJ = 25°C
TJ = 25°C
4.5 V 3.7 V
5

4.3 V 3.9 V
3
4.1 V 3.3 V 3.3 V
4
3 3.1 V 2 3.1 V
2 2.9 V
2.9 V 1
1 2.7 V
2.7 V
2.5 V 2.5 V
0 0
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
6 4
VDS ≥ 10 V VDS ≥ 10 V
5
3
4
TJ = 100°C
3 2
TJ = 100°C
2 25°C
25°C
1
1 – 55°C
– 55°C
0 0
2 2.5 3 3.5 4 1.5 1.7 1.9 2.1 2.3 2.5 2.7 2.9 3.1 3.3 3.5 3.7

MMDF2C03HD

0.6 0.6
ID = 1.5 A ID = 1 A
TJ = 25°C TJ = 25°C
0.5 0.5
0.4 0.4
0.3 0.3
0.2 0.2
0.1 0.1
0 0
2 3 4 5 6 7 8 9 10 0 1 2 3 4 5 6 7 8 9 10


0.08 0.30
TJ = 25°C TJ = 25°C
0.25
0.07
VGS = 4.5 VGS = 4.5 V
0.20
10 V
0.06
0.15
10 V
0.05 0.10
0 0.5 1 1.5 2 2.5 3 0 0.5 1 1.5 2 2.5 3 3.5 4
2.0 1.6
VGS = 10 V VGS = 10 V
ID = 1.5 A ID = 2 A
1.4
1.5
(NORMALIZED)
1.2
1.0
1.0
0.5
0.8
0 0.6
– 50 – 25 0 25 50 75 100 125 150 – 50 – 25 0 25 50 75 100 125 150


MMDF2C03HD
100 1000
VGS = 0 V VGS = 0 V
TJ = 125°C

TJ = 125°C
10 100°C 100
100°C
1 10
0 5 10 15 20 25 30 0 5 10 15 20 25 30

Switching behavior is most easily modeled and predicted td(off) = RG Ciss In (VGG/VGSP)
by recognizing that the power MOSFET is charge controlled.
The lengths of various switching intervals (∆t) are deter- The capacitance (Ciss) is read from the capacitance curve at
mined by how fast the FET input capacitance can be charged a voltage corresponding to the off–state condition when cal-
by current from the generator. culating td(on) and is read at a voltage corresponding to the
During the rise and fall time interval when switching a resis- The MOSFET output capacitance also complicates the
tive load, VGS remains virtually constant at a level known as mathematics. And finally, MOSFETs have finite internal gate
the plateau voltage, VSGP. Therefore, rise and fall times may resistance which effectively adds to the resistance of the
be approximated by the following: driving source, but the internal resistance is difficult to mea-

MMDF2C03HD
1200 VDS = 0 V VGS = 0 V 1200

TJ = 25°C VDS = 0 V VGS = 0 V TJ = 25°C
Ciss
C
1000 1000 iss
C, CAPACITANCE (pF)
C, CAPACITANCE (pF)
800 800
600 Crss 600 Crss

Ciss
Ciss
400 400
Coss
Coss
200 200
Crss
Crss
0 0
10 5 0 5 10 15 20 25 30 10 5 0 5 10 15 20 25 30
VGS VDS VGS VDS
GATE–TO–SOURCE OR DRAIN–TO–SOURCE VOLTAGE (VOLTS) GATE–TO–SOURCE OR DRAIN–TO–SOURCE VOLTAGE (VOLTS)
12 24 12 24


QT QT
10 20
9 18 VGS
VDS VGS
8 VDS 16
6 12 6 ID = 2 A 12
Q1 Q2 TJ = 25°C
Q1 Q2
4 8
3 6
Q3 ID = 3 A 2 4
TJ = 25°C Q3
0 0 0 0
0 2 4 6 8 10 12 0 2 4 6 8 10 12 14 16
Qg, TOTAL GATE CHARGE (nC) Qg, TOTAL GATE CHARGE (nC)

1000 1000
VDD = 15 V VDD = 15 V
ID = 3 A ID = 2 A
VGS = 10 V VGS = 10 V tf
TJ = 25°C TJ = 25°C
100 100 td(off)
t, TIME (ns)
t, TIME (ns)
td(off)
tr tr
tf
10 10 td(on)
td(on)
1 1
1 10 100 1 10 100


MMDF2C03HD
snappy.
3.0 2
TJ = 25°C TJ = 25°C
VGS = 0 V VGS = 0 V
2.5
1.6
IS, SOURCE CURRENT (AMPS)
2.0
1.2
1.5
0.8
1.0
0.5 0.4
0 0
0.5 0.55 0.6 0.65 0.7 0.75 0.8 0.85 0.5 0.7 0.9 1.1 1.3 1.5 1.7 1.9

MMDF2C03HD
trr
High Cell Density
trr
tb
ta
t, TIME
SAFE OPERATING AREA
perature.
100 100
VGS = 20 V VGS = 20 V Mounted on 2” sq. FR4 board (1” sq. 2 oz. Cu 0.06”
SINGLE PULSE 10 µs SINGLE PULSE
TC = 25°C 100 µs TC = 25°C
10 1 ms 10 100 µs
1 ms
10 ms
10 ms
1 dc 1
dc
RDS(on) LIMIT
THERMAL LIMIT
0.1 0.1
PACKAGE LIMIT RDS(on) LIMIT
Mounted on 2” sq. FR4 board (1” sq. 2 oz. Cu 0.06” THERMAL LIMIT
thick single sided) with one die operating, 10s max. PACKAGE LIMIT
0.01 0.01
0.1 1 10 100 0.1 1 10 100

MMDF2C03HD
350 350
ID = 9 A ID = 6 A

300 300

250 250
200 200
150 150
100 100
50 50
0 0
25 50 75 100 125 150 25 50 75 100 125 150
10
THERMAL RESISTANCE
1 D = 0.5
0.2
0.1
0.1
0.02 Chip 0.0175 Ω 0.0710 Ω 0.2706 Ω 0.5776 Ω 0.7086 Ω
0.01
0.01
0.0154 F 0.0854 F 0.3074 F 1.7891 F 107.55 F
Ambient
SINGLE PULSE
0.001
1.0E–05 1.0E–04 1.0E–03 1.0E–02 1.0E–01 1.0E+00 1.0E+01 1.0E+02 1.0E+03
t, TIME (s)
di/dt
IS
trr
ta tb
TIME
tp 0.25 IS
IS

MOTOROLA
Designer's  Data Sheet

Medium Power Surface Mount Products MMDF2N02E
TMOS Dual N-Channel
DUAL TMOS MOSFET
MiniMOS devices are an advanced series of power MOSFETs 3.6 AMPERES
which utilize Motorola’s TMOS process. These miniature surface 25 VOLTS
mount MOSFETs feature ultra low RDS(on) and true logic level
performance. They are capable of withstanding high energy in the
 RDS(on) = 0.1 OHM
avalanche and commutation modes and the drain–to–source diode
for use in low voltage, high speed switching applications where D
converters, and power management in portable and battery
cordless phones. They can also be used for low voltage motor G
controls in mass storage products such as disk drives and tape CASE 751–05, Style 11
drives. The avalanche energy is specified to eliminate the SO–8
S
guesswork in designs where inductive loads are switched and offer
additional safety margin against unexpected voltage transients.
• Logic Level Gate Drive — Can Be Driven by Logic ICs Source–1 1 8 Drain–1
• IDSS Specified at Elevated Temperatures Source–2 3 6 Drain–2
• Avalanche Energy Specified Gate–2 4 5 Drain–2
Top View
Gate–to–Source Voltage — Continuous VGS ± 20 Vdc
Drain Current — Continuous @ TA = 25°C ID 3.6 Adc
Drain Current — Continuous @ TA = 100°C ID 2.5
Drain Current — Single Pulse (tp ≤ 10 µs) IDM 18 Apk
Total Power Dissipation @ TA = 25°C (1) PD 2.0 W
(VDD = 20 Vdc, VGS = 10 Vdc, Peak IL = 9.0 Apk, L = 6.0 mH, RG = 25 Ω) 245
Thermal Resistance, Junction to Ambient (1) RθJA 62.5 °C/W
Maximum Lead Temperature for Soldering Purposes, 0.0625″ from case for 10 seconds TL 260 °C
DEVICE MARKING
F2N02
MMDF2N02ER2 13″ 12 mm embossed tape 2500
REV 4

MMDF2N02E
OFF CHARACTERISTICS
(VGS = 0 Vdc, ID = 250 µAdc) 25 — —

(VDS = 20 Vdc, VGS = 0 Vdc) — — 1.0
(VDS = 20 Vdc, VGS = 0 Vdc, TJ = 125°C) — — 10
Gate–Body Leakage Current (VGS = ± 20 Vdc, VDS = 0) IGSS — — 100 nAdc
(VDS = VGS, ID = 250 µAdc 1.0 2.0 3.0
Static Drain–to–Source On–Resistance RDS(on) Ohm

(VGS = 10 Vdc, ID = 2.2 Adc) — 0.083 0.100
(VGS = 4.5 Vdc, ID = 1.0 Adc) — 0.110 0.200
Forward Transconductance (VDS = 3.0 Vdc, ID = 1.0 Adc) gFS 1.0 2.6 — Mhos
Output Capacitance (VDS = 16 Vdc,
Vd VGS = 0 Vdc,
Vd
Coss — 235 329
f = 1.0 MHz)
Turn–On Delay Time td(on) — 7.0 21 ns
Rise Time (VDD = 10 Vdc, ID = 2.0 Adc, tr — 17 30
VGS = 10 Vdc
Vdc,
Turn–Off Delay Time RG = 6.0 Ω) td(off) — 27 48
Fall Time tf — 18 30
Turn–On Delay Time td(on) — 10 30
VGS = 4.5
4 5 Vdc,
Vdc
Gate Charge QT — 10.6 30 nC
((VDS = 16 Vdc, ID = 2.0 Adc, Q1 — 1.3 —

VGS = 10 Vdc) Q2 — 2.9 —
Q3 — 2.7 —
SOURCE–DRAIN DIODE CHARACTERISTICS
Forward On–Voltage(1) (IS = 2.0 Adc, VGS = 0 Vdc) VSD — 1.0 1.4 Vdc
Reverse Recovery Time trr — 34 66 ns
See Fig
Figure
re 11
((IS = 2.0 Adc, VGS = 0 Vdc, ta — 17 —
dIS/dt = 100 A/µs) tb — 17 —
Reverse Recovery Storage Charge QRR — 0.03 — µC

MMDF2N02E
7 7
VGS = 10 V 3.7 V VDS ≥ 10 V
6 4.5 V 3.5 V 6 TJ = 25°C

4.3 V 3.9 V
5 4.1 V 5
3.3 V
4 4 100°C
3.1 V
3 3
2.9 V 25°C
2 2
2.7 V
1 2.5 V 1
TJ = –55°C
TJ = 25°C
0 0
0 0.25 0.5 0.75 1 1.25 1.5 1.75 2 1.5 2 2.5 3 3.5 4

0.6 0.15
ID = 3.5 A TJ = 25°C
TJ = 25°C
0.5
VGS = 4.5
0.4 0.1
10 V
0.3
0.2 0.05
0.1
0 0
2 3 4 5 6 7 8 9 10 0 1 2 3 4 5 6 7
VGS, GATE–TO–SOURCE VOLTAGE (VOLTS) ID, DRAIN CURRENT (AMPS)
Figure 3. On–Resistance versus Figure 4. On–Resistance versus Drain Current
Gate–to–Source Voltage and Gate Voltage
2.0 10000
VGS = 10 V VGS = 0 V TJ = 125°C
ID = 3.5 A
1.5 1000 100°C

1.0 100
25°C
0.5 10
0 1
– 50 – 25 0 25 50 75 100 125 150 5 10 15 20 25
TJ, JUNCTION TEMPERATURE (°C) VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
Figure 5. On–Resistance Variation with Figure 6. Drain–to–Source Leakage Current

Temperature versus Voltage

MMDF2N02E
t = Q/IG(AV)
1200

12 16
VDS = 0 V VGS = 0 V TJ = 25°C
1000 QT
Ciss
9 VDS VGS 12
C, CAPACITANCE (pF)
800
Crss
600 6 8
Ciss Q1 Q2
400
Coss 3 4
200 ID = 2.3 A
Crss Q3
TJ = 25°C
0 0 0
10 5 0 5 10 15 20 25 0 2 4 6 8 10 12
VGS VDS Qg, TOTAL GATE CHARGE (nC)
GATE–TO–SOURCE OR DRAIN–TO–SOURCE VOLTAGE (VOLTS) Figure 8. Gate–to–Source and
Figure 7. Capacitance Variation Drain–to–Source Voltage versus Total Charge
100 7
VDD = 10 V TJ = 25°C
ID = 2 A 6 VGS = 0 V
td(off)
VGS = 10 V
TJ = 25°C tf
5
tr
4
t, TIME (ns)
10
td(on) 3
1 0
1 10 100 0.5 0.6 0.7 0.8 0.9 1 1.1
RG, GATE RESISTANCE (OHMS) VSD, SOURCE–TO–DRAIN VOLTAGE (VOLTS)
Figure 9. Resistive Switching Time Variation Figure 10. Diode Forward Voltage
versus Gate Resistance versus Current

MMDF2N02E
trr
High Cell Density
trr
tb
ta
t, TIME
SAFE OPERATING AREA
perature.
100 280
I pk = 9 A

SINGLE PULSE 240
TC = 25°C
10 µs
10
100 µs 200
10 ms
160
1 dc
120
80
0.1
RDS(on) LIMIT
THERMAL LIMIT 40
PACKAGE LIMIT
0.01 0
0.1 1 10 100 25 50 75 100 125 150
VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS) TJ, STARTING JUNCTION TEMPERATURE (°C)
Figure 12. Maximum Rated Forward Biased Figure 13. Maximum Avalanche Energy versus
Safe Operating Area Starting Junction Temperature

MMDF2N02E

THERMAL RESISTANCE
1 D = 0.5
0.2
0.1
0.1
0.02 Chip 0.0175 Ω 0.0710 Ω 0.2706 Ω 0.5776 Ω 0.7086 Ω
0.01
0.01
0.0154 F 0.0854 F 0.3074 F 1.7891 F 107.55 F
Ambient
SINGLE PULSE
0.001
1.0E–05 1.0E–04 1.0E–03 1.0E–02 1.0E–01 1.0E+00 1.0E+01 1.0E+02 1.0E+03
t, TIME (s)
di/dt
IS
trr
ta tb
TIME
tp 0.25 IS
IS

MOTOROLA

Medium Power Surface Mount Products MMDF2P01HD
TMOS P-Channel

DUAL TMOS POWER FET
which utilize Motorola’s High Cell Density HDTMOS process. 12 VOLTS
These miniature surface mount MOSFETs feature ultra low RDS(on) RDS(on) = 0.18 OHM
and true logic level performance. They are capable of withstanding
drain–to–source diode has a very low reverse recovery time.
MiniMOS devices are designed for use in low voltage, high speed
D
applications are dc–dc converters, and power management in
portable and battery powered products such as computers,
G SO–8
• Miniature SO–8 Surface Mount Package — Saves Board Space Source–1 1 8 Drain–1
• Diode Exhibits High Speed, With Soft Recovery
Source–2 3 6 Drain–2
• Mounting Information for SO–8 Package Provided Gate–2 4 5 Drain–2
Top View

Drain–to–Gate Voltage (RGS = 1.0 MΩ) VDGR 12 Vdc
Gate–to–Source Voltage — Continuous VGS ± 8.0 Vdc
Total Power Dissipation @ TA = 25°C (2) PD 2.0 Watts
Operating and Storage Temperature Range – 55 to 150 °C
DEVICE MARKING
D2P01
(1) Negative sign for P–Channel device omitted for clarity.
MMDF2P01HDR2 13″ 12 mm embossed tape 2500 units
REV 4

MMDF2P01HD
ELECTRICAL CHARACTERISTICS (TC = 25°C unless otherwise noted)(1)
OFF CHARACTERISTICS
(VGS = 0 Vdc, ID = 250 µAdc) 12 — —
(VDS = 12 Vdc, VGS = 0 Vdc) — — 1.0
Gate–Body Leakage Current (VGS = ± 8.0 Vdc, VDS = 0) IGSS — — 100 nAdc
(VDS = VGS, ID = 250 µAdc) 0.7 1.0 1.1
Temperature Coefficient (Negative) — 3.0 — mV/°C
(VGS = 4.5 Vdc, ID = 2.0 Adc) — 0.16 0.180
(VGS = 2.7 Vdc, ID = 1.0 Adc) — 0.2 0.220
Forward Transconductance (VDS = 2.5 Vdc, ID = 1.0 Adc) gFS 3.0 4.75 — mhos
Vd VGS = 0 Vdc,
Vd
Coss — 410 570
f = 1.0 MHz)
Reverse Transfer Capacitance Crss — 177 250
Turn–On Delay Time td(on) — 21 45 ns
Rise Time (VDD = 6.0 Vdc, ID = 2.0 Adc, tr — 156 315
VGS = 2.7
2 7 Vdc,
Vdc
Rise Time (VDS = 6.0 Vdc, ID = 2.0 Adc, tr — 44 90
VGS = 4.5
4 5 Vdc,
Vdc
((VDS = 10 Vdc, ID = 2.0 Adc, Q1 — 0.8 —

VGS = 4.5 Vdc) Q2 — 4.0 —
Q3 — 3.0 —

Forward On–Voltage(2) VSD Vdc
(IS = 2.0 Adc, VGS = 0 Vdc)
— 1.69 2.0
(IS = 2.0 Adc, VGS = 0 Vdc, TJ = 125°C)
— 1.2 —
((IS = 2.0 Adc, VGS = 0 Vdc, ta — 23 —

dIS/dt = 100 A/µs) tb — 25 —

MMDF2P01HD
4 4
VGS = 8 V 2.5 V TJ = 25°C VDS ≥ 10 V
4.5 V

3.1 V 2.3 V
3 3
2.7 V
2.1 V
2 2
1.9 V 100°C 25°C

1 1
1.7 V TJ = – 55°C
1.5 V
0 0
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 2.8


0.35 0.30
TJ = 25°C TJ = 25°C
ID = 1 A
0.30
0.25
0.25
0.20 VGS = 2.7 V
0.20
4.5 V
0.15
0.15
0.1 0.10
0 2 4 6 8 0 0.8 1.6 2.4 3.2 4

Gate–To–Source Voltage and Gate Voltage
2 1000
VGS = 0 V
VGS = 4.5 V
ID = 2 A
1.5
TJ = 125°C
(NORMALIZED)
1 100
0.5
0 10
– 50 – 25 0 25 50 75 100 125 150 0 4 8 12
Figure 5. On–Resistance Variation with Figure 6. Drain–To–Source Leakage

Temperature Current versus Voltage

MMDF2P01HD
2000
VDS = 0 V VGS = 0 V TJ = 25°C
Ciss
1600
C, CAPACITANCE (pF)
1200
Crss
800
Ciss
400 Coss
Crss
0
8 4 0 4 8 12
VGS VDS
GATE–TO–SOURCE OR DRAIN–TO–SOURCE VOLTAGE (Volts)
Figure 7. Capacitance Variation

MMDF2P01HD
1000

5 10

QT VDD = 6 V
ID = 2 A
4 8 VGS = 4.5 V
VGS TJ = 25°C
VDS
t, TIME (ns)
3 6
100 td(off)
2 Q1 ID = 2 A 4 tf
Q2 TJ = 25°C
tr
1 2
Q3 td(on)
0 0 10
0 2 4 6 8 10 1 10 100
QT, TOTAL CHARGE (nC) RG, GATE RESISTANCE (OHMS)
Figure 8. Gate–To–Source and Drain–To–Source Figure 9. Resistive Switching Time

Voltage versus Total Charge Variation versus Gate Resistance
snappy.
2
VGS = 0 V
TJ = 25°C
1.5
0.5
0
0.4 0.6 0.8 1 1.2 1.4 1.6 1.8
VSD, SOURCE–TO–DRAIN VOLTAGE (VOLTS)
Figure 10. Diode Forward Voltage versus Current

MMDF2P01HD
trr
High Cell Density
trr
tb
ta
t, TIME
SAFE OPERATING AREA
100
SINGLE PULSE
TC = 25°C
10
1 ms
10 ms
1
dc
0.1
RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT
0.01
0.1 1 10 100

Safe Operating Area

MMDF2P01HD
10
THERMAL RESISTANCE
1 D = 0.5
0.2
0.1
0.1
0.02 Chip 0.0175 Ω 0.0710 Ω 0.2706 Ω 0.5776 Ω 0.7086 Ω
0.01
0.01
0.0154 F 0.0854 F 0.3074 F 1.7891 F 107.55 F
Ambient
SINGLE PULSE
0.001
1.0E–05 1.0E–04 1.0E–03 1.0E–02 1.0E–01 1.0E+00 1.0E+01 1.0E+02 1.0E+03
t, TIME (s)
di/dt
IS
trr
ta tb
TIME
tp 0.25 IS
IS

MOTOROLA

Medium Power Surface Mount Products MMDF2P02E
TMOS Dual P-Channel
MiniMOS devices are an advanced series of power MOSFETs DUAL TMOS MOSFET
has a low reverse recovery time. MiniMOS devices are designed 
converters, and power management in portable and battery
powered products such as computers, printers, cellular and D
controls in mass storage products such as disk drives and tape CASE 751–05, Style 11
drives. The avalanche energy is specified to eliminate the SO–8
guesswork in designs where inductive loads are switched and offer G
• Diode Is Characterized for Use In Bridge Circuits Gate–1 2 7 Drain–1
• Diode Exhibits High Speed, with Soft Recovery Source–2 3 6 Drain–2
• IDSS Specified at Elevated Temperatures Gate–2 4 5 Drain–2
• Mounting Information for SO–8 Package Provided Top View

Total Power Dissipation @ TA = 25°C (2) PD 2.0 W
Derate above 25°C 16 mW/°C
(VDD = 20 Vdc, VGS = 10 Vdc, Peak IL = 7.0 Apk, L = 10 mH, RG = 25 Ω) 245
Thermal Resistance, Junction to Ambient (2) RθJA 62.5 °C/W
Maximum Lead Temperature for Soldering Purposes, 0.0625″ from case for 10 seconds TL 260 °C
DEVICE MARKING
F2P02
MMDF2P02ER2 13″ 12 mm embossed tape 2500
REV 4

MMDF2P02E
OFF CHARACTERISTICS
(VGS = 0 Vdc, ID = 250 µAdc) 25 — —
Temperature Coefficient (Positive) — 2.2 — mV/°C
(VDS = 20 Vdc, VGS = 0 Vdc) — — 1.0
(VDS = VGS, ID = 250 µAdc) 1.0 2.0 3.0
Temperature Coefficient (Negative) – 3.8 –
(VGS = 10 Vdc, ID = 2.0 Adc) — 0.19 0.25
(VGS = 4.5 Vdc, ID = 1.0 Adc) — 0.3 0.4
Vd VGS = 0 Vdc,
Vd
Coss — 220 300
f = 1.0 MHz)
VGS = 5.0
5 0 Vdc,
Vdc
VGS = 10 Vdc
Vdc,
Gate Charge QT — 10 15 nC
((VDS = 16 Vdc, ID = 2.0 Adc, Q1 — 1.0 —

VGS = 10 Vdc) Q2 — 3.5 —
Q3 — 3.0 —
See Fig
Figure
re 11
((IS = 2.0 Adc, VGS = 0 Vdc, ta — 19 —
dIS/dt = 100 A/µs) tb — 12 —

MMDF2P02E
4 4
VGS = 10 7 V 5V TJ = 25°C VDS ≥ 10 V
4.7 V
4.5 V

3 3
4.3 V
100°C
2 4.1 V 2
25°C
3.9 V TJ = –55°C
1 1
3.7 V
3.5 V
3.3 V
0 0
0 0.4 0.8 1.2 1.6 2 2.5 3 3.5 4 4.5


0.6 0.6
ID = 1 A TJ = 25°C
0.5 TJ = 25°C
0.5
0.4
0.4
0.3
VGS = 4.5
0.3
0.2
0.2
0.1 10 V
0 0.1
3 4 5 6 7 8 9 10 0 0.5 1 1.5 2

2.0 100
VGS = 10 V VGS = 0 V
ID = 2 A
1.5
TJ = 125°C
1.0 10
0.5 100°C
0 1
– 50 – 25 0 25 50 75 100 125 150 0 4 8 12 16 20


MMDF2P02E
t = Q/IG(AV)
1000

12 16
VDS = 0 V VGS = 0 V TJ = 25°C

QT
Ciss
800
9 VGS 12
C, CAPACITANCE (pF)
VDS
600
6 8
Q1 Q2
400 Crss Ciss
Coss 3 4
200 Q3
ID = 2 A
Crss
TJ = 25°C
0 0 0
10 5 0 5 10 15 20 25 30 0 2 4 6 8 10 12
100 2
VDD = 10 V TJ = 25°C
ID = 2 A VGS = 0 V
VGS = 10 V 1.6
TJ = 25°C
1.2
t, TIME (ns)
td(off) 0.8
tr
tf 0.4
td(on)
10 0
1 10 100 0.6 0.8 1 1.2 1.4 1.6

MMDF2P02E
trr
High Cell Density
trr
tb
ta
t, TIME
SAFE OPERATING AREA
perature.
100 280
I pk = 7 A

SINGLE PULSE 240
TC = 25°C
10 10 µs
100 µs 200
10 ms
160
1 dc
120
80
0.1
RDS(on) LIMIT
THERMAL LIMIT 40
PACKAGE LIMIT
0.01 0
0.1 1 10 100 25 50 75 100 125 150

MMDF2P02E

THERMAL RESISTANCE
1 D = 0.5
0.2
0.1
0.1
0.02 Chip 0.0175 Ω 0.0710 Ω 0.2706 Ω 0.5776 Ω 0.7086 Ω
0.01
0.01
0.0154 F 0.0854 F 0.3074 F 1.7891 F 107.55 F
Ambient
SINGLE PULSE
0.001
1.0E–05 1.0E–04 1.0E–03 1.0E–02 1.0E–01 1.0E+00 1.0E+01 1.0E+02 1.0E+03
t, TIME (s)
di/dt
IS
trr
ta tb
TIME
tp 0.25 IS
IS

MOTOROLA

TMOS P-Channel

DUAL TMOS POWER FET
SO–8
drives and tape drives. The avalanche energy is specified to G
• Diode Exhibits High Speed, With Soft Recovery Top View
(VDD = 20 Vdc, VGS = 5.0 Vdc, IL = 6.0 Apk, L = 18 mH, RG = 25 Ω)
DEVICE MARKING
D2P02
REV 4

MMDF2P02HD
OFF CHARACTERISTICS
(VGS = 0 Vdc, ID = 250 µAdc) 20 — —
(VDS = 20 Vdc, VGS = 0 Vdc) — — 1.0
(VDS = VGS, ID = 250 µAdc) 1.0 1.5 2.0
(VGS = 10 Vdc, ID = 2.0 Adc) — 0.118 0.160
(VGS = 4.5 Vdc, ID = 1.0 Adc) — 0.152 0.180
Vd VGS = 0 Vdc,
Vd
Coss — 290 406
f = 1.0 MHz)
Rise Time (VDS = 10 Vdc, ID = 2.0 Adc, tr — 66 132
VGS = 4.5
4 5 Vdc,
Vdc
VGS = 10 Vdc
Vdc,
((VDS = 16 Vdc, ID = 2.0 Adc, Q1 — 1.2 —

VGS = 10 Vdc) Q2 — 5.0 —
Q3 — 4.0 —

— 1.5 2.1
(IS = 2.0 Adc, VGS = 0 Vdc, TJ = 125°C)
— 1.24 —
(VDD = 15 V, IS = 2.0 A, ta — 17 —
dIS/dt = 100 A/µs)
tb — 21 —
QRR — 0.034 — µC

MMDF2P02HD
4 4
VGS = 10 V 4.5 V 3.9 V 3.7 V TJ = 25°C VDS ≥ 10 V

3.5 V
3 3
3.3 V
2 2
3.1 V
1 2.9 V 1
100°C 25°C
2.7 V
2.5 V TJ = – 55°C
0 0
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 1.0 1.5 2.0 2.5 3.0 3.5


0.6 0.20
ID = 1 A TJ = 25°C
TJ = 25°C
0.16 VGS = 4.5 V

0.4
0.12
10 V
0.2
0.08
0 0.04
0 2 4 6 8 10 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0

1.6 100
ID = 2 A TJ = 125°C
1.4
I DSS, LEAKAGE (nA)
(NORMALIZED)
1.2
10
1.0 100°C
0.8
0.6 1
– 50 – 25 0 25 50 75 100 125 150 0 5 10 15 20
Figure 5. On–Resistance Variation with Figure 6. Drain–To–Source Leakage Current


MMDF2P02HD
1200
VDS = 0 V VGS = 0 V TJ = 25°C
Ciss
1000
C, CAPACITANCE (pF)
800
600
Crss Ciss
400
Coss
200
Crss
0
10 5 0 5 10 15 20
VGS VDS

MMDF2P02HD
12 18 1000
VDS , DRAIN-TO-SOURCE VOLTAGE (VOLTS)

QT VDD = 10 V
ID = 2 A
10 15
VGS = 10 V
VGS
TJ = 25°C
8 12
t, TIME (ns)
6 9 100
td(off)
4 Q1 Q2 6
tf
ID = 2 A
TJ = 25°C tr
2 3
Q3 VDS td(on)
0 0 10
0 4 8 12 16 1 10 100
QT, TOTAL GATE CHARGE (nC) RG, GATE RESISTANCE (OHMS)

snappy.
2.0
VGS = 0 V
TJ = 25°C
1.6
1.2
0.8
0.4
0
0.5 0.7 0.9 1.1 1.3 1.5

MMDF2P02HD
trr
High Cell Density
trr
tb
ta
t, TIME
SAFE OPERATING AREA
perature.
100 350
ID = 6 A

SINGLE PULSE 300
TC = 25°C
100 µs
10
1 ms 250
10 ms
200
1
dc
150
100
0.1
RDS(on) LIMIT
THERMAL LIMIT 50
PACKAGE LIMIT
0.01 0
0.1 1 10 100 25 50 75 100 125 150

MMDF2P02HD
10
THERMAL RESISTANCE
1 D = 0.5
0.2
0.1
0.05
0.02 Chip 0.0175 Ω 0.0710 Ω 0.2706 Ω 0.5776 Ω 0.7086 Ω
0.01
0.01
0.0154 F 0.0854 F 0.3074 F 1.7891 F 107.55 F
Ambient
SINGLE PULSE
0.001
1.0E–05 1.0E–04 1.0E–03 1.0E–02 1.0E–01 1.0E+00 1.0E+01 1.0E+02 1.0E+03
t, TIME (s)
di/dt
IS
trr
ta tb
TIME
tp 0.25 IS
IS

MOTOROLA

TMOS Dual P-Channel Motorola Preferred Device
Field Effect Transistors DUAL TMOS

MiniMOS devices are an advanced series of power MOSFETs POWER MOSFET
D
low voltage motor controls in mass storage products such as disk CASE 751–05, Style 11
drives and tape drives. The avalanche energy is specified to SO–8
eliminate the guesswork in designs where inductive loads are G
• Ultra Low RDS(on) Provides Higher Efficiency and Extends Battery Life Source–1 1 8 Drain–1
• Logic Level Gate Drive — Can Be Driven by Logic ICs Gate–1 2 7 Drain–1
• IDSS Specified at Elevated Temperature Top View
Total Power Dissipation @ TC = 25°C (2) PD 2.0 Watts
(VDD = 30 Vdc, VGS = 5.0 Vdc, Peak IL = 6.0 Apk, L = 18 mH, RG = 25 Ω)
DEVICE MARKING
D2P03
REV 5

MMDF2P03HD
OFF CHARACTERISTICS
(VGS = 0 Vdc, ID = 250 µAdc) 30 — —
(VDS = 30 Vdc, VGS = 0 Vdc) — — 1.0
(VDS = VGS, ID = 250 µAdc) 1.0 1.5 2.0
(VGS = 10 Vdc, ID = 2.0 Adc) — 0.170 0.200
(VGS = 4.5 Vdc, ID = 1.0 Adc) — 0.225 0.300
Vd VGS = 0 Vdc,
Vd
Coss — 189 250
f = 1.0 MHz)
Rise Time (VDD = 15 Vdc, ID = 2.0 Adc, tr — 17.5 35
VGS = 4.5
4 5 Vdc,
Vdc
Turn–Off Delay Time RG = 6.0 Ω) td(off) — 62.5 125
Turn–On Delay Time td(on) — 9.0 18
VGS = 10 Vdc
Vdc,
S Fi
See Figure 8
((VDS = 24 Vdc, ID = 2.0 Adc, Q1 — 1.1 —
VGS = 10 Vdc) Q2 — 4.5 —
Q3 — 3.5 —

(IS = 2.0 Adc, VGS = 0 Vdc, TJ = 125°C) — 1.36 —
Reverse Recovery Time trr — 42.3 — ns
S Figure
See Fi 15
((IS = 2.0 Adc, VGS = 0 Vdc, ta — 15.6 —
dIS/dt = 100 A/µs) tb — 26.7 —

MMDF2P03HD
4 4
VGS = 10 V 4.5 V 3.7 V TJ = 25°C VDS ≥ 10 V
3.5 V

3 3
3.9 V 3.3 V
2 3.1 V 2
TJ = 100°C
2.9 V
25°C
1 1
2.7 V
– 55°C
2.5 V
0 0
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 1.5 1.7 1.9 2.1 2.3 2.5 2.7 2.9 3.1 3.3 3.5 3.7


0.6 0.30
ID = 1 A TJ = 25°C
TJ = 25°C
0.5
0.25
0.4
VGS = 4.5 V
0.3 0.20
10 V
0.2
0.15
0.1
0 0.10
0 1 2 3 4 5 6 7 8 9 10 0 0.5 1 1.5 2 2.5 3 3.5 4

1.6 1000
ID = 2 A
1.4
(NORMALIZED)
1.2
TJ = 125°C
100
1.0
100°C
0.8
0.6 10
– 50 – 25 0 25 50 75 100 125 150 0 10 20 30


MMDF2P03HD
1200
VDS = 0 V VGS = 0 V TJ = 25°C
Ciss
1000
C, CAPACITANCE (pF)
800
600 Crss
Ciss
400
Coss
200
Crss
0
10 5 0 5 10 15 20 25 30
VGS VDS

MMDF2P03HD
12 24 1000

QT VDD = 15 V
10 20 ID = 2 A
VGS VGS = 10 V tf
TJ = 25°C
8 VDS 16 100 td(off)
t, TIME (ns)
6 ID = 2 A 12
TJ = 25°C tr
Q1 Q2
4 8 10 td(on)
2 4
Q3
0 0 1
0 2 4 6 8 10 12 14 16 1 10 100

snappy.
2
TJ = 25°C
VGS = 0 V
1.6
1.2
0.8
0.4
0
0.5 0.7 0.9 1.1 1.3 1.5 1.7 1.9

MMDF2P03HD
trr
High Cell Density
trr
tb
ta
t, TIME
SAFE OPERATING AREA
perature.
100 350
VGS = 20 V Mounted on 2” sq. FR4 board (1” sq. 2 oz. Cu 0.06” ID = 6 A
thick single sided) with one die operating, 10s max. 300
SINGLE PULSE
TC = 25°C
10 100 µs 250
1 ms
10 ms 200
1
dc 150
100
0.1
RDS(on) LIMIT
THERMAL LIMIT 50
PACKAGE LIMIT
0.01 0
0.1 1 10 100 25 50 75 100 125 150

MMDF2P03HD
10
THERMAL RESISTANCE
1 D = 0.5
0.2
0.1
0.1
0.02 Chip 0.0175 Ω 0.0710 Ω 0.2706 Ω 0.5776 Ω 0.7086 Ω
0.01
0.01
0.0154 F 0.0854 F 0.3074 F 1.7891 F 107.55 F
Ambient
SINGLE PULSE
0.001
1.0E–05 1.0E–04 1.0E–03 1.0E–02 1.0E–01 1.0E+00 1.0E+01 1.0E+02 1.0E+03
t, TIME (s)
di/dt
IS
trr
ta tb
TIME
tp 0.25 IS
IS

MOTOROLA

Medium Power Surface Mount Products MMDF3N02HD
TMOS Dual N-Channel

SO–8
G
Top View

DEVICE MARKING
D3N02
MMDF3N02HDR2 13″ 12 mm embossed tape 2500
REV 4

MMDF3N02HD
OFF CHARACTERISTICS
(VGS = 0 Vdc, ID = 250 µAdc) 20 — —
(VDS = 20 Vdc, VGS = 0 Vdc) — — 1.0
(VDS = VGS, ID = 250 µAdc) 1.0 1.5 2.0
Threshold Temperature Coefficient (Negative) — 4.0 — mV/°C
(VGS = 10 Vdc, ID = 3.0 Adc) — 0.058 0.090
(VGS = 4.5 Vdc, ID = 1.5 Adc) — 0.074 0.100
Vd VGS = 0 Vdc,
Vd
Coss — 184 250
f = 1.0 MHz)
VGS = 4.5
4 5 Vdc,
Vdc
Turn–On Delay Time td(on) — 7.0 21
VGS = 10 Vdc
Vdc,
S Fi
See Figure 8
((VDS = 16 Vdc, ID = 3.0 Adc, Q1 — 1.3 —
VGS = 10 Vdc) Q2 — 2.8 —
Q3 — 2.4 —

(IS = 3.0 Adc, VGS = 0 Vdc, TJ = 125°C) — 0.72 —
S Figure
See Fi 15
((IS = 3.0 Adc, VGS = 0 Vdc, ta — 18 —
dIS/dt = 100 A/µs) tb — 5.0 —

MMDF3N02HD
6 6
VGS = 10 V 3.5 V TJ = 25°C
VDS ≥ 10 V
4.5 V 3.3 V
5 3.7 V

3.9 V
4 4
3.1 V TJ = 100°C
3
2.9 V 25°C
2 2
2.7 V – 55°C
1
2.5 V
0 0
0 0.2 0.4 0.6 0.8 1 1.21.6 1.4 1.8 2 1 1.4 1.8 2.2 2.6 3 3.4


0.6 0.08
ID = 1.5 A TJ = 25°C
TJ = 25°C VGS = 4.5 V
0.4 0.07
0.2 0.06 10 V
0 0.05
0 1 2 3 4 5 6 7 8 9 10 0 1 2 3 4 5 6

1.6 1000
VGS = 0 V
VGS = 10 V
ID = 1.5 A
1.4
TJ = 125°C
100
(NORMALIZED)
1.2
100°C
1 25°C
10
0.8
0.6 1
– 50 – 25 0 25 50 75 100 125 150 0 4 8 12 16 20


MMDF3N02HD
1400
VDS = 0 V VGS = 0 V TJ = 25°C
1200 Ciss
C, CAPACITANCE (pF)
1000
800
Crss
600
Ciss
400
Coss
200
Crss
10 5 0 5 10 15 20
VGS VDS

MMDF3N02HD
100

12 24
v DS , DRAIN–TO–SOURCE VOLTAGE (VOLTS)

QT VDD = 10 V
10 20 ID = 3 A
VGS = 10 V tr
VGS
TJ = 25°C t
8 16 d(off)
t, TIME (ns)
tf
6 ID = 3 A 12 10
TJ = 25°C td(on)
4 Q1 Q2 8
2 4
Q3 VDS
0 0 1
0 2 4 6 8 10 12 14 1 10 100

snappy.
3
VGS = 0 V
2.5 TJ = 25°C
1.5
0.5
0
0.5 0.55 0.6 0.65 0.7 0.75 0.8

MMDF3N02HD
trr
High Cell Density
trr
tb
ta
t, TIME
SAFE OPERATING AREA
perature.
100 450
thick single sided) with one die operating, 10s max. 400 ID = 9 A
SINGLE PULSE
TC = 25°C
100 µs 350
10
1 ms
10 ms 300
250
1 dc
200
150
0.1
RDS(on) LIMIT 100
THERMAL LIMIT
50
PACKAGE LIMIT
0.01 0
0.1 1 10 100 25 50 75 100 125 150

MMDF3N02HD
10
THERMAL RESISTANCE
1 D = 0.5
0.2
0.1
0.1
0.02 Chip 0.0175 Ω 0.0710 Ω 0.2706 Ω 0.5776 Ω 0.7086 Ω
0.01
0.01
0.0154 F 0.0854 F 0.3074 F 1.7891 F 107.55 F
Ambient
SINGLE PULSE
0.001
1.0E–05 1.0E–04 1.0E–03 1.0E–02 1.0E–01 1.0E+00 1.0E+01 1.0E+02 1.0E+03
t, TIME (s)
di/dt
IS
trr
ta tb
TIME
tp 0.25 IS
IS

MOTOROLA

TMOS Dual N-Channel

D
drives and tape drives. The avalanche energy is specified to G CASE 751–05, Style 11
eliminate the guesswork in designs where inductive loads are SO–8
switched and offer additional safety margin against unexpected S
voltage transients.
• Logic Level Gate Drive — Can Be Driven by Logic ICs Source–1 1 8 Drain–1
• Miniature SO–8 Surface Mount Package — Saves Board Space Gate–1 2 7 Drain–1
• Diode Is Characterized for Use In Bridge Circuits Source–2 3 6 Drain–2
• Diode Exhibits High Speed, With Soft Recovery Gate–2 4 5 Drain–2
• Avalanche Energy Specified Top View
(VDD = 30 Vdc, VGS = 5.0 Vdc, Peak IL = 9.0 Apk, L = 8.0 mH, RG = 25 Ω)
DEVICE MARKING
D3N03
MMDF3N03HDR2 13″ 12 mm embossed tape 2500 units
(1) When mounted on 2” square FR–4 board (1” square 2 oz. Cu 0.06” thick single sided) with one die operating, 10s max.
REV 5

MMDF3N03HD
OFF CHARACTERISTICS
(VGS = 0 Vdc, ID = 250 µAdc) 30 — —
(VDS = 30 Vdc, VGS = 0 Vdc) — — 1.0
(VDS = VGS, ID = 250 µAdc) 1.0 1.7 3.0
Threshold Temperature Coefficient (Negative) mV/°C
(VGS = 10 Vdc, ID = 3.0 Adc) — 0.06 0.07
(VGS = 4.5 Vdc, ID = 1.5 Adc) — 0.065 0.075
Forward Transconductance gFS Mhos
(VDS = 3.0 Vdc, ID = 1.5 Adc) 2.0 3.6 —
Vd VGS = 0 Vdc,
Vd
Coss — 160 225
f = 1.0 MHz)
VGS = 4
4.55 Vdc,
Vdc
VGS = 10 Vdc
Vdc,
((VDS = 10 Vdc, ID = 3.0 Adc, Q1 — 1.5 —

VGS = 10 Vdc) Q2 — 3.5 —
Q3 — 2.8 —
— 0.82 1.2
(IS = 3.0 Adc, VGS = 0 Vdc, TJ = 125°C)
— 0.7 —
See Figure
Fig re 12 (IS = 3
3.0
0 Ad
Adc, VGS = 0 Vdc,
Vd
ta — 17 —
dIS/dt = 100 A/µs)
tb — 7 —

MMDF3N03HD
6 6
VGS = 10 V 3.9 V 3.5 V
TJ = 25°C VDS ≥ 10 V
4.5 V 3.7 V
5 5

4.3 V
4.1 V 3.3 V
4 4
100°C
3 3.1 V 3
2 2 25°C
2.9 V
1 1 TJ = –55°C
2.7 V
2.5 V
0 0
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 2 2.5 3 3.5 4


0.6 0.08
ID = 1.5 A TJ = 25°C
0.5 TJ = 25°C
0.4 0.07
VGS = 4.5
0.3
0.2 0.06
10 V
0.1
0 0.05
2 3 4 5 6 7 8 9 10 0 0.5 1 1.5 2 2.5 3

2.0 100
ID = 1.5 A
1.5 TJ = 125°C
1.0 10 100°C
0.5
0 1
– 50 – 25 0 25 50 75 100 125 150 0 5 10 15 20 25 30
Figure 5. On–Resistance Variation Figure 6. Drain–to–Source Leakage Current

with Temperature versus Voltage

MMDF3N03HD
t = Q/IG(AV)
snappy.

trr
High Cell Density
trr
tb
ta
t, TIME

MMDF3N03HD
SAFE OPERATING AREA
perature.

1200 VDS = 0 V VGS = 0 V 12 24

TJ = 25°C QT
Ciss
1000
9 18
VGS
C, CAPACITANCE (pF)
800 VDS
600 Crss 6 12
Ciss Q1 Q2
400
3 6
Coss Q3
200 ID = 3 A
Crss TJ = 25°C
0 0 0
10 5 0 5 10 15 20 25 30 0 2 4 6 8 10 12
GATE–TO–SOURCE OR DRAIN–TO–SOURCE VOLTAGE (VOLTS)
Figure 8. Capacitance Variation Figure 9. Gate–to–Source and
Drain–to–Source Voltage versus Total Charge
1000 3.0
VDD = 15 V TJ = 25°C
ID = 3 A VGS = 0 V
2.5
VGS = 10 V
TJ = 25°C
100 2.0
t, TIME (ns)
td(off) 1.5
tr
tf
10 td(on) 1.0
0.5
1 0
1 10 100 0.5 0.55 0.6 0.65 0.7 0.75 0.8 0.85

MMDF3N03HD
100 350
VGS = 20 V ID = 9 A

SINGLE PULSE 10 µs 300
TC = 25°C 100 µs

10 1 ms 250
10 ms
200
1 dc
150
RDS(on) LIMIT
THERMAL LIMIT 100
0.1
PACKAGE LIMIT
Mounted on 2” sq. FR4 board (1” sq. 2 oz. Cu 0.06” 50
0.01 0
0.1 1 10 100 25 50 75 100 125 150
10
THERMAL RESISTANCE
1 D = 0.5
0.2
0.1
0.1
0.02 Chip 0.0175 Ω 0.0710 Ω 0.2706 Ω 0.5776 Ω 0.7086 Ω
0.01
0.01
0.0154 F 0.0854 F 0.3074 F 1.7891 F 107.55 F
Ambient
SINGLE PULSE
0.001
1.0E–05 1.0E–04 1.0E–03 1.0E–02 1.0E–01 1.0E+00 1.0E+01 1.0E+02 1.0E+03
t, TIME (s)
di/dt
IS
trr
ta tb
TIME
tp 0.25 IS
IS

MOTOROLA

TMOS Dual N-Channel

D
SO–8
G
• Miniature SO–8 Surface Mount Package — Saves Board Space S
• Mounting Information for SO–8 Package Provided Gate–2 4 5 Drain–2
Top View

DEVICE MARKING
D4N01
MMSF4N01HDR2 13″ 12 mm embossed tape 2500 units
REV 4

MMDF4N01HD
OFF CHARACTERISTICS
(VGS = 0 Vdc, ID = 0.25 mAdc) 20 — —
(VDS = 12 Vdc, VGS = 0 Vdc) — — 1.0
(VDS = VGS, ID = 0.25 mAdc) 0.6 0.8 1.1
(VGS = 4.5 Vdc, ID = 4.0 Adc) — 0.035 0.045
(VGS = 2.7 Vdc, ID = 2.0 Adc) — 0.043 0.055
Vd VGS = 0 Vdc,
Vd
Coss — 270 378
f = 1.0 MHz)
VGS = 2.7
2 7 Vdc,
Vdc
VGS = 4.5
4 5 Vdc,
Vdc
(S Fi
(See Figure 8)
((VDS = 10 Vdc, ID = 4.0 Adc, Q1 — 1.3 —
VGS = 4.5 Vdc) Q2 — 3.5 —
Q3 — 3.0 —

— 0.95 1.1
(IS = 4.0 Adc, VGS = 0 Vdc, TJ = 125°C)
— 0.78 —
((IS = 4.0 Adc, VGS = 0 Vdc, ta — 17 —

dIS/dt = 100 A/µs) tb — 22 —

MMDF4N01HD
8 8
4.5 V
VGS = 8 V TJ = 25°C VDS ≥ 10 V
2.3 V
3.1 V

2.5 V 2.1 V
6 2.7 V 6
4 1.9 V 4 100°C
25°C
1.7 V
2 2 TJ = – 55°C
1.5 V
1.3 V
0 0
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 1 1.2 1.4 1.6 1.8 2 2.2


0.07 0.050
TJ = 25°C TJ = 25°C
ID = 2 A
0.06 0.045 VGS = 2.7 V
0.05 0.040
4.5 V
0.04 0.035
0.03 0.030
0 2 4 6 8 0 2 4 6 8

2 100
VGS = 0 V
VGS = 4.5 V
ID = 4 A TJ = 125°C
1.5
(NORMALIZED)
1 10
100°C
0.5
0
– 50 – 25 0 25 50 75 100 125 150 0 2 4 6 8 10 12


MMDF4N01HD
2000
VDS = 0 V VGS = 0 V TJ = 25°C
1600 Ciss
C, CAPACITANCE (pF)
1200
800 Crss
Ciss
400 Coss
Crss
0
8 4 0 4 8 12
VGS VDS

MMDF4N01HD
100

5 10

QT VDD = 6 V
ID = 4 A tr
4 8 VGS = 4.5 V
VGS TJ = 25°C tf
VDS td(off)
t, TIME (ns)
3 6
Q1 Q2 10 td(on)
2 ID = 4 A 4
TJ = 25°C
1 2
Q3
0 0 1
0 2 4 6 8 10 0.1 1 10 100

snappy.
4
VV GS= =0 0VV
GS
TJTJ= =25°C
25°C
0
0.3 0.4 0.5 0.6 0.7 0.8 0.9 1

MMDF4N01HD
trr
High Cell Density
trr
tb
ta
t, TIME
SAFE OPERATING AREA
100
VGS = 20 V
SINGLE PULSE 10 µs
TC = 25°C 100 µs
10 1 ms
10 ms
1
dc
RDS(on) LIMIT
THERMAL LIMIT
0.1
PACKAGE LIMIT
0.01
0.1 1 10 100

Safe Operating Area

MMDF4N01HD
10
THERMAL RESISTANCE
1 D = 0.5
0.2
0.1
0.1
0.02 Chip 0.0175 Ω 0.0710 Ω 0.2706 Ω 0.5776 Ω 0.7086 Ω
0.01
0.01
0.0154 F 0.0854 F 0.3074 F 1.7891 F 107.55 F
Ambient
SINGLE PULSE
0.001
1.0E–05 1.0E–04 1.0E–03 1.0E–02 1.0E–01 1.0E+00 1.0E+01 1.0E+02 1.0E+03
t, TIME (s)
di/dt
IS
trr
ta tb
TIME
tp 0.25 IS
IS

MOTOROLA
Product Preview MMDF4N01Z

TMOS Dual N-Channel with
Monolithic Zener ESD

Protected Gate DUAL TMOS
POWER MOSFET
EZFETs are an advanced series of power MOSFETs which 4.0 AMPERES
utilize Motorola’s High Cell Density TMOS process and contain 20 VOLTS
monolithic back–to–back zener diodes. These zener diodes RDS(on) = 0.045 OHM
provide protection against ESD and unexpected transients. These 
miniature surface mount MOSFETs feature ultra low RDS(on) and
true logic level performance. They are capable of withstanding
high energy in the avalanche and commutation modes and the
D
EZFET devices are designed for use in low voltage, high speed
switching applications where power efficiency is important.
Typical applications are dc–dc converters, and power manage-
ment in portable and battery powered products such as comput- G CASE 751–05, Style 11
ers, printers, cellular and cordless phones. They can also be used SO–8
for low voltage motor controls in mass storage products such as S
disk drives and tape drives.
• Zener Protected Gates Provide Electrostatic Discharge Protection
• Ultra Low RDS(on) Provides Higher Efficiency and Extends Battery Life Source–1 1 8 Drain–1
• Logic Level Gate Drive — Can Be Driven by Logic ICs Gate–1 2 7 Drain–1
Drain Current — Continuous @ TA = 25°C (1) ID 4.5 Adc
Drain Current — Continuous @ TA = 70°C (1) ID 4.0
Drain Current — Pulsed Drain Current (3) IDM 23 Apk
Linear Derating Factor (1) 16 mW/°C
Linear Derating Factor (2) 11.11 mW/°C
THERMAL RESISTANCE
Rating Symbol Typ. Max. Unit
Thermal Resistance — Junction to Ambient, PCB Mount (1) RθJA — 62.5 °C/W
— Junction to Ambient, PCB Mount (2) RθJA — 90
(1) When mounted on 1 inch square FR–4 or G–10 board (VGS = 4.5 V, @ 10 Seconds)
(2) When mounted on minimum recommended FR–4 or G–10 board (VGS = 4.5 V, @ Steady State)
(3) Repetitive rating; pulse width limited by maximum junction temperature.
DEVICE MARKING ORDERING INFORMATION
D4N01Z
MMDF4N01ZR2 13″ 12 mm embossed tape 2500 units
This document contains information on a new product. Specifications and information are subject to change without notice.
REV 1

MMDF4N01Z
OFF CHARACTERISTICS
Drain–to–Source Breakdown Voltage (Cpk ≥ 2.0) (3) V(BR)DSS Vdc
(VGS = 0 Vdc, ID = 0.25 mAdc) 20 — —
(VDS = 20 Vdc, VGS = 0 Vdc) — — 2.0
Gate–Body Leakage Current (VGS = ± 8.0 Vdc, VDS = 0) IGSS — — 5.0
Gate Threshold Voltage (Cpk ≥ 2.0) (3) VGS(th) Vdc
(VDS = VGS, ID = 0.25 mAdc) 0.7 0.83 1.1
Static Drain–to–Source On–Resistance (Cpk ≥ 2.0) (3) RDS(on) mΩ
(VGS = 4.5 Vdc, ID = 4.0 Adc) — 35 45
(VGS = 2.7 Vdc, ID = 2.0 Adc) — 45 55
(VDS = 2.5 Vdc, ID = 2.0 Adc) 5.0 8.5 —
Vd VGS = 0 Vdc,
Vd
Coss — 160 225
f = 1.0 MHz)
VGS = 44.5
5 Vdc,
Vdc
VGS = 22.7
7 Vdc,
Vdc
(see fig
figure
re 8)
((VDS = 10 Vdc, ID = 4.0 Adc, Q1 — 0.8 —
VGS = 4.5 Vdc) Q2 — 4.4 —
Q3 — 3.0 —
— 0.84 1.2
(IS = 4.0 Adc, VGS = 0 Vdc, TJ = 125°C)
— 0.65 —
(IS = 4
4.0
0 Ad
Adc, VGS = 0 Vdc,
Vd
ta — 88 —
dIS/dt = 100 A/µs)
tb — 162 —
(3) Reflects typical values. Max limit – Typ
Cpk =
3 x SIGMA

MOTOROLA
Medium Power Field Effect Transistor MMFT1N10E

N–Channel Enhancement Mode
Silicon Gate TMOS E–FETt Motorola Preferred Device
SOT–223 for Surface Mount

MEDIUM POWER
This advanced E–FET is a TMOS Medium Power MOSFET TMOS FET
designed to withstand high energy in the avalanche and commuta- 1 AMP
tion modes. This new energy efficient device also offers a 100 VOLTS
drain–to–source diode with a fast recovery time. Designed for low RDS(on) = 0.25 OHM
voltage, high speed switching applications in power supplies,

dc–dc converters and PWM motor controls, these devices are
particularly well suited for bridge circuits where diode speed and
commutating safe operating areas are critical and offer additional
2,4
safety margin against unexpected voltage transients. The device is D 4
housed in the SOT–223 package which is designed for medium
power surface mount applications. 1
2
• Silicon Gate for Fast Switching Speeds 3
1
• Low RDS(on) — 0.25 Ω max G
• The SOT–223 Package can be Soldered Using Wave or Re-
CASE 318E–04, STYLE 3
flow. The Formed Leads Absorb Thermal Stress During Sol- TO–261AA
dering, Eliminating the Possibility of Damage to the Die S
3
• Available in 12 mm Tape and Reel
Use MMFT1N10ET1 to order the 7 inch/1000 unit reel.
Use MMFT1N10ET3 to order the 13 inch/4000 unit reel.
MAXIMUM RATINGS (TA = 25°C unless otherwise noted)

Drain–to–Source Voltage VDS 100
Vdc
Gate–to–Source Voltage — Continuous VGS ± 20
Drain Current — Continuous ID 1 Adc
Total Power Dissipation @ TA = 25°C 0.8 Watts
PD(1)
Derate above 25°C 6.4 mW/°C
(VDD = 60 V, VGS = 10 V, Peak IL= 1 A, L = 0.2 mH, RG = 25 Ω)
DEVICE MARKING
1N10
Thermal Resistance — Junction–to–Ambient (surface mounted) RθJA 156 °C/W
Maximum Temperature for Soldering Purposes, 260 °C
TL
(1) Power rating when mounted on FR–4 glass epoxy printed circuit board using recommended footprint.
REV 3

MMFT1N10E
OFF CHARACTERISTICS
Drain–to–Source Breakdown Voltage, (VGS = 0, ID = 250 µA) V(BR)DSS 100 — — Vdc
Zero Gate Voltage Drain Current, (VDS = 100 V, VGS = 0) IDSS — — 10 µAdc
Gate–Body Leakage Current, (VGS = 20 V, VDS = 0) IGSS — — 100 nAdc
ON CHARACTERISTICS
Gate Threshold Voltage, (VDS = VGS, ID = 1 mA) VGS(th) 2 — 4.5 Vdc
Static Drain–to–Source On–Resistance, (VGS = 10 V, ID = 0.5 A) RDS(on) — — 0.25 Ohms
Drain–to–Source On–Voltage, (VGS = 10 V, ID = 1 A) VDS(on) — — 0.33 Vdc
Forward Transconductance, (VDS = 10 V, ID = 0.5 A) gFS — 2.2 — mhos
Input Capacitance Ciss — 410 —
(VDS = 20 V,
Output Capacitance VGS = 0, Coss — 145 — pF
f = 1 MHz)
MH )
Turn–On Delay Time td(on) — 15 —
Rise Time (VDD = 25 V, ID = 0.5 A tr — 15 —
VGS = 10 V
V, RG = 50 ohms
ohms, ns
Turn–Off Delay Time RGS = 25 ohms) td(off) — 30 —
Total Gate Charge Qg — 7 —
(VDS = 80 V, ID = 1 A,
Gate–Source Charge VGS = 10 Vdc) Qgs — 1.3 — nC
S Fi
See Figures 15 andd 16
SOURCE DRAIN DIODE CHARACTERISTICS(1)
Forward On–Voltage IS = 1 A, VGS = 0 VSD — 0.8 — Vdc
Forward Turn–On Time IS = 1 A, VGS = 0, ton Limited by stray inductance
dlS/dt = 400 A/µs
A/µs,
Reverse Recovery Time VR = 50 V trr — 90 — ns
(1) Pulse Test: Pulse Width ≤ 300 µs, Duty Cycle ≤ 2%

MMFT1N10E
10 10 V 1.2
8V 7V
VDS = VGS
VGS(TH), GATE THRESHOLD VOLTAGE

9V
TJ = 25°C ID = 1.0 mA
8 1.1
6V
(NORMALIZED)
6 1.0
4 5V 0.9
2 0.8
VGS = 4 V
0 0.7
0 2 4 6 8 10 – 50 0 50 100 150
VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS) TJ, JUNCTION TEMP (°C)
Figure 1. On Region Characteristics Figure 2. Gate–Threshold Voltage Variation

With Temperature

4 0.5
TJ = – 55°C VDS = 10 V VGS = 10 V
100°C 0.4
3
25°C
TJ = 100°C
0.3
2
25°C
0.2
– 55°C
1
0.1
0 0
0 2 4 6 8 10 0 2 4
Figure 3. Transfer Characteristics Figure 4. On–Resistance versus Drain Current

0.5 0.5
TJ = 25°C VGS = 10 V
0.4 ID = 1 A 0.4 ID = 1 A
0.3 0.3
0.2 0.2
0.1 0.1
0 0
4 6 8 10 12 14 16 – 50 0 50 100 150
VGS, GATE–TO–SOURCE VOLTAGE (VOLTS) TJ, JUNCTION TEMPERATURE (°C)
Figure 5. On–Resistance versus Figure 6. On–Resistance versus Junction

Gate–to–Source Voltage Temperature

MMFT1N10E
FORWARD BIASED SAFE OPERATING AREA
The FBSOA curves define the maximum drain–to–source
voltage and drain current that a device can safely handle 10
when it is forward biased, or when it is on, or being turned on. VGS = 20 V
Because these curves include the limitations of simultaneous SINGLE PULSE
TA = 25°C

1
20 ms
curves are based on an ambient temperature of 25°C and a
100 ms
maximum junction temperature of 150°C. Limitations for re-
0.1
petitive pulses at various ambient temperatures can be de- 1s
termined by using the thermal response curves. Motorola DC
Application Note, AN569, “Transient Thermal Resistance– 500 ms
General Data and Its Use” provides detailed instructions. 0.01
RDS(on) LIMIT
THERMAL LIMIT
SWITCHING SAFE OPERATING AREA PACKAGE LIMIT
The switching safe operating area (SOA) is the boundary 0.001
0.1 1 10 100
that the load line may traverse without incurring damage to
the MOSFET. The fundamental limits are the peak current, VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
IDM and the breakdown voltage, BVDSS. The switching SOA
is applicable for both turn–on and turn–off of the devices for
Safe Operating Area
switching times less than one microsecond.
1.0
D = 0.5
r(t), EFFECTIVE THERMAL RESISTANCE
0.2
0.1
(NORMALIZED)
0.1
0.05 P(pk) RθJA(t) = r(t) RθJA
RθJA = 156°C/W MAX
0.02
PULSE TRAIN SHOWN
0.01
0.01 READ TIME AT t1
t1
TJ(pk) – TA = P(pk) RθJA(t)
SINGLE PULSE t2
0.001
1.0E–05 1.0E–04 1.0E–03 1.0E–02 1.0E–01 1.0E+00 1.0E+01
t, TIME (s)
COMMUTATING SAFE OPERATING AREA (CSOA)
The Commutating Safe Operating Area (CSOA) of Figure 10 defines the limits of safe operation for commutated source–drain
current versus re–applied drain voltage when the source–drain diode has undergone forward bias. The curve shows the limita-
tions of IFM and peak VDS for a given rate of change of source current. It is applicable when waveforms similar to those of Figure
9 are present. Full or half–bridge PWM DC motor controllers are common applications requiring CSOA data.
Device stresses increase with increasing rate of change of source current so dIS/dt is specified with a maximum value. Higher
values of dIS/dt require an appropriate derating of IFM, peak VDS or both. Ultimately dIS/dt is limited primarily by device, package,
and circuit impedances. Maximum device stress occurs during trr as the diode goes from conduction to reverse blocking.
VDS(pk) is the peak drain–to–source voltage that the device must sustain during commutation; IFM is the maximum forward
source–drain diode current just prior to the onset of commutation.
VR is specified at 80% rated BVDSS to ensure that the CSOA stress is maximized as IS decays from IRM to zero.
RGS should be minimized during commutation. TJ has only a second order effect on CSOA.
Stray inductances in Motorola’s test circuit are assumed to be practical minimums. dV DS /dt in excess of 10 V/ns was at-
tained with dI S /dt of 400 A/µs.

MMFT1N10E
15 V
VGS
0
IFM
dlS/dt
90%
IS
trr
10%
ton IRM
0.25 IRM
tfrr
VDS(pk)
VR
VDS
Vf VdsL
MAX. CSOA
STRESS AREA
Figure 9. Commutating Waveforms
5
RGS
4.5 dIS/dt ≤ 400 A/µs DUT
IS , SOURCE CURRENT (AMPS)
4
3.5
–
3
VR
2.5 IFM
+ IS Li
2
+ VDS
1.5
20 V
1
–
0.5 VGS
0
0 20 40 60 80 100 120 140 VR = 80% OF RATED VDSS
VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS) VdsL = Vf + Li ⋅ dlS/dt
Figure 10. Commutating Safe Operating Area Figure 11. Commutating Safe Operating Area
(CSOA) Test Circuit
BVDSS
VDS
IL IL(t)
VDD
t RG
VDD
tP t, (TIME)
Figure 12. Unclamped Inductive Switching Figure 13. Unclamped Inductive Switching
Test Circuit Waveforms

MMFT1N10E
VGS VDS
1400
Ciss
TJ = 25°C
1200
Coss f = 1 MHz
Crss
1000
C, CAPACITANCE (pF)
800
600
Ciss
400
Coss
200 Crss
0
20 15 10 5 0 5 10 15 20
Figure 14. Capacitance Variation With Voltage
10
VDS = 50 V VDS = 80 V
8
4
TJ = 25°C
ID = 1 A
2 VGS = 10 V
0
0 2 4 6 8
Qg, TOTAL GATE CHARGE (nC)
Figure 15. Gate Charge versus Gate–To–Source Voltage
+18 V VDD
SAME
1 mA 10 V DEVICE TYPE
47 k 100 k
AS DUT
Vin 15 V
2N3904 0.1 µF
2N3904
100 k FERRITE
100 BEAD DUT
47 k
Vin = 15 Vpk; PULSE WIDTH ≤ 100 µs, DUTY CYCLE ≤ 10%.
Figure 16. Gate Charge Test Circuit

MOTOROLA
Medium Power Field Effect Transistor MMFT2N02EL

N–Channel Enhancement Mode

MEDIUM POWER
This advanced E–FET is a TMOS Medium Power MOSFET LOGIC LEVEL TMOS FET
designed to withstand high energy in the avalanche and commuta- 1.6 AMP
tion modes. This device is also designed with a low threshold 20 VOLTS
voltage so it is fully enhanced with 5 Volts. This new energy efficient RDS(on) = 0.15 OHM
device also offers a drain–to–source diode with a fast recovery 
time. Designed for low voltage, high speed switching applications in
power supplies, dc–dc converters and PWM motor controls, these
devices are particularly well suited for bridge circuits where diode
2,4
speed and commutating safe operating areas are critical and offer D 4
The device is housed in the SOT–223 package which is designed 1
for medium power surface mount applications. 2
1 3
• Silicon Gate for Fast Switching Speeds G
• Low Drive Requirement to Interface Power Loads to Logic
Level ICs, VGS(th) = 2 Volts Max TO–261AA
• Low RDS(on) — 0.15 Ω max S
3
flow. The Formed Leads Absorb Thermal Stress During Sol-
dering, Eliminating the Possibility of Damage to the Die
Use MMFT2N02ELT1 to order the 7 inch/1000 unit reel.
Use MMFT2N02ELT3 to order the 13 inch/4000 unit reel.

Vdc
Drain Current — Continuous ID 1.6 Adc
Drain Current — Pulsed IDM 6.4
PD(1)
(VDD = 10 V, VGS = 5 V, Peak IL= 2 A, L = 0.2 mH, RG = 25 Ω)
DEVICE MARKING
2N02L
TL
REV 3

MMFT2N02EL
OFF CHARACTERISTICS
ON CHARACTERISTICS
Gate Threshold Voltage, (VDS = VGS, ID = 1 mA) VGS(th) 1 — 2 Vdc
Drain–to–Source On–Voltage, (VGS = 5 V, ID = 1.6 A) VDS(on) — — 0.32 Vdc
(VDS = 15 V,
f = 1 MHz)
MH )
VGS = 5 V
V, RG = 50 ohms
ohms, ns
(VDS = 16 V, ID = 1.6 A,
S Fi
See Figures 15 andd 16
Gate–Drain Charge Qgd — 6 —
Forward On–Voltage IS = 1.6 A, VGS = 0 VSD — 0.9 — Vdc
Forward Turn–On Time IS = 1.6 A, VGS = 0, ton Limited by stray inductance
dlS/dt = 400 A/µs
A/µs,

MMFT2N02EL
10 1.2
10 6 5 TJ = 25°C VDS = VGS
7 4.5
VGS(TH), GATE THRESHOLD VOLTAGE

ID = 1 mA
8 1.1
(NORMALIZED)
6 3.5 1
4 3 0.9
2 0.8
VGS = 2.5 V
0 0.7
0 1 2 3 4 5 – 50 0 50 100 150
VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS) TJ, JUNCTION TEMP (°C)

With Temperature

8 0.3
TJ = – 55°C VGS = 5 V
VDS = 8 V
0.25
25°C
6
100°C 0.2
TJ = 100°C
4 0.15
25°C
0.1
2 – 55°C
0.05
0 0
0 2 4 6 7 0 1 2 3 4

0.5 0.5
TJ = 25°C VGS = 5 V
ID = 1.6 A ID = 1.6 A
0.4 0.4
0.3 0.3
0.2 0.2
0.1 0.1
0 0
2 3 4 5 6 7 8 – 50 0 50 100 150
Figure 5. On–Resistance versus Figure 6. On–Resistance versus Junction

Gate–to–Source Voltage Temperature

MMFT2N02EL
VGS = 15 V
when it is forward biased, or when it is on, or being turned on.
SINGLE PULSE
Because these curves include the limitations of simultaneous TA = 25°C

they are especially useful to designers of linear systems. The 1 20 ms
curves are based on an ambient temperature of 25°C and a 100
ms
termined by using the thermal response curves. Motorola DC
0.1
Application Note, AN569, “Transient Thermal Resistance–
500 ms
General Data and Its Use” provides detailed instructions. RDS(on) LIMIT
THERMAL LIMIT
0.1 1 10 100
that the load line may traverse without incurring damage to VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
the MOSFET. The fundamental limits are the peak current,
IDM and the breakdown voltage, BVDSS. The switching SOA is Figure 7. Maximum Rated Forward Biased
applicable for both turn–on and turn–off of the devices for Safe Operating Area
1.0
D = 0.5
0.2
0.1
0.1
(NORMALIZED)

0.02 D CURVES APPLY FOR POWER
PULSE TRAIN SHOWN
0.01 t1
TJ(pk) – TA = P(pk) RθJA(t)
SINGLE PULSE t2
0.001
1.0E–05 1.0E–04 1.0E–03 1.0E–02 1.0E–01 1.0E+00 1.0E+01
t, TIME (s)
Stray inductances in Motorola’s test circuit are assumed to be practical minimums. dVDS/dt in excess of 10 V/ns was at-

MMFT2N02EL
15 V
VGS
0
IFM
dlS/dt
90%
IS
trr
10%
ton IRM
0.25 IRM
tfrr
VDS(pk)
VR
VDS
Vf VdsL
MAX. CSOA
STRESS AREA
10
RGS
9 DUT
8
7 dIS/dt ≤ 400 A/µs
–
6 VR
5 + IFM IS Li
4 + VDS
3 20 V
2 –
VGS
1
0 VR = 80% OF RATED VDSS
0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 VdsL = Vf + Li ⋅ dlS/dt
Figure 10. Commutating Safe Operating Area (CSOA) Figure 11. Commutating Safe Operating Area
Test Circuit
BVDSS
VDS
IL IL(t)
VDD
t RG
VDD
tP t, (TIME)

MMFT2N02EL
VGS VDS
1800 Ciss
Coss TJ = 25°C
1600 Crss
f = 1 MHz
1400
C, CAPACITANCE (pF)
1200
1000
800
Ciss
600
400 Coss
200 Crss
0
20 15 10 5 0 5 10 15 20
Figure 14. Capacitance Variation With Voltage
10
9 TJ = 25°C
VDS = 16 V
8 ID = 1.6 A
7
6
5
4
3
2
1
0
0 5 10 15 20
+18 V VDD
SAME
1 mA 5V DEVICE TYPE
47 k 100 k
AS DUT
Vin 15 V
2N3904 0.1 µF
2N3904
100 k FERRITE
100 BEAD DUT
47 k

MOTOROLA
Medium Power Field Effect Transistor MMFT2955E

P–Channel Enhancement Mode

This advanced E–FET is a TMOS medium power MOSFET TMOS MEDIUM POWER FET
designed to withstand high energy in the avalanche and commuta- 1.2 AMP
tion modes. This new energy efficient device also offers a 60 VOLTS
drain–to–source diode with a fast recovery time. Designed for low RDS(on) = 0.3 OHM
converters and PWM motor controls, these devices are particularly

well suited for bridge circuits where diode speed and commutating
safe operating areas are critical and offer additional safety margin
against unexpected voltage transients. The device is housed in the D 4
SOT–223 package which is designed for medium power surface
mount applications. 1
2
• Silicon Gate for Fast Switching Speeds 3
• Low RDS(on) — 0.3 Ω max G
flow. The Formed Leads Absorb Thermal Stress During Sol- S TO–261AA
dering, Eliminating the Possibility of Damage to the Die
Use MMFT2955ET1 to order the 7 inch/1000 unit reel.
Use MMFT2955ET3 to order the 13 inch/4000 unit reel.

Vdc
Gate–to–Source Voltage — Continuous VGS ±15
Drain Current — Pulsed IDM 4.8
PD(1)
(VDD = 25 V, VGS = 10 V, Peak IL= 1.2 A, L = 0.2 mH, RG = 25 Ω)
DEVICE MARKING
2955
TL
REV 3

MMFT2955E
OFF CHARACTERISTICS
ON CHARACTERISTICS
Gate Threshold Voltage, (VDS = VGS, ID = 1 mA) VGS(th) 2 — 4.5 Vdc
Drain–to–Source On–Voltage, (VGS = 10 V, ID = 1.2 A) VDS(on) — — 0.48 Vdc
(VDS = 20 V,
f = 1 MHz)
MH )
VGS = 10 V
V, RG = 50 ohms
ohms, ns
(VDS = 48 V, ID = 1.2 A,
S Figures
See Fi 15 andd 16
Forward On–Voltage IS = 1.2 A, VGS = 0 VSD — 1 — Vdc
Forward Turn–On Time IS = 1.2 A, VGS = 0, ton Limited by stray inductance
dlS/dt = 400 A/µs
A/µs,

MMFT2955E
VGS(th), GATE THRESHOLD VOLTS (NORMALIZED

10 1.2
20 V 10 V 8V VDS = VGS
15 V ID = 1 mA
8 TJ = 25°C 1.1
7V
6 1
6V
4 0.9
5V
2 0.8
VGS = 4 V
0 0.7
0 2 4 6 8 10 – 50 0 50 100 150
VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS) TJ, JUNCTION TEMPERATURE (°C)

With Temperature

8 0.6
– 55°C 25°C
VGS = 10 V
VDS = 10 V 0.5
100°C
6 100°C
0.4
25°C
4 0.3
25°C – 55°C
– 55°C
0.2
2
100°C 0.1
– 55°C
0 0
0 2 4 6 8 10 0 2 4 6 8

0.5 0.5
TJ = 25°C VGS = 10 V
0.4 ID = 1.2 A 0.4 ID = 1.2 A
0.3 0.3
0.2 0.2
0.1 0.1
0 0
4 7 10 13 16 19 – 50 0 50 100 150

Gate–to–Source Voltage Junction Temperature

MMFT2955E
when it is forward biased, or when it is on, or being turned on. VGS = 20 V
Because these curves include the limitations of simultaneous SINGLE PULSE
20 ms TA = 25°C

they are especially useful to designers of linear systems. The 100 ms
1
curves are based on a ambient temperature of 25°C and a
500 ms
termined by using the thermal response curves. Motorola
0.1 DC
Application Note, AN569, “Transient Thermal Resistance–
General Data and Its Use” provides detailed instructions. RDS(on) LIMIT
THERMAL LIMIT
0.1 1 10 100
that the load line may traverse without incurring damage to
the MOSFET. The fundamental limits are the peak current, VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
IDM and the breakdown voltage, BVDSS. The switching SOA
is applicable for both turn–on and turn–off of the devices for
Safe Operating Area
1.0
D = 0.5
0.2
0.1
0.1
(NORMALIZED)

PULSE TRAIN SHOWN
0.01 t1 TJ(pk) – TA = P(pk) RθJA(t)
t2
SINGLE PULSE
0.001
1.0E–05 1.0E–04 1.0E–03 1.0E–02 1.0E–01 1.0E+00 1.0E+01
t, TIME (s)
Stray inductances in Motorola’s test circuit are assumed to be practical minimums. dV DS /dt in excess of 10 V/ns was at-

MMFT2955E
15 V
VGS
0
IFM
dlS/dt
90%
IS
trr
10%
ton IRM
0.25 IRM
tfrr
VDS(pk)
VR
VDS
Vf VdsL
MAX. CSOA
STRESS AREA
6
RGS
dIS/dt ≤ 400 A/µs DUT
5
4 –
VR
3 + IFM IS Li
+ VDS
2
20 V
1 –
VGS
0 VR = 80% OF RATED VDSS

0 10 20 30 40 50 60 70 80
VdsL = Vf + Li ⋅ dlS/dt
Figure 10. Commutating Safe Operating Figure 11. Commutating Safe Operating Area
Area (CSOA) Test Circuit
BVDSS
VDS
IL IL(t)
VDD
t RG
VDD
tP t, (TIME)

MMFT2955E
VGS VDS
1800
Ciss TJ = 25°C
1600 Crss f = 1 MHz
1400
Coss
C, CAPACITANCE (pF)
1200
1000
800
600 Ciss
400 Coss
200 Crss
0
15 10 5 0 5 10 15 20
VGS VDS
Figure 14. Capacitance Variation with Voltage
10
9
8
7
6 TJ = 25°C
VDS = 48 V
5 ID = 1.2 A
4
3
2
1
0
0 3 7.5 13 20
+18 V VDD
SAME
1 mA 10 V 100 k DEVICE TYPE
47 k
AS DUT
Vin 15 V
2N3904 0.1 µF
2N3904
100 k FERRITE
100 BEAD DUT
47 k

MOTOROLA
Product Preview MMFT3055V

TMOS V
SOT-223 for Surface Mount
TMOS POWER FET
TMOS V is a new technology designed to achieve an on–resis- TM 1.7 AMPERES
tance area product about one–half that of standard MOSFETs. This 60 VOLTS
new technology more than doubles the present cell density of our RDS(on) = 0.130 OHM
50 and 60 volt TMOS devices. Just as with our TMOS E–FET
designs, TMOS V is designed to withstand high energy in the
avalanche and commutation modes. Designed for low voltage, high D
speed switching applications in power supplies, converters and
power motor controls, these devices are particularly well suited for 4
bridge circuits where diode speed and commutating safe operating
areas are critical and offer additional safety margin against
G 1
unexpected voltage transients.
2
New Features of TMOS V 3
S
• On–resistance Area Product about One–half that of Standard
MOSFETs with New Low Voltage, Low RDS(on) Technology CASE 318E–04, Style 3
• Faster Switching than E–FET Predecessors TO–261AA
Features Common to TMOS V and TMOS E–FETS
• IDSS and VDS(on) Specified at Elevated Temperature
• Static Parameters are the Same for both TMOS V and TMOS E–FET
• Available in 12 mm Tape & Reel
Use MMFT3055VT1 to order the 7 inch/1000 unit reel
Use MMFT3055VT3 to order the 13 inch/4000 unit reel
Gate–to–Source Voltage – Continuous VGS ± 20 Vdc
Gate–to–Source Voltage – Non–repetitive (tp ≤ 10 ms) VGSM ± 25 Vpk
Drain Current – Continuous ID 1.7 Adc
Drain Current – Continuous @ 100°C ID 1.4
Drain Current – Single Pulse (tp ≤ 10 µs) IDM 6.0 Apk
Total PD @ TA = 25°C mounted on 1” sq. Drain pad on FR–4 bd material PD 2.0 Watts
Total PD @ TA = 25°C mounted on 0.70” sq. Drain pad on FR–4 bd material 1.7
Total PD @ TA = 25°C mounted on min. Drain pad on FR–4 bd material 0.9
Single Pulse Drain–to–Source Avalanche Energy – Starting TJ = 25°C EAS mJ
(VDD = 25 Vdc, VGS = 10 Vdc, Peak IL = 3.4 Apk, L = 10 mH, RG = 25 Ω ) 58
Thermal Resistance °C/W
– Junction to Ambient on 1” sq. Drain pad on FR–4 bd material RθJA 70
– Junction to Ambient on 0.70” sq. Drain pad on FR–4 bd material RθJA 88
– Junction to Ambient on min. Drain pad on FR–4 bd material RθJA 159
E–FET and TMOS V are trademarks of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.

MMFT3055V
OFF CHARACTERISTICS
Drain–to–Source Breakdown Voltage V(BR)DSS
(VGS = 0 Vdc, ID = 0.25 mAdc) 60 — — Vdc
(VDS = 60 Vdc, VGS = 0 Vdc) — — 10
Gate–Body Leakage Current (VGS = ± 20 Vdc, VDS = 0 Vdc) IGSS — — 100 nAdc
Gate Threshold Voltage VGS(th)
(VDS = VGS, ID = 250 µAdc) 2.0 2.8 4.0 Vdc
Static Drain–to–Source On–Resistance (VGS = 10 Vdc, ID = 0.85 Adc) RDS(on) — 0.115 0.13 Ohm
Drain–to–Source On–Voltage VDS(on) Vdc
(VGS = 10 Vdc, ID = 1.7 Adc) — — 0.27
(VGS = 10 Vdc, ID = 0.85 Adc, TJ = 150°C) — — 0.25
Vd VGS = 0 Vdc,
Vd
Coss — 110 150
f = 1.0 MHz)

VGS = 10 Vdc
Vdc,
((VDS = 48 Vdc, ID = 1.7 Adc, Q1 — 2.0 —

VGS = 10 Vdc) Q2 — 5.0 —
Q3 — 4.0 —
Forward On–Voltage (1) VSD Vdc
— 0.85 1.6
(IS = 1.7 Adc, VGS = 0 Vdc, TJ = 150°C)
— 0.7 —
((IS = 1.7 Adc, VGS = 0 Vdc, ta — 34 —

dIS/dt = 100 A/µs) tb — 6.0 —
(Measured from the drain lead 0.25″ from package to center of die) — 4.5 —

(Measured from the source lead 0.25″ from package to source bond pad) — 7.5 —

MOTOROLA
Product Preview MMFT3055VL

TMOS V
SOT-223 for Surface Mount
TMOS POWER FET
TMOS V is a new technology designed to achieve an on–resis- TM 1.5 AMPERES
tance area product about one–half that of standard MOSFETs. This 60 VOLTS
new technology more than doubles the present cell density of our RDS(on) = 0.140 OHM
avalanche and commutation modes. Designed for low voltage, high D
power motor controls, these devices are particularly well suited for
4
G 1
2
New Features of TMOS V 3
S
MOSFETs with New Low Voltage, Low RDS(on) Technology CASE 318E–04, Style 3
• Faster Switching than E–FET Predecessors TO–261AA
• Available in 12 mm Tape & Reel
Use MMFT3055VLT1 to order the 7 inch/1000 unit reel
Use MMFT3055VLT3 to order the 13 inch/4000 unit reel
Gate–to–Source Voltage – Continuous VGS ± 15 Vdc
Gate–to–Source Voltage – Non–repetitive (tp ≤ 10 ms) VGSM ± 20 Vpk
Drain Current – Continuous ID 1.5 Adc
Drain Current – Single Pulse (tp ≤ 10 µs) IDM 5.0 Apk
Total PD @ TA = 25°C mounted on 1” sq. Drain pad on FR–4 bd material PD 2.0 Watts
Total PD @ TA = 25°C mounted on 0.70” sq. Drain pad on FR–4 bd material 1.7
Total PD @ TA = 25°C mounted on min. Drain pad on FR–4 bd material 0.9
(VDD = 25 Vdc, VGS = 5.0 Vdc, Peak IL = 3.0 Apk, L = 10 mH, RG = 25 Ω ) 45
– Junction to Ambient on 1” sq. Drain pad on FR–4 bd material RθJA 70
– Junction to Ambient on 0.70” sq. Drain pad on FR–4 bd material RθJA 88
– Junction to Ambient on min. Drain pad on FR–4 bd material RθJA 159
E–FET and TMOS V are trademarks of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.

MMFT3055VL
OFF CHARACTERISTICS
(VDS = 60 Vdc, VGS = 0 Vdc) — — 10
Static Drain–to–Source On–Resistance (VGS = 5.0 Vdc, ID = 0.75 Adc) RDS(on) — 0.125 0.14 Ohm
(VGS = 5.0 Vdc, ID = 1.5 Adc) — — 0.25
(VGS = 5.0 Vdc, ID = 0.75 Adc, TJ = 150°C) — — 0.24
Vd VGS = 0 Vdc,
Vd
Coss — 110 150
f = 1.0 MHz)

VGS = 5
5.00 Vdc,
Vdc
((VDS = 48 Vdc, ID = 1.5 Adc, Q1 — 1.0 —

VGS = 5.0 Vdc) Q2 — 4.0 —
Q3 — 4.0 —
— 0.82 1.2
(IS = 1.5 Adc, VGS = 0 Vdc, TJ = 150°C)
— 0.68 —
((IS = 1.5 Adc, VGS = 0 Vdc, ta — 29 —

dIS/dt = 100 A/µs) tb — 12 —


MOTOROLA

Medium Power Surface Mount Products MMSF2P02E
TMOS Single P-Channel
Field Effect Transistors SINGLE TMOS

avalanche and commutation modes and the drain–to–source diode 
drives. The avalanche energy is specified to eliminate the G SO–8
guesswork in designs where inductive loads are switched and offer
S
• Miniature SO–8 Surface Mount Package — Saves Board Space N–C 1 8 Drain
• Diode Is Characterized for Use In Bridge Circuits Source 2 7 Drain
• Diode Exhibits High Speed Source 3 6 Drain
• Avalanche Energy Specified Gate 4 5 Drain

Total Power Dissipation @ TA = 25°C(2) PD 2.5 Watts
Thermal Resistance — Junction to Ambient(2) RθJA 50 °C/W
DEVICE MARKING
S2P02
(2) Mounted on 2” square FR4 board (1” sq. 2 oz. Cu 0.06” thick single sided), 10 sec. max.
MMSF2P02ER2 13″ 12 mm embossed tape 2500 units
REV 3

MMSF2P02E
OFF CHARACTERISTICS
(VGS = 0 Vdc, ID = 250 µAdc) 20 — —
(VDS = 20 Vdc, VGS = 0 Vdc) — — 1.0
(VDS = VGS, ID = 250 µAdc) 1.0 2.0 3.0
Threshold Temperature Coefficient (Negative) 4.7 — mV/°C
(VGS = 10 Vdc, ID = 2.0 Adc) — 0.19 0.25
(VGS = 4.5 Vdc, ID = 1.0 Adc) — 0.3 0.4
Vd VGS = 0 Vdc,
Vd
Coss — 220 300
f = 1.0 MHz)
VGS = 5.0
5 0 Vdc,
Vdc
VGS = 10 Vdc
Vdc,
((VDS = 16 Vdc, ID = 2.0 Adc, Q1 — 1.1 —

VGS = 10 Vdc) Q2 — 3.3 —
Q3 — 2.5 —

((IS = 2.0 Adc, VGS = 0 Vdc, ta — 18 —

dIS/dt = 100 A/µs) tb — 16 —

MMSF2P02E
4 4
VGS = 10 7 V 5V TJ = 25°C VDS ≥ 10 V
4.7 V
4.5 V

3 3
4.3 V
100°C
2 4.1 V 2
25°C
3.9 V TJ = –55°C
1 1
3.7 V
3.5 V
3.3 V
0 0
0 0.4 0.8 1.2 1.6 2 2.5 3 3.5 4 4.5


0.6 0.6
ID = 1 A TJ = 25°C
0.5 TJ = 25°C
0.5
0.4
0.4
0.3
VGS = 4.5
0.3
0.2
0.2
0.1 10 V
0 0.1
3 4 5 6 7 8 9 10 0 0.5 1 1.5 2

2.0 100
ID = 2 A
1.5
TJ = 125°C
1.0 10
0.5 100°C
0 1
– 50 – 25 0 25 50 75 100 125 150 0 4 8 12 16 20


MMSF2P02E
t = Q/IG(AV)
1000

12 16
VDS = 0 V VGS = 0 V TJ = 25°C

QT
Ciss
800
9 VGS 12
C, CAPACITANCE (pF)
VDS
600
6 8
Q1 Q2
400 Crss Ciss
Coss 3 4
200 Q3
ID = 2 A
Crss
TJ = 25°C
0 0 0
10 5 0 5 10 15 20 25 30 0 2 4 6 8 10 12
100 2
VDD = 10 V TJ = 25°C
ID = 2 A VGS = 0 V
VGS = 10 V 1.6
TJ = 25°C
1.2
t, TIME (ns)
td(off) 0.8
tr
tf 0.4
td(on)
10 0
1 10 100 0.6 0.8 1 1.2 1.4 1.6

MMSF2P02E
100 Mounted on 2” sq. FR4 board (1” sq. 2 oz. Cu 0.06”
di/dt = 300 A/µs Standard Cell Density VGS = 20 V
thick single sided), 10s max.
trr SINGLE PULSE
TC = 25°C

High Cell Density
10
trr 1 ms
tb 10 ms
ta
1
dc
0.1
RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT
0.01
0.1 1 10 100
t, TIME VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
Figure 11. Reverse Recovery Time (trr) Figure 12. Maximum Rated Forward Biased
Safe Operating Area
250
ID = 6 A
200
150
100
50
0
25 50 75 100 125 150
TJ, STARTING JUNCTION TEMPERATURE (°C)
Figure 13. Maximum Avalanche Energy versus

Starting Junction Temperature
Although many E–FETs can withstand the stress of drain– rating must be derated for temperature as shown in the ac-
to–source avalanche at currents up to rated pulsed current companying graph (Figure 13). Maximum energy at currents
(IDM), the energy rating is specified at rated continuous cur- below rated continuous ID can safely be assumed to equal
rent (ID), in accordance with industry custom. The energy the values indicated.
10
THERMAL RESISTANCE
1 D = 0.5
0.2
0.1
0.1
0.02 Chip 0.0022 Ω 0.0210 Ω 0.2587 Ω 0.7023 Ω 0.6863 Ω
0.01
0.01
0.0020 F 0.0207 F 0.3517 F 3.1413 F 108.44 F
Ambient
SINGLE PULSE
0.001
1.0E–05 1.0E–04 1.0E–03 1.0E–02 1.0E–01 1.0E+00 1.0E+01 1.0E+02 1.0E+03
t, TIME (s)

MMSF2P02E
di/dt
IS
trr
ta tb
TIME
tp 0.25 IS
IS

MOTOROLA

Medium Power Surface Mount Products MMSF3P02HD
TMOS Single P-Channel

drives and tape drives. The avalanche energy is specified to G SO–8
• Logic Level Gate Drive — Can Be Driven by Logic ICs N–C 1 8 Drain
• Miniature SO–8 Surface Mount Package — Saves Board Space Source 2 7 Drain
Source 3 6 Drain
Gate 4 5 Drain
Thermal Resistance — Junction to Ambient (2) RθJA 50 °C/W
DEVICE MARKING
S3P02
MMSF3P02HDR2 13″ 12 mm embossed tape 2500 units
REV 4

MMSF3P02HD
OFF CHARACTERISTICS
(VGS = 0 Vdc, ID = 250 µAdc) 20 — —
(VDS = 20 Vdc, VGS = 0 Vdc) — — 1.0
(VDS = VGS, ID = 250 µAdc) 1.0 1.5 2.0
Static Drain–Source On–Resistance RDS(on) Ohm
(VGS = 10 Vdc, ID = 3.0 Adc) — 0.06 0.075
(VGS = 4.5 Vdc, ID = 1.5 Adc) — 0.08 0.095
Vd VGS = 0 Vdc,
Vd
Coss — 740 920
f = 1.0 MHz)
VGS = 4.5
4 5 Vdc,
Vdc
VGS = 10 Vdc
Vdc,
S Fi
See Figure 8
((VDS = 16 Vdc, ID = 3.0 Adc, Q1 — 3.0 —
VGS = 10 Vdc) Q2 — 11 —
Q3 — 10 —

— 1.35 1.75
(IS = 3.0 Adc, VGS = 0 Vdc, TJ = 125°C)
— 0.96 —
S Figure
See Fi 15
((IS = 3.0 Adc, VGS = 0 Vdc, ta — 32 —
dIS/dt = 100 A/µs) tb — 44 —

MMSF3P02HD
6 6
VGS = 10 V 3.5 V 3.3 V TJ = 25°C VDS ≥ 10 V
5 3.7 V 5

4.5 V
3.9 V 3.1 V
4 4
3 3
2.9 V
2 2 TJ = 100°C
2.7 V
25°C
1 1
2.5 V – 55°C
0 0
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4

R DS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS)
R DS(on) , DRAIN-TO-SOURCE RESISTANCE (OHMS)

0.6 0.09
TJ = 25°C
ID = 1.5 A
TJ = 25°C
0.08
VGS = 4.5 V
0.4
0.07
0.2
0.06 10 V
0 0.05
0 1 2 3 4 5 6 7 8 9 10 0 1 2 3 4 5 6

1.20 1000
ID = 3.0 A
1.10
(NORMALIZED)
TJ = 125°C
1.00 100
0.90
0.80 10
– 50 0 25 50 75 100 125 150 0 4 8 12 16 20


MMSF3P02HD
3500
VDS = 0 V VGS = 0 V TJ = 25°C
3000
Ciss
C, CAPACITANCE (pF)
2500
2000
1500
Crss Ciss
1000
Coss
500 Crss
0
10 5 0 5 10 15 20
VGS VDS

MMSF3P02HD
1000

12 24

QT VDD = 10 V
10 20 ID = 3 A
VGS VGS = 10 V
TJ = 25°C
8 16
t, TIME (ns)
td(off)
6 ID = 3 A 12 100
Q1 Q2 TJ = 25°C
tf
4 8
tr
2 4
VDS td(on)
Q3
0 0 10
0 4 8 12 16 20 24 28 32 36 1 10 100

snappy.
3
VGS = 0 V
2.5 TJ = 25°C
1.5
0.5
0
0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4

MMSF3P02HD
trr
High Cell Density
trr
tb
ta
t, TIME
SAFE OPERATING AREA
perature.
100 600
VGS = 20 V ID = 9 A
SINGLE PULSE
100 µs
TC = 25°C
10 1 ms 450
10 ms
1 dc 300
RDS(on) LIMIT
THERMAL LIMIT
0.1 150
PACKAGE LIMIT
0.01 0
0.1 1 10 100 25 50 75 100 125 150

MMSF3P02HD
10
THERMAL RESISTANCE
1 D = 0.5
0.2
0.1
0.1
0.02 Chip 0.0163 Ω 0.0652 Ω 0.1988 Ω 0.6411 Ω 0.9502 Ω
0.01
0.01
0.0307 F 0.1668 F 0.5541 F 1.9437 F 72.416 F
Ambient
SINGLE PULSE
0.001
1.0E–05 1.0E–04 1.0E–03 1.0E–02 1.0E–01 1.0E+00 1.0E+01 1.0E+02 1.0E+03
t, TIME (s)
di/dt
IS
trr
ta tb
TIME
tp 0.25 IS
IS

MOTOROLA
Advance Information MMSF3P02Z

TMOS Single P-Channel with Motorola Preferred Device

Protected Gate SINGLE TMOS
POWER MOSFET
EZFETs are an advanced series of power MOSFETs which utilize 3.0 AMPERES
Motorola’s High Cell Density TMOS process and contain monolithic 20 VOLTS
back–to–back zener diodes. These zener diodes provide protection RDS(on) = 0.060 OHM
against ESD and unexpected transients. These miniature surface 
mount MOSFETs feature ultra low RDS(on) amd true logic level
has a very low reverse recovery time. EZFET devices are designed
for use in low voltage, high speed switching applications where power D
efficiency is important. Typical applications are dc–dc converters, and
power management in portable and battery powered products such as
computers, printers, cellular and cordless phones. They can also be CASE 751–05, Style 12
used for low voltage motor controls in mass storage products such as G SO–8
• Zener Protected Gates Provide Electrostatic Discharge Protection S
Source 1 8 Drain
• Designed to withstand 200V Machine Model and 2000V Human Body Model
Source 2 7 Drain
• Diode Is Characterized for Use In Bridge Circuits Gate 4 5 Drain
Top View
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted) *
(VDD = 20 Vdc, VGS = 5.0 Vdc, Peak IL = 9 Apk, L = 14 mH, RG = 25 Ω) 567
— Junction to Ambient (2) 80
* Negative sign for P–Channel omitted for clarity.
(1) When mounted on 1 inch square FR–4 or G–10 board (VGS = 10 V, @ 10 Seconds)
(2) When mounted on minimum recommended FR–4 or G–10 board (VGS = 10 V, @ Steady State)
S3P02Z
MMSF3P02ZR2 13″ 12 mm embossed tape 2500 units
REV 1

MMSF3P02Z
OFF CHARACTERISTICS
Drain–to–Source Breakdown Voltage (Cpk ≥ 2.0) (1) (3) V(BR)DSS Vdc
(VGS = 0 Vdc, ID = 250 µAdc) 20 — —
(VDS = 20 Vdc, VGS = 0 Vdc) — 0.05 2.0
Gate–Body Leakage Current (VGS = ± 15 Vdc, VDS = 0) IGSS — 0.85 5.0 µAdc
Gate Threshold Voltage (Cpk ≥ 2.0) (1) (3) VGS(th) Vdc
(VDS = VGS, ID = 250 µAdc) 1.0 1.8 3.0
Static Drain–to–Source On–Resistance (Cpk ≥ 2.0) (1) (3) RDS(on) mΩ
(VGS = 10 Vdc, ID = 3.0 Adc) — 45 60
(VGS = 4.5 Vdc, ID = 1.5 Adc) — 65 80
Forward Transconductance (VDS = 3.0 Vdc, ID = 1.5 Adc) (1) gFS 4.0 5.6 — Mhos
Vd VGS = 0 Vdc,
Vd
Coss — 720 1440
f = 1.0 MHz)
Rise Time ((VDD = 10 Vdc, ID = 3.0 Adc, tr — 350 700
Turn–Off Delay Time VGS = 10 Vdc, RG = 6.0 Ω) (1) td(off) — 810 1620
Turn–Off Delay Time VGS = 4.5 Vdc, RG = 6.0 Ω) (1) td(off) — 510 1020
((VDS = 16 Vdc, ID = 3.0 Adc, Q1 — 2.7 —

VGS = 10 Vdc) (1) Q2 — 14.3 —
Q3 — 10.2 —

(IS = 3.0 Adc, VGS = 0 Vdc) (1)
— 1.2 1.6
(IS = 3.0 Adc, VGS = 0 Vdc, TJ = 125°C)
— 0.76 —
(IS = 3
3.0
0 Ad
Adc, VGS = 0 Vdc,
Vd
ta — 256 —
dIS/dt = 100 A/µs) (1)
tb — 420 —
Cpk =
3 x SIGMA

MMSF3P02Z
6 6
VGS = 10 V VDS ≥ 10 V
3.3 V TJ = 25°C
4.5 V
5 5

3.8 V
4 3.1 V
4
3 3
2.9 V
2 2 TJ = –55°C
2.7 V 25°C
1 1 100°C
2.4 V
0 0
0 0.5 1 1.5 2 1.5 2 2.5 3 3.5


0.4 0.08
ID = 1.5 A TJ = 25°C
TJ = 25°C VGS = 4.5
0.3 0.06
10 V
0.2 0.04
0.1 0.02
0 0
0 2 4 6 8 10 0 1 2 3 4 5 6

2.0 1000
ID = 1.5 A
1.5
TJ = 125°C
100
1.0
100°C
10
0.5
0 1
– 50 – 25 0 25 50 75 100 125 150 0 5 10 15 20


MMSF3P02Z
2500
TJ = 25°C
VGS = 0 V
2000
C, CAPACITANCE (pF)
1500
Ciss
1000 Coss
500 Crss
0
0 5 10 15 20

MMSF3P02Z

12 16 10000

VDD = 10 V
QT
ID = 3 A
VGS = 10 V
9 12 TJ = 25°C
1000 tf
td(off)
t, TIME (ns)
VDS VGS
6 8 tr
Q1 Q2
100 td(on)
3 4
Q3 ID = 3 A
TJ = 25°C
0 0 10
0 10 20 30 40 1 10 100

snappy.
3
VGS = 0 V
TJ = 25°C
2.5
1.5
0.5
0
0.4 0.6 0.8 1.0 1.2

MMSF3P02Z
trr
High Cell Density
trr
tb
ta
t, TIME
SAFE OPERATING AREA
perature.
100 600
VGS = 15 V
ID = 9 A
SINGLE PULSE
TC = 25°C
10 400
1 ms
10 ms
1 200
RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT dc
0.1 0
0.1 1 10 100 25 50 75 100 125 150

MMSF3P02Z
10
THERMAL RESISTANCE
1 D = 0.5
0.2
0.1
0.1
0.02 Chip 0.0163 Ω 0.0652 Ω 0.1988 Ω 0.6411 Ω 0.9502 Ω
0.01
0.01
0.0307 F 0.1668 F 0.5541 F 1.9437 F 72.416 F
Ambient
SINGLE PULSE
0.001
1.0E–05 1.0E–04 1.0E–03 1.0E–02 1.0E–01 1.0E+00 1.0E+01 1.0E+02 1.0E+03
t, TIME (s)
di/dt
IS
trr
ta tb
TIME
tp 0.25 IS
IS

MOTOROLA

TMOS P-Channel

SINGLE TMOS POWER FET
SO–8
G
N–C 1 8 Drain
Source 2 7 Drain
Source 3 6 Drain
DEVICE MARKING
S3P03
REV 4

MMSF3P03HD
OFF CHARACTERISTICS
(VGS = 0 Vdc, ID = 250 µAdc) 30 — —
(VDS = 30 Vdc, VGS = 0 Vdc) — — 1.0
Gate–Body Leakage Current (VGS = ± 20 Vdc, VDS = 0) IGSS — 5.0 100 nAdc
(VDS = VGS, ID = 250 µAdc) 1.0 1.5 2.0
(VGS = 10 Vdc, ID = 3.0 Adc) — 0.80 0.100
(VGS = 4.5 Vdc, ID = 1.5 Adc) — 0.90 0.110
Vd VGS = 0 Vdc,
Vd
Coss — 470 660
f = 1.0 MHz)
VGS = 4.5
4 5 Vdc,
Vdc
VGS = 10 Vdc
Vdc,
((VDS = 24 Vdc, ID = 3.0 Adc, Q1 — 2.7 —

VGS = 10 Vdc) Q2 — 9.0 —
Q3 — 6.9 —

— 1.3 2.0
(IS = 3.0 Adc, VGS = 0 Vdc, TJ = 125°C)
— 0.85 —
((IS = 3.0 Adc, ta — 22 —

dIS/dt = 100 A/µs) tb — 9.0 —

MMSF3P03HD
6 6
VGS = 10 V TJ = 25°C VDS ≥ 10 V
5 4.5 V
5

3.1 V
3.8 V
4 4
2.9 V
3 3
2 2.7 V 2 TJ = 100°C
25°C
1 1
2.4 V – 55°C
0 0
0 0.4 0.8 1.2 1.6 2 2 2.2 2.4 2.6 2.8 3 3.2


0.6 0.095
ID = 1.5 A TJ = 25°C
0.5 0.09
0.4
0.085 VGS = 4.5 V
0.3
0.08 10 V
0.2
0.075
0.1
0 0.07
0 2 4 6 8 10 0 1 2 3 4 5 6

3.0 1000
VGS = 0 V
VGS = 4.5 V
2.5 ID = 1.5 A
TJ = 125°C
2.0 100
(NORMALIZED)
1.5
1.0 10 100°C
0.5
0 1
– 50 – 25 0 25 50 75 100 125 150 0 5 10 15 20 25 30


MMSF3P03HD
3500
VDS = 0 V VGS = 0 V TJ = 25°C
3000
Ciss
C, CAPACITANCE (pF)
2500
2000
1500
Crss Ciss
1000
Coss
500 Crss
0
10 5 0 5 10 15 20 25 30
VGS VDS

MMSF3P03HD
1000

12 24

QT VDD = 15 V
10 20 ID = 3 A
VGS = 10 V
VGS TJ = 25°C
8 VDS 16
t, TIME (ns)
6 12 100 td(off)
ID = 3 A tf
4 Q1 Q2 TJ = 25°C 8
tr
2 Q3 4
td(on)
0 0 10
0 5 10 15 20 25 30 35 1 10 100

snappy.
3
VGS = 0 V
2.5 TJ = 25°C
1.5
0.5
0
0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3

MMSF3P03HD
trr
High Cell Density
trr
tb
ta
t, TIME
SAFE OPERATING AREA
perature.
100 600
VGS = 20 V ID = 9 A
10 µs
TC = 25°C
1 ms
10
10 ms
400
1 dc 300
RDS(on) LIMIT 200

THERMAL LIMIT
0.1
PACKAGE LIMIT
100
0.01 0
0.1 1 10 100 25 50 75 100 125 150

MMSF3P03HD

THERMAL RESISTANCE
1 D = 0.5
0.2
0.1
0.1
0.02 Chip 0.0163 Ω 0.0652 Ω 0.1988 Ω 0.6411 Ω 0.9502 Ω
0.01
0.01
0.0307 F 0.1668 F 0.5541 F 1.9437 F 72.416 F
Ambient
SINGLE PULSE
0.001
1.0E–05 1.0E–04 1.0E–03 1.0E–02 1.0E–01 1.0E+00 1.0E+01 1.0E+02 1.0E+03
t, TIME (s)
di/dt
IS
trr
ta tb
TIME
tp 0.25 IS
IS

MOTOROLA

TMOS P-Channel

SINGLE TMOS POWER FET
SO–8
drives and tape drives. G
• Miniature SO–8 Surface Mount Package — Saves Board Space N–C 1 8 Drain
Source 2 7 Drain
Source 3 6 Drain
• Mounting Information for SO–8 Package Provided Gate 4 5 Drain
Top View
DEVICE MARKING
S4P01
REV 4

MMSF4P01HD
OFF CHARACTERISTICS
(VGS = 0 Vdc, ID = 250 µAdc) 12 — —
(VDS = 12 Vdc, VGS = 0 Vdc) — — 1.0
(VDS = VGS, ID = 250 µAdc) 0.7 0.95 1.1
(VGS = 4.5 Vdc, ID = 4.0 Adc) — 0.073 0.08
(VGS = 2.7 Vdc, ID = 2.0 Adc) — 0.08 0.09
Vd VGS = 0 Vdc,
Vd
Coss — 935 1300
f = 1.0 MHz)
VGS = 2.7
2 7 Vdc,
Vdc
VGS = 4.5
4 5 Vdc,
Vdc
((VDS = 10 Vdc, ID = 4.0 Adc, Q1 — 2.4 —

VGS = 4.5 Vdc) Q2 — 11.4 —
Q3 — 8.4 —

— 1.3 1.8
(IS = 4.0 Adc, VGS = 0 Vdc, TJ = 125°C)
— 1.1 —
((IS = 4.0 Adc, VGS = 0 Vdc, ta — 66 —

dIS/dt = 100 A/µs) tb — 68 —

MMSF4P01HD
8 8
VGS = 8 V 2.5 V TJ = 25°C VDS ≥ 10 V
2.3 V
4.5 V

3.1 V
6 6
2.7 V
2.1 V
4 4
1.9 V
TJ = 100°C 25°C
2 2
1.7 V – 55°C
1.5 V
0 0
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 1 1.2 1.4 1.6 1.8 2 2.2 2.4

0.16 0.1
TJ = 25°C TJ = 25°C
ID = 2 A
0.12 0.09
VGS = 2.7 V
0.08 0.08
0.04 0.07 4.5 V
0 0.06
0 2 4 6 8 0 2 4 6 8

2 1000
R DS(on) , DRAIN–TO–SOURCE RESISTANCE
VGS = 0 V
VGS = 4.5 V
ID = 4 A TJ = 125°C
1.5
I DSS, LEAKAGE (nA)
(NORMALIZED)
1 100
100°C
0.5
0 10
– 50 – 25 0 25 50 75 100 125 150 0 3 6 9 12


MMSF4P01HD
4800
VDS = 0 V VGS = 0 V TJ = 25°C
4000 Ciss
C, CAPACITANCE (pF)
3200
2400
Crss
1600 Ciss
800 Coss
Crss
0
8 4 0 4 8 12
VGS VDS

MMSF4P01HD
5 10 1000

QT VDD = 6 V
ID = 4 A
4 8 VGS = 4.5 V
VDS VGS TJ = 25°C
3 6 tf
t, TIME (ns)
Q1 Q2 100
td(off)
2 4 tr
ID = 4 A
TJ = 25°C
1 Q3 2
td(on)
0 0 10
0 5 10 15 20 25 1 10 100
QG, TOTAL GATE CHARGE (nC) RG, GATE RESISTANCE (OHMS)

snappy.
4
VGS = 0 V
TJ = 25°C
0
0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3

MMSF4P01HD
trr
High Cell Density
trr
tb
ta
t, TIME
SAFE OPERATING AREA
100
VGS = 10 V
SINGLE PULSE
TC = 25°C
10 1 ms
10 ms
1 dc
RDS(on) LIMIT
THERMAL LIMIT
0.1
PACKAGE LIMIT
0.01
0.1 1 10 100

Safe Operating Area

MMSF4P01HD
10
THERMAL RESISTANCE
1 D = 0.5
0.2
0.1
0.1
0.02 Chip 0.0163 Ω 0.0652 Ω 0.1988 Ω 0.6411 Ω 0.9502 Ω
0.01
0.01
0.0307 F 0.1668 F 0.5541 F 1.9437 F 72.416 F
Ambient
SINGLE PULSE
0.001
1.0E–05 1.0E–04 1.0E–03 1.0E–02 1.0E–01 1.0E+00 1.0E+01 1.0E+02 1.0E+03
t, TIME (s)
di/dt
IS
trr
ta tb
TIME
tp 0.25 IS
IS

MOTOROLA
Advance Information MMSF4P01Z

TMOS Single P-Channel with Motorola Preferred Device

POWER MOSFET
used for low voltage motor controls in mass storage products such as SO–8
G
• Zener Protected Gates Provide Electrostatic Discharge Protection
• Ultra Low RDS(on) Provides Higher Efficiency and Extends Battery Life S
Source 1 8 Drain
Source 2 7 Drain
Top View
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted) *
* Negative sign for P–Channel omitted for clarity.
(1) When mounted on 1 inch square FR–4 or G–10 board (VGS = 4.5 V, @ 10 Seconds)
(2) When mounted on minimum recommended FR–4 or G–10 board (VGS = 4.5 V, @ Steady State)
S4P01Z
MMSF4P01ZR2 13″ 12 mm embossed tape 2500 units
REV 1

MMSF4P01Z
OFF CHARACTERISTICS
(VGS = 0 Vdc, ID = 250 µAdc) 20 — —
(VDS = 12 Vdc, VGS = 0 Vdc) — 0.05 2.0
Gate–Body Leakage Current (VGS = ± 8.0 Vdc, VDS = 0) IGSS — 0.15 5.0 µAdc
(VDS = VGS, ID = 250 µAdc) 0.7 0.85 1.1
(VGS = 4.5 Vdc, ID = 4.0 Adc) — 50 70
(VGS = 2.7 Vdc, ID = 2.0 Adc) — 70 90
Vd VGS = 0 Vdc,
Vd
Coss — 825 1650
f = 1.0 MHz)
Rise Time ((VDD = 6.0 Vdc, ID = 4.0 Adc, tr — 800 1600
Rise Time ((VDD = 6.0 Vdc, ID = 4.0 Adc, tr — 1950 3900
((VDS = 10 Vdc, ID = 4.0 Adc, Q1 — 3.0 —

VGS = 4.5 Vdc) (1) Q2 — 11 —
Q3 — 8.0 —

(IS = 4.0 Adc, VGS = 0 Vdc) (1)
— 1.1 1.8
(IS = 4.0 Adc, VGS = 0 Vdc, TJ = 125°C)
— 0.75 —
(IS = 4
4.0
0 Ad
Adc, VGS = 0 Vdc,
Vd
ta — 750 —
dIS/dt = 100 A/µs) (1)
tb — 1120 —
Cpk =
3 x SIGMA

MMSF4P01Z
8 8
VGS = 8 V 2.7 V TJ = 25°C VDS ≥ 10 V
4.5 V 2.4 V
2V

3.1 V
6 6
4 1.8 V 4
TJ = –55°C 25°C
2 2
1.6 V
100°C
0 0
0 0.4 0.6 1.2 1.6 2 0.4 0.8 1.2 1.6 2


0.4 0.09
ID = 2 A
TJ = 25°C
TJ = 25°C
VGS = 2.7 V
0.3
0.06 4.5 V
0.2
0.03
0.1
0 0
0 2 4 6 8 0 2 4 6 8

2.0 1000
VGS = 4.5 V VGS = 0 V
ID = 2 A TJ = 125°C
1.5
100
100°C
1.0
10
0.5
0 1
– 50 – 25 0 25 50 75 100 125 150 0 3 6 9 12


MMSF4P01Z
3500
TJ = 25°C
VGS = 0 V
2800
C, CAPACITANCE (pF)
2100
Ciss
1400
Coss
700 Crss
0
0 4 8 12

MMSF4P01Z

5 10 10000

QT VDD = 6 V
ID = 4 A
4 8 VGS = 4.5 V tf
TJ = 25°C td(off)
VDS VGS 1000
tr
t, TIME (ns)
3 6
Q1 Q2
2 4 td(on)
100
1 2
ID = 4 A
Q3 TJ = 25°C
0 0 10
0 5 10 15 20 25 1 10 100

snappy.
4
VGS = 0 V
TJ = 25°C
0
0.1 0.3 0.5 0.7 0.9 1.1

MMSF4P01Z
trr
High Cell Density
trr
tb
ta
t, TIME
SAFE OPERATING AREA
The Forward Biased Safe Operating Area curves define in switching circuits with unclamped inductive loads. For reli-
the maximum simultaneous drain–to–source voltage and able operation, the stored energy from circuit inductance dis-
drain current that a transistor can handle safely when it is for- sipated in the transistor while in avalanche must be less than
ward biased. Curves are based upon maximum peak junc- the rated limit and must be adjusted for operating conditions
tion temperature and a case temperature (TC) of 25°C. Peak differing from those specified. Although industry practice is to
repetitive pulsed power limits are determined by using the rate in terms of energy, avalanche energy capability is not a
thermal response data in conjunction with the procedures constant. The energy rating decreases non–linearly with an
discussed in AN569, “Transient Thermal Resistance – Gen- increase of peak current in avalanche and peak junction tem-
eral Data and Its Use.” perature.
Switching between the off–state and the on–state may tra- Although many E–FETs can withstand the stress of drain–
averaged over a complete switching cycle must not exceed ing must be derated for temperature. Maximum energy at
(TJ(MAX) – TC)/(RθJC). currents below rated continuous ID can safely be assumed to
A power MOSFET designated E–FET can be safely used equal the values indicated.
100
VGS = 8 V
SINGLE PULSE
TC = 25°C
10 100 µs
1 ms
10 ms
1
RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT
0.1 dc
0.1 1 10 100

Safe Operating Area

MMSF4P01Z
10
THERMAL RESISTANCE
1 D = 0.5
0.2
0.1
0.1
0.02 Chip 0.0163 Ω 0.0652 Ω 0.1988 Ω 0.6411 Ω 0.9502 Ω
0.01
0.01
0.0307 F 0.1668 F 0.5541 F 1.9437 F 72.416 F
Ambient
SINGLE PULSE
0.001
1.0E–05 1.0E–04 1.0E–03 1.0E–02 1.0E–01 1.0E+00 1.0E+01 1.0E+02 1.0E+03
t, TIME (s)
di/dt
IS
trr
ta tb
TIME
tp 0.25 IS
IS

MOTOROLA

Medium Power Surface Mount Products MMSF5N02HD
TMOS Single N-Channel

SO–8
G
N–C 1 8 Drain
Source 2 7 Drain
Top View
(VDD = 20 Vdc, VGS = 5.0 Vdc, Peak IL = 15 Apk, L = 6.0 mH, RG = 25 Ω)
DEVICE MARKING
S5N02
REV 4

MMSF5N02HD
OFF CHARACTERISTICS
(VGS = 0 Vdc, ID = 250 µAdc) 20 — —
(VDS = 20 Vdc, VGS = 0 Vdc) — 0.02 1.0
(VDS = VGS, ID = 250 µAdc) 1.0 1.5 2.0
(VGS = 10 Vdc, ID = 5.0 Adc) — 0.0185 0.025
(VGS = 4.5 Vdc, ID = 2.5 Adc) — 0.0219 0.040
Forward Transconductance (VDS = 15 Vdc, ID = 2.5 Adc) gFS 3.0 12 — Mhos
Vd VGS = 0 Vdc,
Vd
Coss — 464 650
f = 1.0 MHz)
VGS = 4.5
4 5 Vdc,
Vdc
Turn–On Delay Time td(on) — 9.0 —
Rise Time (VDD = 10 Vdc, ID = 5.0 Adc, tr — 53 —
VGS = 10 Vdc
Vdc,
Turn–Off Delay Time RG = 6.0 Ω) td(off) — 56 —
S Fi
See Figure 8
((VDS = 16 Vdc, ID = 5.0 Adc, Q1 — 3.0 —
VGS = 10 Vdc) Q2 — 7.5 —
Q3 — 6.0 —

— 0.82 1.0
(IS = 5.0 Adc, VGS = 0 Vdc, TJ = 125°C)
— 0.69 —
S Figure
See Fi 15
((IS = 5.0 Adc, VGS = 0 Vdc, ta — 24 —
dIS/dt = 100 A/µs) tb — 8.0 —

MMSF5N02HD
10 10
VGS = 10 V TJ = 25°C VDS ≥ 10 V
3.1 V

8 4.5 V 8
3.8 V
6 6
4 4
TJ = 100°C
25°C
2 2
– 55°C
2.4 V
0 0
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 1.5 1.7 1.9 2.1 2.3 2.5 2.7 2.9 3.1 3.3

0.2 0.023
ID = 2.5 A TJ = 25°C VGS = 4.5 V
0.16
0.021
0.12
0.08
0.019
10 V
0.04
0 0.017
0 1 2 3 4 5 6 7 8 9 10 0 2 4 6 8 10

1.6 1000
VGS = 0 V
VGS = 10 V
ID = 2.5 A TJ = 125°C
1.4
100
(NORMALIZED)
1.2
100°C
1
25°C
10
0.8
0.6 1
– 50 – 25 0 25 50 75 100 125 150 0 4 8 12 16 20


MMSF5N02HD
3500
VDS = 0 V VGS = 0 V TJ = 25°C
3000
Ciss
C, CAPACITANCE (pF)
2500
2000
1500
Crss Ciss
1000
Coss
500 Crss
0
10 5 0 5 10 15 20
VGS VDS

MMSF5N02HD
1000

12 24

QT VDD = 10 V
10 20 ID = 5 A
td(off)
VGS = 10 V
VGS TJ = 25°C tf
8 16 100 tr
t, TIME (ns)
6 ID = 5 A 12
Q1 Q2 TJ = 25°C td(on)
4 8 10
2 4
Q3 VDS
0 0 1
0 4 8 12 16 20 24 28 32 1 10 100

snappy.
5
VGS = 0 V
TJ = 25°C
4
0
0.5 0.55 0.6 0.65 0.7 0.75 0.8 0.85

MMSF5N02HD
trr
High Cell Density
trr
tb
ta
t, TIME
SAFE OPERATING AREA
perature.
100 675
VGS = 10 V ID = 15 A

TC = 25°C
1 ms
10
10 ms 475
375
1 dc
275
RDS(on) LIMIT
THERMAL LIMIT 175
0.1
PACKAGE LIMIT
75
0.01 – 25
0.1 1 10 100 25 50 75 100 125 150

MMSF5N02HD

THERMAL RESISTANCE
1 D = 0.5
0.2
0.1
0.1
0.02 Chip 0.0163 Ω 0.0652 Ω 0.1988 Ω 0.6411 Ω 0.9502 Ω
0.01
0.01
0.0307 F 0.1668 F 0.5541 F 1.9437 F 72.416 F
Ambient
SINGLE PULSE
0.001
1.0E–05 1.0E–04 1.0E–03 1.0E–02 1.0E–01 1.0E+00 1.0E+01 1.0E+02 1.0E+03
t, TIME (s)
di/dt
IS
trr
ta tb
TIME
tp 0.25 IS
IS

MOTOROLA


SO–8
G
N–C 1 8 Drain
Source 2 7 Drain
Source 3 6 Drain
DEVICE MARKING
S5N03
REV 4

MMSF5N03HD
OFF CHARACTERISTICS
(VGS = 0 Vdc, ID = 250 µAdc) 30 — —
(VDS = 30 Vdc, VGS = 0 Vdc) — — 1.0
(VDS = VGS, ID = 250 µAdc) 1.0 2.0 3.0
Static Drain–Source On–Resistance RDS(on) Ohms
(VGS = 10 Vdc, ID = 5.0 Adc) — 0.033 0.040
(VGS = 4.5 Vdc, ID = 2.5 Adc) — 0.04 0.050
Forward Transconductance (VDS = 3 Vdc, ID = 2.5 Adc) gFS 3.0 8.0 — Mhos
Vd VGS = 0 Vdc,
Vd
Coss — 354 490
f = 1.0 MHz)
VGS = 4.5
4 5 Vdc,
Vdc
VGS = 10 Vdc
Vdc,
S Fi
See Figure 8
((VDS = 24 Vdc, ID = 5.0 Adc, Q1 — 3.4 —
VGS = 10 Vdc) Q2 — 6.6 —
Q3 — 5.6 —

(IS = 5 Adc, VGS = 0 Vdc)
— 0.88 1.3
(IS = 5 Adc, VGS = 0 Vdc, TJ = 125°C)
— 0.77 —
S Figure
See Fi 15
((IS = 5.0 Adc, VGS = 0 Vdc, ta — 21 —
dIS/dt = 100 A/µs) tb — 12 —

MMSF5N03HD
10 10
VGS = 10 V TJ = 25°C VDS ≥ 10 V

8 8
4.5 V
6 6
3.8 V
4 4
3.1 V
TJ = 100°C
2 2 25°C
– 55°C
2.4 V
0 0
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 3.8


0.2 0.0425
ID = 2.5 A TJ = 25°C
0.16 0.04
VGS = 4.5 V
0.12 0.0375
0.08 0.035
10 V
0.04 0.0325
0 0.03
0 1 2 3 4 5 6 7 8 9 10 0 2 4 6 8 10

1.6 1000
ID = 5 A
1.4 TJ = 125°C
100
(NORMALIZED)
1.2
1
10 100°C
0.8
25°C
0.6 1
– 50 – 25 0 25 50 75 100 125 150 0 10 20 30


MMSF5N03HD
3500
VDS = 0 V VGS = 0 V TJ = 25°C
3000
Ciss
C, CAPACITANCE (pF)
2500
2000
1500 Ciss
Crss
1000
Coss
500
Crss
0
10 5 0 5 10 15 20 25 30
VGS VDS

MMSF5N03HD
12 25 1000

QT VDD = 15 V
10 ID = 5 A
20
VGS VGS = 4.5 V
TJ = 25°C
8 Q1 Q2
t, TIME (ns)
15
6 ID = 5 A 100 tr
TJ = 25°C 10
4
td(off)
tf
2 5
td(on)
Q3 VDS
0 0 10
0 2 4 6 8 10 12 14 16 1 10 100

snappy.
5
VGS = 0 V
TJ = 25°C
4
0
0.5 0.55 0.6 0.65 0.7 0.75 0.8 0.85 0.9

MMSF5N03HD
trr
High Cell Density
trr
tb
ta
t, TIME
SAFE OPERATING AREA
perature.
100 450
VGS = 10 V
ID = 15 A
SINGLE PULSE
TC = 25°C 100 µs
10 1 ms
10 ms 300
1
dc
RDS(on) LIMIT 150

THERMAL LIMIT
0.1
PACKAGE LIMIT
0.01 0
0.1 1 10 100 25 50 75 100 125 150

MMSF5N03HD
10
THERMAL RESISTANCE
1 D = 0.5
0.2
0.1
0.1
0.02 Chip 0.0163 Ω 0.0652 Ω 0.1988 Ω 0.6411 Ω 0.9502 Ω
0.01
0.01
0.0307 F 0.1668 F 0.5541 F 1.9437 F 72.416 F
Ambient
SINGLE PULSE
0.001
1.0E–05 1.0E–04 1.0E–03 1.0E–02 1.0E–01 1.0E+00 1.0E+01 1.0E+02 1.0E+03
t, TIME (s)
di/dt
IS
trr
ta tb
TIME
tp 0.25 IS
IS

MOTOROLA
Advance Information MMSF5N03Z

TMOS Single N-Channel with Motorola Preferred Device

POWER MOSFET
used for low voltage motor controls in mass storage products such as G SO–8
• Zener Protected Gates Provide Electrostatic Discharge Protection S
Source 1 8 Drain
Source 2 7 Drain
Top View
(VDD = 30 Vdc, VGS = 5.0 Vdc, Peak IL = 15 Apk, L = 4.0 mH, RG = 25 Ω) 450
(1) When mounted on 1 inch square FR–4 or G–10 board (VGS = 10 V, @ Steady State)
(2) When mounted on minimum recommended FR–4 or G–10 board (VGS = 10 V, @ Steady State)
S5N03Z
MMSF5N03ZR2 13″ 12 mm embossed tape 2500 units
REV 1

MMSF5N03Z
OFF CHARACTERISTICS
(VGS = 0 Vdc, ID = 250 µAdc) 30 — —
(VDS = 30 Vdc, VGS = 0 Vdc) — 0.03 2.0
Gate–Body Leakage Current (VGS = ± 15 Vdc, VDS = 0) IGSS — 1.3 5.0 µAdc
(VDS = VGS, ID = 250 µAdc) 1.0 2.0 3.0
(VGS = 10 Vdc, ID = 5.0 Adc) — 22 30
(VGS = 4.5 Vdc, ID = 2.5 Adc) — 30 40
Vd VGS = 0 Vdc,
Vd
Coss — 340 680
f = 1.0 MHz)
Rise Time ((VDS = 15 Vdc, ID = 5.0 Adc, tr — 90 180
Turn–Off Delay Time VGS = 10 Vdc, RG = 6 Ω) (1) td(off) — 470 940
Turn–Off Delay Time VGS = 4.5 Vdc, RG = 6 Ω) (1) td(off) — 430 860
((VDS = 24 Vdc, ID = 5.0 Adc, Q1 — 3.5 —

VGS = 10 Vdc) (1) Q2 — 9.5 —
Q3 — 6.5 —

(IS = 5.0 Adc, VGS = 0 Vdc) (1)
— 0.83 1.6
(IS = 5.0 Adc, VGS = 0 Vdc, TJ = 125°C)
— 0.67 —
(IS = 5
5.0
0 Ad
Adc, VGS = 0 Vdc,
Vd
ta — 22 —
dIS/dt = 100 A/µs) (1)
tb — 90 —
Cpk =
3 x SIGMA

MMSF5N03Z
10 10
TJ = 25°C VDS ≥ 10 V
3.5 V

8 VGS = 10 V 8
4.5 V
3.8 V
6 3.3 V 6
4 4
100°C
3.1 V
25°C
2 2
2.7 V TJ = –55°C
0 0
0 0.4 0.8 1.2 1.6 2 1.8 2.2 2.6 3 3.4 3.8


0.1 0.05
ID = 2.5 A TJ = 25°C
TJ = 25°C
0.08 0.04
VGS = 4.5
0.06 0.03
10 V
0.04 0.02
0.02 0.01
0 0
0 2 4 6 8 10 0 2 4 6 8 10

2.0 1000
ID = 2.5 A
1.5
100 TJ = 125°C
1.0
100°C
10
0.5
0 1
– 50 – 25 0 25 50 75 100 125 150 0 5 10 15 20 25 30


MMSF5N03Z
2500
TJ = 25°C
VGS = 0 V
2000
C, CAPACITANCE (pF)
1500 Ciss
1000
500 Coss
Crss
0
0 6 12 18 24 30

MMSF5N03Z

12 24 1000

VDD = 15 V
QT
ID = 5 A td(off)
10 20 VGS = 10 V
TJ = 25°C
8 16
tf
VDS VGS
t, TIME (ns)
6 12 100 tr
Q1 Q2
4 8
td(on)
ID = 5 A
2 TJ = 25°C 4
Q3
0 0 10
0 5 10 15 20 25 30 35 1 10 100

snappy.
5
VGS = 0 V
TJ = 25°C
4
0
0.5 0.6 0.7 0.8 0.9

MMSF5N03Z
trr
High Cell Density
trr
tb
ta
t, TIME
SAFE OPERATING AREA
perature.
100 500
VGS = 15 V
ID = 15 A
SINGLE PULSE
TC = 25°C 400
10
100 µs
1 ms 300
1 10 ms
200
0.1
RDS(on) LIMIT dc 100
THERMAL LIMIT
PACKAGE LIMIT
0.01 0
0.1 1 10 100 25 50 75 100 125 150

MMSF5N03Z
10
THERMAL RESISTANCE
1 D = 0.5
0.2
0.1
0.1
0.02 Chip 0.0163 Ω 0.0652 Ω 0.1988 Ω 0.6411 Ω 0.9502 Ω
0.01
0.01
0.0307 F 0.1668 F 0.5541 F 1.9437 F 72.416 F
Ambient
SINGLE PULSE
0.001
1.0E–05 1.0E–04 1.0E–03 1.0E–02 1.0E–01 1.0E+00 1.0E+01 1.0E+02 1.0E+03
t, TIME (s)
di/dt
IS
trr
ta tb
TIME
tp 0.25 IS
IS

MOTOROLA


SO–8
G
N–C 1 8 Drain
Source 2 7 Drain
Source 3 6 Drain
DEVICE MARKING
S7N03
REV 2

MMSF7N03HD
OFF CHARACTERISTICS
(VGS = 0 Vdc, ID = 250 µAdc) 30 — —
(VDS = 30 Vdc, VGS = 0 Vdc) — 0.02 1.0
(VDS = VGS, ID = 250 µAdc) 1.0 1.5 2.0
Static Drain–Source On–Resistance RDS(on) Ohms
(VGS = 10 Vdc, ID = 7.0 Adc) — 0.023 0.028
(VGS = 4.5 Vdc, ID = 3.5 Adc) — 0.029 0.040
Forward Transconductance (VDS = 3 Vdc, ID = 2.5 Adc) gFS 3.0 12 — Mhos
Vd VGS = 0 Vdc,
Vd
Coss — 371 490
f = 1.0 MHz)
VGS = 4.5
4 5 Vdc,
Vdc
Turn–On Delay Time td(on) — 9.0 —
VGS = 10 Vdc
Vdc,
Fall Time tf — 39
S Fi
See Figure 8
((VDS = 16 Vdc, ID = 5.0 Adc, Q1 — 3.0 —
VGS = 10 Vdc) Q2 — 7.5 —
Q3 — 6.0 —

— 0.82 1.0
(IS = 7.0 Adc, VGS = 0 Vdc, TJ = 125°C)
— 0.69 —
S Figure
See Fi 15
((IS = 7.0 Adc, VGS = 0 Vdc, ta — 24 —
dIS/dt = 100 A/µs) tb — 8.0 —

MMSF7N03HD
7 7
VGS = 10 V TJ = 25°C VDS ≥ 10 V
6 4.5 V 6 TJ = 25°C

3.9 V
2.9 V
5 3.7 V 5
3.5 V
4 4
3.3 V
3.1 V
3 3 TJ = 100°C
2.7 V
2 2
25°C
2.5 V
1 1
– 55°C
0 0
0 0.25 0.5 0.75 1 1.25 1.5 1.75 2 1.5 2 2.5 3 3.5 4


0.6 0.05
ID = 3.5 A TJ = 25°C
0.5 TJ = 25°C
0.04
0.4
VGS = 4.5 V
0.3 0.03
10 V
0.2
0.02
0.1
0 0.01
2 4 6 8 10 0 5 10 15

2 10000
VGS = 0 V
VGS = 10 V TJ = 125°C
ID = 3.5 A
1000
1.5
(NORMALIZED)
100
1
100°C
10
0.5 25°C
1
0 0.1
– 50 – 25 0 25 50 75 100 125 150 5 10 15 20 25 30


MMSF7N03HD
4000
VDS = 0 V VGS = 0 V TJ = 25°C
3500
Ciss
3000
C, CAPACITANCE (pF)
2500
2000 Crss
1500
Ciss
1000
Coss
500 Crss
0
10 5 0 5 10 15 20 25 30
VGS VDS

MMSF7N03HD
1000

12 24

QT VDD = 10 V
10 20 ID = 5 A
td(off)
VGS = 10 V
VGS TJ = 25°C tf
8 16 100 tr
t, TIME (ns)
6 ID = 5 A 12
Q1 Q2 TJ = 25°C td(on)
4 8 10
2 4
Q3 VDS
0 0 1
0 4 8 12 16 20 24 28 32 1 10 100

snappy.
8
VGS = 0 V
7 TJ = 25°C
0
0.5 0.6 0.7 0.8 0.9 1

MMSF7N03HD
trr
High Cell Density
trr
tb
ta
t, TIME
SAFE OPERATING AREA
perature.
100 480
ID = 9 A
VGS = 10 V 440
10µs I pk = 9 A
SINGLE PULSE 400
TC = 25°C 100 µs L = 4 mH
10 1 ms 360
10 ms 320
280
1 dc 240
200
RDS(on) LIMIT 160
THERMAL LIMIT 120
0.1
PACKAGE LIMIT
80
Mounted on 2” sq. FR4 board (1” sq. 2 oz. Cu 0.06” 40
0.01 0
0.1 1 10 100 25 50 75 100 125 150

MMSF7N03HD
10
THERMAL RESISTANCE
1 D = 0.5
0.2
0.1
0.1
0.02 Chip 0.0163 Ω 0.0652 Ω 0.1988 Ω 0.6411 Ω 0.9502 Ω
0.01
0.01
0.0307 F 0.1668 F 0.5541 F 1.9437 F 72.416 F
Ambient
SINGLE PULSE
0.001
1.0E–05 1.0E–04 1.0E–03 1.0E–02 1.0E–01 1.0E+00 1.0E+01 1.0E+02 1.0E+03
t, TIME (s)
di/dt
IS
trr
ta tb
TIME
tp 0.25 IS
IS

MOTOROLA
Power Products Division

Advance Information MPIC2111
HALF-BRIDGE DRIVER
The MPIC2111 is a high voltage, high speed, power MOSFET and IGBT driver
with dependent high and low side referenced output channels designed for half–
bridge applications. Proprietary HVIC and latch immune CMOS technologies en-
able ruggedized monolithic construction. Logic input is compatible with standard HALF–BRIDGE DRIVER
CMOS outputs. The output drivers feature a high pulse current buffer stage de-
signed for minimum driver cross–conduction. Internal deadtime is provided to
avoid shoot–through in the output half–bridge. The floating channel can be used to
drive an N–channel power MOSFET or IGBT in the high side configuration which
operates from 10 to 600 volts.
• Floating Channel Designed for Bootstrap Operation

• Fully Operational to +600 V
8
• Tolerant to Negative Transient Voltage

1
• dV/dt Immune P SUFFIX

• Gate Drive Supply Range from 10 to 20 V PLASTIC PACKAGE
CASE 626–05
• Undervoltage Lockout for Both Channels
• CMOS Schmitt–triggered Inputs with Pull–down
• Matched Propagation Delay for Both Channels
• Internally Set Deadtime
• High Side Output in Phase with Input 8
PRODUCT SUMMARY D SUFFIX

VOFFSET 600 V MAX PLASTIC PACKAGE
CASE 751–05
IO+/– 200 mA/420 mA (SO–8)
VOUT 10 – 20 V
ton/off (typical) 130 & 90 ns
Device Package
Deadtime (typical) 700 ns MPIC2111D SOIC
MPIC2111P PDIP
PIN CONNECTIONS
(TOP VIEW)
VCC 1 8 VB VCC 1 8 VB
IN 2 7 HO IN 2 7 HO
COM 3 6 VS COM 3 6 VS
LO 4 5 LO 4 5
8 LEADS DIP 8 LEAD SOIC

MPIC2111P MPIC2111D
This document contains information on a new product. Specifications and information herein are subject
to change without notice.
REV 1

MPIC2111
SIMPLIFIED BLOCK DIAGRAM
VB
UV
DEAD HV DETECT
R Q
TIME LEVEL
PULSE R HO
SHIFT
FILTER S
PULSE VS
GEN
IN UV
DETECT VCC
LO
DEAD
TIME
COM
ABSOLUTE MAXIMUM RATINGS

Absolute Maximum Ratings indicate sustained limits beyond which damage to the device may occur. All voltage parameters are absolute
voltages referenced to COM. The Thermal Resistance and Power Dissipation ratings are measured under board mounted and still air
conditions.
Rating Symbol Min Max Unit

High Side Floating Supply Absolute Voltage VB –0.3 625 VDC
High Side Floating Supply Offset Voltage VS VB–25 VB+0.3
High Side Floating Output Voltage VHO VS–0.3
03 VB+0
+0.33
Low Side Fixed Supply
Su ly Voltage VCC –0.3
0.3 25
Low Side Output Voltage VLO –0.3 VCC+0.3
L i IInput V
Logic Voltage
l VIN –0.3
03 VCC+0.3
03
Allowable Offset Supply Voltage Transient dVS/dt – 50 V/ns

*Package Power Dissipation @ TC ≤ +25°C (8 Lead DIP) PD – 1.0 Watt
(8 Lead SOIC) – – 0.625
Thermal Resistance, Junction to Ambient (8 Lead DIP) RθJA – 125 °C/W

(8 Lead SOIC) – 200
Operating and Storage Temperature Tj, Tstg –55 150 °C

Lead Temperature for Soldering Purposes, 10 seconds TL – 260 °C
RECOMMENDED OPERATING CONDITIONS

The Input/Output logic timing Diagram is shown in Figure 1. For proper operation the device should be used within the recommended condi-
tions. The VS offset rating is tested with all supplies biased at 15 V differential.
High Side Floating Supply Absolute Voltage VB VS+10 VS+20 V
High Side Floating Supply Offset Voltage VS Note 1 600
High Side Floating Output Voltage VHO VS VB
Low Side Fixed Supply Voltage VCC 10 20
Low Side Output Voltage VLO 0 VCC mA
Logic Input Voltage VIN 0 VCC
Ambient Temperature TA –40 125 °C
Note 1: Logic operational for VS of –5 to +600 V. Logic state held for VS of –5 V to –VBS.

MPIC2111
ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise specified)
STATIC ELECTRICAL CHARACTERISTICS
VBIAS (VCC, VBS) = 15 V unless otherwise specified. The VIN, VTH and IIN parameters are referenced to COM. The VO and IO parameters
are referenced to COM and are applicable to the respective output leads: HO or LO.
Logic “1” Input Voltage for HO & Logic “0” Input Voltage for LO @ VCC = 10 V VIH 6.4 – – VDC
Logic “1” Input Voltage for HO & Logic “0” Input Voltage for LO @ VCC = 15 V VIH 9.5 – –
Logic “1” Input Voltage for HO & Logic “0” Input Voltage for LO @ VCC = 20 V VIH 12.6 – –
Logic “0” Input Voltage for HO & Logic “1” Input Voltage for LO @ VCC = 10 V VIL – – 3.8
High Level Output Voltage, VBIAS–VO @ IO = 0 A VOH – – 100 mV
Low Level Output Voltage, VO @ IO = 0 A VOL – – 100
Offset Supply Leakage Current @ VB = VS = 600 V ILK – – 50 µA
Quiescent VBS Supply Current @ VIN = 0 V or VCC IQBS – 50 –
Quiescent VCC Supply Current @ VIN = 0 V or VCC IQCC – 70 –
Logic “1” Input Bias Current @ VIN = 15 V IIN+ – 20 40
Logic “0” Input Bias Current @ VIN = 0 V IIN– – – 1.0
VBS Supply Undervoltage Positive Going Threshold VBSUV+ – 8.5 – V
VBS Supply Undervoltage Negative Going Threshold VBSUV– – 8.2 –
VCC Supply Undervoltage Positive Going Threshold VCCUV+ – 8.6 –
VCC Supply Undervoltage Negative Going Threshold VCCUV– – 8.2 –
Output High Short Circuit Pulsed Current @ VOUT = 0 V, PW ≤ 10 µs IO+ 200 250 – mA
Output Low Short Circuit Pulsed Current @ VOUT = 15 V, PW ≤ 10 µs IO– 420 500 –
DYNAMIC ELECTRICAL CHARACTERISTICS
VBIAS (VCC, VBS) = 15 V unless otherwise specified
Turn–On Propagation Delay @ VS = 0 V ton – 850 – ns
Turn–Off Propagation Delay @ VS = 600 V toff – 150 –
Turn–On Rise Time @ CL = 1000 pF tr – 80 –
Turn–Off Fall Time @ CL = 1000 pF tf – 40 –
Deadtime, LS Turn–Off to HS Turn–On & HS Turn–Off to LS Turn–On DT – 700 –
Delay Matching, HS & LS Turn–On/Off MT – 30 –
TYPICAL CONNECTION
10 TO 600 V
VCC
VCC VB
IN IN HO
COM VS TO
LOAD
LO

MPIC2111
LEAD DEFINITIONS
Symbol Lead Description
IN Logic Input for High Side and Low Side Gate Driver Outputs (HO & LO), In Phase with HO
VB High Side Floating Supply
HO High Side Gate Drive Output
VS High Side Floating Supply Return
VCC Low Side Supply
LO Low Side Gate Drive Output
COM Logic and Low Side Return
IN (LO)
IN
50% 50%
IN (HO)
HO tr tf
ton toff
90% 90%
LO LO
HO 10% 10%
Figure 1. Input / Output Timing Diagram Figure 2. Switching Time Waveform

Definitions
50% 50%
IN
90%
HO 10%
DT
LO 90%
10%
Figure 3. Deadtime Waveform Definitions

MOTOROLA

MPIC2112
HIGH AND LOW SIDE DRIVER
The MPIC2112 is a high voltage, high speed, power MOSFET and IGBT driver HIGH AND LOW
with independent high and low side referenced output channels. Proprietary HVIC SIDE DRIVER
and latch immune CMOS technologies enable ruggedized monolithic construction.
Logic inputs are compatible with standard CMOS or LSTTL outputs. The output
drivers feature a high pulse current buffer stage designed for minimum driver
cross–conduction. Propagation delays are matched to simplify use in high frequen-
cy applications. The floating channel can be used to drive an N–channel power
MOSFET or IGBT in the high side configuration which operates from 10 to 600
14
volts.
1
• Floating Channel Designed for Bootstrap Operation P SUFFIX
• Fully Operational to +600 V PLASTIC PACKAGE
CASE 646–06
• dV/dt Immune
• Gate Drive Supply Range from 10 to 20 V 16
• Undervoltage Lockout for Both Channels 1

• Separate Logic Supply DW SUFFIX
• Operating Supply Range from 5 to 20 V PLASTIC PACKAGE
CASE 751G–02
• Logic and Power Ground Operating Offset Range from –5 to +5 V SOIC – WIDE
• CMOS Schmitt–triggered Inputs with Pull–down
• Cycle by Cycle Edge–triggered Shutdown Logic ORDERING INFORMATION
• Matched Propagation Delay for Both Channels Device Package
• Outputs in Phase with Inputs MPIC2112DW SOIC WIDE
MPIC2112P PDIP
PRODUCT SUMMARY
VOFFSET 600 V MAX
IO+/– 200 mA/400 mA
VOUT 10 – 20 V
Delay Matching 30 ns
PIN CONNECTIONS
(TOP VIEW)
9 HO 8
8 HO 7
10 VB 7
9 VDD VB 6
11 VDD VS 6
10 HIN VS 5
12 HIN 5
11 SD 4
13 SD 4
12 LIN VCC 3
14 LIN VCC 3
13 VSS COM 2
15 VSS COM 2
14 LO 1
16 LO 1
14 LEADS PDIP MPIC2112P
16 LEADS SOIC (WIDE BODY)
MPIC2112DW

MPIC2112
VB
UV
VDD HV DETECT
R Q
R Q LEVEL
PULSE R HO
S SHIFT
VDD/VCC FILTER S
HIN LEVEL
SHIFT PULSE VS
GEN
SD VCC
UV
VDD/VCC DETECT
LIN LEVEL LO
S SHIFT
R Q DELAY
VSS COM

conditions.

High Side Floating Absolute Voltage VB –0.3
0.3 625 VDC
High
g Side Floating g Supplyy Offset Voltage
g VS VB–25 VB+0.3
High
g Side Floating g Output Voltage
g VHO VS–0.3 VB+0.3
Low Side Fixed Supplyy Voltageg VCC –0.3 25
Logic Supply Voltage VDD –0.3 VSS+25
L i S
Logic l Off
Supply Offset V l
Voltage VSS VCC–25 VCC+0.3
L i IInputt V
Logic Voltage
lt (HIN
(HIN, LIN & SD) VIN VSS–0.3
03 VDD+0.3
03
*Package Power Dissipation @ TA ≤ +25°C (14 Lead DIP) PD – 1.6 Watt
(16 SOIC–WIDE) – – 1.25

(16 SOIC–WIDE) – 100


tions. The VS and VSS offset ratings are tested with all supplies biased at 15 V differential.
Low Side Output Voltage VLO 0 VCC
Logic Supply Voltage VDD VSS+5 VSS+20
Logic Supply Offset Voltage VSS –5 5
Logic Input Voltage (HIN, LIN & SD) VIN VSS VDD

MPIC2112
ELECTRICAL CHARACTERISTICS (TC = 25°C unless otherwise specified)
STATIC ELECTRICAL CHARACTERISTICS – SUPPLY CHARACTERISTICS
VBIAS (VCC, VBS, VDD) = 15 V and VSS = COM unless otherwise specified. The VIN, VTH and IIN parameters are referenced to VSS and are
applicable to all three logic input leads: HIN, LIN and SD. The VO and IO parameters are referenced to COM or VSS and are applicable to
the respective output leads: HO or LO.
Logic “1” Input Voltage VIH 9.5 – – V
Logic “0” Input Voltage VIL – – 6.0
High Level Output Voltage, VBIAS–VO @ VIN = VIH, IO = 0 A VOH – – 100 mV
Low Level Output Voltage, VO @ VIN = VIL, IO = 0 A VOL – – 100
Quiescent VBS Supply Current @ VIN = 0 V or VDD IQBS – 25 60
Quiescent VCC Supply Current @ VIN = 0 V or VDD IQCC – 80 180
Quiescent VDD Supply Current @ VIN = 0 V or VDD IQDD – 2.0 5.0
VBS Supply Undervoltage Positive Going Threshold VBSUV+ 7.4 – 9.6 V
VBS Supply Undervoltage Negative Going Threshold VBSUV– 7.0 – 9.2
VCC Supply Undervoltage Positive Going Threshold VCCUV+ 7.6 – 9.6
VCC Supply Undervoltage Negative Going Threshold VCCUV– 7.2 – 9.2
Output High Short Circuit Pulsed Current mA
@ VOUT = 0 V, VIN = 15 V, PW ≤10 µs IO+ 200 250 –
Output Low Short Circuit Pulsed Current

@ VOUT = 15 V, VIN = 0 V, PW ≤ 10 µs IO– 420 500 –

VBIAS (VCC, VBS, VDD) = 15 V and VSS = COM unless otherwise specified. TA = 25°C.
Turn–On Propagation Delay @ VS = 0 V ton – 125 180 ns
Turn–Off Propagation Delay @ VS = 600 V toff – 105 160
Shutdown Propagation Delay @ VS = 600 V tsd – 105 160
Turn–On Rise Time @ CL = 1000 pF tr – 80 130
Turn–Off Fall Time @ CL = 1000 pF tf – 40 65
Delay Matching, HS & LS Turn–On/Off MT – – 30
TYPICAL CONNECTION
10 TO 600 V
HO
VDD VDD VB
HIN HIN VS
TO
SD SD LOAD
LIN LIN VCC
VSS VSS COM
VCC LO

MPIC2112
LEAD DEFINITIONS
VDD Logic Supply
HIN Logic Input for High Side Gate Driver Output (HO), In Phase
SD Logic Input for Shutdown
LIN Logic Input for Low Side Gate Driver Output (LO), In Phase
VSS Logic Ground
VCC Low Side Supply
COM Low Side Return
HIN
LIN HIN 50% 50%
LIN
tr tf
ton toff
SD 90% 90%
HO
LO 10% 10%
HO
LO

Definitions
HIN 50% 50%

50% LIN
SD
LO HO
tsd
10%
HO 90%
MT MT
LO
90%
LO HO
Figure 3. Deadtime Waveform Definitions Figure 4. Delay Matching Waveform

Definitions

MOTOROLA
Power Products Division MPIC2113

Advance Information
HIGH AND LOW SIDE DRIVER HIGH AND LOW
SIDE DRIVER
with independent high and low side referenced output channels. Proprietary HVIC
and latch immune CMOS technologies enable ruggedized monolithic construction.
Logic inputs are compatible with standard CMOS or LSTTL outputs. The output
drivers feature a high pulse current buffer stage designed for minimum driver
cross–conduction. Propagation delays are matched to simplify use in high frequen- 14
cy applications. The floating channel can be used to drive an N–channel power

1
MOSFET or IGBT in the high side configuration which operates from 10 to 600
volts. P SUFFIX
PLASTIC PACKAGE
• Floating Channel Designed for Bootstrap Operation CASE 646–06

• Tolerant to Negative Transient Voltage 16
• dV/dt Immune
•
1
Gate Drive Supply Range from 10 to 20 V
• Undervoltage Lockout for Both Channels
DW SUFFIX
PLASTIC PACKAGE
• Separate Logic Supply CASE 751G–02
• Operating Supply Range from 5 to 20 V
SOIC – WIDE
• Logic and Power Ground Operating Offset Range from –5 to +5 V ORDERING INFORMATION
• CMOS Schmitt–triggered Inputs with Pull–down Device Package
• Cycle by Cycle Edge–triggered Shutdown Logic MPIC2113DW SOIC WIDE
• Matched Propagation Delay for Both Channels
MPIC2113P PDIP
• Outputs In Phase with Inputs
PRODUCT SUMMARY
VOFFSET 600 V MAX
IO+/– 2 A/2 A
VOUT 10 – 20 V
Delay Matching 10 ns
PIN CONNECTIONS
(TOP VIEW)
9 HO 8
8 HO 7
10 VB 7
9 VDD VB 6
11 VDD VS 6
10 HIN VS 5
12 HIN 5
11 SD 4
13 SD 4
12 LIN VCC 3
14 LIN VCC 3
13 VSS COM 2
15 VSS COM 2
14 LO 1
16 LO 1
14 LEADS PDIP MPIC2113P
16 LEADS SOIC (WIDE BODY)
MPIC2113DW

MPIC2113
VB
UV
VDD HV DETECT
R Q
R Q LEVEL
PULSE R HO
S SHIFT
VDD/VCC FILTER S
HIN LEVEL
SHIFT PULSE VS
GEN
SD VCC
UV
VDD/VCC DETECT
LIN LEVEL LO
S SHIFT
R Q DELAY
VSS COM

conditions.

High Side Floating Absolute Voltage VB –0.3
0.3 625 VDC
High
g Side Floating g Supplyy Offset Voltage
g VS VB–25 VB+0.3
g Side Floating
High g Output Voltage
Low Side Fixed Supplyy Voltageg VCC –0.3 25
Logic Supply Voltage VDD –0.3 VSS+25
L i S
Logic Supply
l Off
Offset V
Voltage
l VSS VCC–25 VCC+0.3
L i IInputt V
Logic lt
Voltage (HIN
(HIN, LIN & SD) VIN 03
VSS–0.3 03
VDD+0.3
(16 SOIC–WIDE) – – 1.25

(16 SOIC–WIDE) – 100


tions. The VS and VSS offset ratings are tested with all supplies biased at 15 V differential.
Logic Supply Voltage VDD VSS+5 VSS+20
Logic Supply Offset Voltage VSS –5 5
Logic Input Voltage (HIN, LIN & SD) VIN VSS VDD

MPIC2113
STATIC ELECTRICAL CHARACTERISTICS – SUPPLY CHARACTERISTICS
VBIAS (VCC, VBS, VDD) = 15 V and VSS = COM unless otherwise specified. The VIN, VTH and IIN parameters are referenced to VSS and are
applicable to all three logic input leads: HIN, LIN and SD. The VO and IO parameters are referenced to COM or VSS and are applicable to
the respective output leads: HO or LO.
Logic “1” Input Voltage VIH 9.5 – – V
Logic “0” Input Voltage VIL – – 6.0
High Level Output Voltage, VBIAS–VO @ VIN = VIH, IO = 0 A VOH – – 1.2
Low Level Output Voltage, VO @ VIN = VIL, IO = 0 A VOL – – 0.1
Quiescent VBS Supply Current @ VIN = 0 V or VDD IQBS – 125 230
Quiescent VCC Supply Current @ VIN = 0 V or VDD IQCC – 180 340
Quiescent VDD Supply Current @ VIN = 0 V or VDD IQDD – 15 30
VBS Supply Undervoltage Negative Going Threshold VBSUV– 7.0 – 9.4
VCC Supply Undervoltage Positive Going Threshold VCCUV+ 7.4 – 9.6
VCC Supply Undervoltage Negative Going Threshold VCCUV– 7.0 – 9.4
Output High Short Circuit Pulsed Current IO+ 2.0 2.5 – A
@ VOUT = 0 V, VIN = 15 V, PW ≤10 µs
Output Low Short Circuit Pulsed Current IO– 2.0 2.5 –

@ VOUT = 15 V, VIN = 0 V, PW ≤ 10 µs

VBIAS (VCC, VBS, VDD) = 15 V and VSS = COM unless otherwise specified. TA = 25°C.
Turn–On Propagation Delay @ VS = 0 V ton – 120 150 ns
Turn–Off Propagation Delay @ VS = 600 V toff – 94 125
Shutdown Propagation Delay @ VS = 600 V tsd – 110 140
Turn–On Rise Time @ CL = 1000 pF tr – 25 35
Turn–Off Fall Time @ CL = 1000 pF tf – 17 25
Delay Matching, HS & LS Turn–On/Off MT – – 10
TYPICAL CONNECTION
10 TO 600 V
HO
VDD VDD VB
HIN HIN VS
TO
SD SD LOAD
LIN LIN VCC
VSS VSS COM
VCC LO

MPIC2113
LEAD DEFINITIONS
VDD Logic Supply
HIN Logic Input for High Side Gate Driver Output (HO), In Phase
SD Logic Input for Shutdown
LIN Logic Input for Low Side Gate Driver Output (LO), In Phase
VSS Logic Ground
VCC Low Side Supply
COM Low Side Return
HIN
LIN HIN 50% 50%
LIN
tr tf
ton toff
SD 90% 90%
HO
LO 10% 10%
HO
LO

Definitions
HIN 50% 50%

50% LIN
SD
LO HO
tsd
10%
HO 90%
MT MT
LO
90%
LO HO
Figure 3. Shutdown Waveform Definitions Figure 4. Delay Matching Waveform

Definitions

MOTOROLA

SINGLE CHANNEL DRIVER
The MPIC2117 is a high voltage, high speed, power MOSFET and IGBT driver.
Proprietary HVIC and latch immune CMOS technologies enable ruggedized mono-
lithic construction. The logic input is compatible with standard CMOS outputs. The
output drivers feature a high pulse current buffer stage designed for minimum driv- SINGLE CHANNEL DRIVER
er cross–conduction. The floating channel can be used to drive an N–channel pow-
er MOSFET or IGBT in the high side or low side configuration which operates from
10 to 600 volts.

• Tolerant to Negative Transient Voltage 8
• dV/dt Immune 1
• Gate Drive Supply Range from 10 to 20 V
• Undervoltage Lockout P SUFFIX
PLASTIC PACKAGE
• CMOS Schmitt–triggered Input with Pull–down CASE 626–05
• Output In Phase with Input
PRODUCT SUMMARY
VOFFSET 600 V MAX 8
IO+/– 200 mA/420 mA 1

VOUT 10 – 20 V
ton/off (typical) D SUFFIX
125 & 105 ns PLASTIC PACKAGE
CASE 751–05
(SO–8)
Device Package
MPIC2117D SOIC
MPIC2117P PDIP
PIN CONNECTIONS
(TOP VIEW)
VCC 1 8 VB VCC 1 8 VB
IN 2 7 HO IN 2 7 HO
COM 3 6 VS COM 3 6 VS
4 5 4 5
8 LEADS DIP 8 LEAD SOIC

MPIC2117P MPIC2117D
REV 1

MPIC2117
VCC
VB
UV
HV DETECT
R Q
LEVEL
PULSE R HO
SHIFT
FILTER S
IN VS
PULSE
GEN
UV
DETECT
COM

conditions.

High
g Side Floating g Supply
y Absolute Voltage
g VB –0.3 625 VDC
High Side Floating Supply Offset Voltage VS VB–25 VB+0.3
High Side Floating Output Voltage VHO VS–0.3 VB+0.3
Logic
L i S Supply Voltage
l V lt VCC –0.3
03 25
Logic Input Voltage VIN 03
–0.3 VCC+0 3
+0.3

(8 Lead SOIC) – – 0.625



Logic Supply Voltage VCC 10 20
Logic Input Voltage VIN 0 VCC

MPIC2117
VBIAS (VCC, VBS) = 15 V unless otherwise specified. The VIN, VTH and IIN parameters are referenced to COM. The VO and IO parameters
are referenced to COM and are applicable to the respective output leads: HO or LO.
Logic “1” Input Voltage @ VCC = 10 V VIH 6.4 – – VDC
Logic “1” Input Voltage @ VCC = 15 V VIH 9.5 – –
Logic “1” Input Voltage @ VCC = 20 V VIH 12.6 – –
Logic “0” Input Voltage @ VCC = 10 V VIL – – 3.8
High Level Output Voltage, VBS–VO @ VIN = VIH, IO = 0 A VOH – – 100 mV
Low Level Output Voltage, VO @ VIN = VIL, IO = 0 A VOL – – 100
Quiescent VBS Supply Current @ VIN = 0 V or VCC IQBS – 50 –
Quiescent VCC Supply Current @ VIN = 0 V or VCC IQCC – 70 –
VBS Supply Undervoltage Negative Going Threshold VBSUV– – 8.2 –
VCC Supply Undervoltage Positive Going Threshold VCCUV+ – 8.6 –
Output High Short Circuit Pulsed Current IO+ 200 250 – mA
@ VOUT = 0 V, VIN = 15 V, PW ≤ 10 µs
Output Low Short Circuit Pulsed Current IO– 420 500 –
@ VOUT = 15 V, VIN = 0 V, PW ≤ 10 µs
VBIAS (VCC, VBS) = 15 V unless otherwise specified
Turn–On Propagation Delay @ VS = 0 V ton – 125 – ns
Turn–Off Propagation Delay @ VS = 600 V toff – 105 –
Turn–On Rise Time @ CL = 1000 pF tr – 80 –
Turn–Off Fall Time @ CL = 1000 pF tf – 40 –
TYPICAL CONNECTION
VCC VCC VB
IN IN HO
COM VS

MPIC2117
LEAD DEFINITIONS
VCC Logic Supply
IN Logic Input for High Side Gate Driver Outputs (HO), In Phase with HO
COM Logic Ground
IN 50% 50%
IN
tr tf
ton toff
90% 90%
HO HO 10% 10%

Definitions

MOTOROLA

3-PHASE BRIDGE DRIVER
with three independent high side and low side referenced output channels for
3–Phase applications. Proprietary HVIC technology enables ruggedized monolith-
ic construction. Logic inputs are compatible with 5 V CMOS or LSTTL outputs. A 3–PHASE
ground referenced operational amplifier provides an analog feedback of bridge BRIDGE DRIVER
current via an external current sense resistor. A current trip function which termi-
nates all six outputs is also derived from this resistor. An open drain FAULT signal
is provided to indicate that an over–current or undervoltage shutdown has oc-
curred. The output drivers feature a high pulse current buffer stage designed for
minimum driver cross–conduction. Propagation delays are matched to simplify use
in high frequency applications.
The floating channels can be used to drive N–channel power MOSFET or
28
IGBT’s in the high side configuration which operate from 10 to 600 volts.
1

•
P SUFFIX
Fully Operational to +600 V PLASTIC PACKAGE
• Tolerant to Negative Transient Voltage CASE 710–02
• dV/dt Immune
• Gate Drive Supply Range from 10 to 20 V
• Undervoltage Lockout for All Channels
• Over–current Shut Down Turns Off All Six Drivers
PIN CONNECTIONS
• Independent Half–bridge Drivers

1 VCC VB1 28
• Matched Propagation Delay for All Channels
• Outputs Out of Phase with Inputs
2 HIN1 HO1 27
3 HIN2 VS1 26
PRODUCT SUMMARY 4 HIN3 25

VOFFSET 600 V MAX
5 LIN1 VB2 24
IO+/– 200 mA/420 mA
6 LIN2 HO2 23
VOUT 10 – 20 V
7 LIN3 VS2 22
8 FAULT 21
Deadtime (typical) 2.5 ms
9 ITRIP VB3 20
10 CAO HO3 19
11 CA– VS3 18
12 VSS 17
13 VSO LO1 16
14 LO3 LO2 15
(TOP VIEW)
Device Package
This document contains information on a new product. Specifications and information herein are subject MPIC2130P PDIP
REV 1

MPIC2130
VB1
H1 PULSE SET LATCH
HIN1 INPUT
SIGNAL GENERATOR
L1 DRIVER HO1
HIN2 GENERATOR LEVEL UV
SHIFTER RESET DETECTOR
VS1
HIN3
LIN1 VB2
H2 PULSE SET LATCH
INPUT
LIN2 SIGNAL GENERATOR
L2 DRIVER HO2
GENERATOR LEVEL UV
LIN3 SHIFTER RESET DETECTOR
VS2
FAULT VB3
H3 PULSE SET LATCH
FAULT INPUT
CLEAR LOGIC SIGNAL GENERATOR
L3 DRIVER HO3
LOGIC C S GENERATOR LEVEL UV
VS3
VCC
DRIVER LO1
ITRIP UNDER–
VOLTAGE
0.5 V CURRENT DETECTOR
CAO COMPARATOR
CURRENT DRIVER LO2
AMP
– +
CA–
DRIVER LO3
VSS
VSO

voltages referenced to VSS. The Thermal Resistance and Power Dissipation ratings are measured under board mounted and still air condi-
tions.

High Side Floating Absolute Voltage VB1,2,3 –0.3 625 VDC
High Side Floating Supply
Su ly Offset Voltage VS1,2,3
S1 2 3 VB1,2,3
B1 2 3–25 VB1,2,3
B1 2 3+0.3
+0 3
High Side Floating Output Voltage VHO1,2,3 VS1,2,3–0.3 VB1,2,3+0.3
Fi d Supply
Fixed S l V
Voltage
lt VCC –0.3
03 25
Low Side Driver Return VSO VCC–0.3 VCC+0.3
Low Side Output Voltage VLO1,2,3 VSO–0.3 VCC+0.3
Logic Input
In ut Voltage (HIN
(HIN–,, LIN–,
LIN , & ITRIP) VIN –0.3
0.3 VCC+0.3
Fault Output Voltage FAULT– –0.3 VCC+0.3
Amplifier
Am lifier Output
Out ut Voltage CAO –0 3
–0.3 VCC+0.3
+0 3
Amplifier Inverting Input Voltage CA– –0.3 VCC+0.3
*Package Power Dissipation @ TA ≤ +25°C PD – 1.5 Watt
Thermal Resistance, Junction to Ambient RθJA – 83 °C/W

MPIC2130
High Side Floating Supply Absolute Voltage VB1,2,3 VS1,2,3+10 VS1,2,3+20 V

High Side Floating Supply Offset Voltage VS1,2,3 Note 1 VSO+600 V
High Side Floating Output Voltage VHO1,2,3 VS1,2,3 VB1,2,3 V
Fixed Supply Voltage VCC 10 20 V
Low Side Driver Return VSO –5 5 V
Low Side Output Voltage VLO1,2,3 VSO VCC V
Logic Input Voltage (HIN–, LIN–, & ITRIP) VIN VSS 5 V
Fault Output Voltage FAULT– VSS VCC V
Amplifier Output Voltage CAO VSS 5 V
Amplifier Inverting Input Voltage CA– VSS 5 V
Note 1: Logic operational for VS of –5 V to +600 V. Logic state held for VS of VSO–5 V to VSO–VBS.
VBIAS (VCC, VBS1,2,3) = 15 V and VSO = VSS unless otherwise specified. The VIN, VTH and IIN parameters are referenced to VSS and are
applicable to all six channels (HS1,2,3 & LS1,2,3). The VO and IO parameters are referenced to VSO1,2,3 and are applicable to the respec-
tive output leads: HO1,2,3 or LO1,2,3.
Logic “0” Input Voltage (OUT = LO) VIH 2.2 – – V
Logic “1” Input Voltage (OUT = HI) VIL – – 0.8 V
ITRIP Input Positive Going Threshold VIT,TH+ 400 – 580 mV
High Level Output Voltage, VBIAS–VO @ VIN = 0 V, IO = 0 A VOH – – 100 mV
Low Level Output Voltage, VO @ VIN = 5 V, IO = 0 A VOL – – 100 mV
Offset Supply Leakage Current @ VB1,2,3 = VS1,2,3 = 600 V ILK – – 50 µA
Quiescent VBS Supply Current @ VIN = 0 V or 5 V IQBS – 15 30 µA
Quiescent VCC Supply Current @ VIN = 0 V or 5 V IQCC – 3.0 4.0 mA
Logic “1” Input Bias Current (OUT = HI) @ VIN = 0 V IIN+ – 400 500 µA
Logic “0” Input Bias Current (OUT = LO) @ VIN = 5 V IIN– – 200 320 µA
“High” ITRIP Bias Current @ ITRIP = 5 V ITRIP+ – 75 150 µA
“Low” ITRIP Bias Current @ ITRIP = 0 V ITRIP– – – 100 nA
VBS Supply Undervoltage Negative Going Threshold VBSUV– 7.6 – 8.8 V
VCC Supply Undervoltage Positive Going Threshold VCCUV+ 8.3 – 9.7 V
VCC Supply Undervoltage Negative Going Threshold VCCUV– 8.0 – 9.4 V
FAULT – Low On Resistance Ron,FLT – 55 75 Ω
Output High Short Circuit Pulsed Current @ Vout = 0 V, Vin = 0 V, PW ≤ 10 µs IO+ 200 250 – mA
Output Low Short Circuit Pulsed Current @ Vout = 15 V, Vin = 5 V, PW ≤ 10 µs IO– 420 500 – mA
Amplifier Input Offset Voltage @ VSO = CA– = 0.2 VOS – – 30 mV
CA– Input Bias Current @ CA– = 2.5 V ICA– – – 4.0 nA
Amplifier Common Mode Rejection Ratio @ VSO = CA– = 0.1 V & 5 V CMRR 60 80 – dB

MPIC2130
ELECTRICAL CHARACTERISTICS (continued) (TA = 25°C unless otherwise specified)
VBIAS (VCC, VBS1,2,3) = 15 V and VSO = VSS unless otherwise specified. The VIN, VTH and IIN parameters are referenced to VSS and are
applicable to all six channels (HS1,2,3 & LS1,2,3). The VO and IO parameters are referenced to VSO1,2,3 and are applicable to the respec-
tive output leads: HO1,2,3 or LO1,2,3.
Amplifier Power Supply Rejection Ratio
@ VSO = CA–=0.2 V, VCC = 10 & 20 V PSRR 55 75 – dB
Amplifier High Level Output Voltage @ CA– = 0 V, VSO = 1 V VOH,Amp 5.0 – 5.4 V
Amplifier Low Level Output Voltage @ CA– = 1 V, VSO = 0 V VOL,Amp – – 20 mV
Amplifier Output Source Current @ CA– = 0 V, VSO = 1 V, CAO = 4 V ISRC,Amp 2.3 4.0 – mA
Amplifier Output Sink Current @ CA– = 1 V, VSO = 0 V, CAO = 2 V ISNK,Amp 1.0 2.1 – mA
Amplifier Output High Short Circuit Current
@ CA– = 1 V, VSO = 5 V, CAO = 0 V IO+,Amp – 4.5 6.5 mA
Amplifier Output Low Short Circuit Current

@ CA– = 5 V, VSO = 0 V, CAO = 5 V IO–,Amp – 3.2 5.2 mA

VBIAS (VCC, VBS1,2,3) = 15 V, VSO1,2,3 = VSS and CL = 1000 pF unless otherwise specified. TA = 25°C.
Turn–On Propagation Delay @ VIN = 0 & 5 V, VS1,2,3 = 0 V to 600 V ton 500 – 850 ns
Turn–Off Propagation Delay @ VIN = 0 & 5 V, VS1,2,3 = 0 V to 600 V toff 300 – 550 ns
Turn–On Rise Time @ VIN = 0 & 5 V, VS1,2,3 = 0 V to 600 V tr – 80 125 ns
Turn–Off Fall Time @ VIN = 0 & 5 V, VS1,2,3 = 0 V to 600 V tf – 35 55 ns
ITRIP to Output Shutdown Propagation Delay @ VIN, VITRIP = 0 & 5 V titrip 400 – 920 ns
ITRIP Blanking Time @ ITRIP = 1 V tbl – 400 – ns
ITRIP to FAULT– Propagation Delay @ VIN, VITRIP = 0 & 5 V tflt 335 – 845 ns
Input Filter Time (all six inputs) @ VIN = 0 & 5 V tflt,in – 310 – ns
LIN1,2,3 to FAULT Clear Time @ VIN, VITRIP = 0 & 5 V tfltclr 6.0 – 12 µs
Deadtime, LS Turn–Off to HS Turn–On & HS Turn–Off to LS Turn–On
@ VIN = 0 & 5 V DT 1.3 – 3.7 µs
Amplifier Slew Rate (Positive) SR+ 4.4 6.2 – V/µs

Amplifier Slew Rate (Negative) SR– 2.4 3.2 – V/µs
TYPICAL CONNECTION
10 TO 600 V
VCC VCC VB1,2,3

HIN1,2,3 HIN1,2,3 HO1,2,3
LIN1,2,3 LIN1,2,3 VS1,2,3
FAULT FAULT TO
ITRIP LOAD
CAO CAO
CA–
VSS LO1,2,3
VSO
COM

MPIC2130
LEAD DEFINITIONS
HIN1,2,3 Logic Inputs for High Side Gate Driver Outputs (HO1,2,3), Out of Phase
LIN1,2,3 Logic Inputs for Low Side Gate Driver Outputs (LO1,2,3), Out of Phase
FAULT– Indicates Over–current, or Undervoltage Lockout (Low Side) has Occurent, Negative Logic
VCC Logic and Low Side Fixed Supply
ITRIP Input for Over–current Shut Down
CAO Output of Current Amplifier
CA– Negative Input of Current Amplifier
VSS Logic Ground
VB1,2,3 High Side Floating Supplies
HO1,2,3 High Side Gate Drive Outputs
VS1,2,3 High Side Floating Supply Returns
LO1,2,3 Low Side Gate Drive Outputs
VSO Low Side Return, Positive Input of Current Amplifier
HIN
HIN
LIN LIN 50% 50%
ITRIP
tr tf
ton toff
FAULT 90% 90%
HO
HO1–3
LO 10% 10%
LO1–3

Definitions
HIN LIN2 50%

50% 50%
LIN
ITRIP 50%
FAULT 50% 50%

LO
50% 50%
LO2
HO 50%
tflt tfltclr
DT DT
titrip
Figure 3. Deadtime Waveform Definitions Figure 4. Overcurrent Shutdown Waveform

Definitions

MOTOROLA

3-HIGH SIDE &
3-LOW SIDE DRIVER
with three independent high side and low side referenced output channels for 3 HIGH SIDE &
3–Phase applications. Proprietary HVIC technology enables ruggedized monolith- 3 LOW SIDE
ic construction. Logic inputs are compatible with 5 V CMOS or LSTTL outputs. A DRIVER
ground referenced operational amplifier provides an analog feedback of bridge
current via an external current sense resistor. A current trip function which termi-
nates all six outputs is also derived from an external current sense resistor. An ex-
tra shutdown input is provided for customizing the shutdown function. An open
drain FAULT signal is provided to indicate that any of shutdown conditions has oc-
curred. The output drivers feature a high pulse current buffer stage designed for
minimum driver cross–conduction. Propagation delays are matched to simplify use 28
in high frequency applications. 1

The floating channels can be used to drive N–channel power MOSFET or
IGBT’s in the high side configuration which operate from 10 to 600 volts. P SUFFIX
PLASTIC PACKAGE
• Floating Channel Designed for Bootstrap Operation CASE 710–02
• dV/dt Immune
• Gate Drive Supply Range from 10 to 20 V PIN CONNECTIONS
• Undervoltage Lockout for All Channels

1 VCC VB1 28
• Over–current Shut Down Turns Off All Six Drivers
• Independent 3 High Side & 3 Low Side Drivers 2 HIN1 HO1 27
• Matched Propagation Delay for All Channels 3 HIN2 VS1 26

• Outputs Out of Phase with Inputs 4 HIN3 25
5 LIN1 VB2 24
PRODUCT SUMMARY 6 LIN2 HO2 23
VOFFSET 600 V MAX
7 LIN3 VS2 22
IO+/– 200 mA/420 mA
8 FAULT 21
VOUT 10 – 20 V
9 ITRIP VB3 20
ton/off (typical) 1.4 & 0.7 ms
Delay Matching 700 ns 10 FLT+CLR HO3 19
11 SD VS3 18
12 VSS 17
13 COM LO1 16
14 LO3 LO2 15
(TOP VIEW)
Device Package
REV 1

MPIC2131
VB1
H1 PULSE SET LATCH
HIN1 INPUT
SIGNAL GENERATOR
L1 DRIVER HO1
HIN2 GENERATOR LEVEL UV
VS1
HIN3
LIN1 VB2
H2 PULSE SET LATCH
INPUT
LIN2 SIGNAL GENERATOR
L2 DRIVER HO2
GENERATOR LEVEL UV
LIN3 SHIFTER RESET DETECTOR
VS2
FLT–CLR VB3
H3 PULSE SET LATCH
SD INPUT
SIGNAL GENERATOR
L3 DRIVER HO3
GENERATOR LEVEL UV
FAULT SHIFTER RESET DETECTOR
VS3
FAULT
VCC
LOGIC
DRIVER LO1
UNDER–
VSS
VOLTAGE
DETECTOR
DRIVER LO2
ITRIP
CURRENT
COMPARATOR
0.5 V DRIVER LO3
VSS
COM

conditions.

High Side Floating Absolute Voltage VB1,2,3 –0.3 625 VDC
Hi h Side
High Sid Floating
Fl ti Supply
S l Off
Offsett V
Voltage
lt VS1,2,3 VB1,2,3–25
25 VB1,2,3+0.3
03
High Side Floating Out
Outputut Voltage VHO1,2,3
HO1 2 3 VS1,2,3
S1 2 3–0.3
0.3 VB1,2,3
B1 2 3+0.3
Low Side Output Voltage VLO1,2,3
, , –0.3 VCC+0.3
Fixed Supply Voltage VCC –0.3 25
Fixed Su
Supply
ly Offset Voltage VSS VCC–25 VCC+0.3
+0 3
Logic
g Input Voltage
g (HIN–, LIN–, FLT–, CLR–, SD & ITRIP) VIN VSS–0.3 VCC+0.3
Fault Output Voltage FAULT VSS–0.3 VCC+0.3


MPIC2131
High Side Floating Supply Absolute Voltage VB1,2,3 VS1,2,3+10 VS1,2,3+20 V

High Side Floating Supply Offset Voltage VS1,2,3 Note 1 VSO+600 V
High Side Floating Output Voltage VHO1,2,3 VS1,2,3 VB1,2,3 V
Fixed Supply Voltage VCC 10 20 V
Low Side Output Voltage VLO1,2,3 0 VCC V
Low Side Driver Return VSS –5 5 V
Logic Input Voltage (HIN–, LIN–, FLT–CLR, SD & ITRIP) VIN VSS 5 V
Fault Output Voltage FAULT– VSS VCC V
Note 1: Logic operational for VS of –5 V to +600 V. Logic state held for VS of –5 V to –VBS.
VBIAS (VCC, VBS1,2,3) = 15 V and VSS = COM unless otherwise specified. The VIN, VTH and IIN parameters are referenced to VSS and are
applicable to all six channels (HS1,2,3 & LS1,2,3). The VO and IO parameters are referenced to COM and VSO1,2,3 and are applicable to
the respective output leads: HO1,2,3 or LO1,2,3.
Logic “0” Input Voltage (OUT = LO) VIH 2.2 – – V
Logic “1” Input Voltage (OUT = HI) VIL – – 0.8 V
Logic “0” Fault Clear Input Voltage VFCLR,IH 2.2 – – V
Logic “1” Fault Clear Input Voltage VFCLR,IL – – 0.8 V
SD Input Positive Going Threshold VSD,TH+ – 1.8 – V
SD Input Negative Going Threshold VSD,TH– – 1.5 – V
ITRIP Input Positive Going Threshold VIT,TH+ – 485 – mV
ITRIP Input Negative Going Threshold VIT,TH– – 400 – mV
High Level Output Voltage, VBIAS–VO @ VIN = 0 V, IO = 0 A VOH – – 100 mV
Low Level Output Voltage, VO @ VIN = 5 V, IO = 0 A VOL – – 100 mV
Offset Supply Leakage Current @ VB1,2,3 = VS1,2,3 = 600 V ILK – – 50 µA
Quiescent VBS Supply Current @ VIN = 0 V or 5 V IQBS – 30 – µA
Quiescent VCC Supply Current @ VIN = 0 V or 5 V IQCC – 3.0 – mA
Logic “1” Input Bias Current (OUT = HI) @ VIN = 0 V IIN+ – 190 – µA
Logic “0” Input Bias Current (OUT = LO) @ VIN = 5 V IIN– – 100 – µA
“High” ITRIP Bias Current @ ITRIP = 5 V ITRIP+ – 60 – µA
“Low” ITRIP Bias Current @ ITRIP = 0 V ITRIP– – – 50 nA
Logic “1” Fault Clear Bias Current @ FLT–CLR = 0 V IFCLR+ – 190 – µA
Logic “0” Fault Clear Bias Current @ FLT–CLR = 5 V IFCLR– – 100 – µA
Logic “1” Shut Down Bias Current @ SD = 5 V ISD+ – 60 – µA
Logic “0” Shut Down Bias Current @ SD = 5 V ISD– – – 150 nA
VBS Supply Undervoltage Negative Going Threshold VBSUV– – 8.2 – V
VCC Supply Undervoltage Positive Going Threshold VCCUV+ – 9.0 – V
VCC Supply Undervoltage Negative Going Threshold VCCUV– – 8.7 – V
FAULT – Low On Resistance Ron,FLT – 55 – Ω
Output High Short Circuit Pulsed Current @ Vout = 0 V, Vin = 0 V, PW ≤ 10 µs IO+ 200 250 – mA
Output Low Short Circuit Pulsed Current @ Vout = 15 V, Vin = 5 V, PW ≤ 10 µs IO– 420 500 – mA

MPIC2131
VBIAS (VCC, VBS1,2,3) = 15 V, VSO1,2,3 = VSS and CL = 1000 pF unless otherwise specified. TA = 25°C.
Turn–On Propagation Delay @ VIN = 0 & 5 V, VS1,2,3 = 0 V to 600 V ton – 1.4 – µs
Turn–Off Propagation Delay @ VIN = 0 & 5 V, VS1,2,3 = 0 V to 600 V toff – 0.7 – µs
Turn–On Rise Time @ VIN = 0 & 5 V, VS1,2,3 = 0 V to 600 V tr – 80 – ns
Turn–On Fall Time @ VIN = 0 & 5 V, VS1,2,3 = 0 V to 600 V tf – 40 – ns
ITRIP to Output Shutdown Propagation Delay @ VIN, VITRIP = 0 & 5 V titrip – 550 – ns
ITRIP Blanking Time @ ITRIP = 1 V tbl – 400 – ns
ITRIP to FAULT– Propagation Delay @ VIN, VITRIP = 0 & 5 V tflt – 450 – ns
Input Filter Time (all six inputs) @ VIN = 0 & 5 V tflt,in – 310 – ns
FLT–CLR to FAULT Clear Time @ VIN, VIT, VFC = 0 & 5 V tfltclr – 450 – ns
SD to OUTPUT Shutdown Propagation Delay @ VIN, VSD = 0 & 5 V tsd – 550 – ns
Deadtime, LS Turn–Off to HS Turn–On & HS Turn–Off to LS Turn–On
@ VIN = 0 & 5 V DT – 700 – ns
TYPICAL CONNECTION
10 TO 600 V
VCC VB1,2,3
HIN1,2,3 HO1,2,3
LIN1,2,3 VS1,2,3
FAULT TO
ITRIP LOAD
FLT–CLR
SD
VSS LO1,2,3
COM
LEAD DEFINITIONS
HIN1,2,3 Logic Inputs for High Side Gate Driver Outputs (HO1,2,3), Out of Phase
LIN1,2,3 Logic Inputs for Low Side Gate Driver Outputs (LO1,2,3), Out of Phase
FLT–CLR Logic Inputs for Fault Clear
SD Logic Input for Shut Down
FAULT Indicates Over–current, Shut Down or Low Side Undervoltage Condition, Negative Logic
ITRIP Input for Over–current Shut Down
VSS Logic Ground
VB1,2,3 High Side Floating Supplies
HO1,2,3 High Side Gate Drive Outputs
VS1,2,3 High Side Floating Supply Returns
LO1,2,3 Low Side Gate Drive Outputs
COM Low Side Return

MPIC2131
HIN
HIN
LIN
LIN 50% 50%
ITRIP
SD
tr tf
ton toff
FLT–CLR
90% 90%
FAULT
HO
HO LO 10% 10%
LO

Definitions
LIN2
HIN
50% 50% 50%
ITRIP
LIN
SD 50%
FLT–CLR 50%
LO
50% 50% FAULT 50% 50%
HO
LO2 50% 50%
tflt
DT DT titrip tfltclr tsd
Figure 3. Deadtime Waveform Definitions Figure 4. Shutdown Waveform Definitions

MOTOROLA

SELF-OSCILLATING
HALF-BRIDGE DRIVER
The MPIC2151 is a high voltage, high speed, self–oscillating power MOSFET
and IGBT driver with both high side and low side referenced output channels. Pro- SELF–OSCILLATING
prietary HVIC and latch immune CMOS technologies enable ruggedized monolith- HALF–BRIDGE
ic construction. The front–end features a programmable oscillator which is similar DRIVER
to the 555 timer. The output drivers feature a high pulse current buffer stage and an
internal deadtime designed for minimum driver cross–conduction. Propagation de-
lays for the two channels are matched to simplify use in 50% duty cycle applica-
tions. The floating channel can be used to drive an N–channel power MOSFET or
IGBT in the high side configuration that operates off a high voltage rail from 10 to
600 volts. 8
1
• Fully Operational to +600 V P SUFFIX
PLASTIC PACKAGE
CASE 626–05
• dV/dt Immune
• Undervoltage Lockout
• Programmable Oscillator Frequency:
f + 1.4 (RT )1 75W) CT 8
• Matched Propagation Delay for Both Channels 1

• Low Side Output In Phase with RT
D SUFFIX
PLASTIC PACKAGE
CASE 751–05
PRODUCT SUMMARY (SO–8)
VOFFSET 600 V MAX
Duty Cycle 50%
VOUT 10 – 20 V
tr/f (typical) 120 & 60 ns PIN CONNECTIONS
Deadtime (typical) 1.2 µs

VCC 1 8 VB
RT 2 7 HO
CT 3 6 VS
COM 4 5 LO
(TOP VIEW)
Device Package
MPIC2151D SOIC
REV 1

MPIC2151
VB
R HV Q
RT LEVEL
PULSE R HO
SHIFT
FILTER S
–
R Q DEAD PULSE VS
+
TIME GEN
R S Q
VCC
+
CT – 15.6 V
DEAD LO
UV DELAY
TIME
R DETECT
COM

voltages referenced to COM, all currents are defined positive into any lead. The Thermal Resistance and Power Dissipation ratings are
measured under board mounted and still air conditions.

High Side Floating Su
Supply
ly Absolute Voltage VB –0.3
0.3 625 VDC
High
g Side Floatingg Supplyy Offset Voltage
g VS VB–25 VB+0.3
High
g Side Floatingg Output Voltage
Low Side Output Voltage
g VLO –0.3 VCC+0.3
RT Voltage VRT –0.3 VCC+0.3
CT Voltage VCT –0.3 VCC+0.3
Supply
y Current ((Note 1)) ICC – 25 mADC
High Side Output Current IHO –500 500
Low Side Output Current ILO –500 500
RT O
Output
t tCCurrentt IRT –5.0
50 5.0
50

(8 Lead SOIC) – – 0.625


tions.
High Side Floating Supply Absolute Voltage VB VS+10 VS+Vclamp V
High Side Floating Supply Offset Voltage VS – 600
Supply Current (Note 1) ICC – 5.0 mA
Note 1: Because the MPIC2151 is designed specifically for off–line supply systems, this IC contains a zener clamp structure between the chip
VCC and COM which has a nominal breakdown voltage of 15.6 V. Therefore, the IC supply voltage is normally derived by forcing current into
the supply lead (typically by means of a high value resistor connected between the chip VCC and the rectified line voltage and a local decoup-
ling capacitor from VCC to COM) and allowing the internal zener clamp circuit to determine the nominal supply voltage. Therefore, this circuit
should not be driven by a DC, low impedance power source of greater than VCLAMP.

MPIC2151
ELECTRICAL CHARACTERISTICS (TC = 25°C unless otherwise specified)
Supply Characteristics
VBIAS (VCC, VBS) = 12 V, VSS = COM and CL = 1000 pF unless otherwise specified.
VCC Supply Undervoltage Positive Going Threshold VCCUV+ – 8.4 – VDC
Quiescent VCC Supply Current IQCC – 400 – µA
VCC Zener Shunt Clamp Voltage @ IOC = 5 mA VCLAMP – 15.6 – VDC
Floating Supply Characteristics
Offset Supply Leakage Current @ VB = VS = 600 V ILK – – 50 µADC
Quiescent VBS Supply Current IQBS – 10 –
Oscillator I/O Characteristics
Oscillator Frequency @ RT = 35.7 KΩ, CT = 1 nF fOSC – 20 – kHz
Oscillator Frequency @ RT = 7.04 KΩ, CT = 1 nF fOSC – 100 –
CT Input Current ICT – 0.001 1.0 µA
CT Undervoltage Lockout @ 2.5 V < VCC < VCCUV+ VCTUV – 0 – mV
RT High Level Output Voltage, VCC – RT @ IRT = –100 µA VRT+ – 20 –
@ IRT = –1 mA VRT+ – 200 –
RT Low Level Output Voltage, VCC + RT @ IRT = 100 µA VRT– – 20 –

@ IRT = 1 mA VRT– – 200 –
RT Undervoltage Lockout, VCC – RT @ 2.5 V < VCC < VCCUV+ VRTUV – 0 –

2/3 VCC Threshold VCT+ – 8.0 – VDC
1/3 VCC Threshold VCT– – 4.0 –
Output Characteristics
High Level Output Voltage, VBIAS–VO @ IO = 0 A VOH – – 100 mV
Low Level Output Voltage, VO @ IO = 0 A VOL – – 100
Dynamic Electrical Characteristics
VBIAS (VCC, VBS) = 12 V and CL = 1000 pF unless otherwise specified. TA = 25°C.
Turn–On Rise Time tr – 120 – ns
Turn–Off Fall Time tf – 60 –
Deadtime, LS Turn–Off to HS Turn–On & HS Turn–Off to LS Turn–On DT – 1.2 – µA
RT Duty Cycle, fOSC = 20 kHz DC – 50 – %

MPIC2151
TYPICAL CONNECTION
10 TO 600 V
VCC VB
RT HO TO
LOAD
CT VS
COM LO
LEAD DEFINITIONS
RT Oscillator timing resistor input; a resistor is connected from RT to CT. RT is in phase with LO for normal IC operation.
CT Oscillator timing capacitor input; a capacitor is connected from CT to COM in order to program the oscillator frequency
according to the following equation:
f + 1.4 (RT ) 75W) CT
1
where 75Ω is the effective impedance of the RT output stage.
COM Logic and Low Side Return
VCCUV+
VCC VCLAMP
RT(HO)
50% 50%
RT RT(LO)
CT
tr tf
HO 90% 90%
LO
HO 10% 10%
LO
Figure 1. Input / Output Timing Diagram Figure 2. Switching Time Waveform Definitions
RT
50% 50%
90%
HO 10%
DT
LO 90%
10%
Figure 3. Deadtime Waveform Definitions

MOTOROLA
 Data Sheet
Designer's
MTB1N100E
TMOS E-FET. Motorola Preferred Device
High Energy Power FET

D2PAK for Surface Mount TMOS POWER FET
N–Channel Enhancement–Mode Silicon Gate 1.0 AMPERES
1000 VOLTS
The D2PAK package has the capability of housing a larger die
RDS(on) = 9.0 OHM
than any existing surface mount package which allows it to be used
in applications that require the use of surface mount components
with higher power and lower RDS(on) capabilities. This high voltage
MOSFET uses an advanced termination scheme to provide
enhanced voltage–blocking capability without degrading perfor- 
mance over time. In addition, this advanced TMOS E–FET is
designed to withstand high energy in the avalanche and commuta-
tion modes. The new energy efficient design also offers a
drain–to–source diode with a fast recovery time. Designed for high D
safe operating areas are critical and offer additional safety margin G
against unexpected voltage transients. CASE 418B–02, Style 2
D2PAK
• Robust High Voltage Termination S
• Source–to–Drain Diode Recovery Time Comparable to a
Discrete Fast Recovery Diode
• Diode is Characterized for Use in Bridge Circuits
• Short Heatsink Tab Manufactured — Not Sheared
• Specially Designed Leadframe for Maximum Power Dissipation
• Available in 24 mm 13–inch/800 Unit Tape & Reel, Add T4 Suffix to Part Number
Drain–Source Voltage VDSS 1000 Vdc
Drain–Gate Voltage (RGS = 1.0 MΩ) VDGR 1000 Vdc
Gate–Source Voltage — Continuous VGS ± 20 Vdc
Gate–Source Voltage — Non–Repetitive (tp ≤ 10 ms) VGSM ± 40 Vpk
Drain Current — Continuous @ 100°C ID 0.8
Drain Current — Single Pulse (tp ≤ 10 µs) IDM 3.0 Apk
Total Power Dissipation @ TA = 25°C, when mounted with the minimum recommended pad size 2.5 Watts
(VDD = 25 Vdc, VGS = 10 Vdc, IL = 3.0 Apk, L = 10 mH, RG = 25 Ω)
Thermal Resistance — Junction to Ambient RθJA 62.5
Thermal Resistance — Junction to Ambient, when mounted with the minimum recommended pad size RθJA 50
REV 2

MTB1N100E
OFF CHARACTERISTICS
Drain–Source Breakdown Voltage V(BR)DSS
(VGS = 0 Vdc, ID = 250 µAdc) 1000 — — Vdc
(VDS = 1000 Vdc, VGS = 0 Vdc) — — 10
(VDS = VGS, ID = 250 µAdc) 2.0 — 4.0 Vdc
Static Drain–Source On–Resistance (VGS = 10 Vdc, ID = 0.5 Adc) RDS(on) — 6.7 9.0 Ohm
Drain–Source On–Voltage (VGS = 10 Vdc) VDS(on) Vdc
(ID = 1.0 Adc) — 4.86 9.0
(ID = 0.5 Adc, TJ = 125°C) — — 10.5
Forward Transconductance (VDS = 15 Vdc, ID = 0.5 Adc) gFS 0.9 1.32 — mhos
Vd VGS = 0 Vdc,
Vd
Coss — 59.6 120
f = 1.0 MHz)
Reverse Transfer Capacitance Crss — 12.2 25

VGS = 10 Vdc
Vdc,
(See Fig
Figure
re 8)
((VDS = 400 Vdc, ID = 1.0 Adc, Q1 — 2.8 —
VGS = 10 Vdc) Q2 — 6.8 —
Q3 — 5.2 —
— 0.764 1.0
(IS = 1.0 Adc, VGS = 0 Vdc, TJ = 125°C)
— 0.62 —
Fig re 14)
(See Figure
((IS = 1.0 Adc, VGS = 0 Vdc, ta — 42 —
dIS/dt = 100 A/µs) tb — 613 —
Internal Drain Inductance LD — 4.5 — nH
(Measured from the drain lead 0.25″ from package to center of die)
Internal Source Inductance LS — 7.5 — nH

(Measured from the source lead 0.25″ from package to source bond pad)

MTB1N100E
2.0 2.0
1.8 TJ = 25°C 1.8 VDS ≥ 10 V
VGS = 10 V
100°C

1.6 6V 1.6
1.4 1.4
5V
1.2 1.2
1.0 1.0
25°C
0.8 0.8
0.6 0.6
0.4 0.4
TJ = –55°C
0.2 4V 0.2
0 0
0 2 4 6 8 10 12 14 16 18 20 2.0 2.4 2.8 3.2 3.6 4.0 4.4 4.8 5.2 5.6


16 8.0
VGS = 10 V TJ = 25°C
14 7.8
TJ = 100°C 7.6
12
7.4
10 7.2
8 25°C 7.0
VGS = 10 V
6 6.8
6.6
4 15 V
6.4
– 55°C
2 6.2
0 6.0
0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
and Temperature and Gate Voltage
2.8 10000
VGS = 10 V TJ = 125°C
2.4 ID = 0.5 A 1000
100°C
2.0
100
(NORMALIZED)
1.6
10
1.2
1.0 25°C
0.8
0.4 0.1
VGS = 0 V
0 0.01
–50 –25 0 25 50 75 100 125 150 0 100 200 300 400 500 600 700 800 900 1000


MTB1N100E
1200 1000
Ciss VDS = 0 V VGS = 0 V TJ = 25°C
Ciss
1000 VGS = 0 V TJ = 25°C
C, CAPACITANCE (pF)
800 100
C, CAPACITANCE (pF)
Ciss
600 Coss
Crss
400 10
Crss
200 Coss
Crss
0 1
10 5 0 5 10 15 20 25 10 100 1000
VGS VDS VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)
Figure 7b. High Voltage Capacitance
Figure 7a. Capacitance Variation Variation

MTB1N100E
12 480 1000

QT VDD = 500 V
10 400 ID = 1 A
VGS = 10 V
TJ = 25°C
8 VGS 320 100
t, TIME (ns)
Q1 Q2 tf
6 240 tr
td(off)
4 ID = 1 A 160 10 td(on)
TJ = 25°C
2 80
Q3 VDS
0 0 1
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 1 10 100

1.0
VGS = 0 V
TJ = 25°C
0.8
0.6
0.4
0.2
0
0.50 0.54 0.58 0.62 0.66 0.70 0.74 0.78
SAFE OPERATING AREA
drain current that a transistor can handle safely when it is for- the rated limit and adjusted for operating conditions differing
ward biased. Curves are based upon maximum peak junc- from those specified. Although industry practice is to rate in
tion temperature and a case temperature (TC) of 25°C. Peak terms of energy, avalanche energy capability is not a con-
repetitive pulsed power limits are determined by using the stant. The energy rating decreases non–linearly with an in-
thermal response data in conjunction with the procedures crease of peak current in avalanche and peak junction
discussed in AN569, “Transient Thermal Resistance–Gener-
temperature.
al Data and Its Use.”
nor rated voltage (VDSS) is exceeded and the transition time (IDM), the energy rating is specified at rated continuous cur-
(tr,tf) do not exceed 10 µs. In addition the total power aver- rent (ID), in accordance with industry custom. The energy rat-
aged over a complete switching cycle must not exceed ing must be derated for temperature as shown in the
A Power MOSFET designated E–FET can be safely used rents below rated continuous ID can safely be assumed to

MTB1N100E
SAFE OPERATING AREA
10 50
VGS = 20 V ID = 1 A

SINGLE PULSE
TC = 25°C 40

1.0
10 µs 30
100 µs
1 ms 20
0.1
10 ms
RDS(on) LIMIT dc 10
THERMAL LIMIT
PACKAGE LIMIT
0.01 0
0.1 1.0 10 100 1000 25 50 75 100 125 150
1.0
D = 0.5
0.2
0.1
0.1 P(pk)
t1 READ TIME AT t1
0.01
SINGLE PULSE
0.01
1.0E–05 1.0E–04 1.0E–03 1.0E–02 1.0E–01 1.0E+00 1.0E+01
t, TIME (s)
3
RθJA = 50°C/W
Board material = 0.065 mil FR–4
PD, POWER DISSIPATION (WATTS)
2.5 Mounted on the minimum recommended footprint

Collector/Drain Pad Size ≈ 450 mils x 350 mils
2.0
di/dt
IS 1.5
trr
1
ta tb
TIME 0.5
tp 0.25 IS
0
IS 25 50 75 100 125 150
TA, AMBIENT TEMPERATURE (°C)
Figure 14. Diode Reverse Recovery Waveform Figure 15. D2PAK Power Derating Curve

MOTOROLA
 Data Sheet
Designer's
TMOS E-FET. MTB2N40E


400 VOLTS
The D2PAK package has the capability of housing a larger die RDS(on) = 3.8 OHM
with higher power and lower RDS(on) capabilities. This advanced
TMOS E–FET is designed to withstand high energy in the
avalanche and commutation modes. The new energy efficient

design also offers a drain–to–source diode with a fast recovery
power supplies, converters and PWM motor controls, these
devices are particularly well suited for bridge circuits where diode D
speed and commutating safe operating areas are critical and offer
• Avalanche Energy Specified G
CASE 418B–02, Style 2
• Source–to–Drain Diode Recovery Time Comparable to a D2PAK
Discrete Fast Recovery Diode S
• Available in 24 mm 13–inch/800 Unit Tape & Reel, Add T4
Suffix to Part Number
— Non–Repetitive (tp ≤ 10 ms) VGSM ± 40 Vpk
— Continuous @ 100°C ID 1.5
— Single Pulse (tp ≤ 10 µs) IDM 6.0 Apk
Total Power Dissipation @ 25°C PD 40 Watts
Total Power Dissipation @ TA = 25°C (1) 2.5 Watts
(VDD = 100 Vdc, VGS = 10 Vdc, Peak IL = 3.0 Apk, L = 10 mH, RG = 25 Ω)
— Junction to Ambient RθJA 62.5
— Junction to Ambient (1) RθJA 50
REV 1

MTB2N40E
OFF CHARACTERISTICS
(VGS = 0 Vdc, ID = 250 µAdc) 400 — —
(VDS = 400 Vdc, VGS = 0 Vdc) — — 10
(VGS = 10 Vdc, ID = 2.0 Adc) — 7.3 8.4
(VGS = 10 Vdc, ID = 1.0 Adc, TJ = 125°C) — — 7.4
Vd VGS = 0 Vdc,
Vd
Coss — 34 40
f = 1.0 MHz)
Transfer Capacitance Crss — 7.3 10

VGS = 10 Vdc
Vdc,
(S Fi
(See Figure 8)
((VDS = 320 Vdc, ID = 2.0 Adc, Q1 — 2.6 —
VGS = 10 Vdc) Q2 — 3.2 —
Q3 — 5.0 —
(IS = 2.0 Adc, VGS = 0 Vdc )
— 0.88 1.2
(IS = 2.0 Adc, VGS = 0 Vdc , TJ = 125°C)
— 0.76 —
(S Figure
(See Fi 14)
((IS = 2.0 Adc, VGS = 0 Vdc, ta — 99 —
dlS/dt = 100 A/µs) tb — 57 —


MTB2N40E
4 4
TJ = 25°C VGS = 10 V VDS ≥ 10 V
8V

3.2
3
7V
2.4
2
1.6 6V
1
0.8
5V TJ = 100°C 25°C
–55°C
0 0
0 4 8 12 16 20 2 3 4 5 6 7 8


8 5.0
VGS = 10 V TJ = 25°C
4.5
6
100°C
4.0
4 TJ = 25°C VGS = 10 V
3.5
15 V
2 –55°C
3.0
0 2.5
0 1 2 3 4 0 0.5 1 1.5 2 2.5 3 3.5 4
2.5 1000
ID = 1 A
2
TJ = 125°C
(NORMALIZED)
1.5
100
1
0.5
0 10
– 50 – 25 0 25 50 75 100 125 150 0 100 200 300 400


MTB2N40E
500 1000
VDS = 0 V VGS = 0 V TJ = 25°C TJ = 25°C
VGS = 0
Ciss
400
Ciss
C, CAPACITANCE (pF)
C, CAPACITANCE (pF)
100
300
Ciss
Crss Coss
200
10
Crss
100 Coss
Crss
0 1
10 5 0 5 10 15 20 25 10 100 1000
VGS VDS
Figure 7a. Capacitance Variation Figure 7b. High Voltage Capacitance Variation

MTB2N40E

100

12 400 TJ = 25°C
QT ID = 2 A
10 VDD = 200 V
300 VGS = 10 V
VGS
8
t, TIME (ns)
td(off)
6 200 10 tf
Q1 Q2
tr td(on)
4
TJ = 25°C 100
2 ID = 2 A
Q3 VDS
0 0 1
0 2 4 6 8 1 10 100


2
VGS = 0 V
TJ = 25°C
1.5
0.5
0
0.5 0.6 0.7 0.8 0.9
SAFE OPERATING AREA
temperature.

MTB2N40E
SAFE OPERATING AREA
10 45

VGS = 20 V ID = 2 A
40
SINGLE PULSE 10 µs

TC = 25°C 35
1 100 µs 30
1 ms
25
10 ms
20
0.1 dc 15
RDS(on) LIMIT 10
THERMAL LIMIT
5
PACKAGE LIMIT
0.01 0
0.1 1 10 100 1000 25 50 75 100 125 150
r (t), EFFECTIVE TRANSIENT THERMAL RESISTANCE
D = 0.5
0.2
0.1
(NORMALIZED)
0.05
0.1 P(pk)
SINGLE PULSE PULSE TRAIN SHOWN
t1 READ TIME AT t1
0.01
0.00001 0.0001 0.001 0.01 0.1 1 10
t, TIME (SECONDS)
3
RθJA = 50°C/W
Mounted on the minimum recommended footprint
2.5
2.0
di/dt
IS 1.5
trr
1
ta tb
TIME 0.5
tp 0.25 IS
0
IS 25 50 75 100 125 150

MOTOROLA
 Data Sheet
Designer's


600 VOLTS
This high voltage MOSFET uses an advanced termination RDS(on) = 3.8 OHM
scheme to provide enhanced voltage–blocking capability without
degrading performance over time. In addition, this advanced TMOS
E–FET is designed to withstand high energy in the avalanche and
commutation modes. The new energy efficient design also offers a

drain–to–source diode with a fast recovery time. Designed for high
D
against unexpected voltage transients.
G
• Source–to–Drain Diode Recovery Time Comparable to a CASE 418B–02, Style 2
Discrete Fast Recovery Diode D2PAK
• Diode is Characterized for Use in Bridge Circuits S

MTB2N60E
OFF CHARACTERISTICS
(VGS = 0 Vdc, ID = 250 µAdc) 600 — —
(VDS = 600 Vdc, VGS = 0 Vdc) — — 0.25
(VDS = 480 Vdc, VGS = 0 Vdc, TJ = 125°C) — — 1.0
(VGS = 10 Vdc, ID = 2.0 Adc) — — 8.2
(VGS = 10 Vdc, ID = 1.0 Adc, TJ = 125°C) — — 8.4
Forward Transconductance (VDS = 50 Vdc, ID = 1.0 Adc) gFS 1.0 — — mhos
Vd VGS = 0 Vdc,
Vd
Coss — 100 —
f = 1.0 MHz)

VGS = 10 Vdc
Vdc,
Turn–Off Delay Time RG = 18 Ω) td(off) — 30 —
(S Fi
(See Figure 8)
((VDS = 400 Vdc, ID = 2.0 Adc, Q1 — 2.0 —
VGS = 10 Vdc) Q2 — 6.0 —
Q3 — 5.0 —
Forward On–Voltage (IS = 2.0 Adc, VGS = 0 Vdc) VSD — 1.0 1.6 Vdc
(IS = 2.0 Adc, VGS = 0 Vdc, TJ = 125°C) — 0.9 —
Reverse Recovery Time (IS = 2.0 Adc, VGS = 0 Vdc, trr ns
dIS/dt = 100 A/µs) — 340 —



MTB2N60E
4 8
TJ = 25°C VGS = 10 V
7V VDS ≥ 10 V

3 6
6V
2 4
5.5 V TJ = 100°C
1 2
–55°C
5V 25°C
0 0
0 4 8 12 16 20 0 2 4 6 8 10


12 4.5
VGS = 10 V 100°C TJ = 25°C
4.3
4.1
3.9
8
TJ = 25°C 3.7
VGS = 10 V
3.5
3.3
4
–55°C 3.1 15 V
2.9
2.7
0
0 1.5 3 4.5 6 2.5
0 0.5 1 1.5 2 2.5 3 3.5 4
ID, DRAIN CURRENT (AMPS)
ID, DRAIN CURRENT (AMPS)
2.5 1000
ID = 1 A
2 TJ = 125°C
100
(NORMALIZED)
1.5 100°C
1
10
0.5
0 1
– 50 – 25 0 25 50 75 100 125 150 0 100 200 300 400 500 600


MTB2N60E
800 1000
VDS = 0 V VGS = 0 V TJ = 25°C
700 Ciss Ciss
600 100
C, CAPACITANCE (pF)
C, CAPACITANCE (pF)
500 Ciss Coss

Crss 10
400
300
Crss
200 Coss 1
Crss TJ = 25°C
100
VGS = 0
0 0.1
10 5 0 5 10 15 20 25 10 100 1000
VGS VDS
GATE–TO–SOURCE OR DRAIN–TO–SOURCE VOLTAGE (VOLTS) VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS)

MTB2N60E

500 1000

15 TJ = 25°C
TJ = 25°C
ID = 2 A ID = 2 A
VDS
12 400 VDS = 300 V td(off) tf
VGS = 10 V tr
100
QT VDS = 100 V
t, TIME (ns)
9 300
VDS = 250 V
VDS = 400 V
Q1 td(on)
6 200
Q2 10
3 100
VGS
Q3
00 0 1
4 8 12 16 20
1 10 100 1000

2.0
VGS = 0 V
1.8
TJ = 25°C
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
0.50 0.55 0.60 0.65 0.70 0.75 0.80 0.85
SAFE OPERATING AREA
temperature.

MTB2N60E
SAFE OPERATING AREA
10 200

VGS = 20 V Peak IL = 2 A
10 µs VDD = 50 V
SINGLE PULSE

TC = 25°C 150
1 100 µs
1 ms
10 ms 100
0.1 dc 50
RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT 0
0.01 25 50 75 100 125 150
0.1 1 10 100 1000 TJ, STARTING JUNCTION TEMPERATURE (°C)
D = 0.5
0.2
(NORMALIZED)
0.1
0.1 0.05 P(pk)
PULSE TRAIN SHOWN
SINGLE PULSE t2 TJ(pk) – TC = P(pk) RθJC(t)
0.01
0.00001 0.0001 0.001 0.01 0.1 1 10
t, TIME (SECONDS)
3
RθJA = 50°C/W
2.5
2.0
di/dt
IS 1.5
trr
1
ta tb
TIME 0.5
tp 0.25 IS
0
IS 25 50 75 100 125 150

MOTOROLA
 Data Sheet
Designer's
MTB2P50E

P–Channel Enhancement–Mode Silicon Gate 2.0 AMPERES
500 VOLTS
RDS(on) = 6.0 OHM
enhanced voltage–blocking capability without degrading perfor- 
D2PAK
• Source–to–Drain Diode Recovery Time Comparable to a Discrete
Fast Recovery Diode
REV 1

MTB2P50E
OFF CHARACTERISTICS
(VDS = 500 Vdc, VGS = 0 Vdc) — — 10
(ID = 2.0 Adc) — 9.5 14.4
(ID = 1.0 Adc, TJ = 125°C) — — 12.6
Vd VGS = 0 Vdc,
Vd
Coss — 100 140
f = 1.0 MHz)

VGS = 10 dc,
dc
(See Fig
Figure
re 8)
((VDS = 400 Vdc, ID = 2.0 Adc, Q1 — 3.7 —
VGS = 10 Vdc) Q2 — 7.9 —
Q3 — 9.9 —
— 2.3 3.5
(IS = 2.0 Adc, VGS = 0 Vdc, TJ = 125°C)
— 1.85 —
(See Figure
Fig re 14)
((IS = 2.0 Adc, VGS = 0 Vdc, ta — 161 —
dIS/dt = 100 A/µs) tb — 62 —


MTB2P50E
4 4
TJ = 25°C VGS = 10 V VDS ≥ 10 V
3.5 7V 3.5

8V 25°C
3 3
6V TJ = – 55°C
2.5 2.5 100°C
2 2
1.5 1.5
5V
1 1
0.5 0.5
4V
0 0
0 4 8 12 16 20 24 28 2 2.5 3 3.5 4 4.5 5 5.5 6 6.5 7


10 6
VGS = 10 V TJ = 25°C
5.75
TJ = 100°C
8
5.5
6 5.25
25°C VGS = 10 V
5
4 4.75 15 V
– 55°C
4.5
2
4.25
0 4
0 0.5 1 1.5 2 2.5 3 3.5 4 0 0.5 1 1.5 2 2.5 3 3.5 4
2 1000
VGS = 0 V
VGS = 10 V
ID = 1 A TJ = 125°C
1.5 100
(NORMALIZED)
100°C
1 10
25°C
0.5 1
– 50 – 25 0 25 50 75 100 125 150 0 50 100 150 200 250 300 350 400 450 500


MTB2P50E
1800 1000
VDS = 0 V VGS = 0 V TJ = 25°C
1600 VGS = 0 V Ciss
Ciss TJ = 25°C
1400
C, CAPACITANCE (pF)
C, CAPACITANCE (pF)
1200 100
Coss
1000 Ciss
800
Crss
600 Crss 10
400
200 Coss
Crss
0 1
10 5 0 5 10 15 20 25 10 100 1000

MTB2P50E
12 300 1000

QT VDD = 250 V
10 250 ID = 2 A
VGS = 10 V
TJ = 25°C
8 VGS 200
t, TIME (ns)
Q1 Q2
6 150 100
ID = 2 A td(off)
tf
TJ = 25°C
4 100
tr
2 50 td(on)
Q3 VDS
0 0 10
0 2 4 6 8 10 12 14 16 18 20 1 10 100
QG, TOTAL CHARGE (nC) RG, GATE RESISTANCE (OHMS)

2
VGS = 0 V
TJ = 25°C
1.6
1.2
0.8
0.4
0
0.6 0.8 1 1.2 1.4 1.6 1.8 2 2.2 2.4
SAFE OPERATING AREA
discussed in AN569, “Transient Thermal Resistance–General
temperature.
Data and Its Use.”

MTB2P50E
SAFE OPERATING AREA
10 80
VGS = 20 V
ID = 2 A

SINGLE PULSE 10 µs
TC = 25°C

60
1 100 µs
1 ms
40
10 ms
dc
0.1
20
RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT
0.01 0
0.1 1 10 100 1000 25 50 75 100 125 150
1
D = 0.5
0.2
0.1
0.1 0.05 P(pk)

0.01
PULSE TRAIN SHOWN
0.01
1.0E–05 1.0E–04 1.0E–03 1.0E–02 1.0E–01 1.0E+00 1.0E+01
t, TIME (ms)
3
RθJA = 50°C/W
2.0
di/dt
IS 1.5
trr
1
ta tb
TIME 0.5
tp 0.25 IS
0
IS 25 50 75 100 125 150

MOTOROLA
 Data Sheet
Designer's
MTB3N100E

1000 VOLTS

enhanced voltage–blocking capability without degrading perfor-
D
D2PAK
REV 2

MTB3N100E
OFF CHARACTERISTICS
(VDS = 1000 Vdc, VGS = 0 Vdc) — — 10
(ID = 3.0 Adc) — 4.97 14.4
(ID = 1.5 Adc, TJ = 125°C) — — 12.6
Vd VGS = 0 Vdc,
Vd
Coss — 117 260
f = 1.0 MHz)

VGS = 10 Vdc
Vdc,
(See Fig
Figure
re 8)
((VDS = 400 Vdc, ID = 3.0 Adc, Q1 — 6.0 —
VGS = 10 Vdc) Q2 — 14.6 —
Q3 — 13.5 —
— 0.794 1.1
(IS = 3.0 Adc, VGS = 0 Vdc, TJ = 125°C)
— 0.63 —
Fig re 14)
(See Figure
((IS = 3.0 Adc, VGS = 0 Vdc, ta — 104 —
dIS/dt = 100 A/µs) tb — 511 —


MTB3N100E
6 6
TJ = 25°C VDS ≥ 10 V
100°C
5 VGS = 10 V 5

4 6V 4
5V
3 3 25°C
2 2 TJ = –55°C
1 1
4V
0 0
0 2 4 6 8 10 12 14 16 18 20 2.0 2.4 2.8 3.2 3.6 4.0 4.4 4.8 5.2 5.6 6.0


6 3.8
VGS = 10 V TJ = 100°C TJ = 25°C
5 3.6 VGS = 10 V
4 3.4
25°C
3 3.2 15 V
2 3.0
– 55°C
1 2.8
1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
2.4 100000
ID = 1.5 A TJ = 125°C
2.0 10000
100°C
(NORMALIZED)
1.6 1000
1.2 100
25°C
0.8 10
0.4 1
–50 –25 0 25 50 75 100 125 150 0 100 200 300 400 500 600 700 800 900 1000


MTB3N100E
2800 10000
Ciss VDS = 0 V VGS = 0 V TJ = 25°C VGS = 0 V TJ = 25°C
2400
Ciss
1000
2000
C, CAPACITANCE (pF)
C, CAPACITANCE (pF)
1600 Ciss
Crss 100
Coss
1200
800 10 Crss
Coss
400 Crss
0 1
10 5 0 5 10 15 20 25 10 100 1000


MTB3N100E
16 400 1000

VDD = 500 V
14 350
ID = 3 A
QT 300 VGS = 10 V
12
TJ = 25°C
t, TIME (ns)
10 250
8 VGS 200 100
6 Q1 Q2 150
ID = 3 A
4 TJ = 25°C 100 td(off)
tf
2 50 tr
Q3 VDS td(on)
0 0 10
0 4 8 12 16 20 24 28 30 1 10 100

3.0
VGS = 0 V
2.5 TJ = 25°C
2.0
1.5
1.0
0.5
0
0.50 0.54 0.58 0.62 0.66 0.70 0.74 0.78 0.80
SAFE OPERATING AREA
temperature.

MTB3N100E
SAFE OPERATING AREA
100 250
VGS = 20 V ID = 3 A

SINGLE PULSE
TC = 25°C 200

10
150
10 µs
1.0
100 µs
1 ms 100
0.1 10 ms
RDS(on) LIMIT dc 50
THERMAL LIMIT
PACKAGE LIMIT
0.01 0
0.1 1.0 10 100 1000 25 50 75 100 125 150
1.0
D = 0.5
0.2
0.1
0.1 P(pk)
0.05
PULSE TRAIN SHOWN
0.01 DUTY CYCLE, D = t1/t2
SINGLE PULSE
0.01
1.0E–05 1.0E–04 1.0E–03 1.0E–02 1.0E–01 1.0E+00 1.0E+01
t, TIME (ms)
3.0
RθJA = 50°C/W
2.5
2.0
di/dt
IS 1.5
trr
1.0
ta tb
TIME 0.5
tp 0.25 IS
0
IS 25 50 75 100 125 150

MOTOROLA
 Data Sheet
Designer's
MTB3N120E

1200 VOLTS

tion modes. This new energy efficient design also offers a
drain–to–source diode with a fast recovery time. Designed for low D
D2PAK
• Avalanche Energy Capability Specified at Elevated Temperature S
• Low Stored Gate Charge for Efficient Switching
• Internal Source–to–Drain Diode Designed to Replace External Zener Transient Suppressor Absorbs High Energy in the
Avalanche Mode
• Source–to–Drain Diode Recovery time Comparable to Discrete Fast Recovery Diode
* See App. Note AN1327 – Very Wide Input Voltage Range; Off–line Flyback Switching Power Supply

Drain Current — Continuous @ 25°C ID 3.0 Adc



(VDD = 100 Vdc, VGS = 10 Vdc, PEAK IL = 4.5 Apk, L = 10 mH, RG = 25 Ω) 101

Thermal Resistance — Junction to Ambient (1) RθJA 50
REV 1

MTB3N120E
OFF CHARACTERISTICS
(VDS = 1200 Vdc, VGS = 0 Vdc) — — 10
(ID = 3.0 Adc) — — 18.0
(ID = 1.5 Adc, TJ = 125°C) — — 15.8
Vd VGS = 0 Vdc,
Vd
Coss — 1710 2390
f = 1.0 MHz)

VGS = 10 Vdc
Vdc,
Turn–Off Delay Time RG = 9.1 Ω) td(off) — 35.8 70
Fall Time tf — 20.7 40
((VDS = 600 Vdc, ID = 3.0 Adc, Q1 — 8.0 —

VGS = 10 Vdc) Q2 — 11 —
Q3 — 14 —
— 0.80 1.0
(IS = 3.0 Adc, VGS = 0 Vdc, TJ = 125°C)
— 0.65 —
((IS = 3.0 Adc, VGS = 0 Vdc, ta — 118 —

dIS/dt = 100 A/µs) tb — 276 —
Internal Source Inductance LS — 7.5 —

MTB3N120E
6 6
TJ = 25°C VGS = 10 V VDS ≥ 10 V
5 5

4 6V 4 100°C
3 3
2 5V 2
25°C
1 1
4V TJ = – 55°C
0 0
0 6 12 18 24 30 3 3.4 3.8 4.2 4.6 5.0 5.4 5.8 6.2


8 5.4
VGS = 10 V TJ = 100°C TJ = 25°C
6 5.0
VGS = 10 V
4 4.6
25°C
15 V
2 4.2
– 55°C
0 3.8
0 1 2 3 4 5 6 0 1 2 3 4 5 6
2.5 10,000
VGS = 0 V
VGS = 10 V
2.0 ID = 1.5 A TJ = 125°C
1,000
(NORMALIZED)
1.5 100°C
100
1.0
25°C
10
0.5
0 1
– 50 – 25 0 25 50 75 100 125 150 0 200 400 600 800 1000 1200


MTB3N120E
2800 10,000
Ciss VDS = 0 V VGS = 0 V TJ = 25°C VGS = 0 V
2400 TJ = 25°C
Ciss
C, CAPACITANCE (pF)
2000
C, CAPACITANCE (pF)
1,000
1600 Crss
Ciss
1200
100 Coss
800
Coss
400 Crss
Crss
0 10
10 5 0 5 10 15 20 25 10 100 1000
VGS VDS

MTB3N120E
16 400 1000

VDD = 600 V
14 350 ID = 3 A
VGS = 10 V
12 300 TJ = 25°C
QT 100
t, TIME (ns)
10 250
8 200 td(off)
VGS
Q1 Q2 tf
6 150 td(on)
10
ID = 3 A tr
4 100
TJ = 25°C
2 50
Q3 VDS
0 0 1
0 4 8 12 16 20 24 28 32 1 10 10

3.0
VGS = 0 V
2.4 TJ = 25°C
1.8
1.2
0.6
0
0.55 0.59 0.63 0.67 0.71 0.75 0.79
SAFE OPERATING AREA
temperature.

MTB3N120E
SAFE OPERATING AREA
100 120

VGS = 20 V ID = 3 A
SINGLE PULSE 100
TC = 25°C

10 10 µs
80
100 µs
1.0 60
1 ms
10 ms 40
0.1 dc
RDS(on) LIMIT
THERMAL LIMIT 20
PACKAGE LIMIT
0.01 0
0.1 1 10 100 1,000 10,000 25 50 75 100 125 150
1.0
D = 0.5
r (t), NORMALIZED EFFECTIVE
0.2
0.1
0.1 P(pk)
t1 READ TIME AT t1
0.01
1.0E–05 1.0E–04 1.0E–03 1.0E–02 1.0E–01 1.0E+00 1.0E+01
t, TIME (s)
di/dt
IS
trr
ta tb
TIME
tp 0.25 IS
IS

MTB3N120E
H1 L1 D1 – D4
1N4007s
90VAC– C1 C4
0.1 L1 0.1 +Vin
600VAC
1 kV 1 kV 470 k
R4
C6 + 1/2 W
H2 100 mF
450 V 470 k
C3 C2 R3 1/2 W
0.0047 0.0047
3 kV 3 kV
EARTH 470 k
R2
GND C5 + 1/2 W
100 mF
450 V 470 k
R1 1/2 W
INPUT GND
Figure 15. The AC Input/Filter Circuit Section
D9 100 mF
MUR430 20 V
T1 +12 V
+ +
100 mF
D8 C11 C12
+Vin MBR370 10 V
+5 V
Vaux R16 + + R20
R9
120 W
82 k, 1/2 W 1 nF C13 C14
100 k C9
10 mF 3 kV R19
1/2 W U2
R8 R7 R6 R5 25 V C15 32.4 k
D10 + MUR130 MOC8102
1.5 nF
Vaux
R11 C10 LL MUR1100 D6
1.3 mF 7.5 k
D7 C17
1.8 k
7 2.2 nF
UC3845BN MTP3N120E C16 R17

R10 D5 U3
27 k 3.3 V R12 10 W Q1 TL431
6 R21
4 2.49 k
R15 R13 GND
1 680 W 1k
C7
2 5 3
220 pF U2 R14
1/2 C8 1.2 W
MOC8102 1000 pF 1/2 W
INPUT GND
Figure 16. The DC/DC Converter Circuit Section

MOTOROLA
 Data Sheet
Designer's


800 VOLTS

D
D2PAK
REV 2

MTB4N80E
OFF CHARACTERISTICS
(VDS = 800 Vdc, VGS = 0 Vdc) — — 10
(ID = 4.0 Adc) — 8.24 12
(ID = 2.0 Adc, TJ = 125°C) — — 10
Vd VGS = 0 Vdc,
Vd
Coss — 187 400
f = 1.0 MHz)

VGS = 10 Vdc
Vdc,
(See Fig
Figure
re 8)
((VDS = 400 Vdc, ID = 4.0 Adc, Q1 — 7.0 —
VGS = 10 Vdc) Q2 — 16.5 —
Q3 — 12 —
— 0.812 1.5
(IS = 4.0 Adc, VGS = 0 Vdc, TJ = 125°C)
— 0.7 —
Fig re 14)
(See Figure
((IS = 4.0 Adc, VGS = 0 Vdc, ta — 100 —
dIS/dt = 100 A/µs) tb — 457 —


MTB4N80E
8 8
TJ = 25°C VDS ≥ 10 V
7 VGS = 10 V 7

6 6
6V
5 5 100°C
5V
4 4
25°C
3 3
2 2
TJ = –55°C
1 4V 1
0 0
0 2 4 6 8 10 12 14 16 18 20 2.0 2.4 2.8 3.2 3.6 4.0 4.4 4.8 5.2 5.6


4.6 2.6
TJ = 25°C
VGS = 10 V 2.5
3.8 TJ = 100°C
2.4
3.0 2.3
2.2
25°C VGS = 10 V
2.2 2.1
2.0 15 V
1.4
– 55°C 1.9
0.6 1.8
1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8
2.2 10000
ID = 2 A TJ = 125°C
1.8
1000 100°C
(NORMALIZED)
1.4
100
1.0
25°C
10
0.6
0.2 1
–50 –25 0 25 50 75 100 125 150 0 100 200 300 400 500 600 700 800


MTB4N80E
2800 10000
Ciss VDS = 0 V VGS = 0 V TJ = 25°C VGS = 0 V TJ = 25°C
2400 Ciss
1000
2000
C, CAPACITANCE (pF)
C, CAPACITANCE (pF)
1600 Ciss
100
Crss Coss
1200
800 10 Crss
Coss
400
Crss
1
0
10 5 0 5 10 15 20 25 10 100 1000

MTB4N80E
10 500 1000

QT VDD = 400 V
ID = 4 A
8 400 VGS = 10 V
VGS TJ = 25°C
t, TIME (ns)
6 Q1 Q2 300
100
4 tf
200
ID = 4 A
TJ = 25°C td(off) tr
2 100
Q3 VDS td(on)
0 0 10
0 6 12 18 24 30 36 1 10 100

4.0
3.6 VGS = 0 V
TJ = 25°C
3.2
2.8
2.4
2.0
1.6
1.2
0.8
0.4
0
0.50 0.54 0.58 0.62 0.66 0.70 0.74 0.78 0.82
SAFE OPERATING AREA
temperature.

MTB4N80E
SAFE OPERATING AREA
100 350
VGS = 20 V ID = 4 A

SINGLE PULSE 300
TC = 25°C

10 10 µs 250
100 µs 200
1.0
1 ms 150
10 ms
dc 100
0.1
RDS(on) LIMIT
THERMAL LIMIT 50
PACKAGE LIMIT
0.01 0
0.1 1.0 10 100 1000 25 50 75 100 125 150
1.0
D = 0.5
0.2
0.1
P(pk)
0.05
PULSE TRAIN SHOWN
0.01 DUTY CYCLE, D = t1/t2
SINGLE PULSE
0.01
1.0E–05 1.0E–04 1.0E–03 1.0E–02 1.0E–01 1.0E+00 1.0E+01
t, TIME (s)
3
RθJA = 50°C/W
2.5
2.0
di/dt
IS 1.5
trr
1
ta tb
TIME 0.5
tp 0.25 IS
0
IS 25 50 75 100 125 150

MOTOROLA
 Data Sheet
Designer's


600 VOLTS


(VDD = 100 Vdc, VGS = 10 Vdc, Peak IL = 9.0 Apk, L = 10 mH, RG = 25 Ω) 405
REV 1

MTB6N60E
OFF CHARACTERISTICS
(VDS = 600 Vdc, VGS = 0 Vdc) — — 10
Static Drain–to–Source On–Resistance (VGS = 10 Vdc, ID = 3.0 Adc) RDS(on) — 0.94 1.2 Ohms
(VGS = 10 Vdc, ID = 6.0 Adc) — 6.0 8.6
(VGS = 10 Vdc, ID = 3.0 Adc, TJ = 125°C) — — 7.6
Vd VGS = 0 Vdc,
Vd
Coss — 158 217
f = 1.0 MHz)

VGS = 10 Vdc
Vdc,
((VDS = 300 Vdc, ID = 6.0 Adc, Q1 — 8.1 —

VGS = 10 Vdc) Q2 — 14.1 —
Q3 — 15.8 —
— 0.83 1.5
(IS = 6.0 Adc, VGS = 0 Vdc, TJ = 125°C)
— 0.72 —
((IS = 6.0 Adc, VGS = 0 Vdc, ta — 166 —

dIS/dt = 100 A/µs) tb — 100 —
Internal Source Inductance LS — nH
(Measured from the source lead 0.25″ from package to source bond pad) — 7.5

MTB6N60E
12 12
TJ = 25°C VGS = 10 V VDS ≥ 10 V
6V
10 10

7V
8V
8 8
6 6
5V
4 4
100°C
2 2 25°C
4V TJ = – 55°C
0 0
0 2 4 6 8 10 12 14 16 18 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0


2.5 1.4
VGS = 10 V TJ = 25°C
1.3
2.0
TJ = 100°C
1.2
1.5
1.1 VGS = 10 V
25°C
1.0
1.0
– 55°C
15 V
0.5
0.9
0 0.8
0 2 4 6 8 10 12 0 2 4 6 8 10 12
2.5 10000
ID = 3 A
2 TJ = 125°C
1000
(NORMALIZED)
100°C
1.5
100
1
25°C
10
0.5
0 1
– 50 – 25 0 25 50 75 100 125 150 0 100 200 300 400 500 600


MTB6N60E
3200 10000
VDS = 0 V VGS = 0 V TJ = 25°C TJ = 25°C
VGS = 0 V
Ciss Ciss
2400 1000
C, CAPACITANCE (pF)
C, CAPACITANCE (pF)
Ciss Coss
1600 Crss 100
Crss
800 10
Coss
Crss
0 1
10 5 0 5 10 15 20 25 10 100 1000
VGS VDS

MTB6N60E
12 300 100

VDD = 300 V

QT
ID = 6 A
10 VGS = 10 V
TJ = 25°C
8 VGS 200
t, TIME (ns)
Q1 Q2 10 td(off)
6
tf
tr
4 100 td(on)
ID = 6 A
TJ = 25°C
2
Q3 VDS
0 0 1
0 6 12 18 24 30 36 1 10 100

6
VGS = 0 V
TJ = 25°C
5
0
0.50 0.55 0.60 0.65 0.70 0.75 0.80 0.85
SAFE OPERATING AREA
temperature.

MTB6N60E
SAFE OPERATING AREA
100 450
EAS, SINGLE PULSE DRAINN–TO–SOURCE

VGS = 20 V
SINGLE PULSE 400 ID = 6 A
TC = 25°C 350

10 µs
10 300
250
100 µs
1 ms 200
1.0 10 ms 150
100
RDS(on) LIMIT
THERMAL LIMIT 50
PACKAGE LIMIT dc
0.1 0
0.1 1 10 100 1000 25 50 75 100 125 150
1
D = 0.5
0.2
0.1
0.1 P(pk)
0.05
PULSE TRAIN SHOWN
t1 READ TIME AT t1
0.01
0.00001 0.0001 0.001 0.01 0.1 1 10
t, TIME (SECONDS)
3
RθJA = 50°C/W
2.5
2.0
di/dt
IS 1.5
trr
1
ta tb
TIME 0.5
tp 0.25 IS
0
IS 25 50 75 100 125 150

MOTOROLA
Advance Information MTB8N50E


500 VOLTS

D2PAK
Fast Recovery Diode
(VDD = 50 Vdc, VGS = 10 Vdc, IL = 8.0 Apk, L = 15.9 mH, RG = 25 Ω)

MTB8N50E
OFF CHARACTERISTICS
(VDS = 500 Vdc, VGS = 0 Vdc) — — 250
Static Drain–Source On–Resistance (VGS = 10 Vdc, ID = 4.0 Adc) RDS(on) — 0.6 0.8 Ohms
(ID = 8.0 Adc) — — 7.2
(ID = 4.0 Adc, TJ = 125°C) — — 6.4
Vd VGS = 0 Vdc,
Vd
Coss — 176 264
f = 1.0 MHz)

VGS = 10 Vdc
Vdc,
((VDS = 400 Vdc, ID = 8.0 Adc, Q1 — 12 —

VGS = 10 Vdc) Q2 — 45 —
Q3 — 35 —
— 1.1 2.0
(IS = 8.0 Adc, VGS = 0 Vdc, TJ = 125°C)
— 1.0 —
((IS = 8.0 Adc, VGS = 0 Vdc, ta — 280 —

dIS/dt = 100 A/µs) tb — 140 —

MOTOROLA
 Data Sheet
Designer's


250 VOLTS
TMOS E–FET is designed to withstand high energy in the 
power supplies, converters and PWM motor controls, these D
• Avalanche Energy Specified CASE 418B–02, Style 2
S
— Single Pulse (tp ≤ 10 µs) IDM 32 Apk
(VDD = 80 Vdc, VGS = 10 Vdc, Peak IL = 9.0 Apk, L = 3.0 mH, RG = 25 Ω) 122

MTB9N25E
OFF CHARACTERISTICS
(VGS = 0 Vdc, ID = 250 µAdc) 250 — —
(VDS = 250 Vdc, VGS = 0 Vdc) — — 10
(VGS = 10 Vdc, ID = 9.0 Adc) — 3.5 5.4
(VGS = 10 Vdc, ID = 4.5 Adc, TJ = 125°C) — — 4.7
Vd VGS = 0 Vdc,
Vd
Coss — 144 200
f = 1.0 MHz)

VGS = 10 Vdc
Vdc,
(S Fi
(See Figure 8)
((VDS = 200 Vdc, ID = 9.0 Adc, Q1 — 4.8 —
VGS = 10 Vdc) Q2 — 12.7 —
Q3 — 9.2 —
(IS = 9.0 Adc, VGS = 0 Vdc )
— 0.9 1.5
(IS = 9.0 Adc, VGS = 0 Vdc , TJ = 125°C)
— 0.81 —
(S Figure
(See Fi 14)
((IS = 9.0 Adc, VGS = 0 Vdc, ta — 126 —
dlS/dt = 100 A/µs) tb — 65 —


MTB9N25E
18 18
TJ = 25°C VGS = 10 V 8V VDS ≥ 10 V TJ = –55°C
15 9V 15
7V

12 12 25°C
100°C
9 9
6V
6 6
3 5V 3
0 0
0 2 4 6 8 10 12 2 3 4 5 6 7 8


1.2 0.6
VGS = 10 V TJ = 25°C
1.0
0.8 0.5
TJ = 100°C
0.6
VGS = 10 V
25°C
0.4 0.4
15 V
0.2 – 55°C
0 0.3
0 3 6 9 12 15 18 0 3 6 9 12 15 18
2.5 1000
ID = 4.5 A TJ = 125°C
2.0
100
100°C
(NORMALIZED)
1.5
10
1.0 25°C
1
0.5
0 0.1
–50 –25 0 25 50 75 100 125 150 0 50 100 150 200 250


MTB9N25E
2000 VDS = 0 V VGS = 0 V TJ = 25°C

Ciss
1600
C, CAPACITANCE (pF)
1200 Ciss
Crss
800
400 Coss
Crss
0
10 5 0 5 10 15 20 25
VGS VDS

MTB9N25E
16 240 1000

VDD = 250 V

ID = 9 A
VGS = 10 V
12 180 TJ = 25°C
QT
100
t, TIME (ns)
8 VGS 120 tr
td(off) tf
Q1 Q2
ID = 9 A 10 td(on)
4 TJ = 25°C 60
Q3
VDS
0 0 1
0 6 12 18 24 30 1 10 100

9.0
VGS = 0 V
TJ = 25°C
7.5
6.0
4.5
3.0
1.5
0
0.5 0.55 0.6 0.65 0.7 0.75 0.8 0.85 0.9
SAFE OPERATING AREA
temperature.

MTB9N25E
SAFE OPERATING AREA
100 125
VGS = 20 V

SINGLE PULSE ID = 9 A
TC = 25°C
100

10 10 µs
75
100 µs
50
1
1 ms
RDS(on) LIMIT 10 ms 25
THERMAL LIMIT dc
PACKAGE LIMIT
0.1 0
0.1 1.0 10 100 1000 25 50 75 100 125 150
1.0
D = 0.5
0.2
0.1
0.1
0.05 P(pk)
0.01
0.00001 0.0001 0.001 0.01 0.1 1.0 10
t, TIME (s)
3
RθJA = 50°C/W
2.5
2.0
di/dt
IS 1.5
trr
1
ta tb
TIME 0.5
tp 0.25 IS
0
IS 25 50 75 100 125 150

MOTOROLA
 Data Sheet
Designer's
MTB10N40E

N–Channel Enhancement–Mode Silicon Gate 10 AMPERES
400 VOLTS
RDS(on) = 0.55 OHM
MOSFET uses an advanced termination scheme to provide 
D2PAK
Fast Recovery Diode

Drain Current — Continuous ID 10 Amps
(VDD = 25 Vdc, VGS = 10 Vpk, IL = 10 Apk, L = 10 mH, RG = 25 Ω)

MTB10N40E
OFF CHARACTERISTICS
(VDS = 400 Vdc, VGS = 0 Vdc) — — 0.1
Gate–Body Leakage Current–Forward IGSSF — — 100 nAdc
(Vgsf = 20 Vdc, VDS = 0)
Gate–Body Leakage Current–Reverse IGSSR — — 100 nAdc
(Vgsr = 20 Vdc, VDS = 0)
(ID = 10 Adc) — 5.61 6.6
(ID = 5.0 Adc, TJ = 125°C) — — 5.5
Vd VGS = 0 Vdc,
Vd
Coss — 230 325
f = 1.0 MHz)
Rise Time (VDD = 200 Vdc, ID = 10 Adc, tr — 37 75
VGS = 10 Vdc
Vdc,
Turn–Off Delay Time RG = 10 Ω) td(off) — 75 150
(S Fi
(See Figure 8)
((VDS = 320 Vdc, ID = 10 Adc, Q1 — 10 —
VGS = 10 Vdc) Q2 — 23 —
Q3 — — —

— 0.9 2.0
(IS = 10 Adc, VGS = 0 Vdc, TJ = 125°C)
— — —
(See Figure 14) (IS = 10 Adc, VGS = 0 Vdc,
dIS/dt = 100 A/µs)
Reverse Recovery Stored Charge QRR — 3000 — nC

(Measured from the tab to center of die) — 3.5 —

MTB10N40E
20 25
TJ = 25°C
10 V VDS ≥ 10 V
7V

16 20
12 15
8 VGS = 6 V 10
TJ = 25°C
4 5 – 55°C
100°C
5V
0 0
0 4 8 12 16 20 0 1 2 3 4 5 6 7 8 9


1.5 0.55
VGS = 10 V TJ = 25°C
100°C
0.5
1 0.45
TJ = 25°C 0.4 VGS = 10 V
0.5 0.35 15 V
– 55°C
0.3
0 0.25
0 5 10 15 20 25 30 0 5 10 15 20
3 100
ID = 5 A 40 TJ = 125°C
20
2 10
(NORMALIZED)
100°C
4
2
1 1
25°C
0.4
0.2
0 0.1
–50 –25 0 25 50 75 100 125 150 100 150 200 250 300 350 400


MTB10N40E
3500
TJ = 25°C VGS = 0 V
3000
2500
C, CAPACITANCE (pF)
2000 Crss
Ciss
1500
1000
500 VDS = 0 V Coss
0
10 5 0 5 10 15 20 25
VGS VDS

MTB10N40E
16 10000

TJ = 25°C VDS = 100 V VDD = 200 V
4000 ID ≈ 10 A
ID = 10 A
2000 VGS = 10 V td(off)
12 250 V
TJ = 25°C
1000 tf
t, TIME (ns)
320 V tr
400 td(on)
8
200
100
4
40
20
0 10
0 20 40 60 80 1 10 100 1000
Qg, TOTAL CHARGE (nC) RG, GATE RESISTANCE (OHMS)


10
9 VGS = 0 V
8 TJ = 25°C
7
6
5
4
3
2
1
0 0.2 0.4 0.6 0.8 1 1.2

SAFE OPERATING AREA
temperature.

MTB10N40E
SAFE OPERATING AREA
100 600
VGS = 20 V

40 ID = 10 A
SINGLE PULSE
10 µs
20 TC = 25°C

450
10 100 µs
4
1 ms 300
2
1 10 ms
RDS(on) LIMIT 150
0.4 THERMAL LIMIT dc
0.2 PACKAGE LIMIT
0.1 0
1 10 100 1000 25 50 75 100 125 150
1
0.7 D = 0.5
0.5
r(t) , NORMALIZED EFFECTIVE
0.3
0.2
0.2
0.1
P(pk) RθJC = 1°C/W MAX
0.07 0.05
t1 D CURVES APPLY FOR POWER
0.05 t2
0.03 DUTY CYCLE, D = t1/t2 READ TIME AT t1
0.02 TJ(pk) – TC = P(pk) RθJC(t)
0.01 SINGLE PULSE
0.01
0.01 0.02 0.05 0.1 0.2 0.5 1 2 5 10 20 50 100 200 500 1000
t,TIME (ms)
3
RθJA = 50°C/W

2.0
di/dt
IS 1.5
trr
1
ta tb
TIME
0.5
tp 0.25 IS
0
IS 25 50 75 100 125 150

MOTOROLA
 Data Sheet
MTB15N06V
Designer's
TMOS V
Power Field Effect Transistor
60 VOLTS
TMOS V is a new technology designed to achieve an on–resistance RDS(on) = 0.12 OHM
area product about one–half that of standard MOSFETs. This new
technology more than doubles the present cell density of our 50
and 60 volt TMOS devices. Just as with our TMOS E–FET designs,
TMOS V is designed to withstand high energy in the avalanche and
commutation modes. Designed for low voltage, high speed TM
switching applications in power supplies, converters and power
motor controls, these devices are particularly well suited for bridge
D
circuits where diode speed and commutating safe operating areas
are critical and offer additional safety margin against unexpected
voltage transients.
New Features of TMOS V
G
MOSFETs with New Low Voltage, Low RDS(on) Technology CASE 418B–02, Style 2
• Faster Switching than E–FET Predecessors S D2PAK
Features Common to TMOS V and TMOS E–FETs
• Surface Mount Package Available in 16 mm 13–inch/2500 Unit Tape & Reel,
Add T4 Suffix to Part Number

Drain Current — Continuous @ 25°C ID 15 Adc
(VDD = 25 Vdc, VGS = 10 Vdc, IL = 15 Apk, L = 1.0 mH, RG = 25 Ω)
REV 2

MTB15N06V
OFF CHARACTERISTICS
(VDS = 60 Vdc, VGS = 0 Vdc) — — 10
(ID = 15 Adc) — 2.0 2.2
(ID = 7.5 Adc, TJ = 150°C) — — 1.9
Vd VGS = 0 Vdc,
Vd
Coss — 148 200
f = 1.0 MHz)

VGS = 10 Vdc
Vdc,
(See Fig
Figure
re 8)
((VDS = 48 Vdc, ID = 15 Adc, Q1 — 2.8 —
VGS = 10 Vdc) Q2 — 6.4 —
Q3 — 6.1 —
— 1.05 1.6
(IS = 15 Adc, VGS = 0 Vdc, TJ = 150°C)
— 0.9 —
(See Figure
Fig re 14)
((IS = 15 Adc, VGS = 0 Vdc, ta — 46 —
dIS/dt = 100 A/µs) tb — 13.3 —


MTB15N06V
30 30
TJ = 25°C VGS = 10 V VDS ≥ 10 V
9V 8V
25 25

7V 100°C
20 20
25°C
15 15 TJ = – 55°C
6V
10 10
5V
5 5
0 0
0 1 2 3 4 5 6 7 2 4 6 8 10
R DS(on) , DRAIN–TO–SOURCE RESISTANCE (OHMS)

0.2 0.13
VGS = 10 V TJ = 25°C
0.11
0.14 TJ = 100°C
0.09 VGS = 10 V
25°C
0.08
15 V
0.07
– 55°C
(o )
0.02 0.05
0 5 10 15 20 25 30 0 5 10 15 20 25 30
2 100
ID = 7.5 A
1.6
(NORMALIZED)
1.2 TJ = 125°C
0.8
0.4 10
– 50 – 25 0 25 50 75 100 125 150 175 0 10 20 30 40 50 60


MTB15N06V
The lengths of various switching intervals (∆t) are determined culating td(on) and is read at a voltage corresponding to the
by how fast the FET input capacitance can be charged by on–state when calculating td(off).
current from the generator.
The published capacitance data is difficult to use for calculat- At high switching speeds, parasitic circuit elements
ing rise and fall because drain–gate capacitance varies complicate the analysis. The inductance of the MOSFET
greatly with applied voltage. Accordingly, gate charge data is source lead, inside the package and in the circuit wiring
used. In most cases, a satisfactory estimate of average input which is common to both the drain and gate current paths,
current (IG(AV)) can be made from a rudimentary analysis of produces a voltage at the source which reduces the gate
the drive circuit so that drive current. The voltage is determined by Ldi/dt, but since
di/dt is a function of drain current, the mathematical solution
t = Q/IG(AV) is complex. The MOSFET output capacitance also compli-
During the rise and fall time interval when switching a resis- cates the mathematics. And finally, MOSFETs have finite
tive load, VGS remains virtually constant at a level known as internal gate resistance which effectively adds to the
the plateau voltage, VSGP. Therefore, rise and fall times may resistance of the driving source, but the internal resistance is
be approximated by the following: difficult to measure and, consequently, is not specified.
tance (Figure 9) shows how typical switching performance is
tf = Q2 x RG/VGSP affected by the parasitic circuit elements. If the parasitics
where were not present, the slope of the curves would maintain a
used to obtain the data is constructed to minimize common
RG = the gate drive resistance inductance in the drain and gate circuit loops and is believed
and Q2 and VGSP are read from the gate charge curve. readily achievable with board mounted components. Most
ues from the capacitance curves in a standard equation for snubbed inductive load. Power MOSFETs may be safely
voltage change in an RC network. The equations are: operated into an inductive load; however, snubbing reduces
switching losses.
1500
VDS = 0 V VGS = 0 V TJ = 25°C
Ciss
1200
C, CAPACITANCE (pF)
900
Crss
600 Ciss
300 Coss
Crss
0
10 5 0 5 10 15 20 25
VGS VDS

MTB15N06V
12 60 1000

VDD = 30 V
QT ID = 15 A
10 50
VGS = 10 V
VGS TJ = 25°C
8 40 100
t, TIME (ns)
Q1 Q2 tr
6 30 tf
td(off)
ID = 15 A
4 TJ = 25°C 20 10 td(on)
2 10
Q3 VDS
0 0 1
0 3 6 9 12 15 1 10 100

15
VGS = 0 V
TJ = 25°C
12
0
0.5 0.7 0.9 1.1 1.3 1.5
SAFE OPERATING AREA
The Forward Biased Safe Operating Area curves define reliable operation, the stored energy from circuit inductance
the maximum simultaneous drain–to–source voltage and dissipated in the transistor while in avalanche must be less
drain current that a transistor can handle safely when it is than the rated limit and adjusted for operating conditions
forward biased. Curves are based upon maximum peak differing from those specified. Although industry practice is to
junction temperature and a case temperature (TC) of 25°C. rate in terms of energy, avalanche energy capability is not a
Peak repetitive pulsed power limits are determined by using constant. The energy rating decreases non–linearly with an
the thermal response data in conjunction with the procedures increase of peak current in avalanche and peak junction
temperature.
Although many E–FETs can withstand the stress of
Switching between the off–state and the on–state may
traverse any load line provided neither rated peak current drain–to–source avalanche at currents up to rated pulsed
(IDM) nor rated voltage (VDSS) is exceeded and the transition current (I DM ), the energy rating is specified at rated
time (tr,tf) do not exceed 10 µs. In addition the total power continuous current (ID), in accordance with industry custom.
averaged over a complete switching cycle must not exceed The energy rating must be derated for temperature as shown
(TJ(MAX) – TC)/(RθJC). in the accompanying graph (Figure 12). Maximum energy at
A Power MOSFET designated E–FET can be safely used currents below rated continuous ID can safely be assumed to
in switching circuits with unclamped inductive loads. For equal the values indicated.

MTB15N06V
SAFE OPERATING AREA
100 120
VGS = 10 V

TC = 25°C 100
10 µs

10 80
100 µs
60
1 ms
10 ms
1.0 dc 40
RDS(on) LIMIT
20
THERMAL LIMIT
PACKAGE LIMIT
0.1 0
0.1 1.0 10 100 25 50 75 100 125 150 175
1
D = 0.5
0.2
0.1
0.05 P(pk)
PULSE TRAIN SHOWN
0.01
1.0E–05 1.0E–04 1.0E–03 1.0E–02 1.0E–01 1.0E+00 1.0E+01
t, TIME (s)
3
RθJA = 50°C/W
2.0
di/dt
IS 1.5
trr
1
ta tb
TIME 0.5
tp 0.25 IS
0
IS 25 50 75 100 125 150 175

MOTOROLA
 Data Sheet
Designer's
MTB16N25E

250 VOLTS

• Source–to–Drain Diode Recovery Time Comparable to a G CASE 418B–02, Style 2
S
• Available in 24 mm 13–inch/800 Unit Tape & Reel, Add –T4

Drain Current — Continuous @ TC = 100°C ID 10
(VDD = 80 Vdc, VGS = 10 Vdc, IL = 16 Apk, L = 3.0 mH, RG = 25 Ω )

MTB16N25E
OFF CHARACTERISTICS
(VDS = 250 Vdc, VGS = 0 Vdc) — — 10
(ID = 16 Adc) — 3.6 4.8
(ID = 8.0 Adc, TJ = 125°C) — — 4.2
Vd VGS = 0 Vdc,
Vd
Coss — 281 390
f = 1.0 MHz)

VGS = 10 Vdc
Vdc,
(See Fig
Figure
re 8)
((VDS = 200 Vdc, ID = 16 Adc, Q1 — 9.3 —
VGS = 10 Vdc) Q2 — 27.5 —
Q3 — 17.1 —
— 0.915 1.5
(IS = 16 Adc, VGS = 0 Vdc, TJ = 125°C)
— 1.39 —
(See Figure
Fig re 14)
((IS = 16 Adc, VGS = 0 Vdc, ta — 170 —
dIS/dt = 100 A/µs) tb — 64 —


MTB16N25E
32 32
TJ = 25°C VGS = 10 V VDS ≥ 10 V
8V

7V
24 24 25°C
16 6V 16
8 8 100°C
5V
TJ = –55°C
0 0
0 1 2 3 4 5 6 7 8 2 3 4 5 6 7 8


0.6 0.26
VGS = 10 V TJ = 25°C
0.5
0.22
0.4 TJ = 100°C VGS = 10 V
0.3 0.18
15 V
0.2 25°C
0.14
0.1 – 55°C
0 0.1
0 5 10 15 20 25 30 35 0 8 16 24 32 40
3.0 1000
ID = 8 A TJ = 125°C
2.5
2.0 100
(NORMALIZED)
100°C
1.5
1.0 10
25°C
0.5
0 1
–50 –25 0 25 50 75 100 125 150 0 50 100 150 200 250 300


MTB16N25E
switching losses.
5000 VDS = 0 V VGS = 0 V

TJ = 25°C
4000
C, CAPACITANCE (pF)
Ciss
3000
2000 Ciss
Crss
1000
Coss
Crss
0
10 5 0 5 10 15 20 25
VGS VDS

MTB16N25E
12 200 1000

QT VDD = 250 V

ID = 16 A
VGS VGS = 10 V
9 150 TJ = 25°C
100
t, TIME (ns)
Q1 Q2 tr
td(off) tf
6 100
td(on)
ID = 16 A 10
3 TJ = 25°C 50
Q3
VDS
0 0 1
0 10 20 30 40 50 60 1 10 100

16
VGS = 0 V
TJ = 25°C
12
0
0.5 0.55 0.6 0.65 0.7 0.75 0.8 0.85 0.9 0.95
SAFE OPERATING AREA
temperature.

MTB16N25E
SAFE OPERATING AREA
100 400
VGS = 20 V
ID = 16 A

SINGLE PULSE
10 µs
TC = 25°C

300
10 100 µs
200
1 ms
1 10 ms
dc 100
RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT
0.1 0
0.1 1.0 10 100 1000 25 50 75 100 125 150
1.0
D = 0.5
0.2
0.1
0.1
0.05 P(pk)
PULSE TRAIN SHOWN
0.01
0.00001 0.0001 0.001 0.01 0.1 1.0 10
t, TIME (s)
3
RθJA = 50°C/W
Collector/Drain Pad Size 9 450 mils x 350 mils
2.0
di/dt
IS 1.5
trr
1
ta tb
TIME 0.5
tp 0.25 IS
0
IS 25 50 75 100 125 150

MOTOROLA
 Data Sheet
Designer's
MTB20N20E

200 VOLTS

D
G


Drain Current — Continuous @ 100°C ID 12
REV 2

MTB20N20E
OFF CHARACTERISTICS
(VDS = 200 Vdc, VGS = 0 Vdc) — — 10
Static Drain–Source On–Resistance (VGS = 10 Vdc, ID = 10 Adc) RDS(on) — 0.12 0.16 Ohm
(ID = 20 Adc) — — 3.84
(ID = 10 Adc, TJ = 125°C) — — 3.36
Forward Transconductance (VDS = 13 Vdc, ID = 10 Adc) gFS 8.0 11 — mhos
Vd VGS = 0 Vdc,
Vd
Coss — 378 535
f = 1.0 MHz)

VGS = 10 Vdc
Vdc,
(See Figure 8)
(VDS = 160 Vdc, ID = 20 Adc, Q1 — 12 —
VGS = 10 Vdc)
Q2 — 24 —
Q3 — 22 —

— 1.0 1.35
(IS = 20 Adc, VGS = 0 Vdc, TJ = 125°C)
— 0.82 —
(See Figure
Fig re 14)
((IS = 20 Adc, VGS = 0 Vdc, ta — 136 —
dIS/dt = 100 A/µs) tb — 103 —



MTB20N20E
40 40
TJ = 25°C 8V VDS ≥ 10 V
VGS = 10 V 35 TJ = –55°C
9V

7V 25°C
30 30
25
100°C
20 20
6V
15
10 10
5V
5
0 0
0 1 2 3 4 5 6 7 8 9 10 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5


0.35 0.17
VGS = 10 V TJ = 25°C
0.30 0.16
0.15
0.25 TJ = 100°C
0.14
VGS = 10 V
0.20
0.13
0.15 25°C
0.12
15 V
0.10 0.11
– 55°C
0.05 0.10
0 4 8 12 16 20 24 28 32 36 40 0 4 8 12 16 20 24 28 32 36 40
2.4 10000
ID = 10 A
2.0 TJ = 125°C
1000
100°C
(NORMALIZED)
1.6
100 25°C
1.2
10
0.8
0.4 1
–50 –25 0 25 50 75 100 125 150 0 50 100 150 200


MTB20N20E
5000
4000
C, CAPACITANCE (pF)
3000
Crss
Ciss
2000
1000 Coss
Crss
0
10 5 0 5 10 15 20 25
VGS VDS

MTB20N20E
12 180 1000

QT VDD = 30 V
10 150 ID = 20 A
VGS VGS = 10 V
Q1 Q2
TJ = 25°C
8 120
t, TIME (ns)
6 90 100
tr
4 ID = 20 A 60 tf
TJ = 25°C td(off)
2 30
Q3 VDS td(on)
0 0 10
0 10 20 30 40 50 60 1 10 100

20
VGS = 0 V
TJ = 25°C
16
12
0
0.5 0.55 0.6 0.65 0.7 0.75 0.8 0.85 0.9 0.95 1.0
SAFE OPERATING AREA
temperature.

MTB20N20E
SAFE OPERATING AREA
100 600
VGS = 20 V

ID = 20 A
SINGLE PULSE 10 µs
500
TC = 25°C

10
100 µs 400
1 ms
1.0 300
10 ms
dc
200
0.1 RDS(on) LIMIT
THERMAL LIMIT
100
PACKAGE LIMIT
0.01 0
0.1 1.0 10 100 1000 25 50 75 100 125 150
1.0
D = 0.5
0.2
0.1
0.1 P(pk)
0.05
PULSE TRAIN SHOWN
SINGLE PULSE
0.01
1.0E–05 1.0E–04 1.0E–03 1.0E–02 1.0E–01 1.0E+00 1.0E+01
t, TIME (ms)
3.0 RθJA = 50°C/W

2.0
di/dt
IS 1.5
trr 1.0
ta tb
TIME 0.5
tp 0.25 IS
0
IS 25 50 75 100 125 150

MOTOROLA
 Data Sheet
Designer's
TMOS V MTB23P06V

P–Channel Enhancement–Mode Silicon Gate 23 AMPERES
60 VOLTS
TMOS V is a new technology designed to achieve an on–resis- RDS(on) = 0.120 OHM
tance area product about one–half that of standard MOSFETs. This
new technology more than doubles the present cell density of our
TM
avalanche and commutation modes. Designed for low voltage, high
areas are critical and offer additional safety margin against D

• On–resistance Area Product about One–half that of Standard CASE 418B–02, Style 2
MOSFETs with New Low Voltage, Low RDS(on) Technology G D2PAK
• Faster Switching than E–FET Predecessors
S
Gate–to–Source Voltage — Non–repetitive (tp ≤ 10 ms) VGSM ± 25 Vpk
Total Power Dissipation @ TA = 25°C (1) 3.0
Single Pulse Drain–to–Source Avalanche Energy — STARTING TJ = 25°C EAS 794 mJ
(VDD = 25 Vdc, VGS = 10 Vdc, PEAK IL = 23 Apk, L = 3.0 mH, RG = 25 Ω)
Maximum Lead Temperature for Soldering Purposes, 1/8″ from Case for 10 seconds TL 260 °C
REV 1

MTB23P06V
OFF CHARACTERISTICS
(VDS = 60 Vdc, VGS = 0 Vdc) — — 10
Drain–Source On–Voltage VDS(on) Vdc
(VGS = 10 Vdc, ID = 23 Adc) — 2.1 3.3
(VGS = 10 Vdc, ID = 11.5 Adc, TJ = 150°C) — — 3.2
(VDS = 10.9 Vdc, ID = 11.5 Adc) 5.0 11.5 —
Vd VGS = 0 Vdc,
Vd
Coss — 380 530
f = 1.0 MHz)
Rise Time (VDD = 30 Vdc, ID = 23 Adc, tr — 98.3 200
VGS = 10 Vdc
Vdc,
(See Fig
Figure
re 8)
((VDS = 48 Vdc, ID = 23 Adc, Q1 — 7.0 —
VGS = 10 Vdc) Q2 — 18 —
Q3 — 14 —

Forward On–Voltage VSD Vdc
— 2.2 3.5
(IS = 23 Adc, VGS = 0 Vdc, TJ = 150°C)
— 1.8 —
((IS = 23 Adc, VGS = 0 Vdc, ta — 100 —

dIS/dt = 100 A/µs) tb — 41 —

(Measured from contact screw on tab to center of die) — 3.5 —
(Measured from the drain lead 0.25″ from package to center of die) 4.5

MTB23P06V
50 40
TJ = 25°C VGS = 10V VDS ≥ 10 V TJ = –55°C
8V
35

40 25°C
9V 30
7V 100°C
30 25
20
6V
20 15
10
10 5V
5
4V
0 0
0 2 4 6 8 10 2 3 4 5 6 7 8


0.16 0.12
VGS = 10 V TJ = 25°C
TJ = 100°C 0.115
0.14
0.12 0.11
25°C 0.105
0.1 VGS = 10 V
0.1
0.08
– 55°C 0.095
0.06 15 V
0.09
0.04 0.085
0.02 0.08
0 5 10 15 20 25 30 35 40 45 0 5 10 15 20 25 30 35 40 45 50
1.8 100
VGS = 0 V
1.6 VGS = 10 V
ID = 11.5 A
1.4
1.2
(NORMALIZED)
1 TJ = 125°C
10
0.8
0.6
0.4
0.2
0 1
–50 –25 0 25 50 75 100 125 150 175 0 10 20 30 40 50 60


MTB23P06V
4000
VDS = 0 V VGS = 0 V TJ = 25°C
Ciss
3000
C, CAPACITANCE (pF)
Crss
2000
Ciss
1000
Coss
Crss
0
10 5 0 5 10 15 20 25
VGS VDS

MTB23P06V
10 30 1000

QT TJ = 25°C
9 27
ID = 23 A
8 Q2 24 VDD = 30 V
Q1
7 VGS VGS = 10 V
21 100 tr
t, TIME (ns)
6 18 tf
5 15 td(off)
4 12 td(on)
10
3 9
2 TJ = 25°C 6
1 Q3 VDS ID = 23 A 3
0 0 1
0 5 10 15 20 25 30 35 40 1 10 100

25
TJ = 25°C
VGS = 0 V
20
15
10
0
0 0.25 0.5 0.75 1 1.25 1.5 1.75 2 2.25 2.5
SAFE OPERATING AREA
tion temperature and a case temperature (TC) of 25°C. Peak terms of energy, avalanche energy capability is not a
perature.

MTB23P06V
SAFE OPERATING AREA
100 800
VGS = 20 V ID = 23 A

SINGLE PULSE 700
TC = 25°C

600
10 100 µs
500
1 ms
10 ms 400
dc
300
1
200
RDS(on) LIMIT
THERMAL LIMIT 100
PACKAGE LIMIT
0.1 0
0.1 1 10 100 25 50 75 100 125 150 175
1.00
D = 0.5
0.2
0.1
0.10 P(pk)
t1 READ TIME AT t1
0.01
1.0E–05 1.0E–04 1.0E–03 1.0E–02 1.0E–01 1.0E+00 1.0E+01
t, TIME (s)
3
RθJA = 50°C/W
2.0
di/dt
IS 1.5
trr
1
ta tb
TIME 0.5
tp 0.25 IS
0
IS 25 50 75 100 125 150 175

MOTOROLA
 Data Sheet
Designer's
TMOS V MTB30N06VL

60 VOLTS
D
voltage transients.
G
• Static Parameters are the Same for both TMOS V and
TMOS E–FET
• Surface Mount Package Available in 16 mm 13–inch/2500 Unit
Tape & Reel, Add T4 Suffix to Part Number

REV 3

MTB30N06VL
OFF CHARACTERISTICS
(VDS = 60 Vdc, VGS = 0 Vdc) — — 10
Static Drain–to–Source On–Resistance (VGS = 5 Vdc, ID = 15 Adc) RDS(on) — 0.033 0.05 Ohms
(VGS = 5 Vdc, ID = 30 Adc) — 1.1 1.8
(VGS = 5 Vdc, ID = 15 Adc, TJ = 150°C) — — 1.73
Forward Transconductance (VDS = 6.25 Vdc, ID = 15 Adc) gFS 13 21 — Mhos
Vd VGS = 0 Vdc,
Vd
Coss — 360 500
f = 1.0 MHz)

VGS = 5 Vdc
Vdc,
(See Fig
Figure
re 8)
((VDS = 48 Vdc, ID = 30 Adc, Q1 — 5 —
VGS = 5 Vdc) Q2 — 17 —
Q3 — 15 —
— 0.98 1.6
(IS = 30 Adc, VGS = 0 Vdc, TJ = 150°C)
— 0.89 —
((IS = 30 Adc, VGS = 0 Vdc, ta — 49 —

dIS/dt = 100 A/µs) tb — 37 —


MTB30N06VL
60 60
VGS = 10 V TJ = 25°C TJ = –55°C
VDS ≥ 10 V
8V
50 50

6V 25°C
5V 100°C
40 40
30 4V 30
20 20
3V
10 10
0 0
0 1 2 3 4 5 6 7 8 9 10 0 1 2 3 4 5 6


0.08 0.06
VGS = 10 V TJ = 25°C
0.07
0.05
0.06 TJ = 100°C
0.04 VGS = 5 V
0.05
10 V
0.04 25°C 0.03
0.03
0.02
0.02
– 55°C
0.01
0.01
0 0
0 10 20 30 40 50 60 0 10 20 30 40 50 60
2 1000
1.8 VGS = 5 V VGS = 0 V

ID = 15 A
1.6 TJ = 125°C
1.4
100
(NORMALIZED)
1.2
1 100°C
0.8
10
0.6
0.4
0.2
0 1
– 50 – 25 0 25 50 75 100 125 150 175 0 10 20 30 40 50 60


MTB30N06VL
switching losses.
5000
VDS = 0 V VGS = 0 V TJ = 25°C
4500 C
iss
4000
C, CAPACITANCE (pF)
3500
Crss
3000
2500
2000
1500 Ciss
1000
500 Coss
Crss
0
10 5 0 5 10 15 20 25
VGS VDS

MTB30N06VL
5 30 1000

TJ = 25°C
4.5 27
ID = 30 A
4 QT 24 VDD = 30 V tr
VGS = 5 V
3.5 VGS 21
100 tf
t, TIME (ns)
3 Q1 Q2 18
td(off)
2.5 15
2 12 td(on)
10
1.5 TJ = 25°C 9
Q3
1 ID = 30 A 6
0.5 3
VDS
0 0 1
0 5 10 15 20 25 1 10 100

30
TJ = 25°C
VGS = 0 V
25
20
15
10
0
0.5 0.55 0.6 0.65 0.7 0.75 0.8 0.85 0.9 0.95 1
SAFE OPERATING AREA
temperature.

MTB30N06VL
SAFE OPERATING AREA
1000 160
VGS = 20 V RDS(on) LIMIT

THERMAL LIMIT 140
TC = 25°C
PACKAGE LIMIT

120
100
10 µs 100
80
60
10 100 µs
1 ms 40
10 ms
20
1 dc
0
0.1 1 10 100 25 50 75 100 125 150 175
1.00
D = 0.5
0.2
0.1
0.10 0.05 P(pk)

0.02
0.01
1.0E–05 1.0E–04 1.0E–03 1.0E–02 1.0E–01 1.0E+00 1.0E+01
t, TIME (s)
3
RθJA = 50°C/W
2.0
di/dt
IS 1.5
trr
1
ta tb
TIME 0.5
tp 0.25 IS
0
IS 25 50 75 100 125 150 175

MOTOROLA
 Data Sheet
Designer's
TMOS V MTB30P06V

60 VOLTS
TM

• On–resistance Area Product about One–half that of Standard CASE 418B–02, Style 2
MOSFETs with New Low Voltage, Low RDS(on) Technology G D2PAK
S
REV 1

MTB30P06V
OFF CHARACTERISTICS
(VDS = 60 Vdc, VGS = 0 Vdc) — — 10
(VGS = 10 Vdc, ID = 30 Adc) — 2.0 2.9
(VGS = 10 Vdc, ID = 15 Adc, TJ = 150°C) — — 2.8
(VDS = 8.3 Vdc, ID = 15 Adc) 5.0 7.9 —
Vd VGS = 0 Vdc,
Vd
Coss — 524 730
f = 1.0 MHz)
VGS = 10 Vdc
Vdc,
(See Fig
Figure
re 8)
((VDS = 48 Vdc, ID = 30 Adc, Q1 — 9.0 —
VGS = 10 Vdc) Q2 — 26 —
Q3 — 20 —

— 2.3 3.0
(IS = 30 Adc, VGS = 0 Vdc, TJ = 150°C)
— 1.9 —
((IS = 30 Adc, VGS = 0 Vdc, ta — 107 —

dIS/dt = 100 A/µs) tb — 68 —


MTB30P06V
60 60
TJ = 25°C 8V VDS ≥ 10 V 100°C
50 VGS = 10V 9V 7V 50

25°C
40 40
30 6V 30 TJ = –55°C
20 20
5V
10 10
4V
0 0
0 2 4 6 8 10 12 0 1 2 3 4 5 6 7 8


0.12 0.08
VGS = 10 V TJ = 25°C
TJ = 100°C
0.1
VGS = 10 V
0.07
0.08
25°C
15 V
0.06 0.06
– 55°C
0.04
0.05
0.02
0 0.04
0 10 20 30 40 50 60 0 10 20 30 40 50 60
1.8 100
VGS = 0 V
1.6 VGS = 10 V
ID = 15 A TJ = 125°C
1.4
1.2
(NORMALIZED)
1
10
0.8 100°C
0.6
0.4
0.2
0 1
–50 –25 0 25 50 75 100 125 150 175 0 10 20 30 40 50 60 70


MTB30P06V
6000
VDS = 0 V VGS = 0 V TJ = 25°C
Ciss
5000
C, CAPACITANCE (pF)
4000
Crss
3000
Ciss
2000
Coss
1000
Crss
0
10 5 0 5 10 15 20 25
VGS VDS

MTB30P06V
10 30 1000

VGS TJ = 25°C
9 QT 27
ID = 30 A
8 24 VDD = 30 V
Q1 Q2 VGS = 10 V
7 21 100
t, TIME (ns)
td(off)
6 18
tf
5 15
tr
4 12 td(on)
10
3 9
2 Q3 TJ = 25°C 6
1 VDS ID = 30 A 3
0 0 1
0 10 20 30 40 50 60 1 10 100

30
TJ = 25°C
25 VGS = 0 V
20
15
10
0
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 2.2
SAFE OPERATING AREA
perature.

MTB30P06V
SAFE OPERATING AREA
1000 450
VGS = 20 V RDS(on) LIMIT ID = 30 A

SINGLE PULSE THERMAL LIMIT 400
TC = 25°C
PACKAGE LIMIT 350

100 300
250
10 µs
200
10 100 µs 150
1 ms 10 ms 100
dc
50
1 0
0.1 1 10 100 25 50 75 100 125 150 175
1.00
D = 0.5
0.2
0.1
0.10 P(pk)
t1 READ TIME AT t1
SINGLE PULSE
0.01
1.0E–05 1.0E–04 1.0E–03 1.0E–02 1.0E–01 1.0E+00 1.0E+01
t, TIME (s)
3
RθJA = 50°C/W
Collector/Drain Pad Size 9 450 mils x 350 mils
2.0
di/dt
IS 1.5
trr
1
ta tb
TIME 0.5
tp 0.25 IS
0
IS 25 50 75 100 125 150 175

MOTOROLA
 Data Sheet
Designer's
MTB33N10E

100 VOLTS

D
G


REV 2

MTB33N10E
OFF CHARACTERISTICS
(VDS = 100 Vdc, VGS = 0 Vdc) — — 10
(VDS = 100 Vdc, VGS = 0 Vdc, TJ = – 25°C) — — 100
(ID = 33 Adc) — 1.6 2.4
(ID = 16.5 Adc, TJ = – 25°C) — — 2.1
Forward Transconductance (VDS = 8.0 Vdc, ID = 16.5 Adc) gFS 8.0 — — mhos
Vd VGS = 0 Vdc,
Vd
Coss — 678 1200
f = 1.0 MHz)

VGS = 10 Vdc
Vdc,
(See Figure 8)
(VDS = 80 Vdc, ID = 33 Adc, Q1 — 12 —
VGS = 10 Vdc)
Q2 — 32 —
Q3 — 24 —

— 1.0 2.0
(IS = 33 Adc, VGS = 0 Vdc, TJ = 125°C)
— 0.98 —
(See Figure
Fig re 14)
((IS = 33 Adc, VGS = 0 Vdc, ta — 108 —
dIS/dt = 100 A/µs) tb — 36 —



MTB33N10E
90 90
TJ = 25°C VGS = 10 V VDS ≥ 10 V
80 80 TJ = –55°C

70 9V 70
25°C
60 60
8V
50 50
100°C
40 40
7V
30 30
20 6V 20
10 5V 10
0 0
0 1 2 3 4 5 6 7 8 9 10 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.5 10


0.09 0.053
VGS = 10 V TJ = 25°C
0.08 0.051
TJ = 100°C
0.049
0.07
0.047
0.06
0.045 VGS = 10 V
0.05 25°C
0.043
0.04
0.041
– 55°C 15 V
0.03 0.039
0.02 0.037
0 6 12 18 24 30 36 42 48 54 60 66 5 11 17 23 29 35 41 47 53 59 65
2.0 10000
1.8 ID = 16.5 A
1.6
1000 TJ = 125°C
(NORMALIZED)
1.4
1.2 100°C
100
1.0
25°C
0.8
0.6 10
–50 –25 0 25 50 75 100 125 150 20 30 40 50 60 70 80 90 100


MTB33N10E
5000
VDS = 0 V VGS = 0 V TJ = 25°C
4500 Ciss
4000
C, CAPACITANCE (pF)
3500
Crss
3000
2500
Ciss
2000
1500
1000 Coss
500
Crss
0
10 5 0 5 10 15 20 25
VGS VDS

MTB33N10E
14 140 1000

VGS VDD = 50 V
12 120 ID = 33 A
QT VGS = 10 V
10 100 TJ = 25°C
Q2
t, TIME (ns)
tr
8 Q1 80
100
6 60 tf
ID = 33 A
4 TJ = 25°C 40 td(off)
2 Q3 20
VDS td(on)
0 0 10
0 10 20 30 40 50 60 1 10 100

33
30 VGS = 0 V
TJ = 25°C
27
24
21
18
15
12
9
6
3
0
0.5 0.55 0.6 0.65 0.7 0.75 0.8 0.85 0.9 0.95 1.0 1.05
SAFE OPERATING AREA
temperature.

MTB33N10E
SAFE OPERATING AREA
1000 550
VGS = 20 V

500 ID = 33 A
SINGLE PULSE
450
100 TC = 25°C

400
350
10 100 µs
300
1 ms
250
1.0 10 ms
dc 200
RDS(on) LIMIT 150
0.1 THERMAL LIMIT 100
PACKAGE LIMIT
50
0.01 0
0.1 1.0 10 100 25 50 75 100 125 150
1.0
D = 0.5
0.2
0.1
0.1 P(pk)
0.05
PULSE TRAIN SHOWN
0.01
1.0E–05 1.0E–04 1.0E–03 1.0E–02 1.0E–01 1.0E+00 1.0E+01
t, TIME (ms)
3.0
RθJA = 50°C/W
2.5
2.0
di/dt
IS 1.5
trr
ta tb 1.0
TIME
0.5
tp 0.25 IS
0
IS 25 50 75 100 125 150

MOTOROLA
Product Preview
MTB35N06ZL
HDTMOS E-FET.
60 VOLTS
This advanced high voltage TMOS E–FET is designed to RDS(on) = 26 mΩ
withstand high energy in the avalanche mode and switch efficiently.
This new high energy device also offers a drain–to–source diode
with fast recovery time. Designed for high voltage, high speed
switching applications in power supplies, PWM motor controls and
other inductive loads, the avalanche energy capability is specified
to eliminate the guesswork in designs where inductive loads are
voltage transients.
D
• Avalanche Energy Capability Specified at Elevated
Temperature
Discrete Fast Recovery Diode G
• Low Stored Gate Charge for Efficient Switching CASE 418B–02, Style 2
• Internal Source–to–Drain Diode Designed to Replace External D2PAK
Zener Transient Suppressor–Absorbs High Energy in the S
Avalanche Mode
• ESD Protected. 400 V Machine Model Level and 4000 V
Human Body Model Level.

Gate–to–Source Voltage — Non–Repetitive (tp ≤ 10 ms) VGSM ± 20 Vpk
(VDD = 25 Vdc, VDS = 60 Vdc, VGS = 5.0 Vdc, Peak IL = 35 Apk, L = 0.3 mH, RG = 25 Ω)
This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice.

MTB35N06ZL
OFF CHARACTERISTICS
(Cpk ≥ 3.0) 60 — — Vdc
(VGS = 0 Vdc, ID = 250 µAdc) — 52 — mV/°C
Temperature Coefficient (Positive)
(VDS = 60 Vdc, VGS = 0 Vdc) — — 10
Gate–Body Leakage Current (VGS = ±15 Vdc, VDS = 0) IGSS — — 5.0 µAdc
Gate Threshold Voltage (Cpk ≥ 3.0) VGS(th)
Static Drain–to–Source On–Resistance RDS(on) — 22 26 mΩ
(Cpk ≥ 2.0)
(VGS = 5.0 Vdc, ID = 11.5 Adc)
Drain–to–Source On–Voltage (VGS = 5.0 Vdc) VDS(on) Vdc
(ID = 23 Adc) — 0.78 1.1
(ID = 11.5 Adc, TJ = 125°C) — 0.7 1.0
Forward Transconductance (VDS = 4.0 Vdc, ID = 11.5 Adc) gFS 10 12 — mhos
Vd VGS = 0 Vdc,
Vd
Coss — 560 —
f = 1.0 MHz)

Turn–On Delay Time td(on) — 40 ns
Rise Time (VDD = 30 Vdc, ID = 23 Adc, tr — 250
VGS(on) = 5.0
5 0 Vdc,
Vdc
Turn–Off Delay Time RG = 9.1 Ω) td(off) — 130
Fall Time tf — 170
Gate Charge QT — 45 nC
(See Fig
Figure
re 8)
((VDS = 48 Vdc, ID = 23 Adc, Q1 — 8.0 —
VGS = 5.0 Vdc) Q2 — 22 —
Q3 — 19 —

— 0.92 1.1
(IS = 23 Adc, VGS = 0 Vdc, TJ = 125°C)
— 0.81 —
((IS = 23 Adc, VGS = 0 Vdc, ta — 24 —

dIS/dt = 100 A/µs) tb — 20 —

(Measured from drain lead 0.25″ from package to center of die) — 4.5 —

MOTOROLA
 Data Sheet
MTB36N06V
Designer's
TMOS V
Power Field Effect Transistor Motorola Preferred Device

60 VOLTS
D
voltage transients.
G
TMOS E–FET

Gate–Source Voltage — Non–Repetitive (tp ≤ 50 µs) VGSM ± 25 Vpk
REV 2

MTB36N06V
OFF CHARACTERISTICS
(VDS = 60 Vdc, VGS = 0 Vdc) — — 10
Static Drain–to–Source On–Resistance (VGS = 10 Vdc, ID = 16 Adc) RDS(on) — 0.034 0.04 Ohm
(VGS = 10 Vdc, ID = 32 Adc) — 1.25 1.54
(VGS = 10 Vdc, ID = 16 Adc, TJ = 150°C) — — 1.47
Forward Transconductance (VDS = 7.6 Vdc, ID = 16 Adc) gFS 5.0 7.83 — mhos
Vd VGS = 0 Vdc,
Vd
Coss — 337 470
f = 1.0 MHz)

VGS = 10 Vdc
Vdc,
(See Fig
Figure
re 8)
((VDS = 48 Vdc, ID = 32 Adc, Q1 — 7 —
VGS = 10 Vdc) Q2 — 17 —
Q3 — 13 —
— 1.03 2.0
(IS = 32 Adc, VGS = 0 Vdc, TJ = 150°C)
— 0.94 —
((IS = 32 Adc, VGS = 0 Vdc, ta — 64 —

dIS/dt = 100 A/µs) tb — 28 —


MTB36N06V
72 72
VGS = 10 V TJ = 100°C
TJ = 25°C VDS ≥ 10 V
7V

9V 25°C
54 54
8V
6V
36 36
5V
18 18
4V –55°C
0 0
0 1 2 3 4 1 2 3 4 5 6 7 8 9


0.1 0.052
VGS = 10 V TJ = 25°C
0.08
TJ = 100°C 0.044
0.06
VGS = 10 V
25°C
0.04
0.036 15 V
– 55°C
0.02
0 0.028
0 18 36 54 72 0 18 36 54 72
1.8 1000
1.6 ID = 16 A
TJ = 125°C
1.4 100
(NORMALIZED)
100°C
1.2
1 10 25°C
0.8
0.6 1
– 50 – 25 0 25 50 75 100 125 150 175 0 10 20 30 40 50 60


MTB36N06V
switching losses.
4000
VDS = 0 V VGS = 0 V TJ = 25°C
3000 Ciss
C, CAPACITANCE (pF)
2000
Crss Ciss
1000
Coss
Crss
0
10 5 0 5 10 15 20 25
VGS VDS

MTB36N06V
12 30 1000

TJ = 25°C
QT
ID = 32 A
10 25 VDD = 30 V
VGS VGS = 10 V tr
8 20 100
t, TIME (ns)
Q2 tf
Q1
6 15 td(off)
td(on)
4 10 10
TJ = 25°C
Q3 ID = 32 A
2 5
VDS
0 0 1
0 5 10 15 20 25 30 35 40 1 10 100

32
TJ = 25°C
VGS = 0 V
24
16
0
0.5 0.55 0.6 0.65 0.7 0.75 0.8 0.85 0.9 0.95 1 1.05
SAFE OPERATING AREA
temperature.

MTB36N06V
SAFE OPERATING AREA
1000 225
VGS = 20 V RDS(on) LIMIT

SINGLE PULSE 200 ID = 32 A
THERMAL LIMIT
TC = 25°C
PACKAGE LIMIT 175

100 150
10 µs 125
100
10 100 µs 75
1 ms 50
10 ms
25
1 dc
0
0.1 1 10 100 25 50 75 100 125 150 175
1.00
D = 0.5
0.2
0.1
0.10 0.05 P(pk)

PULSE TRAIN SHOWN
SINGLE PULSE
0.01
1.0E–05 1.0E–04 1.0E–03 1.0E–02 1.0E–01 1.0E+00 1.0E+01
t, TIME (s)

3
RθJA = 50°C/W
2.0
di/dt
1.5
IS
trr 1
ta tb
TIME 0.5
tp 0.25 IS
0
25 50 75 100 125 150 175
IS

MOTOROLA
 Data Sheet
Designer's
MTB50P03HDL
HDTMOS E-FET. Motorola Preferred Device

LOGIC LEVEL
The D2PAK package has the capability of housing a larger die 30 VOLTS
than any existing surface mount package which allows it to be used RDS(on) = 0.025 OHM
high–cell density HDTMOS power FET is designed to withstand
high energy in the avalanche and commutation modes. This new

energy efficient design also offers a drain–to–source diode with a
fast recovery time. Designed for low voltage, high speed switching
applications in power supplies, converters and PWM motor
D
controls, these devices are particularly well suited for bridge circuits
where diode speed and commutating safe operating areas are
critical and offer additional safety margin against unexpected
voltage transients.
G

Gate–Source Voltage — Continuous VGS ±15 Vdc
Total Power Dissipation @ TC = 25°C, when mounted with the minimum recommended pad size 2.5 Watts
REV 1

MTB50P03HDL
OFF CHARACTERISTICS
(VGS = 0 Vdc, ID = 250 µAdc) 30 — —
(VDS = 30 Vdc, VGS = 0 Vdc) — — 10
(VGS = ±15 Vdc, VDS = 0 Vdc) — — 100
(VDS = VGS, ID = 250 µAdc) 1.0 1.5 2.0
Static Drain–Source On–Resistance (Cpk ≥ 3.0) (3) RDS(on) mOhm
(VGS = 5.0 Vdc, ID = 25 Adc) — 20.9 25
Drain–Source On–Voltage (VGS = 5.0 Vdc) VDS(on) Vdc
(ID = 50 Adc) — 0.83 1.5
(ID = 25 Adc, TJ =125°C) — — 1.3
(VDS = 5.0 Vdc, ID = 25 Adc) 15 20 —
Output Capacitance Vd VGS = 0 Vdc,
(VDS = 25 Vdc, Vd
Coss — 1550 2170
f = 1.0 MHz)
Rise Time (VDD= 15 Vdc, ID = 50 Adc, tr — 340 466
VGS = 5.0
5 0 Vdc,
Vdc
(S Fi
(See Figure 8)
((VDS = 24 Vdc, ID = 50 Adc, Q1 — 13.6 —
VGS = 5.0 Vdc) Q2 — 44.8 —
Q3 — 35 —
— 2.39 3.0
(IS = 50 Adc, VGS = 0 Vdc, TJ = 125°C)
— 1.84 —
(S Figure
(See Fi 15)
((IS = 50 Adc, VGS = 0 Vdc, ta — 58 —
dIS/dt = 100 A/µs) tb — 48 —
Cpk =
3 x SIGMA

MTB50P03HDL
100 100
TJ = 25°C VGS = 10 V 5V VDS ≥ 5 V TJ = – 55°C
8V 25°C 100°C

80 6V 80
4V
4.5 V
60 60
3.5 V
40 40
3V
20 20
2.5 V
0 0
0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 1.5 1.9 2.3 2.7 3.1 3.5 3.9 4.3


0.029 0.022
VGS = 5 V TJ = 25°C VGS = 5 V
0.027 0.021
0.025 0.020
TJ = 100°C
0.023 0.019
25°C
0.021 0.018
0.019 0.017
10 V
0.017 – 55°C 0.016
0.015 0.015
0 20 40 60 80 100 0 20 40 60 80 100
1.35 1000
VGS = 5 V VGS = 0 V
ID = 25 A
1.25
I DSS, LEAKAGE (nA)
TJ = 125°C
(NORMALIZED)
1.15
100
1.05
0.95
100°C
0.85 10
– 50 – 25 0 25 50 75 100 125 150 0 5 10 15 20 25 30
Figure 5. On–Resistance Variation with Figure 6. Drain–to–Source Leakage


MTB50P03HDL
14000
VDS = 0 V VGS = 0 V
TJ = 25°C
C
12000 iss
C, CAPACITANCE (pF)
10000
8000
Crss
6000
Ciss
4000
Coss
2000
Crss
0
10 5 0 5 10 15 20 25
VGS VDS

MTB50P03HDL

6 30

1000 VDD = 30 V ID = 50 A
QT VGS = 10 V TJ = 25°C
5 VGS 25 tr
Q1 Q2 tf
4 20
td(off)
t, TIME (ns)
3 15 100
ID = 50 A
2 10
TJ = 25°C
td(on)
1 5
Q3 VDS
0 0 10
0 10 20 30 40 50 60 70 80 1 10
QT, TOTAL GATE CHARGE (nC) RG, GATE RESISTANCE (Ohms)

snappy.
50
VGS = 0 V
TJ = 25°C
40
30
20
10
0
0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4

MTB50P03HDL
trr
High Cell Density
trr
tb
ta
t, TIME
SAFE OPERATING AREA
perature.
1000 1400
VGS = 20 V ID = 50 A
SINGLE PULSE 1200
TC = 25°C
1000
100
100 µs
800
1 ms 600
10 10 ms 400
RDS(on) LIMIT dc
THERMAL LIMIT 200
PACKAGE LIMIT
1 0
0.1 1.0 10 100 25 50 75 100 125 150

MTB50P03HDL
r(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE 1.0

D = 0.5
0.2
(NORMALIZED)
0.1
0.1 P(pk)
t1 READ TIME AT t1
0.01
0.01
1.0E–05 1.0E–04 1.0E–03 1.0E–02 1.0E–01 1.0E+00 1.0E+01
t, TIME (s)
3
RθJA = 50°C/W
PD, POWER DISSIPATION (WATTS) 2.5 Mounted on the minimum recommended footprint
2.0
di/dt
IS 1.5
trr
1
ta tb
TIME 0.5
tp 0.25 IS
0
IS 25 50 75 100 125 150

MOTOROLA
Product Preview
TMOS V MTB52N06V

60 VOLTS
D
voltage transients.
G


MTB52N06V
OFF CHARACTERISTICS
Temperature Coefficient (Positive) — TBD — mV/°C
(VDS = 60 Vdc, VGS = 0 Vdc) — — 10
Temperature Coefficient (Negative) — TBD — mV/°C
(VGS = 10 Vdc, ID = 52 Adc) — — 1.4
(VGS = 10 Vdc, ID = 26 Adc, TJ = 150°C) — — 1.2
Forward Transconductance (VDS = 6.3 Vdc, ID = 20 Adc) gFS 17 25 — mhos
Vd VGS = 0 Vdc,
Vd
Coss — 500 700
f = 1.0 MHz)

VGS = 10 Vdc
Vdc,
(See Fig
Figure
re 8)
((VDS = 48 Vdc, ID = 52 Adc, Q1 — 10 —
VGS = 10 Vdc) Q2 — 30 —
Q3 — 20 —
— 1.0 1.5
(IS = 52 Adc, VGS = 0 Vdc, TJ = 150°C)
— 0.9 —
(See Figure
Fig re 14)
((IS = 52 Adc, VGS = 0 Vdc, ta — 80 —
dIS/dt = 100 A/µs) tb — 10 —

MOTOROLA
Product Preview MTB52N06VL

TMOS V

TMOS V is a new technology designed to achieve an on–resistance 60 VOLTS
area product about one–half that of standard MOSFETs. This new RDS(on) = 0.025 OHM
commutation modes. Designed for low voltage, high speed
TM
circuits where diode speed and commutating safe operating areas D
voltage transients.
• On–resistance Area Product about One–half that of Standard G
MOSFETs with New Low Voltage, Low RDS(on) Technology
• Faster Switching than E–FET Predecessors CASE 418B–02, Style 2
S D2PAK
— Continuous @ 100°C ID 41

MTB52N06VL
OFF CHARACTERISTICS
(VGS = 0 Vdc, ID = .25 mAdc) 60 — — Vdc
(VDS = 60 Vdc, VGS = 0 Vdc) — — 10
Threshold Temperature Coefficient (Negative) — TBD — mV/°C
(VGS = 5 Vdc, ID = 52 Adc) — — 1.5
(VGS = 5 Vdc, ID = 26 Adc, TJ = 150°C) — — 1.3
Forward Transconductance (VDS = 6.3 Vdc, ID = 20 Adc) gFS 17 30 — Mhos
Vd VGS = 0 Vdc,
Vd
Coss — 550 770
f = 1.0 MHz)

VGS = 5 Vdc
Vdc,
(See Fig
Figure
re 8)
((VDS = 48 Vdc, ID = 52 Adc, Q1 — 12 —
VGS = 5 Vdc) Q2 — 22 —
Q3 — 18 —
— 1.0 1.5
(IS = 52 Adc, VGS = 0 Vdc, TJ = 150 °C)
— 0.9 —
((IS = 52 Adc, VGS = 0 Vdc, ta — 65 —

dIS/dt = 100 A/µs) tb — 28 —

MOTOROLA
Product Preview
TMOS E-FET. MTB55N06Z
60 VOLTS
This advanced high voltage TMOS E–FET is designed to RDS(on) = 16 mΩ
withstand high energy in the avalanche mode and switch efficiently.
This new high energy device also offers a drain–to–source diode
switching applications in power supplies, PWM motor controls and 
voltage transients.
• Avalanche Energy Capability Specified at Elevated D
Temperature
Discrete Fast Recovery Diode G
• Low Stored Gate Charge for Efficient Switching CASE 418B–02, Style 2
• Internal Source–to–Drain Diode Designed to Replace External D2PAK
Zener Transient Suppressor–Absorbs High Energy in the S
Avalanche Mode
• ESD Protected. 400 V Machine Model Level and 4000 V
Human Body Model Level.

(VDD = 25 Vdc, VDS = 60 Vdc, VGS = 10 Vdc, Peak IL = 55 Apk, L = 0.3 mH, RG = 25 Ω)

MTB55N06Z
OFF CHARACTERISTICS
(Cpk ≥ 2.0) 60 — — Vdc
(VGS = 0 Vdc, ID = 250 µAdc) — 53 — mV/°C
Temperature Coefficient (Positive)
(VDS = 60 Vdc, VGS = 0 Vdc) — — 10
Gate–Body Leakage Current (VGS = ± 20 Vdc, VDS = 0) IGSS — — 5.0 µAdc
Gate Threshold Voltage (Cpk ≥ 2.0) VGS(th)
Static Drain–to–Source On–Resistance RDS(on) — 14 16 mΩ
(Cpk ≥ 2.0)
(VGS = 10 Vdc, ID = 15 Adc)
Drain–to–Source On–Voltage (VGS = 10 Vdc) VDS(on) Vdc
(ID = 30 Adc) — 0.825 1.2
(ID = 15 Adc, TJ = 125°C) — 0.74 1.0
Forward Transconductance (VDS = 4.0 Vdc, ID = 15 Adc) gFS 12 15 — mhos
Vd VGS = 0 Vdc,
Vd
Coss — 520 730
f = 1.0 MHz)

VGS(on) = 10 Vdc
Vdc,
(See Fig
Figure
re 8)
((VDS = 48 Vdc, ID = 30 Adc, Q1 — 7.0 —
VGS = 10 Vdc) Q2 — 18 —
Q3 — 15 —

— 0.93 1.1
(IS = 30 Adc, VGS = 0 Vdc, TJ = 125°C)
— 0.82 —
((IS = 30 Adc, VGS = 0 Vdc, ta — 32 —

dIS/dt = 100 A/µs) tb — 25 —


MOTOROLA
 Data Sheet
Designer's
MTB60N06HD

60 VOLTS
high energy in the avalanche and commutation modes. This new 
controls, these devices are particularly well suited for bridge circuits D
voltage transients.
(VDD = 25 Vdc, VGS = 10 Vdc, Peak IL = 60 Apk, L = 0.3 mH, RG = 25 Ω)
(1) When mounted with the minimum recommended pad size.
REV 2

MTB60N06HD
OFF CHARACTERISTICS
(VGS = 0 Vdc, ID = 250 µAdc) 60 — —
(VDS = 60 Vdc, VGS = 0 Vdc) — — 10
(VGS = ± 20 Vdc, VDS = 0 Vdc) — — 100
(VDS = VGS, ID = 250 µAdc) 2.0 3.0 4.0
Static Drain–Source On–Resistance (Cpk ≥ 3.0) (3) RDS(on) Ohm
(VGS = 10 Vdc, ID = 30 Adc) — 0.011 0.014
(ID = 60 Adc) — — 1.0
(ID = 30 Adc, TJ =125°C) — — 0.9
(VDS = 4.0 Vdc, ID = 30 Adc) 15 20 —
(VDS = 25 Vdc, Vd
Coss — 660 920
f = 1.0 MHz)
Rise Time (VDD= 30 Vdc, ID = 60 Adc, tr — 197 394
VGS = 10 Vdc
Vdc,
(S Fi
(See Figure 8)
((VDS = 48 Vdc, ID = 60 Adc, Q1 — 12 —
VGS = 10 Vdc) Q2 — 24 —
Q3 — 21 —
— 0.99 1.0
(IS = 60 Adc, VGS = 0 Vdc, TJ = 125°C)
— 0.89 —
(S Figure
(See Fi 15)
((IS = 60 Adc, VGS = 0 Vdc, ta — 36 —
dIS/dt = 100 A/µs) tb — 24 —
Cpk =
3 x SIGMA

MTB60N06HD
120 120
8V 7V
VGS = 10 V VDS ≥ 10 V
100 100

9V
TJ = 25°C
80 80
60 6V 60
40 40
100°C
5V 25°C
20 20
TJ = – 55°C
0 0
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 2.0 2.8 3.6 4.4 5.2 6.0 6.8 7.6


0.020 0.0132
VGS = 10 V TJ = 25°C
0.018 0.0128
TJ = 100°C 0.0124
0.016
0.0120
0.014 VGS = 10 V
0.0116
0.012 25°C
0.0112
0.010
0.0108
– 55°C 15 V
0.008 0.0104
0.006 0.0100
0 10 20 30 40 50 60 70 80 90 100 110 120 0 10 20 30 40 50 60 70 80 90 100 110 120
1.8 1000
1.6 ID = 30 A
TJ = 125°C
I DSS, LEAKAGE (nA)
(NORMALIZED)
1.4 100
1.2 100°C
25°C
1.0 10
0.8
0.6 1
– 50 – 25 0 25 50 75 100 125 150 0 10 20 30 40 50 60


MTB60N06HD
5000
VDS = 0 V VGS = 0 V
Ciss TJ = 25°C
4000
C, CAPACITANCE (pF)
3000
Crss
Ciss
2000
Coss
1000
Crss
0
10 5 0 5 10 15 20 25
VGS VDS

MTB60N06HD
12 60 1000

QT VDD = 30 V
10 50 ID = 60 A
VGS VGS = 10 V
TJ = 25°C
8 40 tr
Q1 Q2
t, TIME (ns)
tf
6 30 100
4 ID = 60 A 20 td(off)
TJ = 25°C
2 10
Q3
VDS td(on)
0 0 10
0 8 16 24 32 40 48 56 1 10 100
QT, TOTAL GATE CHARGE (nC) RG, GATE RESISTANCE (Ohms)

snappy.
60
VGS = 0 V
50 TJ = 25°C
40
30
20
10
0
0.5 0.6 0.7 0.8 0.9 1.0

MTB60N06HD
trr
High Cell Density
trr
tb
ta
t, TIME
SAFE OPERATING AREA
perature.
1000 600
VGS = 20 V ID = 60 A
SINGLE PULSE
500
TC = 25°C
100 10 µs 400
300
100 µs
10 200
1 ms
RDS(on) LIMIT 10 ms
THERMAL LIMIT 100
PACKAGE LIMIT dc
1 0
0.1 1.0 10 100 25 50 75 100 125 150

MTB60N06HD
r(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE

1.0
D = 0.5
0.2
(NORMALIZED)
0.1
0.1 P(pk)
t1 READ TIME AT t1
0.01
0.01
1.0E–05 1.0E–04 1.0E–03 1.0E–02 1.0E–01 1.0E+00 1.0E+01
t, TIME (s)
3
RθJA = 50°C/W
2.0
di/dt
IS 1.5
trr
1
ta tb
TIME 0.5
tp 0.25 IS
0
IS 25 50 75 100 125 150

MOTOROLA
Advanced Information MTB75N03HDL

High Density Power FET

LOGIC LEVEL
The D2PAK package has the capability of housing a larger die 25 VOLTS
than any existing surface mount package which allows it to be used RDS(on) = 9 mOHM

controls, these devices are particularly well suited for bridge circuits D
voltage transients.
• Ultra Low RDS(on), High–Cell Density, HDTMOS
• Short Heatsink Tab Manufactured — Not sheared
(VDD = 25 Vdc, VGS = 5.0 Vdc, IL = 75 Apk, L = 0.1 mH, RG = 25 Ω)
(1) When mounted with the minimum recommended pad size.
REV 2

MTB75N03HDL
OFF CHARACTERISTICS
Drain–Source Breakdown Voltage (Cpk ≥ 2.0) (3) V(BR)DSS Vdc
(VGS = 0 Vdc, ID = 250 µAdc) 25 — —
Temperature Coefficient (Positive) mV/°C
(VDS = 25 Vdc, VGS = 0 Vdc) — — 100
Gate–Body Leakage Current (VGS = ± 20 Vdc, VDS = 0 V) IGSS — — 100 nAdc
(VDS = VGS, ID = 250 µAdc) 1.0 1.5 2.0
Temperature Coefficient (Negative) mV/°C
Static Drain–Source On–Resistance (Cpk ≥ 2.0) (3) RDS(on) mΩ
(VGS = 5.0 Vdc, ID = 37.5 Adc) — 6.0 9.0
(ID = 75 Adc) — — 0.68
(ID = 37.5 Adc, TJ = 125°C) — — 0.6
Forward Transconductance (VDS = 3 Vdc, ID = 20 Adc) gFS 15 55 — mhos
Vd VGS = 0 Vdc,
Vd
Coss — 1353 1894
f = 1.0 MHz)
Rise Time (VDS= 15 Vdc, ID = 75 Adc, tr — 493 986
VGS = 5.0
5 0 Vdc,
Vdc
((VDS = 24 Vdc, ID = 75 Adc, Q1 — 14 28

VGS = 5.0 Vdc) Q2 — 33 66
Q3 — 27 54

— 0.97 1.1
(IS = 75 Adc, VGS = 0 Vdc, TJ = 125°C)
— 0.87 —
((IS = 75 Adc, ta — 27 —
dIS/dt = 100 A/µs) tb — 30 —
Cpk =
3 x SIGMA

MTB75N03HDL
150 150
VGS = 10 V 5V 4.5 V TJ = 25°C VDS ≥ 10 V
8V

120 4V 120
6V
90 90
3.5 V
60 60
100°C 25°C
30 3V 30
TJ = –55°C
2.5 V
0 0
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 1.5 2 2.5 3 3.5 4 4.5


0.01 0.009
VGS = 5 V
TJ = 25°C
TJ = 100°C 0.008
0.008
0.007
25°C VGS = 5 V
0.006
0.006
– 55°C
10 V
0.004
0.005
0.002 0.004
0 30 60 90 120 150 0 25 50 75 100 125 150
2 10000
TJ = 125°C
VGS = 10 V
1.6 ID = 37.5 A
1000 100°C
(NORMALIZED)
1.2
100
0.8
10
0.4 25°C
VGS = 0 V
0 1
–50 –25 0 25 50 75 100 125 150 0 5 10 15 20 25 30


MTB75N03HDL
15000
VDS = 0 V VGS = 0 V
TJ = 25°C
12000 Ciss
C, CAPACITANCE (pF)
9000
Crss
6000 Ciss
Coss
3000
Crss
0
10 5 0 5 10 15 20 25
VGS VDS

MTB75N03HDL
7 28 10000

TJ = 25°C
6 24 ID = 75 A
QT VDD = 15 V
5 20 tr VGS = 5 V
VGS 1000
t, TIME (ns)
Q1 Q2
4 16
3 12 tf
td(off)
TJ = 25°C 100
2 8 td(on)
ID = 75 A
1 4
Q3 VDS
0 0 10
0 10 20 30 40 50 60 70 1 10 100
QT, TOTAL GATE CHARGE (nC) RG, GATE RESISTANCE (OHMS)

snappy.
75
TJ = 25°C
60 VGS = 0 V
45
30
15
0
0.5 0.6 0.7 0.8 0.9 1

MTB75N03HDL
SAFE OPERATING AREA
perature.
1000 280
VGS = 20 V

240
TC = 25°C

200
100
160
100 µs
120
1 ms
10 10 ms
80
RDS(on) LIMIT dc
THERMAL LIMIT 40
PACKAGE LIMIT
1 0
0.1 1 10 100 25 50 75 100 125 150

MTB75N03HDL
1.0
D = 0.5
0.2
(NORMALIZED)
0.1
0.1 P(pk)
0.02
PULSE TRAIN SHOWN
SINGLE PULSE
0.01
1.0E–05 1.0E–04 1.0E–03 1.0E–02 1.0E–01 1.0E+00 1.0E+01
t, TIME (s)
3
RθJA = 50°C/W
PD, POWER DISSIPATION (WATTS) 2.5 Mounted on the minimum recommended footprint
2.0
di/dt
IS 1.5
trr
1
ta tb
TIME 0.5
tp 0.25 IS
0
IS 25 50 75 100 125 150

MOTOROLA
 Data Sheet
Designer's
MTB75N05HD

50 VOLTS
The D2PAK package has the capability of housing a larger die RDS(on) = 9.5 mΩ
high–cell density HDTMOS power FET is designed to withstand 
D
voltage transients.
G
Drain–to–Source Voltage VDSS 50 Volts
Drain–to–Gate Voltage (RGS = 1.0 MΩ) VDGR 50
Drain Current — Continuous ID 75 Amps
Drain Current — Single Pulse (tp ≤ 10 µs) IDM 225
Total Power Dissipation @ TA = 25°C (minimum footprint, FR–4 board) 2.5 Watts
(VDD = 25 V, VGS = 10 V, Peak IL = 75 A, L = 0.177 mH, RG = 25 Ω)
Thermal Resistance — Junction to Ambient (minimum footprint, FR–4 board) RθJA 50
Maximum Temperature for Soldering Purposes, 1/8″ from case for 10 seconds TL 260 °C
REV 2

MTB75N05HD
OFF CHARACTERISTICS
Drain–to–Source Breakdown Voltage (Cpk ≥ 2)(2) V(BR)DSS
(VGS = 0, ID = 250 µAdc) 50 — — Vdc
(VDS = 50 V, VGS = 0) — — 10
(VDS = 50 V, VGS = 0, TJ = 125°C) — — 100
(VGS = ± 20 Vdc, VDS = 0) — — 100
Gate Threshold Voltage (Cpk ≥ 1.5)(2) VGS(th)
Static Drain–to–Source On–Resistance(3) (Cpk ≥ 3.0)(2) RDS(on) mΩ
(VGS = 10 Vdc, ID = 20 Adc) — 7.0 9.5
Drain–to–Source On–Voltage (VGS = 10 Vdc)(3) VDS(on) Vdc

(ID = 75 A) — 0.63 —
(ID = 20 Adc, TJ = 125°C) — — 0.34
Forward Transconductance (VDS = 10 Vdc, ID = 20 Adc) gFS 15 — — mhos
(VDS = 25 V, 0, (Cpk ≥ 2
V VGS = 0 0)(2)
2.0)
Output Capacitance f = 1.0 MHz) (Cpk ≥ 2.0)(2) Coss — 1000 1100
Transfer Capacitance (Cpk ≥ 2.0)
2 0)(2)
Crss — 230 275

Rise Time (VDD = 25 V, ID = 75 A, tr — 170 340
VGS = 10 V,V
((VDS = 40 V, ID = 75 A, Q1 — 13 —
VGS = 10 V) Q2 — 33 —
Q3 — 26 —
Forward On–Voltage (IS = 75 A, VGS = 0) (Cpk ≥ 10)(2) VSD 0.97 — Vdc
(IS = 20 A, VGS = 0) — 0.80 1.00
(IS = 20 A, VGS = 0, TJ = 125°C) — 0.68 —
((IS = 37.5 A, VGS = 0, ta — 40 —

dIS/dt = 100 A/µs) tb — 17 —

Internal Source Inductance LS
(2) Reflects Typical Values. Cpk = ABSOLUTE VALUE OF (SPEC – AVG) / 3 * SIGMA).
(3) For accurate measurements, good Kelvin contact required.

MTB75N05HD
TYPICAL ELECTRICAL CHARACTERISTICS(1)
160 160
VGS = 10 V 7V TJ = 25°C VDS ≥ 10 V
140 140

120 120
100 100
80 6V 80
60 60
40 40 100°C TJ = – 55°C
20 5V 20
25°C
0 0
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 0 1 2 3 4 5 6 7 8


0.014 0.009
VGS = 10 V TJ = 25°C
0.012
TJ = 100°C
0.008 VGS = 10 V
0.01
0.008 25°C 0.007

15 V
0.006
– 55°C
0.006
0.004
0.002 0.005
0 20 40 60 80 100 120 140 0 20 40 60 80 100 120 140 160
2 10000
ID = 37.5 A
1.5 1000 TJ = 125°C
I DSS, LEAKAGE (nA)
(NORMALIZED)
1 100 100°C
0.5 10
25°C
0 0
– 50 – 25 0 25 50 75 100 125 150 0 5 10 15 20 25 30 35 40 45 50

(1)Pulse Tests: Pulse Width ≤ 250 µs, Duty Cycle ≤ 2%.

MTB75N05HD
readily achievable with board–mounted components. Most
voltage change in a RC network. The equations are:
8000
VDS = 0 VGS = 0
7000 TJ = 25°C
Ciss
6000
C, CAPACITANCE (pF)
5000
4000
Ciss
3000 Crss
Coss
2000
1000 Crss
0
10 5 0 5 10 15 20 25
VGS VDS


MTB75N05HD
12 60 1000

TJ = 25°C
QT ID = 75 A
10 50 tf
VDD = 35 V
VGS
VGS = 10 V tr
8 40 100
td(off)
t, TIME (ns)
Q1 Q2
6 30
TJ = 25°C td(on)
4 ID = 75 A 20 10
2 10
Q3 VDS
0 0 1
0 25 50 75 1 10 100

snappy.
80 40
TJ = 25°C di/dt = 300 A/µs STANDARD CELL DENSITY
70 VGS = 0 V 30 trr
60 20 HIGH CELL DENSITY

trr
50 10 tb
ta
40 0
30 – 10
20 – 20
10 – 30
0 – 40
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 – 120 – 100 – 80 – 60 – 40 – 20 0 20 40 60 80
VSD, SOURCE–TO–DRAIN VOLTAGE (VOLTS) t, TIME (ns)
Figure 10. Diode Forward Voltage versus Current Figure 11. Reverse Recovery Time (trr)

MTB75N05HD
SAFE OPERATING AREA
perature.
1000 500
VGS = 20 V ID = 75 A

TC = 25°C 400

100
350
300
10 100 µs 250
1 ms
10 ms 200
dc 150
1 RDS(on) LIMIT
THERMAL LIMIT 100
PACKAGE LIMIT 50
0.1 0
0.1 1 10 100 25 50 75 100 125 150 175
1
D = 0.5
0.2
(NORMALIZED)
0.1 P(pk) RθJC(t) = r(t) RθJC

0.1 RθJC = 1.0°C/W MAX
PULSE TRAIN SHOWN
0.01 t2
TJ(pk) – TC = P(pk) RθJC(t)
SINGLE PULSE
0.01
1.0E– 05 1.0E– 04 1.0E– 03 1.0E– 02 1.0E– 01 1.0E+00 1.0E+01
t, TIME (s)

MTB75N05HD
3
RθJA = 50°C/W

2.5
2.0
1.5
0.5
0
25 50 75 100 125 150
Figure 15. D2PAK Power Derating Curve

MOTOROLA
 Data Sheet
Designer's
MTD1N50E

DPAK for Surface Mount TMOS POWER FET
N–Channel Enhancement–Mode Silicon Gate 1.0 AMPERE
500 VOLTS
degrading performance over time. In addition this advanced TMOS
commutation modes. The new energy efficient design also offers a 
converters and PWM motor controls, these devices are particularly D
• Avalanche Energy Specified CASE 369A–13, Style 2
DPAK
• Surface Mount Package Available in 16 mm, 13–inch/2500
Unit Tape & Reel, Add –T4 Suffix to Part Number

— Non–repetitive (tp ≤ 10 ms) VGSM ±40 Vpk
Total Power Dissipation @ TA = 25°C, when mounted to minimum recommended pad size 1.75 Watts
— Junction to Ambient, when mounted to minimum recommended pad size RθJA 71.4
REV 1

MTD1N50E
OFF CHARACTERISTICS
(VGS = 0 Vdc, ID = 0.25 µAdc) 500 — — Vdc
(VDS = 500 Vdc, VGS = 0 Vdc) — — 10
(ID = 1.0 Adc) — 4.5 6.0
(ID = 0.5 Adc, TJ = 125°C) — — 5.3
Forward Transconductance (VDS = Vdc, ID = 0.5 Adc) gFS 0.5 0.9 — mhos
Vd VGS = 10 Vd
Vdc,
Coss — 30.2 42
f = 1.0 MHz)

VGS = 10 Vdc
Vdc,
Gate Charge QT — 7.4 9.0 nC
(See Fig
Figure
re 8)
((VDS = 400 Vdc, ID = 1.0 Adc, Q1 — 1.6 —
VGS = 10 Vdc) Q2 — 3.8 —
Q3 — 5.0 —
— 0.81 1.2
(IS = 1.0 Adc, VGS = 0 Vdc, TJ = 125°C)
— 0.68 —
(See Figure
Fig re 14)
((IS = 1.0 Adc, VGS = 0 Vdc, ta — 82 —
dIS/dt = 100 A/µs) tb — 58.5 —

MTD1N50E
2.0 2.0
TJ = 25°C VGS = 10 V VDS ≥ 10 V
1.75 7V 1.75

8V 6V
1.50 1.50
1.25 1.25
1.0 1.0
0.75 0.75
0.50 5V 0.50 TJ = 100°C

25°C
0.25 0.25
– 55°C
0 0
0 2 4 6 8 10 12 14 16 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5


10 6.0
VGS = 10 V TJ = 25°C
TJ = 100°C
5.5
8
5.0
6 VGS = 10 V
25°C 4.5
4 15 V
4.0
– 55°C
2
3.5
0 3.0
0 0.4 0.8 1.2 1.6 2.0 0 0.25 0.50 0.75 1.0 1.25 1.50 1.75 2.0
2.5 10000
ID = 0.5 A
2.0 TJ = 125°C
1000
(NORMALIZED)
1.5 100°C
100
1.0
10 25°C
0.5
0 1
– 50 – 25 0 25 50 75 100 125 150 0 100 200 300 400 500


MTD1N50E
500 1000
VDS = 0 V VGS = 0 V TJ = 25°C VGS = 0 V
450
TJ = 25°C Ciss
400
350 Ciss
C, CAPACITANCE (pF)
100
C, CAPACITANCE (pF)
300
250 Ciss
Coss
200
10
150
Crss
100 Crss
Coss
50 Crss
0 1
10 5 0 5 10 15 20 25 10 100 1000
Figure 7a. Capacitance Variation Figure 7b. High Voltage Capacitance

Variation

MTD1N50E
12 360 100

VDD = 250 V
QT ID = 1 A
10 300
VGS VGS = 10 V
TJ = 25°C
8 Q1 Q2 240 tf
t, TIME (ns)
td(off)
6 180 10
td(on)
tr
4 120
ID = 1 A
TJ = 25°C
2 60
Q3 VDS
0 0 1
0 2 4 6 8 1 10 100

1.0
VGS = 0 V
TJ = 25°C
0.8
0.6
0.4
0.2
0
0.5 0.54 0.58 0.62 0.66 0.70 0.74 0.78 0.82
SAFE OPERATING AREA
The Forward Biased Safe Operating Area curves define the reliable operation, the stored energy from circuit inductance
maximum simultaneous drain–to–source voltage and drain dissipated in the transistor while in avalanche must be less
current that a transistor can handle safely when it is forward than the rated limit and adjusted for operating conditions
biased. Curves are based upon maximum peak junction differing from those specified. Although industry practice is to
temperature and a case temperature (TC) of 25°C. Peak rate in terms of energy, avalanche energy capability is not a
thermal response data in conjunction with the procedures increase of peak current in avalanche and peak junction
temperature.
time (tr,tf) do not exceed 10 µs. In addition the total power av- continuous current (ID), in accordance with industry custom.
eraged over a complete switching cycle must not exceed The energy rating must be derated for temperature as shown

MTD1N50E
SAFE OPERATING AREA
10 50
VGS = 20 V ID = 1 A

SINGLE PULSE 10 µs
TC = 25°C
40

1.0
30
100 µs
1 ms
10 ms 20
0.1 dc
RDS(on) LIMIT 10
THERMAL LIMIT
PACKAGE LIMIT
0.01 0
0.1 1.0 10 100 1000 25 50 75 100 125 150
1.0
D = 0.5
0.2
0.1
0.1 0.05 P(pk)

t1 READ TIME AT t1
0.01
1.0E–05 1.0E–04 1.0E–03 1.0E–02 1.0E–01 1.0E+00 1.0E+01
t, TIME (s)
di/dt
IS
trr
ta tb
TIME
tp 0.25 IS
IS

MOTOROLA
 Data Sheet
Designer's
MTD1N60E

N–Channel Enhancement–Mode Silicon Gate 1.0 AMPERE
600 VOLTS

well suited for bridge circuits where diode speed and commutating D
• Source–to–Drain Diode Recovery Time Comparable to a Discrete DPAK
Fast Recovery Diode S
Unit Tape & Reel, Add T4 Suffix to Part Number

REV 1

MTD1N60E
OFF CHARACTERISTICS
(VDS = 600 Vdc, VGS = 0 Vdc) — — 10
(ID = 1.0 Adc) — — 9.6
(ID = 0.5 Adc, TJ = 125°C) — — 8.4
Vd VGS = 0 Vdc,
Vd
Coss — 27 40
f = 1.0 MHz)

VGS = 10 Vdc
Vdc,
(See Fig
Figure
re 8)
((VDS = 400 Vdc, ID = 1.0 Adc, Q1 — 1.7 —
VGS = 10 Vdc) Q2 — 3.2 —
Q3 — 3.9 —
— 0.82 1.4
(IS = 1.0 Adc, VGS = 0 Vdc, TJ = 125°C)
— 0.7 —
(See Figure
Fig re 14)
((IS = 1.0 Adc, VGS = 0 Vdc, ta — 36 —
dIS/dt = 100 A/µs) tb — 428 —

MTD1N60E
2 2
TJ = 25°C VGS = 10 V VDS ≥ 10 V
1.8 7V 6V

1.6 1.6
1.4
1.2 1.2
1
0.8 0.8
0.6 5V
100°C
0.4 0.4 25°C
0.2 TJ = – 55°C
0 0
0 2 4 6 8 10 12 14 16 18 20 2 2.4 2.8 3.2 3.6 4 4.4 4.8 5.2 5.6 6 6.4 6.8


16 9
VGS = 10 V TJ = 25°C
14 8.5
12 TJ = 100°C 8
10 7.5
8 7
25°C VGS = 10 V
6 6.5
15 V
4 – 55°C 6
2 5.5
0 5
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
2.4 1000
VGS = 0 V
VGS = 10 V
2 ID = 0.5 A TJ = 125°C
1.6 100 100°C

(NORMALIZED)
1.2
0.8 10
25°C
0.4
0 1
– 50 – 25 0 25 50 75 100 125 150 0 100 200 300 400 500 600


MTD1N60E
500 1000
450
Ciss TJ = 25°C
Ciss
400
350
C, CAPACITANCE (pF)
C, CAPACITANCE (pF)
100
300
250 Ciss
Crss
200 Coss
10
150
100 Crss
Coss
50
Crss
0 1
10 5 0 5 10 15 20 25 10 100 1000

MTD1N60E
100

12 600
QT

VDD = 300 V
10 500 ID = 1 A
VGS = 10 V
VGS TJ = 25°C
8 400 tf
t, TIME (ns)
Q1 Q2
td(off)
6 300 10 td(on)
ID = 1 A
TJ = 25°C
4 200 tr
2 100
Q3 VDS
0 0 1
0 1 2 3 4 5 6 7 8 1 10 100

1
VGS = 0 V
TJ = 25°C
0.8
0.6
0.4
0.2
0
0.5 0.54 0.58 0.62 0.66 0.7 0.74 0.78 0.82
SAFE OPERATING AREA

temperature.

MTD1N60E
SAFE OPERATING AREA
10 50
EAS, SINGLE PULSE DRAINN–TO–SOURCE

VGS = 20 V
ID = 1 A
SINGLE PULSE
10 µs
TC = 25°C 40

1
100 µs 30
0.1
1 ms dc
20
10 ms
0.01
RDS(on) LIMIT 10
THERMAL LIMIT
PACKAGE LIMIT
0.001 0
0.1 1 10 100 1000 25 50 75 100 125 150
1
D = 0.5
0.2
0.1
0.1 P(pk)
PULSE TRAIN SHOWN
0.01
t1 READ TIME AT t1
0.01
1.0E–05 1.0E–04 1.0E–03 1.0E–02 1.0E–01 1.0E+00 1.0E+01
t,TIME (s)
di/dt
IS
trr
ta tb
TIME
tp 0.25 IS
IS

MOTOROLA
 Data Sheet
Designer's
MTD1N80E

800 VOLTS
This high voltage MOSFET uses an advanced termination RDS(on) = 12 OHM
commutation modes. The new energy efficient design also offers a 
D
G
DPAK
Fast Recovery Diode S

(VDD = 100 Vdc, VGS = 10 Vdc, IL = 2.0 Apk, L = 10 mH, RG = 25 Ω) 20
Thermal Resistance — Junction to Ambient, when mounted to minimum recommended pad size RθJA 71.4
REV 1

MTD1N80E
OFF CHARACTERISTICS
(VGS = 0 Vdc, ID = 0.250 µAdc) 800 — —
(VDS = 800 Vdc, VGS = 0 Vdc) — — 10
(VDS = VGS, ID = 250 µAdc) 2.0 3.3 4.0
Static Drain–to–Source On–Resistance (VGS = 10 Vdc, ID = 0.5 Adc) RDS(on) — 10.3 12 Ohm
(VGS = 10 Vdc, ID = 1.0 Adc) — 11 14.4
(VGS = 10 Vdc, ID = 0.5 Adc, TJ = 125°C) — — 12.6
Vd VGS = 0 Vdc,
Vd
Coss — 29 40
f = 1.0 MHz)

VGS = 10 Vdc
Vdc,
((VDS = 400 Vdc, ID = 1.0 Adc, Q1 — 2.1 —

VGS = 10 Vdc) Q2 — 4.2 —
Q3 — 4.7 —
— 0.82 1.2
(IS = 1.0 Adc, VGS = 0 Vdc, TJ = 125°C)
— 0.7 —
((IS = 1.0 Adc, VGS = 0 Vdc, ta — 56 —

dIS/dt = 100 A/µs) tb — 261 —


MTD1N80E
2.0 TJ = 25°C 2.0

VDS ≥ 10 V

1.6 VGS = 10 V 1.6
6V
1.2 8V 1.2
0.8 0.8
5V
TJ = 100°C
0.4 0.4 25°C
4V
–55°C
0 0
0 5 10 15 20 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0


18 16
VGS = 10 V TJ = 25°C
15 100°C 15
14
12
TJ = 25°C 13
9
12 VGS = 10 V
6
–55°C 11
15 V
3
10
0 9
0 0.25 0.50 0.75 1.0 1.25 1.50 1.75 2.0 0 0.4 0.8 1.2 1.6 2.0
2.5 1000
ID = 0.5 A
2 TJ = 125°C
100 100°C
(NORMALIZED)
1.5
10
1
25°C
1
0.5
0 0.1
– 50 – 25 0 25 50 75 100 125 150 0 100 200 300 400 500 600 700 800


MTD1N80E
700 1000
TJ = 25°C TJ = 25°C
VGS = 0 V VGS = 0 Ciss
600
C, CAPACITANCE (pF)
500
C, CAPACITANCE (pF)
100
400
Ciss
Coss
300
10
200
Coss Crss
100
Crss
0 1
0 5 10 15 20 25 10 100 1000

MTD1N80E
12 400 100

VDD = 400 V
QT ID = 1 A
10
VGS = 10 V
VGS 300 TJ = 25°C tf
8
t, TIME (ns)
td(off)
6 200 10 td(on)
tr
Q1 Q2
4
ID = 1 A 100
2 TJ = 25°C
Q3 VDS
0 0 1
0 2 4 6 8 10 1 10 100

1.0
VGS = 0 V
TJ = 25°C
0.8
0.6
0.4
0.2
0
0.40 0.45 0.50 0.55 0.60 0.65 0.70 0.75 0.80 0.85
SAFE OPERATING AREA
temperature.

MTD1N80E
SAFE OPERATING AREA
10 20

VGS = 20 V
10 µs ID = 1 A
SINGLE PULSE
TC = 25°C

15
1
100 µs
10
1 ms
10 ms
0.1
dc
5
RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT
0.01 0
0.1 1 10 100 1000 25 50 75 100 125 150
D = 0.5
0.2
(NORMALIZED)
0.1
0.1 0.05 P(pk)
0.01
0.00001 0.0001 0.001 0.01 0.1 1 10
t, TIME (SECONDS)
di/dt
IS
trr
ta tb
TIME
tp 0.25 IS
IS

MOTOROLA
Product Preview MTD1P50E


P–Channel Enhancement–Mode Silicon Gate
TMOS POWER FET
This advanced high voltage TMOS E–FET is designed to 1.0 AMPERES
withstand high energy in the avalanche mode and switch efficiently. 500 VOLTS
This new high energy device also offers a drain–to–source diode 15 Ω
switching applications such as power supplies, PWM motor
controls and other inductive loads, the avalanche energy capability
is specified to eliminate the guesswork in designs where inductive 
loads are switched and offer additional safety margin against
• Avalanche Energy Capability Specified at Elevated
Temperature D
• Low Stored Gate Charge for Efficient Switching
• Internal Source–to–Drain Diode Designed to Replace External
Zener Transient Suppressor–Absorbs High Energy in the
Avalanche Mode
G
• Source–to–Drain Diode Recovery Time Comparable to Discrete CASE 369A–13, Style 2
Fast Recovery Diode DPAK Surface Mount
S
Gate–to–Source Voltage — Single Pulse (tp ≤ 50 µs) VGSM ± 40
Drain Current — Continuous @ TC = 25°C ID 1.0 Adc
Drain Current — Continuous @ TC = 100°C ID 0.8
Total Power Dissipation @ TC = 25°C, when mounted to minimum recommended pad size 1.75 Watts
UNCLAMPED DRAIN–TO–SOURCE AVALANCHE CHARACTERISTICS (TJ < 150°C)

Thermal Resistance — Junction to Ambient (1) RθJA 71.4

MTD1P50E
OFF CHARACTERISTICS
Temperature Coefficient (Positive) — TBD — V/°C
(VDS = 500 Vdc, VGS = 0 Vdc) — — 10
ON CHARACTERISTICS*
(VDS = VGS, ID = 0.25 mAdc) 2.0 3.1 4.0 Vdc
Static Drain–to–Source On–Resistance (VGS = 10 Vdc, ID = 0.5 Adc) RDS(on) — 12 15 Ohms
(ID = 1.0 Adc) — — 18
(ID = 0.5 Adc, TJ = 125°C) — — 15.8
Input Capacitance Ciss — TBD TBD pF
Vd VGS = 0 Vdc,
Vd
Coss — TBD TBD
f = 1.0 MHz)
Transfer Capacitance Crss — TBD TBD
SWITCHING CHARACTERISTICS*
Turn–On Delay Time td(on) — TBD TBD ns
Rise Time (VDS = 250 Vdc, ID = 1.0 Adc, tr — TBD TBD
VGS = 10 Vdc
Vdc,
Turn–Off Delay Time RG = 9.1 Ω) td(off) — TBD TBD
Fall Time tf — TBD TBD
Gate Charge QT — TBD TBD nC
((VDS = 400 Vdc, ID = 1.0 Adc, Q1 — TBD —

VGS = 10 Vdc) Q2 — TBD —
Q3 — TBD —
— 2.0 3.5
(IS = 1.0 Adc, VGS = 0 Vdc, TJ = 125°C)
— TBD —
Reverse Recovery Time trr — TBD — ns
((IS = 1.0 Adc, ta — TBD —

dIS/dt = 100 A/µs) tb — TBD —
Reverse Recovery Stored Charge QRR — TBD — µC
* Pulse Test: Pulse Width ≤ 300 µs, Duty Cycle ≤ 2%.

MOTOROLA
 Data Sheet
Designer's
MTD2N40E

400 VOLTS
This advanced high voltage TMOS E–FET is designed to RDS(on) = 3.5 OHM
withstand high energy in the avalanche and switch efficiently. This
new high energy device also offers a drain–to–soure diode with fast
recovery time. Designed for high voltage, high speed switching
applications such as power supplies, PWM motor controls and

voltage transients.
DPAK
• Avalanche Energy Specified D
• IDSS and VDS(on) Specified at Elevated Temperature G
S
• Replaces MTD1N40E

Drain Current — Continuous @ TC = 25°C ID 2.0 Adc
Total Power Dissipation @ TC = 25°C, when mounted to minimum recommended pad size 1.75 Watts

MTD2N40E
OFF CHARACTERISTICS
(VDS = 400 Vdc, VGS = 0 Vdc) — — 10
(VDS = VGS, ID = 0.25 mA) 2.0 3.2 4.0 Vdc
(ID = 2.0 Adc) — 7.3 8.4
(ID = 1.0 Adc, TJ = 125°C) — — 7.4
Vd VGS = 0 Vdc,
Vd
Coss — 34 40
f = 1.0 MHz)

VGS = 10 Vdc
Vdc,
((VDS = 320 Vdc, ID = 2.0 Adc, Q1 — 2.6 —

VGS = 10 Vdc) Q2 — 3.2 —
Q3 — 5.0 —
— 0.88 1.2
(IS = 2.0 Adc, VGS = 0 Vdc, TJ = 125°C)
— 0.76 —
((IS = 2.0 Adc, VGS = 0 Vdc, ta — 99 —

dIS/dt = 100 A/µs) tb — 57 —


MTD2N40E
4 4
TJ = 25°C VGS = 10 V VDS ≥ 10 V
8V

3.2
3
7V
2.4
2
1.6 6V
1
0.8
5V TJ = 100°C 25°C
–55°C
0 0
0 4 8 12 16 20 2 3 4 5 6 7 8


8 5.0
VGS = 10 V TJ = 25°C
4.5
6
100°C
4.0
4 TJ = 25°C VGS = 10 V
3.5
15 V
2 –55°C
3.0
0 2.5
0 1 2 3 4 0 0.5 1 1.5 2 2.5 3 3.5 4
2.5 1000
ID = 1 A
2
TJ = 125°C
(NORMALIZED)
1.5
100
1
0.5
0 10
– 50 – 25 0 25 50 75 100 125 150 0 100 200 300 400

MTD2N40E
500 1000
VDS = 0 V VGS = 0 V TJ = 25°C TJ = 25°C
VGS = 0 V
Ciss
400
Ciss
C, CAPACITANCE (pF)
C, CAPACITANCE (pF)
100
300
Ciss
Crss Coss
200
10
Crss
100 Coss
Crss
0 1
10 5 0 5 10 15 20 25 10 100 1000
VGS VDS

MTD2N40E

100

12 400 TJ = 25°C
QT ID = 2 A
10 VDD = 200 V
300 VGS = 10 V
VGS
8
t, TIME (ns)
td(off)
6 200 10 tf
Q1 Q2
tr td(on)
4
TJ = 25°C 100
2 ID = 2 A
Q3 VDS
0 0 1
0 2 4 6 8 1 10 100


2
VGS = 0 V
TJ = 25°C
1.5
0.5
0
0.5 0.6 0.7 0.8 0.9
SAFE OPERATING AREA
temperature.

MTD2N40E
SAFE OPERATING AREA
10 45

VGS = 20 V ID = 2 A
40
SINGLE PULSE 10 µs

TC = 25°C 35
1 100 µs 30
1 ms
25
10 ms
20
0.1 dc 15
RDS(on) LIMIT 10
THERMAL LIMIT
5
PACKAGE LIMIT
0.01 0
0.1 1 10 100 1000 25 50 75 100 125 150
D = 0.5
0.2
0.1
0.1 0.05 P(pk)
0.01
0.00001 0.0001 0.001 0.01 0.1 1 10
t, TIME (SECONDS)
di/dt
IS
trr
ta tb
TIME
tp 0.25 IS
IS

MOTOROLA
 Data Sheet
Designer's
TMOS E-FET. MTD2N50E

DPAK for Surface Mount

TMOS POWER FET
This high voltage MOSFET uses an advanced termination 2.0 AMPERES
scheme to provide enhanced voltage–blocking capability without 500 VOLTS
degrading performance over time. In addition this advanced TMOS RDS(on) = 3.6 OHM
drain–to–source diode with a fast recovery time. Designed for high 
D
• Diode is Characterized for Use in Bridge Circuits G
• IDSS and VDS(on) Specified at Elevated Temperature DPAK
• Surface Mount Package Available in 16 mm, 13–inch/2500 S
• Replaces MTD2N50

REV 1

MTD2N50E
OFF CHARACTERISTICS
(VDS = 500 Vdc, VGS = 0 Vdc) — — 0.1
(ID = 2.0 Adc) — 6.0 8.64
(ID = 1.0 Adc, TJ = 125°C) — — 6.48
Vd VGS = 0 Vdc,
Vd
Coss — 45 63
f = 1.0 MHz)

VGS = 10 Vdc
Vdc,
(See Figure 8)
(VDS = 400 Vdc, ID = 2.0 Adc, Q1 — 2.0 —
VGS = 10 Vdc)
Q2 — 5.4 —
Q3 — 5.1 —

— 0.8 1.6
(IS = 2.0 Adc, VGS = 0 Vdc, TJ = 125°C)
— 0.69 —
(See Figure
Fig re 14)
((IS = 2.0 Adc, VGS = 0 Vdc, ta — 62 —
dIS/dt = 100 A/µs) tb — 272 —



MTD2N50E
4 4.0
TJ = 25°C VGS = 10 V VDS ≥ 10 V
3.5 25°C
6V TJ = –55°C

3 3.0
100°C
2.5
2 2.0
1.5
5V
1 1.0
0.5
0 0
0 2 4 6 8 10 12 14 16 18 20 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0


8 4.2
VGS = 10 V TJ = 25°C
7
6 TJ = 100°C 3.8
4 3.4
25°C
VGS = 10 V
3
2 – 55°C 3.0
15 V
1
0 2.6
0 0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.2 3.6 4.0 0 0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.2 3.6 4.0
2.0 1000
ID = 1 A
TJ = 125°C
1.6
100
(NORMALIZED)
100°C
1.2
25°C
10
0.8
0.4 1
–50 –25 0 25 50 75 100 125 150 0 50 100 150 200 250 300 350 400 450 500


MTD2N50E
700 1000
Ciss Ciss
600
500
C, CAPACITANCE (pF)
C, CAPACITANCE (pF)
100
400
Ciss Coss
Crss
300
10
200 Crss
100 Coss
Crss
0 1
10 5 0 5 10 15 20 25 10 100 1000
GATE–TO–SOURCE OR DRAIN–TO–SOURCE VOLTAGE (VOLTS) Figure 7b. High Voltage Capacitance

MTD2N50E
18 450 100

ID = 2 A VDD = 250 V
16 400 ID = 2 A
TJ = 25°C
14 350 VGS = 10 V
TJ = 25°C
12 300
t, TIME (ns)
QT
td(off)
10 250
VGS 10 tf
8 200 td(on)
Q1 Q2
6 150 tr
4 100
2 50
Q3 VDS
0 0 1
0 1 2 3 4 5 6 7 8 9 10 1 10 100

2.0
VGS = 0 V
TJ = 25°C
1.6
1.2
0.8
0.4
0
0.50 0.55 0.60 0.65 0.70 0.75 0.80 0.85
SAFE OPERATING AREA
temperature.

MTD2N50E
SAFE OPERATING AREA
10 100
VGS = 20 V

ID = 2 A
SINGLE PULSE
TC = 25°C 80

1.0 10 µs
60
100 µs
1 ms
40
0.1 10 ms
dc
RDS(on) LIMIT 20
THERMAL LIMIT
PACKAGE LIMIT
0.01 0
0.1 1.0 10 100 1000 25 50 75 100 125 150
1.0
D = 0.5
0.2
0.1
0.1 P(pk)
t1 READ TIME AT t1
0.01
0.01
1.0E–05 1.0E–04 1.0E–03 1.0E–02 1.0E–01 1.0E+00 1.0E+01
t, TIME (s)
di/dt
IS
trr
ta tb
TIME
tp 0.25 IS
IS

MOTOROLA
 Data Sheet
Designer's


TMOS POWER FET
This advanced TMOS E–FET is designed to withstand high 3 AMPERES
energy in the avalanche and commutation modes. The new energy 250 VOLTS
efficient design also offers a drain–to–source diode with a fast RDS(on) = 1.4 OHM
recovery time. Designed for low voltage, high speed switching

voltage transients.
D
Unit Tape & Reel, Add T4 Suffix to Part Number G CASE 369A–13, Style 2
DPAK
S
(VDD = 25 Vdc, VGS = 10 Vdc, IL = 3.0 Apk, L = 10 mH, RG = 25 Ω )
REV 2

MTD3N25E
OFF CHARACTERISTICS
(VDS = 250 Vdc, VGS = 0 Vdc) — — 10
(ID = 3.0 Adc) — — 5.04
(ID = 1.5 Adc, TJ = 125°C) — — 4.41
Vd VGS = 0 Vdc,
Vd
Coss — 57 75
f = 1.0 MHz)
VGS = 10 Vdc
Vdc,
Turn–Off Delay Time RG = 4.7 Ω)) td(off) — 15 30
(S Fi
(See Figure 8)
((VDS = 200 Vdc, ID = 3.0 Adc, Q1 — 2.1 —
VGS = 10 Vdc) Q2 — 4.2 —
Q3 — 3.8 —
— 0.9 1.6
(IS = 3.0 Adc, VGS = 0 Vdc, TJ = 125°C)
— 0.728 —
(S Fi
(See Figure 14)
((IS = 3.0 Adc, VGS = 0 Vdc, ta — 64 —
dIS/dt = 100 A/µs) tb — 89 —

MTD3N25E
6 6
TJ = 25°C VDS ≥ 10 V TJ = – 55°C
VGS = 10 V
5 5

25°C
7V
4 4
6V 100°C
3 3
2 2
5V
1 1
4V
0 0
0 1 2 3 4 5 6 7 8 9 10 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 7.5


3.2 1.7
VGS = 10 V TJ = 25°C
2.8 1.6
2.4 1.5
2.0 TJ = 100°C
1.4
1.6 1.3
25°C
1.2 1.2 VGS = 10 V
0.8 1.1
– 55°C 15 V
0.4 1.0
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
2.0 100
VGS = 0 V TJ = 125°C
VGS = 10 V
ID = 1.5 A
1.6 100°C
(NORMALIZED)
1.2 10
25°C
0.8
0.4 1.0
– 50 – 25 0 25 50 75 100 125 150 0 50 100 150 200 250


MTD3N25E
800
VDS = 0 VGS = 0 TJ = 25°C
Ciss
700
600
C, CAPACITANCE (pF)
500
Crss
400 Ciss
300
200 Coss
100 Crss
0
10 5 0 5 10 15 20 25
VGS VDS

MTD3N25E
12 240 100

VDD = 125 V

QT
ID = 3 A
10 200 VGS = 10 V
TJ = 25°C
8 VGS 160
t, TIME (ns)
Q1 Q2 td(off)
6 120 10
tf td(on)
4 TJ = 25°C 80 tr
ID = 3 A
2 40
Q3 VDS
0 0 1
0 1 2 3 4 5 6 7 8 9 10 1 10 100

Voltage versus Ttotal Charge Variation versus Gate Resistance
3.0
VGS = 0 V
2.5 TJ = 25°C
2.0
1.5
1.0
0.5
0
0.5 0.55 0.6 0.65 0.7 0.75 0.8 0.85 0.9
SAFE OPERATING AREA
temperature.

MTD3N25E
SAFE OPERATING AREA
10 45
10 µs

VGS = 20 V 40 ID = 3 A
SINGLE PULSE
35

TC = 25°C 100 µs
1.0 30
1 ms
25
10 ms
20
ds
0.1 15
RDS(on) LIMIT 10
THERMAL LIMIT
PACKAGE LIMIT 5
0.01 0
0.1 1.0 10 100 1000 25 50 75 100 125 150
1.0
D = 0.5
0.2
0.1
0.1 P(pk)
PULSE TRAIN SHOWN
0.02
t1 READ TIME AT t1
0.01
1.0E–05 1.0E–04 1.0E–03 1.0E–02 1.0E–01 1.0E+00 1.0E+01
t, TIME (s)
di/dt
IS
trr
ta tb
TIME
tp 0.25 IS
IS

MOTOROLA
 Data Sheet
Designer's
MTD4N20E

200 VOLTS
This advanced TMOS E–FET is designed to withstand high RDS(on) = 1.2 OHM
energy in the avalanche and commutation modes. The new energy
efficient design also offers a drain–to–source diode with a fast

voltage transients. D
DPAK

— Non–repetitive (tp ≤ 10 ms) VGSM ± 40 Vpk
REV 1

MTD4N20E
OFF CHARACTERISTICS
(VDS = 200 Vdc, VGS = 0 Vdc) — — 10
(ID = 4.0 Adc) — 3.5 5.8
(ID = 2.0 Adc, TJ = 125°C) — — 5.0
(VDS = 25 Vdc,
Vd VGS = 0 Vdc,
Vd
Output Capacitance Coss — 66 80
f = 1.0 MHz)

VGS = 10 Vdc
Vdc,
(See Fig
Figure
re 8)
((VDS = 160 Vdc, ID = 4.0 Adc, Q1 — 2.4 —
VGS = 10 Vdc) Q2 — 4.1 —
Q3 — 5.6 —
— 0.92
(IS = 4.0 Adc, VGS = 0 Vdc, TJ = 125°C)
— 0.82 —
(See Figure
Fig re 14)
((IS = 4.0 Adc, VGS = 0 Vdc, ta — 82 —
dIS/dt = 100 A/µs) tb — 41 —


MTD4N20E
8 8
TJ = 25°C VGS = 10 V VDS ≥ 10 V TJ = – 55°C
7 8V 7

9V
6 6 25°C
7V
5 5 100°C
4 4
3 6V 3
2 2
1 5V 1
0 0
0 2 4 6 8 10 12 14 2 3 4 5 6 7 8 9

4.5 2.8
VGS = 10 V TJ = 25°C
4.0 2.4
3.5
2.0
3.0
2.5 1.6
VGS = 10 V
2.0 TJ = 100°C 1.2
1.5 15 V
0.8
1.0
25°C
0.5 0.4
– 55°C
0 0
0 1 2 3 4 5 6 7 8 0 1 2 3 4 5 6 7 8
100
2.5
VGS = 10 V VGS = 0 V TJ = 125°C
ID = 4 A
2.0 100°C
I DSS, LEAKAGE (nA)
(NORMALIZED)
1.5
10
1.0
25°C
0.5
0 1
– 50 – 25 0 25 50 75 100 125 150 0 50 100 150 200 250


MTD4N20E
800
VDS = 0 V VGS = 0 V TJ = 25°C
600 Ciss
C, CAPACITANCE (pF)
400
Crss Ciss
200
Coss
Crss
0
10 5 0 5 10 15 20 25
VGS VDS

MTD4N20E

18 100

180
VDD = 100 V
16 160 ID = 4 A
QT
14 140 VGS = 10 V
TJ = 25°C
12 120
t, TIME (ns)
10 VGS 100 td(off)
Q1 Q2 10 td(on)
8 80
6 60 tf
ID = 4 A
4 TJ = 25°C 40
2 20 tr
Q3 VDS
0 0 1
0 2 4 6 8 10 1 10 100


4.0
VGS = 0 V
TJ = 25°C
3.2
2.4
1.6
0.8
0
0.50 0.55 0.60 0.65 0.70 0.75 0.80 0.85 0.90 0.95
SAFE OPERATING AREA

temperature.

MTD4N20E
SAFE OPERATING AREA
100 80

VGS = 20 V ID = 4 A
SINGLE PULSE

TC = 25°C
10 60
10 µs
100 µs
1.0 40
1 ms
10 ms
dc
0.1 20
RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT
0.01 0
0.1 1.0 10 100 1000 25 50 75 100 125 150
1.0
D = 0.5
0.2
0.1
0.05
0.1 P(pk)
0.01
1.0E–05 1.0E–04 1.0E–03 1.0E–02 1.0E–01 1.0E+00 1.0E+01
t, TIME (s)
di/dt
IS
trr
ta tb
TIME
tp 0.25 IS
IS

MOTOROLA
 Data Sheet
Designer's
MTD5N25E

250 VOLTS
controls, these devices are particularly well suited for bridge circuits 
DPAK
Unit Tape & Reel, Add – T4 Suffix to Part Number

REV 1

MTD5N25E
OFF CHARACTERISTICS
(VDS = 250 Vdc, VGS = 0 Vdc) — — 10
(ID = 5.0 Adc) — 3.4 6.0
(ID = 2.5 Adc, TJ = 125°C) — — 5.3
Vd VGS = 0 Vdc,
Vd
Coss — 66 90
f = 1.0 MHz)

VGS = 10 Vdc
Vdc,
(See Fig
Figure
re 8)
((VDS = 200 Vdc, ID = 5.0 Adc, Q1 — 2.9 —
VGS = 10 Vdc) Q2 — 6.2 —
Q3 — 5.9 —
— 0.93 1.6
(IS = 5.0 Adc, VGS = 0 Vdc, TJ = 125°C)
— 0.82 —
(See Figure
Fig re 14)
((IS = 5.0 Adc, VGS = 0 Vdc, ta — 100 —
dIS/dt = 100 A/µs) tb — 47 —


MTD5N25E
10 10
TJ = 25°C VGS = 10 V VDS ≥ 10 V TJ = –55°C
9V 8V

8 8
7V
6 6 25°C
100°C
6V
4 4
2 2
5V
0 0
0 2 4 6 8 10 12 14 16 18 2 3 4 5 6 7 8


3.5 1.7
VGS = 10 V TJ = 25°C
3.0
1.5
2.5
1.3
2.0
TJ = 100°C VGS = 10 V
1.5 1.1
25°C
1.0 15 V
– 55°C 0.9
0.5
0 0.7
0 1 2 3 4 5 6 7 8 9 10 0 1 2 3 4 5 6 7 8 9 10
2.5 100
ID = 2.5 A TJ = 125°C
2.0
100°C
(NORMALIZED)
1.5
10
1.0
25°C
0.5
0 1
–50 –25 0 25 50 75 100 125 150 0 50 100 150 200 250


MTD5N25E
Switching behavior is most easily modeled and predicted by The capacitance (Ciss) is read from the capacitance curve at a
recognizing that the power MOSFET is charge controlled. The voltage corresponding to the off–state condition when calculat-
lengths of various switching intervals (∆t) are determined by ing td(on) and is read at a voltage corresponding to the on–state
how fast the FET input capacitance can be charged by current when calculating td(off).
from the generator.
ing rise and fall because drain–gate capacitance varies greatly complicate the analysis. The inductance of the MOSFET
with applied voltage. Accordingly, gate charge data is used. In source lead, inside the package and in the circuit wiring which
most cases, a satisfactory estimate of average input current is common to both the drain and gate current paths, produces
(IG(AV)) can be made from a rudimentary analysis of the drive a voltage at the source which reduces the gate drive current.
circuit so that The voltage is determined by Ldi/dt, but since di/dt is a function
t = Q/IG(AV) of drain current, the mathematical solution is complex. The
MOSFET output capacitance also complicates the mathemat-
During the rise and fall time interval when switching a resistive
ics. And finally, MOSFETs have finite internal gate resistance
load, VGS remains virtually constant at a level known as the
which effectively adds to the resistance of the driving source,
plateau voltage, VSGP. Therefore, rise and fall times may be
but the internal resistance is difficult to measure and,
approximated by the following:
consequently, is not specified.
tr = Q2 x RG/(VGG – VGSP) The resistive switching time variation versus gate
tf = Q2 x RG/VGSP resistance (Figure 9) shows how typical switching perform-
where ance is affected by the parasitic circuit elements. If the para-
sitics were not present, the slope of the curves would
VGG = the gate drive voltage, which varies from zero to VGG maintain a value of unity regardless of the switching speed.
RG = the gate drive resistance The circuit used to obtain the data is constructed to minimize
and Q2 and VGSP are read from the gate charge curve. common inductance in the drain and gate circuit loops and is
believed readily achievable with board mounted components.
During the turn–on and turn–off delay times, gate current is not
Most power electronic loads are inductive; the data in the
constant. The simplest calculation uses appropriate values
figure is taken with a resistive load, which approximates an
from the capacitance curves in a standard equation for volt-
optimally snubbed inductive load. Power MOSFETs may be
age change in an RC network. The equations are:
safely operated into an inductive load; however, snubbing
td(on) = RG Ciss In [VGG/(VGG – VGSP)] reduces switching losses.
1000 VDS = 0 V VGS = 0 V TJ = 25°C
800 Ciss
C, CAPACITANCE (pF)
600
Ciss
400 Crss
200
Coss
Crss
0
10 5 0 5 10 15 20 25
VGS VDS

MTD5N25E
12 300 100

VDD = 125 V

QT
ID = 5 A
10 250 VGS = 10 V
VGS TJ = 25°C
8 200 td(off) tf
t, TIME (ns)
Q1 Q2 tr
6 150 10 td(on)
4 ID = 5 A 100
TJ = 25°C
2 50
Q3
VDS
0 0 1
0 2 4 6 8 10 12 14 1 10 100

5
VGS = 0 V
TJ = 25°C
0
0.5 0.55 0.6 0.65 0.7 0.75 0.8 0.85 0.9 0.95
SAFE OPERATING AREA

The Forward Biased Safe Operating Area curves define the operation, the stored energy from circuit inductance
temperature.
(IDM) nor rated voltage (VDSS) is exceeded and the transition current (IDM), the energy rating is specified at rated continuous
time (tr,tf) do not exceed 10 µs. In addition the total power current (ID), in accordance with industry custom. The energy
averaged over a complete switching cycle must not exceed rating must be derated for temperature as shown in the
(TJ(MAX) – TC)/(RθJC). accompanying graph (Figure 12). Maximum energy at
A Power MOSFET designated E–FET can be safely used in currents below rated continuous ID can safely be assumed to
switching circuits with unclamped inductive loads. For reliable equal the values indicated.

MTD5N25E
SAFE OPERATING AREA
100 120
VGS = 20 V

TC = 25°C
80

10 10 µs
60
100 µs
40
1
1 ms
RDS(on) LIMIT 10 ms 20
THERMAL LIMIT dc
PACKAGE LIMIT
0.1 0
0.1 1.0 10 100 1000 25 50 75 100 125 150
1.0
D = 0.5
0.2
0.1
0.1 0.05
P(pk)
t1 READ TIME AT t1
0.01
0.00001 0.0001 0.001 0.01 0.1 1.0 10
t, TIME (s)
di/dt
IS
trr
ta tb
TIME
tp 0.25 IS
IS

MOTOROLA

MTD5P06V
TMOS V.

TMOS POWER FET
60 VOLTS
TM
MOSFETs with New Low Voltage, Low RDS(on) Technology G CASE 369A–13, Style 2
• Faster Switching than E–FET Predecessors DPAK Surface Mount
Features Common to TMOS V and TMOS E–FETS S

• Surface Mount Package Available in 16 mm, 13–inch/2500 Unit Tape & Reel,
Add –T4 Suffix to Part Number
Derate above 25°C 0 27
0.27 W/°C
(VDD = 25 Vdc, VGS = 10 Vdc, PEAK IL = 5 Apk, L = 10 mH, RG = 25 Ω)
REV 1

MTD5P06V
OFF CHARACTERISTICS
(VGS = 0 Vdc, ID = 0.25 mAdc) 60 — —
(VDS = 60 Vdc, VGS = 0 Vdc) — — 10
(VDS = VGS, ID = 250 µAdc) 2.0 2.8 4.0
(VGS = 10 Vdc, ID = 5 Adc) — — 2.7
(VGS = 10 Vdc, ID = 2.5 Adc, TJ = 150°C) — — 2.6
(VDS = 15 Vdc, ID = 2.5 Adc) 1.5 3.6 —
Vd VGS = 0 Vdc,
Vd
Coss — 140 200
f = 1.0 MHz)
VGS = 10 Vdc
Vdc,
(See Fig
Figure
re 8)
((VDS = 48 Vdc, ID = 5 Adc, Q1 — 3.0 —
VGS = 10 Vdc) Q2 — 5.0 —
Q3 — 5.0 —

— 1.72 3.5
(IS = 5 Adc, VGS = 0 Vdc, TJ = 150°C)
— 1.34 —
((IS = 5 Adc, VGS = 0 Vdc, ta — 73 —

dIS/dt = 100 A/µs) tb — 24 —



MTD5P06V
10 10
VGS = 10V 8V VDS ≥ 10 V TJ = –55°C
9V 7V 9
25°C

8 TJ = 25°C 8 100°C
7
6V
6 6
5
4 4
3
5V
2 2
4V 1
0 0
0 1 2 3 4 5 6 7 8 9 2 3 4 5 6 7 8


0.6 0.4
VGS = 10 V TJ = 25°C
0.55
TJ = 100°C VGS = 10 V
0.5 0.35
0.45
0.4 0.3 15 V
25°C
0.35
0.3 0.25
0.25 – 55°C
0.2 0.2
1 2 3 4 5 6 7 8 9 10 1 2 3 4 5 6 7 8 9 10
1.8 100
1.6 ID = 2.5 A
1.4
(NORMALIZED)
1.2
1 10 TJ = 125°C
0.8
0.6
0.4
0.2 1
–50 –25 0 25 50 75 100 125 150 175 0 10 20 30 40 50 60


MTD5P06V
1000
VDS = 0 V TJ = 25°C
900 Ciss
800
C, CAPACITANCE (pF)
700
600 Crss
500
400 Ciss
300 Coss
200
100 Crss
VGS = 0 V
0
10 5 0 5 10 15 20 25
VGS VDS

MTD5P06V
10 60 100

VGS TJ = 25°C
9 QT 54
ID = 5 A
8 48 VDD = 30 V
7 Q2 42 VGS = 10 V tr
Q1
t, TIME (ns)
6 td(off)
36
tf
5 30 10 td(on)
4 24
3 18
2 Q3 TJ = 25°C 12
1 VDS ID = 5 A 6
0 0 1
0 2 4 6 8 10 12 14 1 10 100

5
4.5 TJ = 25°C
VGS = 0 V
4
3.5
3
2.5
2
1.5
1
0.5
0
0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8
SAFE OPERATING AREA
perature.

MTD5P06V
SAFE OPERATING AREA
100 140
VGS = 20 V ID = 5 A

SINGLE PULSE
120
TC = 25°C

100
10
80
100 µs
60
1 ms
1 10 ms 40
RDS(on) LIMIT dc
THERMAL LIMIT 20
PACKAGE LIMIT
0.1 0
0.1 1 10 100 25 50 75 100 125 150 175
1.0
D = 0.5
0.2
0.1
0.1 P(pk)
0.05
0.01
1.0E–05 1.0E–04 1.0E–03 1.0E–02 1.0E–01 1.0E+00 1.0E+01
t, TIME (s)
di/dt
IS
trr
ta tb
TIME
tp 0.25 IS
IS

MOTOROLA
 Data Sheet
Designer's
MTD6N10E

100 VOLTS
controls, these devices are particularly well suited for bridge circuits 
Fast Recovery Diode
• Replaces MTD5N10

(VDD = 25 Vdc, VGS = 10 Vdc, IL = 6.0 Apk, L = 3.0 mH, RG =25 Ω)
REV 1

MTD6N10E
OFF CHARACTERISTICS
(VDS = 100 Vdc, VGS = 0 Vdc) — — 10
(ID = 6.0 Adc) — 1.75 2.9
(ID = 3.0 Adc, TJ = 125°C) — — 2.5
(VDS = 25 Vdc,
Vd VGS = 0 Vdc,
Vd
f = 1.0 MHz)

VGS = 10 Vdc
Vdc,
(See Fig
Figure
re 8)
((VDS = 80 Vdc, ID = 6.0 Adc, Q1 — 3.3 —
VGS = 10 Vdc) Q2 — 4.3 —
Q3 — 5.5 —
— 0.98 2.0
(IS = 6.0 Adc, VGS = 0 Vdc, TJ = 125°C)
— 0.9 —
(See Figure
Fig re 14)
((IS = 6.0 Adc, VGS = 0 Vdc, ta — 64 —
dIS/dt = 100 A/µs) tb — 22.7 —


MTD6N10E
12 12
TJ = 25°C VGS = 10 V VDS ≥ 10 V TJ = – 55°C
9V
10 10

25°C
8 8V 8 100°C
6 6
7V
4 4
6V
2 2
5V
0 0
0 1 2 3 4 5 6 7 8 2 3 4 5 6 7 8 9 10


0.65 0.45
VGS = 10 V TJ = 25°C
0.55 0.40
TJ = 100°C
0.45 VGS = 10 V
0.35
0.35 25°C 0.30
15 V
0.25 0.25
– 55°C
0.15 0.20
0 2 4 6 8 10 12 14 0 2 4 6 8 10 12 14 16
1.8 100
VGS = 10 V VGS = 0 V TJ = 125°C

ID = 3 A
1.6
100°C
1.4
(NORMALIZED)
1.2 10
25°C
1.0
0.8
0.6 1
– 50 – 25 0 25 50 75 100 125 150 0 20 40 60 80 100 120


MTD6N10E
During the rise and fall time interval when switching a resis- mathematics. And finally, MOSFETs have finite internal gate
800
VDS = 0 V VGS = 0 V TJ = 25°C
600 Ciss
C, CAPACITANCE (pF)
400
Ciss
Crss
200
Coss
Crss
0
10 5 0 5 10 15 20 25
VGS VDS

MTD6N10E
1000

12 120

QT VDD = 50 V
ID = 6 A
10 100 VGS = 10 V
VGS TJ = 25°C
8 Q1 Q2 80 100
t, TIME (ns)
6 60 tr
td(off)
4 ID = 6 A 40 10 tf
TJ = 25°C td(on)
2 20
Q3
VDS
0 0 1
0 2 4 6 8 10 1 10 100

6
VGS = 0 V
TJ = 25°C
5
0
0.50 0.55 0.60 0.65 0.70 0.75 0.80 0.85 0.90 0.95 1.0
SAFE OPERATING AREA
temperature.

MTD6N10E
SAFE OPERATING AREA
100 50
VGS = 20 V ID = 6 A

SINGLE PULSE 45
TC = 25°C
40

10 35
30
100 µs 25
1 ms 20
1.0 10 ms 15
RDS(on) LIMIT 10
dc
THERMAL LIMIT
PACKAGE LIMIT 5
0.1 0
0.1 1.0 10 100 25 50 75 100 125 150
1.0
D = 0.5
0.2
0.1
0.1 0.05 P(pk)
t1 READ TIME AT t1
0.01
1.0E–05 1.0E–04 1.0E–03 1.0E–02 1.0E–01 1.0E+00 1.0E+01
t, TIME (s)
di/dt
IS
trr
ta tb
TIME
tp 0.25 IS
IS

MOTOROLA
 Data Sheet
Designer's
Power Field Effect Transistor MTD6N15

TMOS POWER FET
This TMOS Power FET is designed for high speed, low loss 6.0 AMPERES
power switching applications such as switching regulators, convert- 150 VOLTS
ers, solenoid and relay drivers. RDS(on) = 0.3 OHM
• Silicon Gate for Fast Switching Speeds
• Low RDS(on) — 0.3 Ω Max 
• Rugged — SOA is Power Dissipation Limited
• Source–to–Drain Diode Characterized for Use With
Inductive Loads
• Low Drive Requirement — VGS(th) = 4.0 V Max D
• Surface Mount Package on 16 mm Tape
G CASE 369A–13, Style 2

DPAK (TO–252)
MAXIMUM RATINGS S

Gate–Source Voltage — Non–Repetitive (tp ≤ 50 µs) VGSM ± 40 Vpk
Total Power Dissipation @ TA = 25°C PD 1.25 Watts
Operating and Storage Junction Temperature Range TJ, Tstg – 65 to +150 °C

Characteristic Symbol Min Max Unit
OFF CHARACTERISTICS
Drain–Source Breakdown Voltage V(BR)DSS 150 — Vdc
(VGS = 0 Vdc, ID = 0.25 mAdc)

(VDS = Rated VDSS, VGS = 0 Vdc) — 10
TJ = 125°C — 100
(1) These ratings are applicable when surface mounted on the minimum pad size recommended. (continued)

MTD6N15
Characteristic Symbol Min Max Unit
OFF CHARACTERISTICS — continued
Gate–Body Leakage Current, Forward (VGSF = 20 Vdc, VDS = 0) IGSSF — 100 nAdc
Gate–Body Leakage Current, Reverse (VGSR = 20 Vdc, VDS = 0) IGSSR — 100 nAdc
ON CHARACTERISTICS*
Gate Threshold Voltage (VDS = VGS, ID = 1.0 mAdc) VGS(th) 2.0 4.5 Vdc
TJ = 100°C 1.5 4.0
Static Drain–Source On–Resistance (VGS = 10 Vdc, ID = 3.0 Adc) RDS(on) — 0.3 Ohm
(ID = 6.0 Adc) — 1.8
(ID = 3.0 Adc, TJ = 100°C) — 1.5
Forward Transconductance (VDS = 15 Vdc, ID = 3.0 Adc) gFS 2.5 — mhos
Input Capacitance Ciss — 1200 pF
(VDS = 25 Vdc, VGS = 0 Vdc,
Output Capacitance f = 1.0 MHz) Coss — 500
S Fi
See Figure 11
Reverse Transfer Capacitance Crss — 120
SWITCHING CHARACTERISTICS* (TJ = 100°C)
Turn–On Delay Time td(on) — 50 ns
Rise Time (VDD = 25 Vdc, ID = 3.0 Adc, tr — 180
RG = 50 Ω)
Turn–Off Delay Time See Figures 13 and 14 td(off) — 200
Fall Time tf — 100
Total Gate Charge Qg 15 (Typ) 30 nC
(VDS = 0.8 Rated VDSS,
Gate–Source Charge ID = Rated ID, VGS = 10 Vdc) Qgs 8.0 (Typ) —
S Figure
See Fi 12
Gate–Drain Charge Qgd 7.0 (Typ) —
SOURCE–DRAIN DIODE CHARACTERISTICS*

Forward On–Voltage VSD 1.3 (Typ) 2.0 Vdc
(IS = 6.0
6 0 Adc,
Ad di/dt = 25 A/µs
A/
Forward Turn–On Time ton Limited by stray inductance
VGS = 0 Vdc,)
Reverse Recovery Time trr 325 (Typ) — ns
* Pulse Test: Pulse Width ≤ 300 µs, Duty Cycle ≤ 2%.
TA TC
2.5 25
2 20
1.5 15 TC
1 10
0.5 5
0 0
25 50 75 100 125 150
T, TEMPERATURE (°C)
Figure 1. Power Derating

MTD6N15
24 3.6
VGS(th) , GATE THRESHOLD VOLTAGE (VOLTS)

10 V
20 9V VDS = VGS
3.2
TJ = 25°C ID = 1 mA
16
8V 2.8
12
2.4
8 7V
6V 2
4
5V
0
0 10 20 30 40 50 60 – 50 0 50 100 150
VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS) TJ, JUNCTION TEMPERATURE (°C)
Figure 2. On–Region Characteristics Figure 3. Gate–Threshold Voltage Variation

With Temperature
V(BR)DSS , DRAIN–TO–SOURCE BREAKDOWN VOLTAGE

14 2
VDS = 10 V TJ = 25°C VGS = 0 V
12 ID = 0.25 mA
1.6
10
(NORMALIZED)
8 1.2
6
0.8
4 100°C
– 55°C 0.4
2
0 0
4 6 8 10 – 50 0 50 100 150 200
Figure 4. Transfer Characteristics Figure 5. Breakdown Voltage Variation

With Temperature
0.30 2
VGS = 10 V VGS = 10 V
TJ = 100°C
0.25 ID = 3 A
1.6
0.20
(NORMALIZED)
25°C 1.2
0.15
– 55°C 0.8
0.10
0.4
0.05
0 0
0 4 8 12 16 20 – 50 0 50 100 150 200
ID, DRAIN CURRENT (AMPS) TJ, JUNCTION TEMPERATURE (°C)
Figure 6. On–Resistance versus Drain Current Figure 7. On–Resistance Variation

With Temperature

MTD6N15
SAFE OPERATING AREA
20
20
100 µs 10 µs
10

1 ms 15
5
2
10 ms
1 10 TJ ≤ 150°C
0.5 RDS(on) LIMIT
THERMAL LIMIT
0.2 PACKAGE LIMIT dc
5
0.1 TC = 25°C
0.05 VGS = 20 V SINGLE PULSE
0.03 0
0.3 0.5 0.7 1 2 3 5 7 10 20 30 50 70 100 200 300 0 20 40 60 80 100 120 140 160
Figure 8. Maximum Rated Forward Biased Figure 9. Maximum Rated Switching

FORWARD BIASED SAFE OPERATING AREA SWITCHING SAFE OPERATING AREA

The FBSOA curves define the maximum drain–to–source The switching safe operating area (SOA) of Figure 9 is the
voltage and drain current that a device can safely handle boundary that the load line may traverse without incurring
when it is forward biased, or when it is on, or being turned on. damage to the MOSFET. The fundamental limits are the
Because these curves include the limitations of simultaneous peak current, IDM and the breakdown voltage, V(BR)DSS. The
high voltage and high current, up to the rating of the device, switching SOA shown in Figure 8 is applicable for both turn–
they are especially useful to designers of linear systems. The on and turn–off of the devices for switching times less than
curves are based on a case temperature of 25°C and a maxi- one microsecond.
mum junction temperature of 150°C. Limitations for repetitive The power averaged over a complete switching cycle must
pulses at various case temperatures can be determined by be less than:
using the thermal response curves. Motorola Application
Note, AN569, “Transient Thermal Resistance–General Data TJ(max) – TC
and Its Use” provides detailed instructions. RθJC
THERMAL RESISTANCE (NORMALIZED)
0.7 D = 0.5
0.5
r(t), EFFECTIVE TRANSIENT
0.3 0.2
0.2
0.1
0.1 0.05 P(pk)
0.07 RθJC(t) = 6.25°C/W MAX
0.02
t1 PULSE TRAIN SHOWN
0.03
0.01 SINGLE PULSE t2 READ TIME AT t1
0.02 DUTY CYCLE, D = t1/t2 TJ(pk) – TC = P(pk) RθJC(t)
0.01
0.01 0.02 0.03 0.05 0.1 0.2 0.3 0.5 1 2 3 5 10 20 50 100 200 500 1000
t, TIME OR PULSE WIDTH (ms)

MTD6N15
2000 16
VGS, GATE SOURCE VOLTAGE (VOLTS)

TJ = 25°C TJ = 25°C
VGS = 0 ID = 6 A
1600
12
C, CAPACITANCE (pF)
75 V 120 V
1200
VDS = 50 V
8
800
VDS = 0 Ciss 4
400
Coss
Crss
0 0
15 10 5 0 5 10 15 20 3525 30 0 4 8 12 16 20
Figure 11. Capacitance Variation Figure 12. Gate Charge versus
Gate–To–Source Voltage
RESISTIVE SWITCHING
VDD
ton toff
RL td(on) tr td(off) tf
Vout 90% 90%
OUTPUT, Vout
Vin INVERTED
PULSE GENERATOR DUT
z = 50 Ω 10%
Rgen
50 Ω 90%
50 Ω
50% 50%
INPUT, Vin
10%
PULSE WIDTH

MOTOROLA
 Data Sheet
Designer's
MTD6N20E

200 VOLTS

DPAK
Unit Tape & Reel, Add –T4 Suffix to Part Number S


MTD6N20E
OFF CHARACTERISTICS
(VDS = 200 Vdc, VGS = 0 Vdc) — — 10
(ID = 6.0 Adc) — 2.9 5.0
(ID = 3.0 Adc, TJ = 125°C) — — 4.4
Vd VGS = 0 Vdc,
Vd
Coss — 92 130
f = 1.0 MHz)

VGS = 10 Vdc
Vdc,
Fall Time tf — 20 40.8
(See Fig
Figure
re 8)
((VDS = 160 Vdc, ID = 6.0 Adc, Q1 — 2.7 —
VGS = 10 Vdc) Q2 — 7.1 —
Q3 — 5.9 —
— 0.99 1.2
(IS = 6.0 Adc, VGS = 0 Vdc, TJ = 125°C)
— 0.9 —
(See Figure
Fig re 14)
((IS = 6.0 Adc, VGS = 0 Vdc, ta — 93 —
dIS/dt = 100 A/µs) tb — 45 —


MTD6N20E
12 12
10 8V 10

25°C
8 7V 8 100°C
6 6
4 6V 4
2 5V 2
0 0
0 1 2 3 4 5 6 7 8 9 2 3 4 5 6 7 8 9


1.2 0.70
VGS = 10 V TJ = 25°C
1.0 0.65
0.8 TJ = 100°C 0.60
0.6 0.55
25°C VGS = 10 V
0.4 0.50
– 55°C
0.2 0.45 15 V
0 0.40
0 2 4 6 8 10 12 0 2 4 6 8 10 12
2.5 100
VGS = 10 V VGS = 0 V TJ = 125°C

ID = 3 A
2.0
100°C
(NORMALIZED)
1.5
10
1.0
25°C
0.5
0 1
– 50 – 25 0 25 50 75 100 125 150 0 50 100 150 200


MTD6N20E
900
VDS = 0 V VGS = 0 V TJ = 25°C
750 Ciss
C, CAPACITANCE (pF)
600
450 Ciss
Crss
300
Coss
150
Crss
0
10 5 0 5 10 15 20 25
VGS VDS

MTD6N20E
12 90 1000

QT VDD = 100 V
ID = 6 A
10 75
VGS = 10 V
VGS
TJ = 25°C
8 Q1 Q2 60 100
t, TIME (ns)
6 45 tr
td(off) tf
4 30 10
ID = 6 A td(on)
TJ = 25°C
2 15
Q3 VDS
0 0 1
0 2 4 6 8 10 12 14 1 10 100

6
VGS = 0 V
5 TJ = 25°C
0
0.5 0.6 0.7 0.8 0.9 1.0
SAFE OPERATING AREA
temperature.

MTD6N20E
SAFE OPERATING AREA
100 60
VGS = 20 V ID = 6 A

SINGLE PULSE
50
TC = 25°C

10 10 µs 40
30
100 µs
1.0 1 ms 20
RDS(on) LIMIT 10 ms
10
THERMAL LIMIT dc
PACKAGE LIMIT
0.1 0
0.1 1.0 10 100 1000 25 50 75 100 125 150
D = 0.5
0.2
0.1
0.1 0.05 P(pk)
0.02
PULSE TRAIN SHOWN
0.01
1.0E–05 1.0E–04 1.0E–03 1.0E–02 1.0E–01 1.0E+00 1.0E+01
t, TIME (s)
di/dt
IS
trr
ta tb
TIME
tp 0.25 IS
IS

MOTOROLA
 Data Sheet
Designer's
MTD6P10E

P–Channel Enhancement–Mode Silicon Gate 6.0 AMPERES
100 VOLTS

voltage transients.
DPAK
• Source–to–Drain Diode Recovery Time Comparable to a D
• Surface Mount Package Available in 16 mm, 13–inch/2500 G
S


MTD6P10E
OFF CHARACTERISTICS
(VDS = 100 Vdc, VGS = 0 Vdc) — — 10
Gate–Body Leakage Current (VGS = ±15 Vdc, VDS = 0) IGSS — — 100 nAdc
(ID = 6.0 Adc) — 3.6 4.8
(ID = 3.0 Adc, TJ = 125°C) — — 4.2
Vd VGS = 0 Vdc,
Vd
Coss — 154 240
f = 1.0 MHz)

VGS = 10 Vdc
Vdc,
(See Fig
Figure
re 8)
((VDS = 80 Vdc, ID = 6.0 Adc, Q1 — 4.1 —
VGS = 10 Vdc) Q2 — 7.1 —
Q3 — 6.8 —
— 1.8 5.0
(IS = 6.0 Adc, VGS = 0 Vdc, TJ = 125°C)
— 1.5 —
(See Figure
Fig re 14)
((IS = 6.0 Adc, VGS = 0 Vdc, ta — 92 —
dIS/dt = 100 A/µs) tb — 20 —


MTD6P10E
12 12
TJ = 25°C VGS = 10 V VDS ≥ 10 V TJ = – 55°C
10 9V 10 25°C

100°C
8 8V 8
6 6
7V
4 4
2 6V 2
5V
0 0
0 2 4 6 8 10 12 14 16 18 20 2 3 4 5 6 7 8 9 10


1.3 1.0
1.2 VGS = 10 V TJ = 25°C
0.9
1.1
1.0
TJ = 100°C 0.8
0.9
0.8 0.7 VGS = 10 V
0.7 25°C
0.6
0.6
0.5 15 V
– 55°C 0.5
0.4
0.3 0.4
0 2 4 6 8 10 12 0 2 4 6 8 10 12
1.8 100
1.6 ID = 3 A
1.4
(NORMALIZED)
1.2
TJ = 125°C
1.0
0.8
0.6
0.4 10
– 50 – 25 0 25 50 75 100 125 150 – 120 – 100 – 80 – 60 – 40 – 20 0


MTD6P10E
1600
VDS = 0 V VGS = 0 V TJ = 25°C
1400
Ciss
1200
C, CAPACITANCE (pF)
1000
800
Crss Ciss
600
400
Coss
200 Crss
0
10 5 0 5 10 15 20 25
VGS VDS

MTD6P10E
12 90 1000

VDD = 50 V
QT
10 75 ID = 6 A
VGS VGS = 10 V
Q1 Q2
TJ = 25°C
8 60 100
t, TIME (ns)
6 45
tr
td(off)
4 30 10 td(on)
ID = 6 A
tf
TJ = 25°C
2 15
Q3 VDS
0 0 1
0 2 4 6 8 10 12 14 16 1 10 100

6
VGS = 0 V
5 TJ = 25°C
0
0.50 0.75 1.0 1.25 1.50 1.75 2.0
SAFE OPERATING AREA
temperature.

MTD6P10E
SAFE OPERATING AREA
100 200
VGS = 10 V ID = 6 A

SINGLE PULSE
TC = 25°C 160

10
120
100 µs
1 ms 80
1.0 10 ms
dc
RDS(on) LIMIT 40
THERMAL LIMIT
PACKAGE LIMIT
0.1 0
0.1 1.0 10 100 25 50 75 100 125 150
D = 0.5
0.2
0.1
0.1 0.05 P(pk)
0.02
0.01
1.0E–05 1.0E–04 1.0E–03 1.0E–02 1.0E–01 1.0E+00 1.0E+01
t, TIME (s)
di/dt
IS
trr
ta tb
TIME
tp 0.25 IS
IS

MOTOROLA
 Data Sheet
Designer's


TMOS POWER FET
This advanced TMOS E–FET is designed to withstand high 9.0 AMPERES
energy in the avalanche and commutation modes. The new energy 100 VOLTS
efficient design also offers a drain–to–source diode with a fast RDS(on) = 0.25 OHM

voltage transients.
G
Unit Tape & Reel, Add T4 Suffix to Part Number CASE 369A–13, Style 2
• Replaces MTD6N10 DPAK
S

REV 2

MTD9N10E
OFF CHARACTERISTICS
(VDS = 100 Vdc, VGS = 0 Vdc) — — 10
(ID = 9.0 Adc) — — 2.43
(ID = 4.5 Adc, TJ = 125°C) — — 2.40
Forward Transconductance (VDS = 8.0 Vdc, ID = 4.5 Adc) gFS 4.0 — — mhos
Vd VGS = 0 Vdc,
Vd
Coss — 176 400
f = 1.0 MHz)
VGS = 10 Vdc
Vdc,
Turn–Off Delay Time RG = 9.1 Ω)) td(off) — 16 30
(S Fi
(See Figure 8)
((VDS = 80 Vdc, ID = 9.0 Adc, Q1 — 5.2 —
VGS = 10 Vdc) Q2 — 3.2 —
Q3 — 6.6 —
— 0.98 1.8
(IS = 9.0 Adc, VGS = 0 Vdc, TJ = 125°C)
— 0.9 —
(S Fi
(See Figure 14)
((IS = 9.0 Adc, VGS = 0 Vdc, ta — 71 —
dIS/dt = 100 A/µs) tb — 20 —

MTD9N10E
18 18
VGS = 10 V TJ = 25°C VDS ≥ 10 V TJ = – 55°C
16 16

14 8V 14
7V 25°C
12 12
100°C
10 10
8 8
6V
6 6
4 4
2 5V 2
4V
0 0
0 1 2 3 4 5 6 7 8 9 10 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5 9.0


0.45 0.25
VGS = 10 V TJ = 25°C
0.40
0.23
0.35
0.30 TJ = 100°C 0.21
0.25
0.19 VGS = 10 V
0.20 25°C
0.17
0.15
– 55°C 15 V
0.10 0.15
0 2 4 6 8 10 12 14 16 18 0 2 4 6 8 10 12 14 16 18
1.9 100
1.7 ID = 4.5 A
1.5 TJ = 125°C
10
(NORMALIZED)
1.3 100°C
1.1
1.0
0.9
25°C
0.7
0.5 0.1
– 50 – 25 0 25 50 75 100 125 150 30 40 50 60 70 80 90 100


MTD9N10E
The published capacitance data is difficult to use for calcu- At high switching speeds, parasitic circuit elements com-
lating rise and fall because drain–gate capacitance varies plicate the analysis. The inductance of the MOSFET source
greatly with applied voltage. Accordingly, gate charge data lead, inside the package and in the circuit wiring which is
is used. In most cases, a satisfactory estimate of average common to both the drain and gate current paths, produces a
input current (IG(AV)) can be made from a rudimentary anal- voltage at the source which reduces the gate drive current.
ysis of the drive circuit so that The voltage is determined by Ldi/dt, but since di/dt is a func-
the plateau voltage, VSGP. Therefore, rise and fall times
may be approximated by the following:
not constant. The simplest calculation uses appropriate
values from the capacitance curves in a standard equation
for voltage change in an RC network. The equations are:
1200
VDS = 0 VGS = 0 TJ = 25°C
1000 Ciss
C, CAPACITANCE (pF)
800
Ciss
600 Crss
400 Coss
200
Crss
0
10 5 0 5 10 15 20 25
VGS VDS

MTD9N10E
12 120 100

VDD = 50 V

QT
ID = 9 A
10 100 VGS = 10 V
VGS TJ = 25°C
8 Q2 80 tr
t, TIME (ns)
Q1 td(off)
6 60 10
td(on)
4 ID = 9 A 40
TJ = 25°C tf
2 20
Q3 VDS
0 0 1
0 2 4 6 8 10 12 14 1 10 100

9
VGS = 0 V
8
TJ = 25°C
7
6
5
4
3
2
1
0
0.5 0.55 0.6 0.65 0.7 0.75 0.8 0.85 0.9 0.95 1.0
SAFE OPERATING AREA
temperature.

MTD9N10E
SAFE OPERATING AREA
100 40
VGS = 20 V

ID = 9 A
SINGLE
PULSE 10 µs 32

10 TC = 25°C
100 µs 24
1.0 1 ms
10 ms 16
dc
0.1 RDS(on) LIMIT
THERMAL LIMIT 8
PACKAGE LIMIT
0.01 0
0.1 1.0 10 100 25 50 75 100 125 150
1.0
D = 0.5
0.2
0.1
P(pk)
t1 READ TIME AT t1
0.01
0.01
1.0E–05 1.0E–04 1.0E–03 1.0E–02 1.0E–01 1.0E+00 1.0E+01
t, TIME (s)
di/dt
IS
trr
ta tb
TIME
tp 0.25 IS
IS

MOTOROLA
 Data Sheet
Designer's
MTD10N10EL

100 VOLTS
applications in power supplies, converters and PWM motor 
critical and offer additional safety margin against unexpected D
voltage transients.
Fast Recovery Diode G
• Diode is Characterized for Use in Bridge Circuits CASE 369A–13, Style 2
• IDSS and VDS(on) Specified at Elevated Temperature DPAK Surface Mount
S

Gate–to–Source Voltage — Non–Repetitive (tp ≤ 10 ms) VGSM ±20 Vpk
(VDD = 25 Vdc, VGS = 5.0 Vdc, IL = 10 Apk, L = 1.0 mH, RG =25 Ω) 50

MTD10N10EL
OFF CHARACTERISTICS
(VGS = 0 Vdc, ID = 0.25 mAdc) 100 — —
(VDS = 100 Vdc, VGS = 0 Vdc) — — 10
(VDS = VGS, ID = 250 µAdc) 1.0 1.45 2.0
(VGS = 5.0 Vdc, ID = 10 Adc) — 1.85 2.6
(VGS = 5.0 Vdc, ID = 5.0 Adc, TJ = 125°C) — — 2.3
(VDS = 25 Vdc,
Vd VGS = 0 Vdc,
Vd
f = 1.0 MHz)

VGS = 5
5.0
0 Vdc,
Vdc
(See Fig
Figure
re 8)
((VDS = 80 Vdc, ID = 10 Adc, Q1 — 2.56 —
VGS = 5.0 Vdc) Q2 — 4.4 —
Q3 — 4.66 —
— 0.98 1.6
(IS = 10 Adc, VGS = 0 Vdc, TJ = 125°C)
— 0.898 —
(See Figure
Fig re 14)
((IS = 10 Adc, VGS = 0 Vdc, ta — 86 —
dIS/dt = 100 A/µs) tb — 38.7 —


MTD10N10EL
20 7V 20
VGS = 10 V
TJ = 25°C
5V VDS ≥ 5 V

4.5 V –55°C
15 15
4V 25°C
TJ = 100°C
10 10
3.5 V
5 5
3V
2V
0 0
0 1 2 3 4 5 1 2 3 4 5


0.35 0.25
VGS = 10 V TJ = 25°C
100°C
0.25 0.2 VGS = 5 V
TJ = 25°C
10 V
0.15 0.15
–55°C
0.05 0.1
0 5 10 15 20 0 5 10 15 20
2 100
VGS = 5 V VGS = 0 V
ID = 5 A TJ = 125°C
1.5
(NORMALIZED)
1 10 100°C
0.5
0 1
– 50 – 25 0 25 50 75 100 125 150 0 20 40 60 80 100


MTD10N10EL
Switching behavior is most easily modeled and predicted The capacitance (Ciss) is read from the capacitance curve at a
by recognizing that the power MOSFET is charge controlled. voltage corresponding to the off–state condition when calcu-
The lengths of various switching intervals (∆t) are deter- lating td(on) and is read at a voltage corresponding to the on–
mined by how fast the FET input capacitance can be charged state when calculating td(off).
ing rise and fall because drain–gate capacitance varies great- plicate the analysis. The inductance of the MOSFET source
ly with applied voltage. Accordingly, gate charge data is used. lead, inside the package and in the circuit wiring which is
In most cases, a satisfactory estimate of average input current common to both the drain and gate current paths, produces a
(IG(AV)) can be made from a rudimentary analysis of the drive voltage at the source which reduces the gate drive current.
circuit so that The voltage is determined by Ldi/dt, but since di/dt is a func-
During the rise and fall time interval when switching a resistive mathematics. And finally, MOSFETs have finite internal gate
load, VGS remains virtually constant at a level known as the
plateau voltage, VSGP. Therefore, rise and fall times may be
approximated by the following:
During the turn–on and turn–off delay times, gate current is not
constant. The simplest calculation uses appropriate values
from the capacitance curves in a standard equation for voltage
change in an RC network. The equations are:
1800
VDS = 0 V VGS = 0 V TJ = 25°C
1600 C
iss
1400
C, CAPACITANCE (pF)
1200
1000
Crss Ciss
800
600
400
Coss
200
Crss
0
10 5 0 5 10 15 20 25
VGS VDS

MTD10N10EL
VDS , DRAIN–TO–SOURCE VOLTAGE (VOLTS

90 1000

12
TJ = 25°C
QT ID = 10 A
75 VDS = 100 V
VGS = 5 V
8 VGS 60 100
t, TIME (ns)
tr
45 tf
Q1 Q2 td(off)
4 30 10
TJ = 25°C td(on)
ID = 10 A
15
Q3 VDS
0 0 1
0 2 4 6 8 10 1 10 100

10
VGS = 0 V
TJ = 25°C
0
0.5 0.6 0.7 0.8 0.9 1.0
SAFE OPERATING AREA
temperature.

MTD10N10EL
SAFE OPERATING AREA
100 50

VGS = 20 V ID = 10 A
SINGLE PULSE
TC = 25°C

10 µs 40
10
30
100 µs
1 ms
20
1 10 ms
dc
RDS(on) LIMIT 10
THERMAL LIMIT
PACKAGE LIMIT
0.1 0
0.1 1 10 100 25 50 75 100 125 150
1.0
D = 0.5
0.2
0.1
0.1 0.05 P(pk)
t1 READ TIME AT t1
0.01
0.00001 0.0001 0.001 0.01 0.1 1.0 10
t, TIME (ms)
di/dt
IS
trr
ta tb
TIME
tp 0.25 IS
IS

MOTOROLA
 Data Sheet
Designer's
MTD12N06EZL
TMOS E-FET.
DPAK for Surface Mount or TMOS POWER FET
Insertion Mount 12 AMPERES
60 VOLTS
N–Channel Enhancement–Mode Silicon Gate RDS(on) = 0.180 OHM
This advanced TMOS power FET is designed to withstand high
energy in the avalanche and mode and switch efficiently. This new
high energy device also offers a gate–to–source zener diode
designed for 4 kV ESD protection (human body model).
• ESD Protected 
• 4 kV Human Body Model
• 400 V Machine Model
• Avalanche Energy Capability D
• Internal Source–To–Drain Diode Designed to Replace External
Zener Transient Suppressor–Absorbs High Energy in the
Avalanche Mode
G
DPAK Surface Mount
S
Gate–Source Voltage — Non–Repetitive (tp ± 50 ms) VGSM ± 20 Vpk

MTD12N06EZL
OFF CHARACTERISTICS
(VDS = 60 Vdc, VGS = 0 Vdc) — — 10
Gate–Source Breakdown Voltage 18 — — Vdc
(VDS = 0 V, IG = 10 mA)
Gate–Body Leakage Current IGSS

(VGS = ± 10 Vdc, VDS = 0 V, TJ = 25°C) — — 500 nAdc
(VGS = ± 10 Vdc, VDS = 0 V, TJ = 150°C) — — 100 µAdc
Static Drain–Source On–Resistance (VGS = 5.0 Vdc, ID = 6.0 Adc) RDS(on) — — 0.18 Ohm
(ID = 12 Adc) — — 2.6
(ID = 6.0 Adc, TJ = 125°C) — — 2.3
Vd VGS = 0 Vdc,
Vd
Coss — 224 310
f = 1.0 MHz)

Rise Time (VDS = 30 Vdc, ID = 12 Adc, tr — 436 540
VGS = 55.0
0 Vdc,
Vdc
(See Fig res 8 & 9)
Figures
((VDS = 48 Vdc, ID = 12 Adc, Q1 — 1.4 —
VGS = 5.0 Vdc) Q2 — 5.9 —
Q3 — 6.0 —
— 1.1 1.4
(IS = 12 Adc, VGS = 0 Vdc, TJ = 125°C)
— 1.05 —
(See Figure
Fig re 14)
((IS = 12 Adc, VGS = 0 Vdc, ta — 124 —
dIS/dt = 100 A/µs) tb — 201 —


MTD12N06EZL
24 24
TJ = 25°C VGS = 10 V
7V VDS ≥ 10 V
5V
8V

6V
18 18
TJ = – 55°C
25°C
12 12
100°C
4V
6 6
0 0
0 0.5 1 1.5 2 2.5 3 2 2.5 3 3.5 4 4.5 5 5.5 6

0.15 0.096
VGS = 5 V TJ = 25°C
0.13
TJ = 100°C 0.092
0.11 VGS = 10 V
0.088
25°C
0.09
0.084 15 V
0.07
– 55°C
0.05 0.08
0 6 12 18 24 0 6 12 18 24
1.8 100
VGS = 5 V VGS = 0 V TJ = 125°C

1.6
ID = 12 A
1.4
1.2
(NORMALIZED)
1
10 100°C
0.8
0.6
0.4
25°C
0.2
0 1
– 50 – 25 0 25 50 75 100 125 150 0 10 20 30 40 50 60


MTD12N06EZL
1200
VDS = 0 V TJ = 25°C
1000
C, CAPACITANCE (pF)
800
600
Ciss
400
Coss
200
Crss
0
0 5 10 15 20 25

MTD12N06EZL
6 60 1000

VDD = 30 V
QT
5 50 ID = 12 A
tr
VGS = 5 V
VGS TJ = 25°C
4 40 tf
t, TIME (ns)
Q2 td(off)
Q1
3 30 100
td(on)
2 ID = 12 A 20
TJ = 25°C
1 10
Q3 VDS
0 0 10
0 2 4 6 8 10 1 10 100

12
VGS = 0 V
10 TJ = 25°C
0
0 0.2 0.4 0.6 0.8 1 1.2
SAFE OPERATING AREA
temperature.

MTD12N06EZL
SAFE OPERATING AREA
100 75
VGS = 20 V
10 µs

1 ms 100 µs ID = 12 A
SINGLE PULSE
10 ms
TC = 25°C 60

dc
10
45
30
1
RDS(on) LIMIT
THERMAL LIMIT
15
PACKAGE LIMIT
0.1 0
0.1 1 10 100 25 50 75 100 125 150
1
D = 0.5
0.2
0.1
0.1 0.05 P(pk)

t1 READ TIME AT t1
0.01
1.0E–05 1.0E–04 1.0E–03 1.0E–02 1.0E–01 1.0E+00 1.0E+01
t, TIME (s)
di/dt
IS
trr
ta tb
TIME
tp 0.25 IS
IS

MOTOROLA
Designer's  Data Sheet MTD15N06V

TMOS V

60 VOLTS
avalanche and commutation modes. Designed for low voltage, high TM

• On–resistance Area Product about One–half that of Standard G CASE 369A–13, Style 2
MOSFETs with New Low Voltage, Low RDS(on) Technology DPAK Surface Mount
S

• Surface Mount Package Available in 16 mm 13–inch/2500 Unit Tape & Reel, Add T4 Suffix to Part Number

Gate–Source Voltage — Single Pulse (tp ≤ 50 ms) VGSM ± 25 Vpk
REV 2

MTD15N06V
OFF CHARACTERISTICS
(VDS = 60 Vdc, VGS = 0 Vdc) — — 10
(ID = 15 Adc) — 2.0 2.2
(ID = 7.5 Adc, TJ = 150°C) — — 1.9
Vd VGS = 0 Vdc,
Vd
Coss — 148 200
f = 1.0 MHz)

VGS = 10 Vdc
Vdc,
(See Fig
Figure
re 8)
((VDS = 48 Vdc, ID = 15 Adc, Q1 — 2.8 —
VGS = 10 Vdc) Q2 — 6.4 —
Q3 — 6.1 —
— 1.05 1.6
(IS = 15 Adc, VGS = 0 Vdc, TJ = 150°C)
— 1.5 —
(See Figure
Fig re 14)
((IS = 15 Adc, VGS = 0 Vdc, ta — 46 —
dIS/dt = 100 A/µs) tb — 13.3 —


MTD15N06V
30 30
VGS = 10 V 8V 100°C
TJ = 25°C VDS ≥ 10 V
9V
25 25

7V 25°C
TJ = – 55°C
20 20
15 6V 15
10 10
5V
5 5
0 0
0 1 2 3 4 5 6 7 2 4 6 8 10


0.20 0.13
VGS = 10 V TJ = 25°C
0.15 TJ = 100°C 0.11
0.10 25°C 0.09 VGS = 10 V
– 55°C 15 V
0.05 0.07
0 0.05
0 5 10 15 20 25 30 0 5 10 15 20 25 30
2 100
VGS = 0 V
VGS = 10 V
ID = 7.5 A
1.6
(NORMALIZED)
TJ = 125°C
1.2
0.8
0.4 10
– 50 – 25 0 25 50 75 100 125 150 175 0 10 20 30 40 50 60


MTD15N06V
1500
VDS = 0 V VGS = 0 V TJ = 25°C
1200
Ciss
C, CAPACITANCE (pF)
900
600 Crss Ciss
300 Coss
Crss
0
10 5 0 5 10 15 20 25
VGS VDS

MTD15N06V
12 60 1000

VDD = 30 V
QT ID = 15 A
10 50 VGS = 10 V
VGS TJ = 25°C
8 40 100
t, TIME (ns)
tr
Q1 Q2
6 30 tf
td(off)
4 20 10 td(on)
ID = 15 A
TJ = 25°C
2 10
Q3 VDS
0 0 1
0 3 6 9 12 15 1 10 100

15
VGS = 0 V
TJ = 25°C
12
0
0.5 0.7 0.9 1.1 1.3 1.5
SAFE OPERATING AREA
temperature.

MTD15N06V
SAFE OPERATING AREA
100 120
VGS = 10 V

TC = 25°C 10 µs 100

10 80
100 µs
60
1 ms
10 ms
1.0 dc 40
RDS(on) LIMIT
THERMAL LIMIT 20
PACKAGE LIMIT
0.1 0
0.1 1.0 10 100 25 50 75 100 125 150 175
1.0
D = 0.5
0.2
0.1
0.1 0.05 P(pk)
PULSE TRAIN SHOWN
0.01
1.0E–05 1.0E–04 1.0E–03 1.0E–02 1.0E–01 1.0E+00 1.0E+01
t, TIME (s)
di/dt
IS
trr
ta tb
TIME
tp 0.25 IS
IS

MOTOROLA
Product Preview MTD15N06VL

TMOS V
60 VOLTS

• On–resistance Area Product about One–half that of Standard G CASE 369A–13, Style 2
MOSFETs with New Low Voltage, Low RDS(on) Technology DPAK Surface Mount
S


Total Power Dissipation @ 25°C(1) 2.1 Watts
Thermal Resistance — Junction to Ambient(1) RθJA 71.4

MTD15N06VL
OFF CHARACTERISTICS
(VGS = 0 Vdc, ID = 0.25 mAdc) 60 — —
(VDS = 60 Vdc, VGS = 0 Vdc) — — 10
(VDS = VGS, ID = 250 µAdc) 1.0 1.5 2.0
Temperature Coefficient (Negative) — TBD — mV/°C
(VGS = 5.0 Vdc, ID = 15 Adc) — — 1.5
(VGS = 5.0 Vdc, ID = 7.5 Adc, TJ = 150°C) — — 1.3
Forward Transconductance (VDS = 8.0 Vdc, ID = 7.5 Adc) gFS 8.0 10 — mhos
Vd VGS = 0 Vdc,
Vd
Coss — 270 380
f = 1.0 MHz)

VGS = 55.0
0 Vdc,
Vdc
((VDS = 48 Vdc, ID = 15 Adc, Q1 — 3.0 —

VGS = 5.0 Vdc) Q2 — 8.0 —
Q3 — 10 —
— 1.0 1.6
(IS = 15 Adc, VGS = 0 Vdc, TJ = 150°C)
— 0.9 —
((IS = 15 Adc, VGS = 0 Vdc, ta — 55 —

dIS/dt = 100 A/µs) tb — 45 —

MOTOROLA
 Data Sheet
Designer's
MTD20N03HDL

LOGIC LEVEL
This advanced HDTMOS power FET is designed to withstand 30 VOLTS
high energy in the avalanche and commutation modes. This new RDS(on) = 0.035 OHM

• Source–to–Drain Diode Recovery Time Comparable to a Dis-
crete Fast Recovery Diode

Total Power Dissipation @ TC = 25°C, when mounted with the minimum recommended pad size 1.75
Thermal Resistance — Junction to Ambient, when mounted with the minimum recommended pad size RθJA 71.4
REV 1

MTD20N03HDL
OFF CHARACTERISTICS
(VGS = 0 Vdc, ID = 250 µAdc) 30 — —
(VDS = 30 Vdc, VGS = 0 Vdc) — — 10
(VGS = ±15 Vdc, VDS = 0 Vdc) — — 100
(VDS = VGS, ID = 250 µAdc) 1.0 1.5 2.0
Static Drain–to–Source On–Resistance (Cpk ≥ 2.0) (3) RDS(on) Ohm
(VGS = 4.0 Vdc, ID = 10 Adc) — 0.034 0.040
(VGS = 5.0 Vdc, ID = 10 Adc) 0.030 0.035
(ID = 20 Adc) — 0.55 0.8
(ID = 10 Adc, TJ = 125°C) — — 0.7
(VDS = 5.0 Vdc, ID = 10 Adc) 10 13 —
Vd VGS = 0 Vdc,
Vd
Coss — 300 420
f = 1.0 MHz)
Turn–On Delay Time td(on) — 13 15.8 ns
VGS = 5.0
5 0 Vdc,
Vdc
(S Fi
(See Figure 8)
((VDS = 24 Vdc, ID = 20 Adc, Q1 — 3.0 —
VGS = 5.0 Vdc) Q2 — 7.3 —
Q3 — 6.0 —

(Cpk ≥ 2.0) (3) — 0.95 1.1
(IS = 20 Adc, VGS = 0 Vdc, TJ = 125°C)
— 0.87 —
(S Figure
(See Fi 15)
((IS = 20 Adc, VGS = 0 Vdc, ta — 23 —
dIS/dt = 100 A/µs) tb — 10 —
Reverse Recovery Stored Charge QRR — 33 — µC

(3) Reflects typical values. Cpk = Absolute Value of Spec (Spec–AVG/3.516 µA).

MTD20N03HDL
40 40
TJ = 25°C VGS = 10 V 5V 4.5 V VDS ≥ 10 V
8V

4V
30 6V 30
20 20
3.5 V
10 10
3V 100°C 25°C
2.5 V TJ = – 55°C
0 0
0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 1.0 1.4 1.8 2.2 2.6 3.0 3.4 3.8 4.2 4.6 5.0
VDS, DRAIN–TO–SOURCE VOLTAGE (Volts) VGS, GATE–TO–SOURCE VOLTAGE (Volts)


0.052 0.036
VGS = 5 V TJ = 25°C
0.044 0.032 VGS = 5 V

TJ = 100°C
0.036 0.028
25°C
0.028 0.024 10 V
– 55°C
0.020 0.020
0 8 16 24 32 40 0 8 16 24 32 40
ID, DRAIN CURRENT (Amps) ID, DRAIN CURRENT (Amps)
1.8 1000
VGS = 5 V VGS = 0 V
ID = 10 A
1.6 TJ = 125°C
I DSS, LEAKAGE (nA)
1.4 100
(NORMALIZED)
100°C
1.2
1.0 10
25°C
0.8
0.6 1
– 50 – 25 0 25 50 75 100 125 150 0 6 12 18 24 30
TJ, JUNCTION TEMPERATURE (°C) VDS, DRAIN–TO–SOURCE VOLTAGE (Volts)


MTD20N03HDL
2800
VDS = 0 V VGS = 0 V TJ = 25°C
2400
Ciss
C, CAPACITANCE (pF)
2000
1600
Crss
1200
Ciss
800
Coss
400 Crss
0
10 5 0 5 10 15 20 25
VGS VDS

MTD20N03HDL
14 28 1000

VDD = 15 V
12 24 ID = 20 A
QT VGS = 5.0 V
10 20 TJ = 25°C
tr
t, TIME (ns)
8 VGS 16
100
6 12 tf
Q1 Q2
4 8
ID = 20 A
2 TJ = 25°C 4 td(off)
Q3 VDS td(on)
0 0 10
0 2 4 6 8 10 12 14 1 10 100
QG, TOTAL GATE CHARGE (nC) RG, GATE RESISTANCE (Ohms)

snappy.
20
VGS = 0 V
TJ = 25°C
16
12
0
0.50 0.55 0.60 0.65 0.70 0.75 0.80 0.85 0.90 0.95 1.0
VSD, SOURCE–TO–DRAIN VOLTAGE (Volts)

MTD20N03HDL
trr
High Cell Density
trr
tb
ta
t, TIME
SAFE OPERATING AREA
perature.
100 200
VGS = 20 V ID = 20 A
SINGLE PULSE
TC = 25°C 160
100 µs
120
10
1 ms
80
10 ms
RDS(on) LIMIT dc 40
THERMAL LIMIT
PACKAGE LIMIT
1 0
0.1 1.0 10 100 25 50 75 100 125 150

MTD20N03HDL

1.0
D = 0.5
0.2
(NORMALIZED)
0.1
0.05 P(pk)
PULSE TRAIN SHOWN
0.01
t1 READ TIME AT t1
0.01
1.0E–05 1.0E–04 1.0E–03 1.0E–02 1.0E–01 1.0E+00 1.0E+01
t, TIME (s)
di/dt
IS
trr
ta tb
TIME
tp 0.25 IS
IS

MOTOROLA
 Data Sheet
Designer's
MTD20N06HD

60 VOLTS
This advanced HDTMOS power FET is designed to withstand RDS(on) = 0.045 OHM

Fast Recovery Diode

REV 2

MTD20N06HD
OFF CHARACTERISTICS
(VGS = 0 Vdc, ID = 250 µAdc) 60 — —
(VDS = 60 Vdc, VGS = 0 Vdc) — — 10
(VGS = ± 20 Vdc, VDS = 0 Vdc) — — 100
(VDS = VGS, ID = 250 µAdc) 2.0 — 4.0
Static Drain–to–Source On–Resistance (Cpk ≥ 2.0) (3) RDS(on) Ohm
(VGS = 10 Vdc, ID = 10 Adc) — 0.035 0.045

(ID = 20 Adc) — — 1.2
(ID = 10 Adc, TJ = 125°C) — — 1.1
(VDS = 4.0 Vdc, ID = 10 Adc) 5.0 6.0 —
(VDS = 25 Vdc, Vd
Coss — 218 290
f = 1.0 MHz)
VGS = 10 Vdc
Vdc,
(See Fig
Figure
re 7)
((VDS = 48 Vdc, ID = 20 Adc, Q1 — 3.4 —
VGS = 10 Vdc) Q2 — 7.75 —
Q3 — 7.46 —
— 0.95 1.0
(IS = 20 Adc, VGS = 0 Vdc, TJ = 125°C)
(Cpk ≥ 8.0) (3) — 0.88 —
(See Figure
Fig re 14)
((IS = 20 Adc, VGS = 0 Vdc, ta — 24 —
dIS/dt = 100 A/µs) tb — 11.7 —


MTD20N06HD
40 40
9V VDS ≥ 10 V
VGS = 10 V 7V
8V
32

30
TJ = 25°C
24
6V 20
16
10
8 5V 25°C
100°C
TJ = – 55°C
0 0
0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 2 3 4 5 6 7 8
VDS, DRAIN–TO–SOURCE VOLTAGE (Volts) VGS, GATE–TO–SOURCE VOLTAGE (Volts)


0.052 0.040
VGS = 10 V TJ = 25°C
0.048
TJ = 100°C 0.038
0.044
VGS = 10 V
0.036
0.040
0.036 25°C 0.034
0.032
0.032 15 V
0.028
– 55°C 0.030
0.024
0.020 0.028
0 10 20 30 40 0 10 20 30 40
1.6
VGS = 10 V
1.4 ID = 10 A
(NORMALIZED)
1.2
1.0
0.8
0.6
– 50 – 25 0 25 50 75 100 125 150
Figure 5. On–Resistance Variation with

Temperature

MTD20N06HD
1600
VDS = 0 V VGS = 0 V TJ = 25°C
1400
Ciss
1200
C, CAPACITANCE (pF)
1000
800 Crss
Ciss
600
400 Coss
200 Crss
0
10 5 0 5 10 15 20 25
VGS VDS

MTD20N06HD
1000

12 60

QT VDD = 30 V
50 ID = 20 A
10
VGS = 10 V
VGS TJ = 25°C
8 40 100 tr
Q1 Q2
t, TIME (ns)
6 30 tf
ID = 20 A td(off)
4 TJ = 25°C 20 10
td(on)
2 10
Q3
VDS
0 0 1
0 2 4 6 8 10 12 14 16 18 1 10 100

the body diode itself. The body diode is a minority carrier comparative estimate of probable noise generated. A ratio of
device, therefore it has a finite reverse recovery time, trr, due 1 is considered ideal and values less than 0.5 are considered
to the storage of minority carrier charge, QRR, as shown in
snappy.
the typical reverse recovery wave form of Figure 10. It is this
repeatedly forcing the diode through reverse recovery further (shorter trr), have less stored charge and a softer reverse
increases switching losses. Therefore, one would like a recovery characteristic. The softness advantage of the high
20
18 VGS = 0 V
TJ = 25°C
16
14
12
10
8
6
4
2
0
0.50 0.58 0.66 0.74 0.82 0.90 0.98

MTD20N06HD
trr
High Cell Density
trr
tb
ta
t, TIME
SAFE OPERATING AREA
drain current that a transistor can handle safely when it is the rated limit and must be adjusted for operating conditions
forward biased. Curves are based upon maximum peak junc- differing from those specified. Although industry practice is to
perature.
time (tr, tf) does not exceed 10 µs. In addition the total power rent (ID), in accordance with industry custom. The energy
averaged over a complete switching cycle must not exceed rating must be derated for temperature as shown in the ac-
(TJ(MAX) – TC)/(RθJC). companying graph (Figure 12). Maximum energy at currents
A power MOSFET designated E–FET can be safely used below rated continuous ID can safely be assumed to equal
in switching circuits with unclamped inductive loads. For reli- the values indicated.
100 60
VGS = 20 V ID = 20 A
SINGLE PULSE
10 µs 50
TC = 25°C
10 100 µs 40
1 ms
10 ms 30
dc
1.0 20
RDS(on) LIMIT
THERMAL LIMIT 10
PACKAGE LIMIT
0.1 0
0.1 1.0 10 100 25 50 75 100 125 150

MTD20N06HD

1.0
D = 0.5
0.2
(NORMALIZED)
0.1
0.05 P(pk)
PULSE TRAIN SHOWN
0.01
t1 READ TIME AT t1
0.01
1.0E–05 1.0E–04 1.0E–03 1.0E–02 1.0E–01 1.0E+00 1.0E+01
t, TIME (s)
di/dt
IS
trr
ta tb
TIME
tp 0.25 IS
IS

MOTOROLA
Advance Information MTD20N06HDL

HDTMOS E-FET  Motorola Preferred Device

DPAK for Surface Mount or TMOS POWER FET
Insertion Mount
LOGIC LEVEL
20 AMPERES
60 VOLTS
N–Channel Enhancement–Mode Silicon Gate RDS(on) = 0.045 OHM
This advanced high–cell density HDTMOS E–FET is designed to
withstand high energy in the avalanche and commutation modes.
The new energy efficient design also offers a drain–to–source
diode with a fast recovery time. Designed for low–voltage, 
high–speed switching applications in power supplies, converters
and PWM motor controls, these devices are particularly well suited
for bridge circuits, and inductive loads. The avalanche energy D
capability is specified to eliminate the guesswork in designs where
inductive loads are switched, and to offer additional safety margin
• Source–to–Drain Diode Recovery Time Comparable to a Discrete CASE 369A–13, Style 2
Fast Recovery Diode DPAK
• Available in Insertion Mount, Add –1 or 1 to Part Number


Total Power Dissipation @ TC = 25°C (1) 1.75 Watts
(VDD = 25 Vdc, VGS = 5.0 Vdc, IL = 20 Apk, L = 1.0 mH, RG = 25 Ω) 200

(1) When surface mounted to an FR–4 board using the minimum recommended pad size.
REV 1

MTD20N06HDL
OFF CHARACTERISTICS
(VGS = 0 Vdc, ID = 0.25 mAdc) 60 — —
(VDS = 60 Vdc, VGS = 0 Vdc) — — 10
(VDS = VGS, ID = 250 µAdc) 1.0 1.5 2.0
Static Drain–Source On–Resistance RDS(on) Ohm
(VGS = 4.0 Vdc, ID = 10 Adc) — 0.045 0.070
(VGS = 5.0 Vdc, ID = 10 Adc) — 0.037 0.045
(ID = 20 Adc) — 0.76 1.2
(ID = 10 Adc, TJ = 125°C) — — 1.1
Forward Transconductance (VDS = 4.0 Vdc, ID = 10 Adc) gFS 6.0 12 — mhos
Vd VGS = 0 Vdc,
Vd
Coss — 216 300
f = 1.0 MHz)

VGS = 5.0
5 0 Vdc,
Vdc
((VDS = 48 Vdc, ID = 20 Adc, Q1 — 3.25 —

VGS = 5.0 Vdc) Q2 — 7.75 —
Q3 — 7.0 —
— 0.95 1.1
(IS = 20 Adc, VGS = 0 Vdc, TJ = 125°C)
— 0.88 —
((IS = 20 Adc, ta — 12 —
dIS/dt = 100 A/µs) tb — 34 —


MTD20N06HDL
40 40
TJ = 25°C VGS = 10 V VDS ≥ 10 V
8V
4V
6V

30 30
5V
4.5 V
3.5 V
20 20
3V 100°C
10 10
25°C
2.5 V
TJ = – 55°C
0 0
0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 1.5 2 2.5 3 3.5 4 4.5
VDS, DRAIN–TO–SOURCE VOLTAGE (VOLTS) VGS, GATE–TO–SOURCE VOLTAGE (Volts)


0.07 0.05
VGS = 5 V TJ = 25°C
0.06
TJ = 100°C 0.045
0.05
25°C 0.04 5V
0.04
0.03 – 55°C
0.035
VGS = 10 V
0.02
0.03
0.01
0 0.025
0 10 20 30 40 0 10 20 30 40
1.6 1000
VGS = 5 V VGS = 0 V
ID = 10 A
1.4
100 TJ = 125°C
(NORMALIZED)
1.2
100°C
1.0
10 25°C
0.8
0.6 1
– 50 – 25 0 25 50 75 100 125 150 0 10 20 30 40 50 60


MTD20N06HDL
3000
VDS = 0 V VGS = 0 V TJ = 25°C
2500 Ciss
C, CAPACITANCE (pF)
2000
1500 C
rss
1000 Ciss
Coss
500
Crss
0
10 5 0 5 10 15 20 25
VGS VDS

MTD20N06HDL
1000

12 60

QT VDD = 30 V
50 ID = 20 A
10
VGS = 5 V
TJ = 25°C tr
8 VDS VGS 40 100
tf
t, TIME (ns)
6 30
td(off)
Q1 Q2 ID = 20 A
4 TJ = 25°C 20 10 td(on)
2 10
Q3
0 0 1
0 2 4 6 8 10 12 14 16 1 10 100

snappy.
20
VGS = 0 V
TJ = 25°C
16
12
0
0.5 0.55 0.6 0.65 0.7 0.75 0.8 0.9 0.95

MTD20N06HDL
trr
High Cell Density
trr
tb
ta
t, TIME
SAFE OPERATING AREA
perature.
100 200
VGS = 20 V ID = 20 A
SINGLE PULSE
10 µs
TC = 25°C
150
100 µs
10 1 ms 100
10 ms
50
RDS(on) LIMIT
THERMAL LIMIT dc
PACKAGE LIMIT
1.0 0
0.1 1.0 10 100 25 50 75 100 125 150

MTD20N06HDL

1.0
D = 0.5
0.2
(NORMALIZED)
0.1
0.05 P(pk)
PULSE TRAIN SHOWN
0.01
t1 READ TIME AT t1
0.01
0.00001 0.0001 0.001 0.01 0.1 1.0 10
t, TIME (s)
di/dt
IS
trr
ta tb
TIME
tp 0.25 IS
IS

MOTOROLA
Product Preview MTD20N06V

TMOS V
60 VOLTS
50 and 60 volt TMOS devices. Just as with our TMOS E–FET TM
power motor controls, these devices are particularly well suited for D
G
MOSFETs with New Low Voltage, Low RDS(on) Technology S
DPAK Surface Mount



MTD20N06V
OFF CHARACTERISTICS
(VGS = 0 Vdc, ID = 0.25 mAdc) 60 — —
(VDS = 60 Vdc, VGS = 0 Vdc) — — 10
(VDS = VGS, ID = 250 µAdc) 2.0 2.8 4.0
(VGS = 10 Vdc, ID = 10 Adc) — — 2.0
(VGS = 10 Vdc, ID = 10 Adc, TJ = 150°C) — — 1.9
Forward Transconductance (VDS = 6.0 Vdc, ID = 10 Adc) gFS 6.0 8.0 — mhos
Vd VGS = 0 Vdc,
Vd
Coss — 180 250
f = 1.0 MHz)

VGS = 10 Vdc
Vdc,
((VDS = 48 Vdc, ID = 20 Adc, Q1 — 4.0 —

VGS = 10 Vdc) Q2 — 9.0 —
Q3 — 8.0 —
— 1.0 1.6
(IS = 20 Adc, VGS = 0 Vdc, TJ = 150°C)
— 0.96 —
((IS = 20 Adc, VGS = 0 Vdc, ta — 52 —

dIS/dt = 100 A/µs) tb — 8.0 —

MOTOROLA
 Data Sheet
Designer's
MTD20P03HDL

LOGIC LEVEL
This advanced HDTMOS power FET is designed to withstand 30 VOLTS
high energy in the avalanche and commutation modes. This new RDS(on) = 0.099 OHM
applications in power supplies, converters and PWM motor 
• Source–to–Drain Diode Recovery Time Comparable to a Dis-
crete Fast Recovery Diode

Total Power Dissipation @ TC = 25°C, when mounted with the minimum recommended pad size 1.75
REV 2

MTD20P03HDL
OFF CHARACTERISTICS
(VGS = 0 Vdc, ID = 250 µAdc) 30 — —
(VDS = 30 Vdc, VGS = 0 Vdc) — — 10
(VGS = ±15 Vdc, VDS = 0 Vdc) — — 100
(VDS = VGS, ID = 250 µAdc) 1.0 1.5 2.0
(VGS = 4.0 Vdc, ID = 10 Adc) — 120 —
(VGS = 5.0 Vdc, ID = 9.5 Adc) 90 99
(ID = 19 Adc) — 0.94 2.2
(ID = 9.5 Adc, TJ = 125°C) — — 1.9
(VDS = 8.0 Vdc, ID = 9.5 Adc) 5.0 6.0 —
Vd VGS = 0 Vdc,
Vd
Coss — 360 504
f = 1.0 MHz)
Turn–On Delay Time td(on) — 18 25.2 ns
Rise Time (VDD = 15 Vdc, ID = 19 Adc, tr — 178 246.4
VGS = 5.0
5 0 Vdc,
Vdc
Turn–Off Delay Time RG = 1.3 Ω) td(off) — 21 26.6
Gate Charge QT — 15 22.4 nC
(See Fig
Figure
re 8)
((VDS = 24 Vdc, ID =19 Adc, Q1 — 3.0 —
VGS = 5.0 Vdc) Q2 — 11 —
Q3 — 8.2 —

(Cpk ≥ 2.0) (3) — 3.1 3.4
(IS = 19 Adc, VGS = 0 Vdc, TJ = 125°C)
— 2.56 —
(See Figure
Fig re 15)
((IS = 19 Adc, VGS = 0 Vdc, ta — 50 —
dIS/dt = 100 A/µs) tb — 28 —


MTD20P03HDL
40 40
8V 5V 25°C
32

32
100°C
4.5 V
24 24
4V
16 16
3.5 V
8 8
3V
2.5 V
0 0
0 1 2 3 4 5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5

0.16 0.16
VGS = 5 V TJ = 25°C
0.14 0.14
TJ = 100°C
0.12 0.12
0.10 25°C 0.10 VGS = 5 V
0.08 – 55°C 0.08
10 V
0.06 0.06
0 4 8 12 16 20 24 28 32 36 40 0 4 8 12 16 20 24 28 32 36 40
1.3 100
VGS = 5 V VGS = 0 V
TJ = 125°C
ID = 10 A
1.2
I DSS, LEAKAGE (nA)
(NORMALIZED)
1.1
10
1.0
100°C
0.9
0.8 1
– 50 – 25 0 25 50 75 100 125 150 0 4 8 12 16 20 24 28 32


MTD20P03HDL
2800
VDS = 0 V VGS = 0 V TJ = 25°C
2400
Ciss
C, CAPACITANCE (pF)
2000
1600
1200 C
rss
Ciss
800
Coss
400
Crss
0
10 5 0 5 10 15 20 25
VGS VDS

MTD20P03HDL
7 35 1000

VDD = 15 V
6 QT 30 ID = 19 A
VGS = 5.0 V tr
5 Q2 25 TJ = 25°C
Q1 VGS
t, TIME (ns)
4 20
100 tf
3 15
ID = 19 A
2 TJ = 25°C 10 td(off)
1 5
Q3 VDS td(on)
0 0 10
0 2 4 6 8 10 12 14 16 1 10

snappy.
20
VGS = 0 V
TJ = 25°C
16
12
0
0.3 0.7 1.1 1.5 1.9 2.3 2.7 3.1

MTD20P03HDL
trr
High Cell Density
trr
tb
ta
t, TIME
SAFE OPERATING AREA
perature.
100 200
VGS = 20 V ID = 19 A
SINGLE PULSE
TC = 25°C 100 µs 160
10 1 ms
10 ms 120
dc
80
1.0
RDS(on) LIMIT
THERMAL LIMIT 40
PACKAGE LIMIT
0.1 0
0.1 1.0 10 100 25 50 75 100 125 150

MTD20P03HDL

1.0
D = 0.5
0.2
(NORMALIZED)
0.1
0.05 P(pk)
PULSE TRAIN SHOWN
0.01
t1 READ TIME AT t1
0.01
1.0E–05 1.0E–04 1.0E–03 1.0E–02 1.0E–01 1.0E+00 1.0E+01
t, TIME (s)
di/dt
IS
trr
ta tb
TIME
tp 0.25 IS
IS

MOTOROLA
 Data Sheet
Designer's
MTD20P06HDL
HDTMOS E-FET  Motorola Preferred Device

LOGIC LEVEL
This advanced high–cell density HDTMOS E–FET is designed to 60 VOLTS
withstand high energy in the avalanche and commutation modes. RDS(on) = 175 MΩ
The new energy efficient design also offers a drain–to–source
diode with a fast recovery time. Designed for low–voltage,
high–speed switching applications in power supplies, converters 
and PWM motor controls, and other inductive loads. The avalanche
energy capability is specified to eliminate the guesswork in designs
where inductive loads are switched, and to offer additional safety
D
margin against unexpected voltage transients.
• Ultra Low RDS(on), High–Cell Density, HDTMOS
G
• Avalanche Energy Specified CASE 369A–13, Style 2
• Surface Mount Package Available in 16 mm, 13–inch/2500 DPAK
Unit, Tape & Reel, Add T4 Suffix to Part Number S


Total Power Dissipation @ TC = 25°C (1) 1.75 Watts
REV 1

MTD20P06HDL
OFF CHARACTERISTICS
(VGS = 0 Vdc, ID = 250 µAdc) 60 — —
(VDS = 60 Vdc, VGS = 0 Vdc) — — 1.0
(VDS = VGS, ID = 250 µAdc) 1.0 1.7 2.0
Static Drain–Source On–Resistance RDS(on) — 143 175 mΩ
(VGS = 5.0 Vdc, ID = 7.5 Adc)

(ID = 15 Adc) — 2.3 3.0
(ID = 7.5 Adc, TJ = 125°C) — 1.6 2.0
Forward Transconductance (VDS = 10 Vdc, ID = 7.5 Adc) gFS 9.0 11 — mhos
Vd VGS = 0 Vdc,
Vd
Coss — 210 290
f = 1.0 MHz)
VGS = 5.0
5 0 Vdc,
Vdc
((VDS = 48 Vdc, ID = 15 Adc, Q1 — 3.7 —

VGS = 5.0 Vdc) Q2 — 7.6 —
Q3 — 8.4 —

— 2.5 3.0
(IS = 15 Adc, VGS = 0 Vdc, TJ = 125°C)
— 1.9 —
((IS = 15 Adc, VGS = 0 Vdc, ta — 50 —

dIS/dt = 100 A/µs) tb — 14 —


MTD20P06HDL
30 30
TJ = 25°C VGS = 10 V 9V VDS ≥ 5 V
8V
25 25

TJ = – 55°C 25°C
20 7V 20
100°C
15 15
6V
10 10
5V
5 5
4V
0 0
0 1 2 3 4 5 6 7 8 9 10 1 2 3 4 5 6

0.40 0.275
VGS = 5 V TJ = 25°C
0.250
0.32
0.225
0.24 0.200
TJ = 100°C
25°C 0.175
0.16
VGS = 5 V
– 55°C 0.150
0.08
0.125 10 V
0 0.100
0 5 10 15 20 25 30 0 5 10 15 20 25 30
100
1.8
VGS = 5 V VGS = 0 V
1.6 ID = 7.5 A
1.4
I DSS, LEAKAGE (nA)
(NORMALIZED)
1.2
TJ = 125°C
1
10 100°C
0.8
0.6
0.4
0.2
0 1
– 50 – 25 0 25 50 75 100 125 150 0 10 20 30 40 50 60


MTD20P06HDL
2500
VDS = 0 V VGS = 0 V TJ = 25°C
Ciss
2000
C, CAPACITANCE (pF)
1500
Crss
1000 Ciss
500
Coss
Crss
0
10 5 0 5 10 15 20 25
VGS VDS

MTD20P06HDL
6 50 1000

QT VDD = 30 V
45 ID = 15 A
5
40 VGS = 5.0 V
TJ = 25°C tr
4 35 100
tf
VDS VGS 30
t, TIME (ns)
3 25 td(off)
Q1 Q2 20 td(on)
ID = 15 A
2 TJ = 25°C 10
15
10
1 Q3
5
0 0 1
0 4 8 12 16 20 24 1 10 100

snappy.
15
VGS = 0 V
TJ = 25°C
12
0
0.5 0.75 1 1.25 1.5 1.75 2 2.25 2.5

MTD20P06HDL
trr
High Cell Density
trr
tb
ta
t, TIME
SAFE OPERATING AREA
perature.
100 300
VGS = 20 V
ID = 15 A
SINGLE PULSE
TC = 25°C 240
10 100 µs
180
1 ms
10 ms
120
1.0 dc
RDS(on) LIMIT 60
THERMAL LIMIT
PACKAGE LIMIT
0.1 0
0.1 1.0 10 100 25 50 75 100 125 150

MTD20P06HDL

1.0
D = 0.5
0.2
(NORMALIZED)
0.1
P(pk)
0.1 0.05 RθJC(t) = r(t) RθJC
PULSE TRAIN SHOWN
0.01
1.0E–05 1.0E–04 1.0E–03 1.0E–02 1.0E–01 1.0E+00 1.0E+01
t, TIME (s)
di/dt
IS
trr
ta tb
TIME
tp 0.25 IS
IS

MOTOROLA
Product Preview
TMOS V MTD2955V
60 VOLTS
50 and 60 volt TMOS devices. Just as with our TMOS E–FET TM
power motor controls, these devices are particularly well suited for D
G
MOSFETs with New Low Voltage, Low RDS(on) Technology S
DPAK Surface Mount



MTD2955V
OFF CHARACTERISTICS
(VGS = 0 Vdc, ID = 0.25 mAdc) 60 — —
(VDS = 60 Vdc, VGS = 0 Vdc) — — 10
(VDS = VGS, ID = 250 µAdc) 2.0 2.8 4.0
(VGS = 10 Vdc, ID = 12 Adc) — — 2.9
(VGS = 10 Vdc, ID = 6.0 Adc, TJ = 150°C) — — 2.8
Vd VGS = 0 Vdc,
Vd
Coss — 200 280
f = 1.0 MHz)

VGS = 10 Vdc
Vdc,
((VDS = 48 Vdc, ID = 12 Adc, Q1 — 4.0 —

VGS = 10 Vdc) Q2 — 7.0 —
Q3 — 6.0 —
— 1.8 3.0
(IS = 12 Adc, VGS = 0 Vdc, TJ = 150°C)
— TBD —
((IS = 12 Adc, VGS = 0 Vdc, ta — 86 —

dIS/dt = 100 A/µs) tb — 28 —

MOTOROLA
Designer's  Data Sheet MTD3055V

TMOS V

60 VOLTS
bridge circuits where diode speed and commutating safe operating D
New Features of TMOS V G DPAK
MOSFETs with New Low Voltage, Low RDS(on) Technology
S

TMOS E–FET
Gate–Source Voltage – Continuous VGS ± 20 Vdc
Gate–Source Voltage – Non–repetitive (tp ≤ 10 ms) VGSM ± 25 Vpk
Drain Current – Continuous @ 25°C ID 12 Adc
Drain Current – Single Pulse (tp ≤ 10 µs) IDM 37 Apk
Single Pulse Drain–to–Source Avalanche Energy – Starting TJ = 25°C EAS 72 mJ
(VDD = 25 Vdc, VGS = 10 Vdc, IL = 12 Apk, L = 1.0 mH, RG = 25 Ω )
Thermal Resistance – Junction to Ambient RθJA 100
Thermal Resistance – Junction to Ambient, when mounted to minimum recommended pad size RθJA 71.4
E–FET, Designer’s and TMOS V are trademarks of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.
REV 2

MTD3055V
OFF CHARACTERISTICS
(VGS = 0 Vdc, ID = 250 µAdc) 60 – – Vdc
Temperature Coefficient (Positive) – 65 – mV/°C
(VDS = 60 Vdc, VGS = 0 Vdc) – – 10
(VDS = 60 Vdc, VGS = 0 Vdc, TJ = 150°C) – – 100
Gate–Body Leakage Current (VGS = ± 20 Vdc, VDS = 0) IGSS – – 100 nAdc
Temperature Coefficient (Negative) – 5.4 – mV/°C
Static Drain–Source On–Resistance (VGS = 10 Vdc, ID = 6.0 Adc) RDS(on) – 0.10 0.15 Ohm
(ID = 12 Adc) – 1.3 2.2
(ID = 6.0 Adc, TJ = 150°C) – – 1.9
Forward Transconductance (VDS = 7.0 Vdc, ID = 6.0 Adc) gFS 4.0 5.0 – mhos
Input Capacitance Ciss – 410 500 pF
Vd VGS = 0 Vdc,
Vd
Coss – 130 180
f = 1.0 MHz)
Reverse Transfer Capacitance Crss – 25 50

Turn–On Delay Time td(on) – 7.0 10 ns
Rise Time (VDD = 30 Vdc, ID = 12 Adc, tr – 34 60
VGS = 10 Vdc
Vdc,
Turn–Off Delay Time RG = 9.1 Ω) td(off) – 17 30
Fall Time tf – 18 50
Gate Charge QT – 12.2 17 nC
(See Fig
Figure
re 8)
((VDS = 48 Vdc, ID = 12 Adc, Q1 – 3.2 –
VGS = 10 Vdc) Q2 – 5.2 –
Q3 – 5.5 –
– 1.0 1.6
(IS = 12 Adc, VGS = 0 Vdc, TJ = 150°C)
– 0.91 –
Reverse Recovery Time trr – 56 – ns
(See Figure
Fig re 15)
((IS = 12 Adc, VGS = 0 Vdc, ta – 40 –
dIS/dt = 100 A/µs) tb – 16 –
Reverse Recovery Stored Charge QRR – 0.128 – µC
Internal Drain Inductance LD – 4.5 – nH
Internal Source Inductance LS – 7.5 – nH


MTD3055V
24 24
9V
20 20 100°C

25°C
7V
16 16
12 6V 12
8 8
5V
4 4
4V
0 0
0 1 2 3 4 5 2 3 4 5 6 7 8 9 10

R DS(on), DRAIN–TO–SOURCE RESISTANCE (OHMS)

0.3 0.15
VGS = 10 V TJ = 25°C
0.25 0.14
0.13
0.2
TJ = 100°C
0.12
0.15 VGS = 10 V
25°C 0.11
0.1
0.1
– 55°C 15 V
0.05
0.09
0 0.08
0 4 8 12 16 20 24 0 4 8 12 16 20 24
1.6 100
VGS = 0 V
VGS = 10 V
ID = 6 A
1.4
(NORMALIZED)
1.2
10
1.0
TJ = 125°C
0.8
0.6 1
– 50 – 25 0 25 50 75 100 125 150 175 0 10 20 30 40 50 60


MTD3055V
1200
VDS = 0 V VGS = 0 V TJ = 25°C
1000
Ciss
C, CAPACITANCE (pF)
800
600
Crss Ciss
400
Coss
200
Crss
0
10 5 0 5 10 15 20 25
VGS VDS

MTD3055V
12 60 1000

VDD = 30 V
QT
ID = 12 A
10 50 VGS = 10 V
VGS
TJ = 25°C
8 Q1 Q2 40 100
t, TIME (ns)
6 30 tr
td(off)
4 20 10 tf
ID = 12 A td(on)
TJ = 25°C
2 10
Q3 VDS
0 0 1
0 1 2 3 4 5 6 7 8 9 10 11 12 13 1 10 100

12
VGS = 0 V
TJ = 25°C
10
0
0.5 0.55 0.6 0.65 0.7 0.75 0.8 0.85 0.9 0.95 1.0
SAFE OPERATING AREA
temperature.

MTD3055V
SAFE OPERATING AREA
100 75
VGS = 20 V 10 µs ID = 12 A

SINGLE PULSE
TC = 25°C

10 50
100 µs
1 ms
1.0 10 ms 25
dc
RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT
0.1 0
0.1 1.0 10 100 25 50 75 100 125 150 175
1.0
D = 0.5
0.2
0.1
0.1 0.05 P(pk)

t1 READ TIME AT t1
0.01
1.0E–05 1.0E–04 1.0E–03 1.0E–02 1.0E–01 1.0E+00 1.0E+01
t, TIME (s)
di/dt
IS
trr
ta tb
TIME
tp 0.25 IS
IS

MOTOROLA
Designer's  Data Sheet MTD3055VL

TMOS V

60 VOLTS
MOSFETs with New Low Voltage, Low RDS(on) Technology G CASE 369A–13, Style 2
• Faster Switching than E–FET Predecessors DPAK Surface Mount
Features Common to TMOS V and TMOS E–FETS S
TMOS E–FET
Gate–Source Voltag — Single Pulse (tp ≤ 50 ms) VGSM ± 20 Vpk
REV 2

MTD3055VL
OFF CHARACTERISTICS
(VDS = 60 Vdc, VGS = 0 Vdc) — — 10
Gate–Body Leakage Current (VGS = ±15 Vdc, VDS = 0 Vdc) IGSS — — 100 nAdc
Static Drain–Source On–Resistance (VGS = 5.0 Vdc, ID = 6.0 Adc) RDS(on) — 0.12 0.18 Ohm
(ID = 12 Adc) — 1.6 2.6
(ID = 6.0 Adc, TJ = 150°C) — — 2.5
Vd VGS = 0 Vdc,
Vd
Coss — 114 160
f = 1.0 MHz)

VGS = 55.0
0 Vdc,
Vdc
(See Fig
Figure
re 8)
((VDS = 48 Vdc, ID = 12 Adc, Q1 — 1.8 —
VGS = 5 Vdc) Q2 — 4.2 —
Q3 — 3.8 —
— 0.97 1.3
(IS = 12 Adc, VGS = 0 Vdc, TJ = 150°C)
— 0.86 —
(See Figure
Fig re 14)
((IS = 12 Adc, VGS = 0 Vdc, ta — 37 —
dIS/dt = 100 A/µs) tb — 18.7 —


MTD3055VL
24 24
25°C
20 4.5 V 20 100°C

16 16
4V
12 12
3.5 V
8 8
3V
4 4
2.5 V
0 0
0 1 2 3 4 5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0


0.32 0.27
VGS = 5 V
TJ = 25°C
0.26
0.22
0.20 TJ = 100°C
0.17
0.14 25°C
– 55°C 0.12 5V
0.08
VGS = 10 V
0.02 0.07
0 4 8 12 16 20 24 0 4 8 12 16 20 24
2.0 100
VGS = 5 V VGS = 0 V
ID = 6 A
1.5
10 TJ = 125°C
(NORMALIZED)
1.0
1.0 100°C
0.5
0 0.1
– 50 – 25 0 25 50 75 100 125 150 175 0 10 20 30 40 50 60


MTD3055VL
1400
VDS = 0 V VGS = 0 V TJ = 25°C
1200 Ciss
C, CAPACITANCE (pF)
1000
800
600
Crss Ciss
400
Coss
200
Crss
0
10 5 0 5 10 15 20 25
VGS VDS

MTD3055VL
6 60 1000

QT VDD = 30 V
ID = 12 A
50 VGS = 5 V
TJ = 25°C
4 40 100 tr
t, TIME (ns)
VGS
tf
30
Q1 Q2 td(off)
2 20 10 td(on)
ID = 12 A
TJ = 25°C
10
Q3 VDS
0 0 1
0 2 4 6 8 10 1 10 100

12
VGS = 0 V
TJ = 25°C
10
0
0.50 0.55 0.60 0.65 0.70 0.75 0.80 0.85 0.90 0.95 1.0
SAFE OPERATING AREA
temperature.

MTD3055VL
SAFE OPERATING AREA
100 75
VGS = 5 V
ID = 12 A

SINGLE PULSE
TC = 25°C 10 µs

10 50
100 µs
1 ms
1.0 10 ms 25
dc
RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT
0.1 0
0.1 1.0 10 100 25 50 75 100 125 150 175
1.0
D = 0.5
0.2
0.1
0.1 0.05 P(pk)
PULSE TRAIN SHOWN
SINGLE PULSE
0.01
1.0E–05 1.0E–04 1.0E–03 1.0E–02 1.0E–01 1.0E+00 1.0E+01
t, TIME (s)
di/dt
IS
trr
ta tb
TIME
tp 0.25 IS
IS

MOTOROLA
Advance Information MTDF1N02HD

TMOS Dual N-Channel Motorola Preferred Device
Field Effect Transistor SINGLE TMOS

Micro8 devices are an advanced series of power MOSFETs
which utilize Motorola’s High Cell Density HDTMOS process to POWER MOSFET
achieve lowest possible on–resistance per silicon area. They are 1.7 AMPERES
capable of withstanding high energy in the avalanche and commuta- 20 VOLTS
tion modes and the drain–to–source diode has a very low reverse RDS(on) = 0.120 OHM
recovery time. Micro8 devices are designed for use in low voltage,
high speed switching applications where power efficiency is important. 
Typical applications are dc–dc converters, and power management in
portable and battery powered products such as computers, printers,
cellular and cordless phones. They can also be used for low voltage D
motor controls in mass storage products such as disk drives and tape
drives. The avalanche energy is specified to eliminate the guesswork
in designs where inductive loads are switched and offer additional
safety margin against unexpected voltage transients. CASE 846A–02, Style 2
G
• Miniature Micro8 Surface Mount Package — Saves Board Space Micro8
• Extremely Low Profile (<1.1mm) for thin applications such as
PCMCIA cards S
• Ultra Low RDS(on) Provides Higher Efficiency and Extends Battery Life Source1 1 8 Drain1
• Logic Level Gate Drive — Can Be Driven by Logic ICs Gate1 2 7 Drain1
• Diode Is Characterized for Use In Bridge Circuits Source2 3 6 Drain2
Gate2 4 5 Drain2
• Mounting Information for Micro8 Package Provided
THERMAL RESISTANCE
Thermal Resistance — Junction to Ambient, PCB Mount (1) RθJA 160 200 °C/W
— Junction to Ambient, PCB Mount (2) RθJA 240 300
— Junction to Ambient, PBD Mount (3) RθJA 80 100
(1) When mounted on FR–4/G–10 board using min. recommended footprint, based on PD in 1 die, 1 die operating. (VGS = 4.5 V, @ Steady State)
(2) When mounted on FR–4/G–10 board using min. recommended footprint, based on PD in 1 die, both dies operating. (VGS = 4.5 V, @ Steady State)
(3) When mounted on 1 inch square copper board, for comparison to the other SMD devices. (VGS = 4.5 V, @ Steady State)
BA
MTDF1N02HDR2 13″ 12 mm embossed tape 4000 units
REV 1

MTDF1N02HD
OFF CHARACTERISTICS
(VGS = 0 Vdc, ID = 250 µAdc) 20 — —
(VDS = 16 Vdc, VGS = 0 Vdc) — — 1.0
(VDS = VGS, ID = 250 µAdc) 0.7 0.9 —
(VGS = 4.5 Vdc, ID = 1.7 Adc) — 99 120
(VGS = 2.7 Vdc, ID = 0.85 Adc) — 133 160
Forward Transconductance (VDS = 10 Vdc, ID = 0.85 Adc) gFS 2.0 — — Mhos
Vd VGS = 0 Vdc,
Vd
Coss — 90 —
f = 1.0 MHz)
Turn–On Delay Time td(on) — 8.0 — ns
Rise Time ((VDS = 10 Vdc, ID = 1.7 Adc, tr — 27 —
Turn–Off Delay Time VGS = 4.5 Vdc, RG = 6 Ω) (1) td(off) — 23 —
Rise Time ((VDD = 10 Vdc, ID = 0.85 Adc, tr — 79 —
((VDS = 16 Vdc, ID = 1.7 Adc, Q1 — 0.4 —

VGS = 4.5 Vdc) Q2 — 1.7 —
Q3 — 1.5 —

(IS = 1.7 Adc, VGS = 0 Vdc) (1)
— 0.84 1.0
(IS = 1.7 Adc, VGS = 0 Vdc, TJ = 125°C)
— 0.71 —
(IS = 1
1.7
7 Ad
Adc, VGS = 0 Vdc,
Vd
ta — 14 —
dIS/dt = 100 A/µs) (1)
tb — 15 —
Cpk =
3 x SIGMA

MTDF1N02HD
4 4
TJ = 25°C VDS ≥ 10 V
VGS = 10 V

3 4.5 V 3
2.7 V 1.9 V
2.3 V
2.1 V
2 2
1.7 V
100°C
1 1.5 V 1 25°C
TJ = –55°C
0 0
0 0.4 0.8 1.2 1.6 2 0.5 1 1.5 2 2.5


0.6 0.15
ID = 1.7 A
2.7 V
0.5 TJ = 25°C
0.13 TJ = 25°C
0.4
0.11
VGS = 4.5 V
0.3
0.09
0.2
0.1 0.07
0 0.05
0 2 4 6 8 10 0 1 2 3 4

2.0 1000
VGS = 4.5 V VGS = 0 V
ID = 1.7 A TJ = 125°C
1.6
100
100°C
1.2
10
0.8
25°C
1
0.4
0 0.1
– 50 – 25 0 25 50 75 100 125 150 0 5 10 15 20


MTDF1N02HD
800
VDS = 0 V VGS = 0 V TJ = 25°C
Ciss
600
C, CAPACITANCE (pF)
Crss
400
200 Coss
Ciss
Crss
0
10 5 0 5 10 15 20
VGS VDS

MTDF1N02HD

6 18 100

QT VDD = 10 V
ID = 1.7 A
5 15 VGS = 4.5 V
TJ = 25°C tf
tr
4 12
td(off)
VDS VGS
t, TIME (ns)
3 9 10
Q1 Q2 td(on)
2 6
1 ID = 1.7 A 3
Q3 TJ = 25°C
0 0 1
0 1 2 3 4 5 1 10 100

snappy.
2.0
VGS = 0 V
TJ = 25°C
1.6
1.2
0.8
0.4
0
0.5 0.55 0.6 0.65 0.7 0.75 0.8 0.85 0.9

MTDF1N02HD
trr
High Cell Density
trr
tb
ta
t, TIME
SAFE OPERATING AREA
The Forward Biased Safe Operating Area curve (Figure – General Data and Its Use.”
12) defines the maximum simultaneous drain–to–source vol- Switching between the off–state and the on–state may tra-
tage and drain current that a transistor can handle safely verse any load line provided neither rated peak current (IDM)
when it is forward biased. Curves are based upon maximum nor rated voltage (VDSS) is exceeded, and that the transition
peak junction temperature and a case temperature (TC) of time (tr, tf) does not exceed 10 µs. In addition the total power
25°C. Peak repetitive pulsed power limits are determined by averaged over a complete switching cycle must not exceed
using the thermal response data in conjunction with the pro- (TJ(MAX) – TC)/(RθJC).
cedures discussed in AN569, “Transient Thermal Resistance
100
VGS = 8 V
SINGLE PULSE
TC = 25°C
10
100 µs
1 ms
10 ms
1
dc
0.1
RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT
0.01
0.1 1 10 100

Safe Operating Area

MTDF1N02HD
D = 0.5
THERMAL RESISTANCE
100
0.2
0.1
0.05
10
0.02 P(pk)
1 PULSE TRAIN SHOWN
t1 READ TIME AT t1
0.1
1.0E–05 1.0E–04 1.0E–03 1.0E–02 1.0E–01 1.0E+00 1.0E+01 1.0E+02 1.0E+03
t, TIME (s)
di/dt
IS
trr
ta tb
TIME
tp 0.25 IS
IS

MTDF1N02HD
TAPE & REEL INFORMATION
Micro8
Dimensions are shown in millimeters (inches)
2.05 (.080) 1.60 (.063)

1.95 (.077) 1.50 (.059)
PIN 4.10 (.161) B B A 1.85 (.072) 0.35 (.013)

NUMBER 1 3.90 (.154) 1.65 (.065) 0.25 (.010)
12.30 5.55 (.218)

11.70 5.45 (.215)
(.484) 3.50 (.137)
(.461) 3.30 (.130)
A 1.60 (.063) 1.50 (.059)

1.50 (.059) 1.30 (.052)
FEED DIRECTION TYP.
8.10 (.318)
7.90 (.312) SECTION A–A
5.40 (.212)
5.20 (.205)
SECTION B–B
NOTES:
1. CONFORMS TO EIA–481–1.
2. CONTROLLING DIMENSION: MILLIMETER.
18.4 (.724)
MAX.
NOTE 3
13.2 (.52)
12.8 (.50)
330.0 50.0
(13.20) (1.97)
MAX. MIN.
14.4 (.57)
12.4 (.49)
NOTE 4
NOTES:
3. INCLUDES FLANGE DISTORTION AT OUTER EDGE.
4. DIMENSION MEASURED AT INNER HUB.

MOTOROLA
Advance Information MTDF1N03HD

TMOS Dual N-Channel Motorola Preferred Device
Field Effect Transistor SINGLE TMOS

Micro8 devices are an advanced series of power MOSFETs
which utilize Motorola’s High Cell Density HDTMOS process to POWER MOSFET
achieve lowest possible on–resistance per silicon area. They are 1.7 AMPERES
capable of withstanding high energy in the avalanche and commuta- 30 VOLTS
tion modes and the drain–to–source diode has a very low reverse RDS(on) = 0.120 OHM
recovery time. Micro8 devices are designed for use in low voltage,
high speed switching applications where power efficiency is important. 
Typical applications are dc–dc converters, and power management in
portable and battery powered products such as computers, printers,
D
cellular and cordless phones. They can also be used for low voltage
motor controls in mass storage products such as disk drives and tape
drives. The avalanche energy is specified to eliminate the guesswork
in designs where inductive loads are switched and offer additional
safety margin against unexpected voltage transients. G CASE 846A–02, Style 2
• Miniature Micro8 Surface Mount Package — Saves Board Space Micro8
• Extremely Low Profile (<1.1mm) for thin applications such as
PCMCIA cards S
Source1 1 8 Drain1
Gate1 2 7 Drain1
• Diode Exhibits High Speed, With Soft Recovery Source2 3 6 Drain2
• IDSS Specified at Elevated Temperature Gate2 4 5 Drain2
Top View
• Mounting Information for Micro8 Package Provided
THERMAL RESISTANCE
Thermal Resistance — Junction to Ambient, PCB Mount (1) RθJA 160 200 °C/W
— Junction to Ambient, PCB Mount (2) RθJA 240 300
— Junction to Ambient, PBD Mount (3) RθJA 80 100
(1) When mounted on FR–4/G–10 board using min. recommended footprint, based on PD in 1 die, 1 die operating. (VGS = 10 V, @ Steady State)
(2) When mounted on FR–4/G–10 board using min. recommended footprint, based on PD in 1 die, both dies operating. (VGS = 10 V, @ Steady State)
(3) When mounted on 1 inch square copper board, for comparison to the other SMD devices. (VGS = 10 V, @ Steady State)
BB
MTDF1N03HDR2 13″ 12 mm embossed tape 4000 units
REV 1

MTDF1N03HD
OFF CHARACTERISTICS
(VGS = 0 Vdc, ID = 250 µAdc) 30 — —
(VDS = 24 Vdc, VGS = 0 Vdc) — — 1.0
(VDS = VGS, ID = 250 µAdc) 1.0 1.6 —
(VGS = 10 Vdc, ID = 1.7 Adc) — 96 120
(VGS = 4.5 Vdc, ID = 0.85 Adc) — 135 160
Forward Transconductance (VDS = 10 Vdc, ID = 0.85 Adc) (1) gFS 1.0 2.0 — Mhos
Vd VGS = 0 Vdc,
Vd
Coss — 70 —
f = 1.0 MHz)
Rise Time ((VDS = 15 Vdc, ID = 1.7 Adc, tr — 10 —
Turn–Off Delay Time VGS = 10 Vdc, RG = 6 Ω) (1) td(off) — 22 —
Rise Time ((VDD = 15 Vdc, ID = 0.85 Adc, tr — 8.2 —
Fall Time tf — 14.5 —
((VDS = 24 Vdc, ID = 1.7 Adc, Q1 — 0.5 —

VGS = 10 Vdc) Q2 — 1.65 —
Q3 — 1.3 —

(IS = 1.7 Adc, VGS = 0 Vdc) (1)
— 0.84 1.0
(IS = 1.7 Adc, VGS = 0 Vdc, TJ = 125°C)
— 0.7 —
(IS = 1
1.7
7 Ad
Adc, VGS = 0 Vdc,
Vd
ta — 12 —
dIS/dt = 100 A/µs) (1)
tb — 8.0 —
Cpk =
3 x SIGMA

MTDF1N03HD
4 4
VGS = 10 V 6V TJ = 25°C
3.5 V VDS ≥ 10 V
4.5 V
3.9 V

3 3.7 V 3
3.3 V
2 3.1 V 2
2.9 V
1 1 100°C
2.7 V
25°C
2.5 V
2.3 V TJ = –55°C
0 0
0 0.5 1 1.5 2 1.5 2 2.5 3 3.5 4 4.5


0.6 0.18
ID = 1.7 A TJ = 25°C
0.5 TJ = 25°C
0.16
VGS = 4.5
0.4
0.14
0.3
0.12
0.2
10 V
0.1 0.1
0 0.08
0 2 4 6 8 10 0 1 2 3 4

2.5 100
ID = 0.85 A TJ = 125°C
2.0
10
1.5 100°C
1.0
1
25°C
0.5
0 0.1
– 50 – 25 0 25 50 75 100 125 150 0 5 10 15 20 25 30


MTDF1N03HD
500
VDS = 0 V VGS = 0 V TJ = 25°C
Ciss
400
C, CAPACITANCE (pF)
300 Crss
200
Ciss
100 Coss
Crss
0
10 5 0 5 10 15 20 25 30
VGS VDS

MTDF1N03HD

12 30 100

VDD = 15 V
QT ID = 1.7 A
10 25 VGS = 10 V
TJ = 25°C
td(off)
8 20
tf
VDS VGS
t, TIME (ns)
6 15 10 tr
td(on)
4 Q1 Q2 10
2 ID = 1.7 A 5
Q3 TJ = 25°C
0 0 1
0 1 2 3 4 5 6 1 10 100

snappy.
2
VGS = 0 V
TJ = 25°C
1.5
0.5
0
0.6 0.65 0.7 0.75 0.8 0.85 0.9

MTDF1N03HD
trr
High Cell Density
trr
tb
ta
t, TIME
SAFE OPERATING AREA
The Forward Biased Safe Operating Area curve (Figure able operation, the stored energy from circuit inductance dis-
12) defines the maximum simultaneous drain–to–source vol- sipated in the transistor while in avalanche must be less than
tage and drain current that a transistor can handle safely the rated limit and must be adjusted for operating conditions
when it is forward biased. Curves are based upon maximum differing from those specified. Although industry practice is to
peak junction temperature and a case temperature (TC) of rate in terms of energy, avalanche energy capability is not a
25°C. Peak repetitive pulsed power limits are determined by constant. The energy rating decreases non–linearly with an
using the thermal response data in conjunction with the pro- increase of peak current in avalanche and peak junction tem-
cedures discussed in AN569, “Transient Thermal Resistance
perature.
– General Data and Its Use.”
100 200
VGS = 20 V VDD = 30 V
SINGLE PULSE VGS = 10 V

TC = 25°C 160
10 µs IL = 2.4 A
10
L = 69 mH
100 µs 120
1 1 ms
10 ms 80
0.1
RDS(on) LIMIT 40
THERMAL LIMIT
dc
PACKAGE LIMIT
0.01 0
0.1 1 10 100 25 50 75 100 125 150

MTDF1N03HD
D = 0.5
THERMAL RESISTANCE
100
0.2
0.1
0.05
10
0.02 P(pk)
1 PULSE TRAIN SHOWN
t1 READ TIME AT t1
0.1
1.0E–05 1.0E–04 1.0E–03 1.0E–02 1.0E–01 1.0E+00 1.0E+01 1.0E+02 1.0E+03
t, TIME (s)
di/dt
IS
trr
ta tb
TIME
tp 0.25 IS
IS

MTDF1N03HD
TAPE & REEL INFORMATION
Micro8
Dimensions are shown in millimeters (inches)
2.05 (.080) 1.60 (.063)

1.95 (.077) 1.50 (.059)
PIN 4.10 (.161) B B A 1.85 (.072) 0.35 (.013)

NUMBER 1 3.90 (.154) 1.65 (.065) 0.25 (.010)
12.30 5.55 (.218)

11.70 5.45 (.215)
(.484) 3.50 (.137)
(.461) 3.30 (.130)
A 1.60 (.063) 1.50 (.059)

1.50 (.059) 1.30 (.052)
FEED DIRECTION TYP.
8.10 (.318)
7.90 (.312) SECTION A–A
5.40 (.212)
5.20 (.205)
SECTION B–B
NOTES:
18.4 (.724)
MAX.
NOTE 3
13.2 (.52)
12.8 (.50)
330.0 50.0
(13.20) (1.97)
MAX. MIN.
14.4 (.57)
12.4 (.49)
NOTE 4
NOTES:
3. INCLUDES FLANGE DISTORTION AT OUTER EDGE.
4. DIMENSION MEASURED AT INNER HUB.

MOTOROLA
Advance Information MTE30N50E

ISOTOP TMOS E-FET. Motorola Preferred Device

TMOS POWER FET
This advanced TMOS E–FET is designed to withstand high 30 AMPERES
energy in the avalanche mode and switch efficiently. This new 500 VOLTS
energy design also offers a drain–to–source diode with fast RDS(on) = 0.150 OHM
recovery time. Designed for high voltage, high speed switching
applications in power supplies, PWM motor controls, and other

inductive loads. The avalanche energy capability is specified to
switched and offer additional safety margin against unexpected 4
voltage transients. 1 3
• 2500 V RMS Isolated ISOTOP Package 2
D
Fast Recovery Diode
• Very Low Internal Parasitic Inductance G
• IDSS and VDS(on) Specified at Elevated Temperature SOT–227B
• U.L. Recognized, File #E69369 S
1. Source
2. Gate
3. Drain
4. Source 2
(VDD = 100 Vdc, VGS = 10 Vdc, Peak IL= 30 Apk, L = 10 mH, RG = 25 Ω) 3000

MTE30N50E
OFF CHARACTERISTICS
(VGS = 0 Vdc, ID = 0.25 mAdc) 500 560 —
(VDS = 500 Vdc, VGS = 0 Vdc) — — 10
(VDS = VGS, ID = 250 µAdc) 2.0 3.2 4.0
Static Drain–to–Source On–Resistance (VGS = 10 Vdc, ID = 15 Adc) RDS(on) — 0.13 0.15 Ohms
(VGS = 10 Vdc, ID = 30 Adc) — 4.1 5.0
(VGS = 10 Vdc, ID = 15 Adc) — — 7.0
Forward Transconductance (VDS = 15 Vdc, ID = 15 Adc) gFS 17 — — mhos
Vd VGS = 0 Vdc,
Vd
Coss — 775 1200
f = 1.0 MHz)

VGS = 10 Vdc
Vdc,
(see fig
figure
re 8)
((VDS = 400 Vdc, ID = 30 Adc, Q1 — 35 —
VGS = 10 Vdc) Q2 — 110 —
Q3 — 65 —
— 0.95 1.2
(IS = 30 Adc, VGS = 0 Vdc, TJ = 125°C)
— 0.88 —
((IS = 30 Adc, VGS = 0 Vdc, ta — 312 —

dIS/dt = 100 A/µs) tb — 173 —

MTE30N50E
60 60
TJ = 25°C VGS = 10 V VDS ≥ 10 V
50 50

8V
40 6V 40
30 5V 30
20 20 100°C
10 10 25°C
4V
TJ = – 55°C
0 0
0 2 4 6 8 10 12 2 2.5 3 3.5 4 4.5 5 5.5 6 6.5 7


0.35 0.17
VGS = 10 V TJ = 25°C
0.3
TJ = 100°C 0.16
0.25
0.15
0.2
25°C VGS = 10 V
0.15 0.14
0.1 15 V
– 55°C
0.13
0.5
0 0.12
0 10 20 30 40 50 60 0 10 20 30 40 50 60
2.5 10000
ID = 15 A TJ = 125°C
2
1000
I DSS, LEAKAGE (nA)
100°C
(NORMALIZED)
1.5
100
1
25°C
10
0.5
0 1
– 50 – 25 0 25 50 75 100 125 150 0 100 200 300 400 500


MTE30N50E
24000 100000
VDS = 0 V VGS = 0 V TJ = 25°C VGS = 0 V TJ = 25°C
20000
Ciss 10000 Ciss
C, CAPACITANCE (pF)
C, CAPACITANCE (pF)
16000
12000 Crss 1000 Coss

Ciss
8000
Crss
100
Coss
4000
Crss
0 10
10 5 0 5 10 15 20 25 10 100 1000
VGS VDS
GATE–TO–SOURCE OR DRAIN–TO–SOURCE VOLTAGE (VOLTS) DRAIN–TO–SOURCE VOLTAGE (VOLTS)
Figure 7. Capacitance Variation Figure 7b. High Voltage Capacitance Variation

MTE30N50E
12

600 10000

VDD = 250 V
QT ID = 30 A
10 500 VGS = 10 V
TJ = 25°C
8 VGS 400 1000
t, TIME (ns)
6 Q1 Q2
300
td(off)
tf
4 200 100
tr
ID = 30 A
2 TJ = 25°C td(on)
100
Q3 VDS
0 0 10
0 50 100 150 200 250 1 10 100
Figure 8. Gate–To–Source and Figure 9. Resistive Switching Time

Drain–To–Source Voltage versus Total Charge Variation versus Gate Resistance
SAFE OPERATING AREA
The Forward Biased Safe Operating Area curves define aged over a complete switching cycle must not exceed
drain current that a transistor can handle safely when it is for- A Power MOSFET designated E–FET can be safely used
thermal response data in conjunction with the procedures the rated limit and adjusted for operating conditions differing
discussed in AN569, “Transient Thermal Resistance–General from those specified. Although industry practice is to rate in
Data and Its Use.” terms of energy, avalanche energy capability is not a con-
Switching between the off–state and the on–state may tra- stant. The energy rating decreases non–linearly with an in-
verse any load line provided neither rated peak current (IDM) crease of peak current in avalanche and peak junction
nor rated voltage (VDSS) is exceeded and the transition time temperature.
(tr,tf) do not exceed 10 µs. In addition the total power aver-
9 30
dlS/dt = 100 A/µs VGS = 0 V
8 VDD = 50 V TJ = 25°C
QRR, STORED CHARGE (µ C)
TJ = 25°C
7
20
6
5
10
4
2 0
0 6 12 18 24 30 0.5 0.55 0.6 0.65 0.7 0.75 0.8 0.85 0.9 0.95
IS, SOURCE CURRENT (AMPS) VSD, SOURCE–TO–DRAIN VOLTAGE (VOLTS)
Figure 10. Stored Charge Figure 11. Diode Forward Voltage versus Current

MTE30N50E
SAFE OPERATING AREA
100 3000

VGS = 20 V 10 µs ID = 30 A
SINGLE PULSE
2500

TC = 25°C
10 100 µs 2000
1 ms
10 ms 1500
dc
1 1000
RDS(on) LIMIT
THERMAL LIMIT 500
PACKAGE LIMIT
0.1 0
0.1 1 10 100 1000 25 50 75 100 125 150
1.0
r(t), EFFECTIVE TRANSIENT THERMAL
D = 0.5
0.2
0.1
0.05
0.1
0.02
0.01
SINGLE PULSE
0.01
1.0E–05 1.0E–04 1.0E–03 1.0E–02 1.0E–01 1.0E+00 1.0E+01
t, TIME (s)
di/dt
IS
trr
ta tb
TIME
tp 0.25 IS
IS

MOTOROLA
 Data Sheet
Designer's
MTE53N50E

TMOS POWER FET
This advanced high voltage TMOS E–FET is designed to 53 AMPERES
This new high energy device also offers a drain–to–source diode RDS(on) = 0.080 OHM

is specified to eliminate the guesswork in designs where inductive
loads are switched and offer additional safety margin against 4
unexpected voltage transients. 1 3
• 2500 V RMS Isolated Isotop Package 2
Fast Recovery Diode
D
• Very Low Internal Parasitic Inductance
• U. L. Recognized, File #E69369
1. Source
G 2. Gate
3. Drain
4. Source 2
S
Single Pulse Drain–to–Source Avalanche Energy EAS mJ
(VDD = 25 Vdc, VGS = 10 Vdc, IL= 53 Apk, L = 0.29 mH, RG =25Ω) 400
RMS Isolation Voltage VISO 2500 Vac
REV 1

MTE53N50E
OFF CHARACTERISTICS
(VGS = 0 Vdc, ID = 250 µAdc) 500 560 — Vdc
(VDS = 500 Vdc, VGS = 0 Vdc) — — 10
Threshold Temperature Coefficient (Negative) — — — mV/°C
Static Drain–Source On–Resistance (VGS = 10 Vdc, ID = 26.5 Adc) RDS(on) — 63 80 mOhm
Drain–Source On–Voltage (VGS = Vdc) VDS(on) Vdc
(ID = 53 Adc) — — 4.8
(ID = 26.5 Adc, TJ = 125°C) — — 4.3
Forward Transconductance (VDS = 15 Vdc, ID = 26.5 Adc) gFS 25 45 — mhos
Vd VGS = 0 Vdc,
Vd
Coss — 1560 —
f = 1.0 MHz)

Rise Time (VDD = 250 Vdc, ID = 53 Adc, tr — 322 —
VGS = 10 Vdc
Vdc,
((VDS = 400 Vdc, ID = 53 Adc, Q1 — 86 —

VGS = 10 Vdc) Q2 — 206 —
Q3 — 148 —
— 0.95 1.3
(IS = 53 Adc, VGS = 0 Vdc, TJ = 125°C)
— 0.90 —
((IS = 53 Adc, VGS = 0 Vdc, ta — 460 —

dIS/dt = 100 A/µs) tb — 260 —
Reverse Recovery Stored Charge QRR — 15 — µC
(Measured from the source lead 0.25″ from package to center of die)

MTE53N50E
120 120
VGS = 10 V
TJ = 25°C VDS ≥ 10 V
100 8V 100

7V
80 6V 80
60 5V 60 100°C
40 40
25°C
20 20
4V TJ = – 55°C
0 0
0 1 2 3 4 5 6 7 8 9 2 3 4 5 6


0.16 0.085
VGS = 10 V TJ = 25°C
TJ = 100°C
0.08
0.12
0.075
0.08 25°C VGS = 10 V
0.07
0.04 – 55°C 15 V
0.065
0 0.06
0 20 40 60 80 100 120 0 20 40 60 80 100 120
2.5 100000
ID = 26.5 A TJ = 125°C
2 10000
I DSS, LEAKAGE (nA)
(NORMALIZED)
100°C
1.5 1000
1 100
25°C
0.5 10
0 1
– 50 – 25 0 25 50 75 100 125 150 0 100 200 300 400 500


MTE53N50E
60000 100000
VDS = 0 V VGS = 0 V TJ = 25°C VGS = 0 V TJ = 25°C
50000 Ciss
Ciss
10000
C, CAPACITANCE (pF)
C, CAPACITANCE (pF)
40000
Coss
30000 Crss 1000
20000 Ciss
Crss
100
10000 Coss
Crss
0 10
10 5 0 5 10 15 20 25 10 100 1000
VGS VDS DRAIN–TO–SOURCE VOLTAGE (VOLTS)
Figure 7. Capacitance Variation Figure 7b. High Voltage Capacitance Variation

MTE53N50E
12 420 10000

VDD = 250 V
QT ID = 53 A
10 350
VGS = 10 V
TJ = 25°C td(off)
8 VGS 280 1000
t, TIME (ns)
tr
6 210 tf
Q1 Q2
td(on)
ID = 53 A
4 TJ = 25°C 140 100
2 70
Q3 VDS
0 0 10
0 100 200 300 400 500 1 10 100

SAFE OPERATING AREA
60
VGS = 0 V
50 TJ = 25°C
40
30
20
10
0
0.5 0.6 0.7 0.8 0.9 1 1.1

MTE53N50E
SAFE OPERATING AREA
1000 400

VGS = 20 V ID = 53 A
SINGLE PULSE 350

TC = 25°C 100 µs
100 300
1 ms 250
10 10 ms 200
dc 150
1 100
RDS(on) LIMIT
THERMAL LIMIT 50
PACKAGE LIMIT
0.1 0
0.1 1 10 100 1000 25 50 75 100 125 150
1
D = 0.5
0.2
0.1 0.1
0.05
0.02
0.01
0.01 CHIP 0.0315 Ω 0.1856 Ω 0.0629 Ω
JUNCTION
0.0318 F 0.1239 F 0.9536 F
0.001
SINGLE PULSE AMBIENT
0.0001
1.0E–05 1.0E–04 1.0E–03 1.0E–02 1.0E–01 1.0E+00 1.0E+01
t, TIME (s)
di/dt
IS
trr
ta tb
TIME
tp 0.25 IS
IS

MOTOROLA
 Data Sheet
Designer's
MTE125N20E

TMOS POWER FET

Fast Recovery Diode
D
• U.L. Recognized, File #E69369
1. Source
G 2. Gate
3. Drain
4. Source 2
S
(VDD = 50 Vdc, VGS = 10 Vdc, IL = 125 Apk, L = 0.05mH, RG = 25 Ω) 400
REV 1

MTE125N20E
OFF CHARACTERISTICS
(VDS = 200 Vdc, VGS = 0 Vdc) — — 10
Static Drain–Source On–Resistance (VGS = 10 Vdc, ID = 62.5 Adc) RDS(on) — 12 15 mOhm
(ID = 125 Adc) — — 2.1
(ID = 62.5 Adc, TJ = 125°C) — — 1.9
Vd VGS = 0 Vdc,
Vd
Coss — 3600 —
f = 1.0 MHz)

VGS = 10 Vdc
Vdc,
((VDS = 160 Vdc, ID = 125 Adc, Q1 — 100 —

VGS =10 Vdc) Q2 — 245 —
Q3 — 158 —
— 1.00 1.5
(IS = 125 Adc, VGS = 0 Vdc, TJ = 125°C)
— 1.00 —
((IS = 125 Adc, VGS = 0 Vdc, ta — 220 —

dIS/dt = 100 A/µs) tb — 90 —

MTE125N20E
210 160
VGS = 10 V
TJ = 25°C 7V VDS ≥ 10 V
8V
9V

120
140 6V
80
70 5V 100°C
40 25°C
4V TJ = – 55°C
0 0
0 1 2 3 4 5 6 3 4 5 6 7


0.028 0.02
VGS = 10 V
TJ = 100°C TJ = 25°C
0.024
0.018 VGS = 10 V
0.02
25°C
0.016 0.016
0.012 15 V
– 55°C 0.014
0.008
0.004 0.012
0 40 80 120 160 200 0 40 80 120 160 200
2.2 100000
1.8 ID = 62.5 A 10000 TJ = 125°C
I DSS, LEAKAGE (nA)
(NORMALIZED)
100°C
1.4 1000
1 100
25°C
0.6 10
0.2 1
– 50 – 25 0 25 50 75 100 125 150 0 50 100 150 200


MTE125N20E
60000
VDS = 0 V VGS = 0 V TJ = 25°C
Ciss
C, CAPACITANCE (pF)
40000
Crss
20000 Ciss
Coss
Crss
0
10 5 0 5 10 15 20 25
VGS VDS

MTE125N20E
12 120 1000

VDD = 250 V
QT ID = 125 A tr
10 100 tf
VGS = 10 V
TJ = 25°C td(off)
8 VGS 80
t, TIME (ns)
6 Q1 Q2 60 100
td(on)
ID = 62.5 A
4 TJ = 25°C 40
2 20
Q3 VDS
0 0 10
0 60 120 180 240 300 360 420 480 540 1 10 100

SAFE OPERATING AREA
125
VGS = 0 V
TJ = 25°C
100
75
50
25
0
0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2

MTE125N20E
SAFE OPERATING AREA
1000 400

VGS = 20 V ID = 125 A
SINGLE PULSE 350

TC = 25°C 100 µs 300

100
250
1 ms 200
150
10 10 ms
100
RDS(on) LIMIT
THERMAL LIMIT dc 50
PACKAGE LIMIT
1 0
0.1 1 10 100 1000 25 50 75 100 125 150
1
D = 0.5
0.2
0.1
0.1
0.05
0.02 CHIP 0.0174 Ω 0.1409 Ω 0.1217 Ω

JUNCTION
0.01 0.01 0.0 F 0.0994 F 0.5750 F
AMBIENT
SINGLE PULSE
0.001
1.0E–05 1.0E–04 1.0E–03 1.0E–02 1.0E–01 1.0E+00 1.0E+01
t, TIME (s)
di/dt
IS
trr
ta tb
TIME
tp 0.25 IS
IS

MOTOROLA
 Data Sheet
Designer's
MTE215N10E

TMOS POWER FET
controls and other inductive loads, the avalanche energy capability 
Fast Recovery Diode
D
• U. L. Recognized, File #E69369
1. Source
G 2. Gate
3. Drain
4. Source 2
S
(VDD = 25 Vdc, VGS = 10 Vdc, IL = 215 Apk, L = 0.017 mH, RG = 25 Ω,) 400
REV 1

MTE215N10E
OFF CHARACTERISTICS
(VDS = 100 Vdc, VGS = 0 Vdc) — — 10
Static Drain–Source On–Resistance (VGS = 10 Vdc, ID = 107.5 Adc) RDS(on) — 4.6 5.5 mOhm
(ID = 215 Adc) — — 1.5
(ID = 107.5 Adc, TJ = 125°C) — — 1.2
Vd VGS = 0 Vdc,
Vd
Coss — 6600 —
f = 1.0 MHz)

VGS = 10 Vdc
Vdc,
((VDS = 80 Vdc, ID = 215 Adc, Q1 — 104 —

VGS =10 Vdc) Q2 — 300 —
Q3 — 440 —
— 1.0 1.5
(IS = 215 Adc, VGS = 0 Vdc, TJ = 125°C)
— 1.2 —
((IS = 215 Adc, VGS = 0 Vdc, ta — 90 —

dIS/dt = 100 A/µs) tb — 55 —
(Measured from the source lead 0.25″ from package to source pad)

MTE215N10E
220 240
VGS = 10 V VDS ≥ 5 V
7V
9V 8V 200

165
TJ = 25°C 100°C
6V 160
110 120 25°C
5V
80
55
40 TJ = – 55°C
4V
0 0
0 0.5 1 1.5 2 2.5 3 3.5 4 1 2 3 4 5 6 7 8


0.018 0.016
VGS = 10 V TJ = 25°C
0.016
0.014
0.014
0.012 0.012
TJ = 100°C
0.01 0.01
25°C
0.008
VGS = 10 V
0.008
0.006 – 55°C 15 V
0.004 0.006
0 50 100 150 200 250 0 50 100 150 200 250
1.6 100000
1.4 ID = 107.5 A 10000 TJ = 125°C
I DSS, LEAKAGE (nA)
(NORMALIZED)
1.2 1000 100°C
1 100
25°C
0.8 10
0.6 1
– 50 – 25 0 25 50 75 100 125 150 0 20 40 60 80 100


MTE215N10E
60000
VDS = 0 V VGS = 0 V TJ = 25°C
50000
Ciss
C, CAPACITANCE (pF)
40000
30000 Crss
20000 Ciss
Coss
10000
Crss
0
10 5 0 5 10 15 20 25
VGS VDS

MTE215N10E
12 120 1000

tr
QT tf
10 100
td(off)
8 80
t, TIME (ns)
Q1 VGS
Q2
6 60 100
td(on)
4 40
VDD = 50 V
ID = 215 A ID = 215 A
2 20 VGS = 10 V
TJ = 25°C
VDS TJ = 25°C
Q3
0 0 10
0 200 400 600 800 1000 1200 1 10 100

SAFE OPERATING AREA
220
200 VGS = 0 V
180 TJ = 25°C
160
140
120
100
80
60
40
20
0
0.5 0.7 0.9 1.1 1.3 1.5 1.7

MTE215N10E
SAFE OPERATING AREA
1000 400

VGS = 20 V 10 µs ID = 215 A
SINGLE PULSE 350
100 µs

TC = 25°C
300
100 1 ms
250
200
10 ms
150
10
RDS(on) LIMIT dc 100
THERMAL LIMIT
PACKAGE LIMIT 50
1 0
0.1 1 10 100 25 50 75 100 125 150
1
D = 0.5
0.2
0.1 0.1
0.05
0.02
0.01
0.01 CHIP 0.0307 Ω 0.1127 Ω 0.1366 Ω
JUNCTION
0.0325 F 0.1065 F 0.6663 F
0.001
SINGLE PULSE AMBIENT
0.0001
1.0E–05 1.0E–04 1.0E–03 1.0E–02 1.0E–01 1.0E+00 1.0E+01
t, TIME (s)
di/dt
IS
trr
ta tb
TIME
tp 0.25 IS
IS

MOTOROLA
 Data Sheet
Designer's
MTP1N50E

TMOS POWER FET
degrading performance over time. In addition, this advanced TMOS RDS(on) = 5.0 OHM
• Source–to–Drain Diode Recovery Time Comparable to a Discrete D
Fast Recovery Diode
G
TO–220AB
S
(VDD = 100 Vdc, VGS =10 Vdc, IL = 3.0 Apk, L =10 mH, RG = 25 Ω)
— Junction to Case RθJC 3.13
— Junction to Ambient, when surface mounted using minimum recommended pad size RθJA 62.5
REV 1

MTP1N50E
OFF CHARACTERISTICS
(VDS = 500 Vdc, VGS = 0 Vdc) — — 10
(VDS = 500 Vdc, VGS = 0 Vdc, TJ = 125 °C) — — 100
(ID = 1 .0 Adc) — 4.5 6.0
(ID = 0.5 Adc, TJ = 125 °C) — — 5.30
Vd VGS = 0 Vdc,
Vd
Coss — 30.2 42
f = 1.0 MHz)

VGS = 10 Vdc
Vdc,
(See Fig
Figure
re 8)
((VDS = 400 Vdc, ID = 1.0 Adc, Q1 — 1.6 —
VGS = 10 Vdc) Q2 — 3.8 —
Q3 — 5 —
Forward On–Voltage (1) (IS = 1.0 Adc, VGS = 0 Vdc) VSD Vdc
(IS = 1.0 Adc, VGS = 0 Vdc, — 0.81 1.2
TJ = 125 °C) — 0.68 —
(See Figure
Fig re 14)
((IS = 1.0 Adc, VGS = 0 Vdc, ta — 85 —
dIS/dt = 100 A/µs) tb — 60 —

MTP1N50E
2.0 2.0
TJ = 25°C VGS = 10 V 7V VDS ≥ 10 V
1.75 1.75
8V

1.50 6V 1.50
1.25 1.25
1.0 1.0
0.75 0.75
0.50 5V 0.50 TJ = 100°C

25°C
0.25 0.25
– 55°C
0 0
0 2 4 6 8 10 12 14 16 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5


10 6.0
VGS = 10 V TJ = 25°C
TJ = 100°C 5.5
8
5.0
6 VGS = 10 V
25°C 4.5
4 15 V
4.0
– 55°C
2
3.5
0 3.0
0 0.4 0.8 1.2 1.6 2.0 0 0.25 0.50 0.75 1.0 1.25 1.50 1.75 2.0
2.5 10000
ID = 0.5 A
2.0
1000 TJ = 125°C
(NORMALIZED)
1.5
100°C
100
1.0
10 25°C
0.5
0 1
–50 –25 0 25 50 75 100 125 150 0 100 200 300 400 500


MTP1N50E
500 1000
450
TJ = 25°C
400 Ciss
350 Ciss
C, CAPACITANCE (pF)
C, CAPACITANCE (pF)
100
300
250 Ciss Coss
200
10
150
Crss
100 Crss
50 Crss Coss
0 1
10 5 0 5 10 15 20 25 10 100 1000
GATE–TO–SOURCE OR DRAIN–TO–SOURCE VOLTAGE (VOLTS) Figure 7b. High Voltage Capacitance

MTP1N50E
12 360 100

VDD = 250 V
QT
ID =1 A
10 300 VGS = 10 V
VGS
Q1 TJ = 25°C
Q2
8 240
t, TIME (ns)
tf
td(off)
6 180 10 td(on)
tr
4 120
ID = 1 A
TJ = 25°C
2 60
Q3
VDS
0 0 1
0 2 4 6 8 1 10 100

1.0
VGS = 0 V
TJ = 25°C
0.8
0.6
0.4
0.2
0
0.50 0.54 0.58 0.62 0.66 0.70 0.74 0.78 0.82
SAFE OPERATING AREA
temperature.

MTP1N50E
SAFE OPERATING AREA
10 50
VGS = 20 V

10 µs ID = 1 A
SINGLE PULSE
TC = 25°C
40

1.0
100 µs 30
1 ms
10 ms 20
0.1
dc
RDS(on) LIMIT 10
THERMAL LIMIT
PACKAGE LIMIT
0.01 0
0.1 1.0 10 100 1000 25 50 75 100 125 150
1.0
D = 0.5
0.2
0.1
0.05 P(pk)
0.1
t1 READ TIME AT t1
SINGLE PULSE
0.01
1.0E–05 1.0E–04 1.0E–03 1.0E–02 1.0E–01 1.0E+00 1.0E+01
t,TIME (ms)
di/dt
IS
trr
ta tb
TIME
tp 0.25 IS
IS

MOTOROLA
 Data Sheet
Designer's
MTP1N60E

TMOS POWER FET
D
Fast Recovery Diode
G
TO–220AB
S


REV 1

MTP1N60E
OFF CHARACTERISTICS
(VDS = 600 Vdc, VGS = 0 Vdc) — — 10
(ID = 1.0 Adc) — 6.4 9.6
(ID = 0.5 Adc, TJ = 125°C) — — 8.4
Vd VGS = 0 Vdc,
Vd
Coss — 27 40
f = 1.0 MHz)

Rise Time (VDD = 300 Vdc, ID = 1.0 Adc, tr — 6.8 13.6
VGS = 10 Vdc
Vdc,
(See Fig
Figure
re 8)
((VDS = 300 Vdc, ID = 1.0 Adc, Q1 — 1.7 —
VGS = 10 Vdc) Q2 — 3.2 —
Q3 — 3.9 —
— 0.82 1.4
(IS = 1.0 Adc, VGS = 0 Vdc, TJ = 125°C)
— 0.7 —
(See Figure
Fig re 14)
((IS = 1.0 Adc, VGS = 0 Vdc, ta — 36 —
dIS/dt = 100 A/µs) tb — 428 —

MTP1N60E
2 2
TJ = 25°C VGS = 10 V VDS ≥ 10 V
1.8 7V

1.6 6V 1.6
1.4
1.2 1.2
1
0.8 0.8
25°C
0.6 5V 100°C
0.4 0.4 TJ = – 55°C
0.2
4V
0 0
0 2 4 6 8 10 12 14 16 18 20 2 2.4 2.8 3.2 3.6 4 4.4 4.8 5.2 5.6 6 6.4 6.8


16 9
VGS = 10 V TJ = 25°C
14 8.5
12 TJ = 100°C 8
10 7.5
8 7
25°C VGS = 10 V
6 6.5
4 15 V
– 55°C 6
2 5.5
0 5
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
2.4 1000
VGS = 0 V
VGS = 10 V TJ = 125°C
2 ID = 0.5 A
100°C
1.6 100
(NORMALIZED)
1.2
0.8 10
25°C
0.4
0 1
– 50 – 25 0 25 50 75 100 125 150 0 100 200 300 400 500 600


MTP1N60E
500 1000
VDS = 0 V VGS = 0 V TJ = 25°C
VGS = 0 V
450
Ciss TJ = 25°C Ciss
400
C, CAPACITANCE (pF)
350
C, CAPACITANCE (pF)
100
300
250 Ciss
Crss
200 Coss
10
150
100 Crss
Coss
50
Crss
0 1
10 5 0 5 10 15 20 25 10 100 1000

MTP1N60E
100

12 600

QT VDD = 300 V
10 500 ID = 1 A
VGS = 10 V
VGS TJ = 25°C
8 400
t, TIME (ns)
tf
Q1 Q2 td(off)
6 ID = 1 A 300 10 td(on)
TJ = 25°C
4 200 tr
2 100
Q3
VDS
0 0 1
0 1 2 3 4 5 6 7 8 1 10 100

1
VGS = 0 V
TJ = 25°C
0.8
0.6
0.4
0.2
0
0.5 0.54 0.58 0.62 0.66 0.7 0.74 0.78 0.82
SAFE OPERATING AREA

temperature.

MTP1N60E
SAFE OPERATING AREA
10 50
VGS = 20 V

ID = 1 A
SINGLE PULSE
10 µs
TC = 25°C 40

1
100 µs 30
0.1 1 ms
dc
10 ms 20
0.01
RDS(on) LIMIT 10
THERMAL LIMIT
PACKAGE LIMIT
0.001 0
0.1 1 10 100 1000 25 50 75 100 125 150
1
D = 0.5
0.2
0.1
P(pk)
0.1 0.05 RθJC(t) = r(t) RθJC
0.01
1.0E–05 1.0E–04 1.0E–03 1.0E–02 1.0E–01 1.0E+00 1.0E+01
t, TIME (s)
di/dt
IS
trr
ta tb
TIME
tp 0.25 IS
IS

MOTOROLA
 Data Sheet
Designer's
MTP1N80E

TMOS POWER FET
degrading performance over time. In addition, this advanced TMOS RDS(on) = 12 OHMS
D
Fast Recovery Diode

TO–220AB

(VDD = 100 Vdc, VGS = 10 Vdc, IL = 2.0 Apk, L = 10 mH, RG = 25 Ω) 20
Thermal Resistance — Junction to Case° RθJC 2.63° °C/W
— Junction to Ambient° RθJA 62.5°

MTP1N80E
OFF CHARACTERISTICS
(VGS = 0 Vdc, ID = 0.25 mAdc) 800 — —
(VDS = 800 Vdc, VGS = 0 Vdc) — — 10
(VDS = VGS, ID = 250 µAdc) 2.0 3.3 4.0
Static Drain–to–Source On–Resistance (VGS = 10 Vdc, ID = 0.5 Adc) RDS(on) — 10.3 12 Ohm
(VGS = 10 Vdc, ID = 1.0 Adc) — 11 14.4
(VGS = 10 Vdc, ID = 0.5 Adc, TJ = 125°C) — — 12.6
Vd VGS = 0 Vdc,
Vd
Coss — 29 40
f = 1.0 MHz)

VGS = 10 Vdc
Vdc,
((VDS = 400 Vdc, ID = 1.0 Adc, Q1 — 2.1 —

VGS = 10 Vdc) Q2 — 4.2 —
Q3 — 4.7 —
— 0.82 1.2
(IS = 1.0 Adc, VGS = 0 Vdc, TJ = 125°C)
— 0.7 —
((IS = 1.0 Adc, VGS = 0 Vdc, ta — 56 —

dIS/dt = 100 A/µs) tb — 261 —

MTP1N80E
2.0 TJ = 25°C 2.0

VDS ≥ 10 V

1.6 VGS = 10 V 1.6
6V
1.2 8V 1.2
0.8 0.8
5V
TJ = 100°C
0.4 0.4 25°C
4V
–55°C
0 0
0 5 10 15 20 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0


18 16
VGS = 10 V TJ = 25°C
15 100°C 15
14
12
TJ = 25°C 13
9
12 VGS = 10 V
6
–55°C 11
15 V
3
10
0 9
0 0.25 0.50 0.75 1.0 1.25 1.50 1.75 2.0 0 0.4 0.8 1.2 1.6 2.0
2.5 1000
ID = 0.5 A
2 TJ = 125°C
100 100°C
(NORMALIZED)
1.5
10
1
25°C
1
0.5
0 0.1
– 50 – 25 0 25 50 75 100 125 150 0 100 200 300 400 500 600 700 800


MTP1N80E
700 1000
TJ = 25°C TJ = 25°C
VGS = 0 V VGS = 0 Ciss
600
C, CAPACITANCE (pF)
500
C, CAPACITANCE (pF)
100
400
Ciss
Coss
300
10
200
Coss Crss
100
Crss
0 1
0 5 10 15 20 25 10 100 1000

MTP1N80E
12 400 100

VDD = 400 V
QT ID = 1 A
10
VGS = 10 V
VGS 300 TJ = 25°C tf
8
t, TIME (ns)
td(off)
6 200 10 td(on)
tr
Q1 Q2
4
ID = 1 A 100
2 TJ = 25°C
Q3 VDS
0 0 1
0 2 4 6 8 10 1 10 100

1.0
VGS = 0 V
TJ = 25°C
0.8
0.6
0.4
0.2
0
0.40 0.45 0.50 0.55 0.60 0.65 0.70 0.75 0.80 0.85
SAFE OPERATING AREA
temperature.

MTP1N80E
SAFE OPERATING AREA
10 20

VGS = 20 V
10 µs ID = 1 A
SINGLE PULSE
TC = 25°C

15
1
100 µs
1 ms 10
10 ms
0.1
dc
5
RDS(on) LIMIT
THERMAL LIMIT
PACKAGE LIMIT
0.01 0
0.1 1 10 100 1000 25 50 75 100 125 150
D = 0.5
0.2
(NORMALIZED)
0.1
0.1 0.05 P(pk)
PULSE TRAIN SHOWN
0.01
0.00001 0.0001 0.001 0.01 0.1 1 10
t, TIME (SECONDS)
di/dt
IS
trr
ta tb
TIME
tp 0.25 IS
IS

MOTOROLA
 Data Sheet
Designer's
MTP1N100E

TMOS POWER FET
G
TO–220AB
S
REV 2

MTP1N100E
OFF CHARACTERISTICS
(VDS = 1000 Vdc, VGS = 0 Vdc) — — 10
(ID = 1.0 Adc) — 4.86 9.0
(ID = 0.5 Adc, TJ = 125°C) — — 9.9
Vd VGS = 0 Vdc,
Vd
Coss — 59.6 120
f = 1.0 MHz)

VGS = 10 Vdc
Vdc,
(S Fi
(See Figure 8)
((VDS = 400 Vdc, ID = 1.0 Adc, Q1 — 2.8 —
VGS = 10 Vdc) Q2 — 6.8 —
Q3 — 5.2 —
— 0.764 1.0
(IS = 1.0 Adc, VGS = 0 Vdc, TJ = 125°C)
— 0.62 —
(S Figure
(See Fi 14)
((IS = 1.0 Adc, VGS = 0 Vdc, ta — 42 —
dIS/dt = 100 A/µs) tb — 613 —

MTP1N100E
2.0 2.0
1.8 TJ = 25°C 1.8 VDS ≥ 10 V
VGS = 10 V
100°C

1.6 6V 1.6
1.4 1.4
5V
1.2 1.2
1.0 1.0
25°C
0.8 0.8
0.6 0.6
0.4 0.4
TJ = –55°C
0.2 4V 0.2
0 0
0 2 4 6 8 10 12 14 16 18 20 2.0 2.4 2.8 3.2 3.6 4.0 4.4 4.8 5.2 5.6


16 8.0
VGS = 10 V TJ = 25°C
14 7.8
TJ = 100°C 7.6
12
7.4
10 7.2
8 25°C 7.0
VGS = 10 V
6 6.8
6.6
4 15 V
6.4
– 55°C
2 6.2
0 6.0
0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
2.8 10000
VGS = 10 V TJ = 125°C
2.4 ID = 0.5 A 1000
100°C
2.0
100
(NORMALIZED)
1.6
10
1.2
1.0 25°C
0.8
0.4 0.1
VGS = 0 V
0 0.01
–50 –25 0 25 50 75 100 125 150 0 100 200 300 400 500 600 700 800 900 1000


MTP1N100E
1200 1000
VGS = 0 V Ciss
1000 TJ = 25°C
C, CAPACITANCE (pF)
C, CAPACITANCE (pF)
800 100
Ciss
Coss
600 Crss
400 10
Crss
Coss
200
Crss
0 1
10 5 0 5 10 15 20 25 10 100 1000

MTP1N100E
12 480 1000

QT VDD = 500 V
10 400 ID = 1 A
VGS = 10 V
TJ = 25°C
8 VGS 320 100
t, TIME (ns)
Q1 Q2 tf
6 240
td(off) tr
4 ID = 1 A 160 10 td(on)
TJ = 25°C
2 80
Q3 VDS
0 0 1
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 1 10 100

1.0
VGS = 0 V
TJ = 25°C
0.8
0.6
0.4
0.2
0
0.50 0.54 0.58 0.62 0.66 0.70 0.74 0.78
SAFE OPERATING AREA
temperature.

MTP1N100E
SAFE OPERATING AREA
10 50
VGS = 20 V ID = 1 A

SINGLE PULSE
TC = 25°C 40

1.0
10 µs 30
100 µs
1 ms 20
0.1 10 ms
RDS(on) LIMIT dc 10
THERMAL LIMIT
PACKAGE LIMIT
0.01 0
0.1 1.0 10 100 1000 25 50 75 100 125 150
1.0
D = 0.5
0.2
0.1
P(pk)
0.05
t1 READ TIME AT t1
0.01
SINGLE PULSE
0.01
1.0E–05 1.0E–04 1.0E–03 1.0E–02 1.0E–01 1.0E+00 1.0E+01
t, TIME (s)
di/dt
IS
trr
ta tb
TIME
tp 0.25 IS
IS

MOTOROLA
 Data Sheet
Designer's
MTP2N40E

TMOS POWER FET
Fast Recovery Diode D
G
TO–220AB
S



MTP2N40E
OFF CHARACTERISTICS
(VDS = 400 Vdc, VGS = 0 Vdc) — — 10
Static Drain–Source On–Resistance (VGS = 10 Vdc, ID = 1.0 Adc) RDS(on) — 3.1 3.5 Ohms
(ID = 2.0 Adc) — 7.3 8.4
(ID = 1.0 Adc, TJ = 125°C) — — 7.4
Vd VGS = 0 Vdc,
Vd
Coss — 34 40
f = 1.0 MHz)

VGS = 10 Vdc
Vdc,
((VDS = 320 Vdc, ID = 2.0 Adc, Q1 — 2.6 —

VGS = 10 Vdc) Q2 — 3.2 —
Q3 — 5.0 —
— 0.88 1.2
(IS = 2.0 Adc, VGS = 0 Vdc, TJ = 125°C)
— 0.76 —
((IS = 2.0 Adc, VGS = 0 Vdc, ta — 99 —

dIS/dt = 100 A/µs) tb — 57 —

MTP2N40E
4 4
TJ = 25°C VDS ≥ 10 V
VGS = 10 V

3.2 8V
3
7V
2.4
2
1.6 6V
1
0.8 25°C
100°C
5V
TJ = – 55°C
0 0
0 4 8 12 16 20 2 3 4 5 6 7 8

8 5
VGS = 10 V TJ = 25°C
TJ = 100°C 4.5
6
4
4 25°C VGS = 10 V
3.5
15 V
2 – 55°C
3
0 2.5
0 1 2 3 4 0 0.5 1 1.5 2 2.5 3 3.5 4
2.5 1000
VGS = 0 V
VGS = 10 V
2 ID = 1 A
TJ = 125°C
(NORMALIZED)
1.5
100
1
0.5
0 10
– 50 – 25 0 25 50 75 100 125 150 0 100 200 300 400


MTP2N40E
tion of drain current, the mathematical solution is complex.
t = Q/IG(AV) The MOSFET output capacitance also complicates the
During the rise and fall time interval when switching a resis- mathematics. And finally, MOSFETs have finite internal gate
tive load, VGS remains virtually constant at a level known as resistance which effectively adds to the resistance of the
the plateau voltage, VSGP. Therefore, rise and fall times may driving source, but the internal resistance is difficult to mea-
be approximated by the following: sure and, consequently, is not specified.
tance (Figure 9. ) shows how typical switching performance
tf = Q2 x RG/VGSP is affected by the parasitic circuit elements. If the parasitics
switching losses.
500 1000
TJ = 25°C
Ciss
400
Ciss
C, CAPACITANCE (pF)
C, CAPACITANCE (pF)
100
300
Ciss
Coss
200 Crss
10
Crss
100 Coss
Crss
0 1
–10 –5 0 5 10 15 20 25 10 100 1000

Figure 7. b. High Voltage Capacitance
Figure 7. a. Capacitance Variation Variation

MTP2N40E
12 400 100

VDD = 200 V
QT ID = 2 A
10
VGS = 10 V
300
TJ = 25°C
8
VGS
t, TIME (ns)
td(off)
6 200 10 tf
Q1 Q2
ID = 2 A tr td(on)
4 TJ = 25°C
100
2
VDS
0 Q3 1
0
0 2 4 6 8 1 10 100


2
VGS = 0 V
TJ = 25°C
1.5
0.5
0
0.5 0.6 0.7 0.8 0.9
SAFE OPERATING AREA
drain current that a transistor can handle safely when it is for-

Power MOSFET Transistor Data PDF

Uploaded by

Document Information

Original Title

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

Power MOSFET Transistor Data PDF

Uploaded by

Copyright:

Available Formats

TMOS Power MOSFET Transistor Device Data

Alphanumeric Index of Part Numbers 1

Introduction to Power MOSFETs

Surface Mount Package Information and

Package Outline Dimensions and Footprints 6

Distributors and Sales Offices 7

 Motorola, Inc. 1996

Three Ways To Receive

Mfax - Touch–Tone Fax

How to reach us:

Alphanumeric Index of Part Numbers . . . . . . . . . . . . . . . 1–2

Motorola Data Sheet Motorola Data Sheet Motorola Data Sheet

MC33153 4–2 MTB1N100E 4–317 MTDF1N02HD 4–620

Motorola Data Sheet Motorola Data Sheet Motorola Data Sheet

MTP3055VL 4–926 MTV32N25E 4–995 MTW32N25E 4–1055

Obsolete Part Numbers Cross Reference

BUZ11 MTP36N06V IRFZ20 MTP15N06V MTP8N06E MTP15N06V

In Brief . . . Table of Contents

Motorola TMOS Power MOSFET Transistors Device Data Selector Guide

TMOS Power MOSFETs Numbering System

SO–8 (MiniMOS), Micro8 and SOT–223 Power MOSFETs

Selector Guide Motorola TMOS Power MOSFET Transistor Device Data

Micro8 HDTMOS Products

Table 3. N – Channel and P– Channel

Devices listed in bold, italic are Motorola preferred devices.

Motorola TMOS Power MOSFET Transistors Device Data Selector Guide

0.13 0.85 MMFT3055V 1.7

Table 6. SOT–223 — P–Channel

Table 7. DPAK — N–Channel

Devices listed in bold, italic are Motorola preferred devices.

Selector Guide Motorola TMOS Power MOSFET Transistor Device Data

Table 7. DPAK — N–Channel (continued)

Table 9. D2PAK — N–Channel

Devices listed in bold, italic are Motorola preferred devices.

Motorola TMOS Power MOSFET Transistors Device Data Selector Guide

Table 9. D2PAK — N–Channel (continued)

Devices listed in bold, italic are Motorola preferred devices.

Selector Guide Motorola TMOS Power MOSFET Transistor Device Data

Devices listed in bold, italic are Motorola preferred devices.

Motorola TMOS Power MOSFET Transistors Device Data Selector Guide

Table 13. TO–220AB — P–Channel

TO–247 (Isolated Mounting Hole)

Table 14. TO–247 — N–Channel

Devices listed in bold, italic are Motorola preferred devices.

Selector Guide Motorola TMOS Power MOSFET Transistor Device Data

Devices listed in bold, italic are Motorola preferred devices.

Motorola TMOS Power MOSFET Transistors Device Data Selector Guide

Power MOS Gate Drivers

Devices listed in bold, italic are Motorola preferred devices.

Selector Guide Motorola TMOS Power MOSFET Transistor Device Data

Symbol Term Definition

IS source current, dc The direct current into the source terminal.

Input Voltage Pulse

Figure 1–1. Waveforms for Resistive–Load Switching

Figure 1–2. Waveforms for Inductive Load Switching, Turn–Off

Motorola’s TMOS Power MOSFET family is a matrix of dif- CURRENT

(1) ID [ ZL mCo [VGS–VGS(th)] VDS (4) RDS(on) + rCH ) rACC ) rJFET ) rD

N+ Breakdown Voltage, V(BR)DSS:

Distinct Advantages of Power MOSFETs

Figure 1–10. TMOS Output Stage

Figure 1–11. Bipolar Driver and Output Stage

Figures 1–10 and 1–11. Circuit Configurations for a TMOS and

VCC 1N4933 +10 µF