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Supervisor
Voltage stability
interconnections.
OPPORTUNITIES
Prevent blackouts.
V L in e
0 .8 0 1 .0 0
Id & Iq o f th e S T A T C O M
P & Q o f th e S T A T C O M
0 .8 0
P
VL
0 .4 0 0 .0 0
0 .4 0 Q
0 .0 0 P - 1 .0 0
0 .0 0 - 0 .4 0 - 2 .0 0
0 .0 0 0 .4 0 0 .8 0 1 .2 0 1 .6 0 2 .0 0 0 .0 0 0 .4 0 0 .8 0 1 .2 0 1 .6 0 2 .0 0 0 .0 0 0 .4 0 0 .8 0 1 .2 0 1 .6 0 2 .0 0
T im e (S e c ) T im e (S e c ) T im e (S e c )
P
Id 2 .0 0
2 .0 0 0 .8 0
I d & I q o f th e T r a n s m is s io n L in e
P & Q o f th e T r a n s m is s io n L in e
1 .0 0
V dc
0 .0 0 0 .4 0
Iq
0 .0 0
V dc
Q
- 2 .0 0 0 .0 0
- 1 .0 0
- 4 .0 0 - 2 .0 0 - 0 .4 0
0 .0 0 0 .4 0 0 .8 0 1 .2 0 1 .6 0 2 .0 0 0 .0 0 0 .4 0 0 .8 0 1 .2 0 1 .6 0 2 .0 0 0 .0 0 0 .4 0 0 .8 0 1 .2 0 1 .6 0 2 .0 0
T im e (S e c ) T im e (S e c ) T im e (S e c )
System is subjected to load switching at t=0.5 sec (inductive load added), t=1 sec (capacitive load added)
and t=1.5 (Both inductive and capacitive load removed)
STATIC SYNCHRONOUS SERIES COMPENSATOR
It is increase or decrease the overall reactive voltage drop across the line
and thereby controlling the transmitted electric power.
Fig. 3 Single line diagram representing the series SSSC scheme interfaced
at sending end of the Transmission line (Bus B1)
Novel Controller
Alpha vs time Iqref,Iqm vs time Id, Iq of STATCOM vs time P & Q of STATCOM vs time
P, Q of SSSC vs time Vdc vs time Line Voltage vs time Line voltage and current vs time
Damping Reactive
Controller Voltage Transient Power Power Power Flow SSR
Control stability Oscillations Compensation Control Mitigation
STATCOM X x x x
SSSC X x x x x x
UPFC X x x x x X
POWER QUALITY ENHANCEMENT
This chapter studies the power system power quality and harmonics and
SSR/ Tortional stability enhancement to reduce harmonics, improve the
power quality and enhance the system harmonic stability.
Three different cases were studied in order to improve power quality and
enhance system stability using a novel Active Power Filter (APF)
combining with and Tuned arm filter switched capacitive compensation.
A COMBINED CAPACITIVE COMPENSATION AND
ACTIVE POWER FILTER
2 2 2
Re = e v +e i +e I Fig. 12.a. Sample study of the unified power system
Voltageof phasec Ph
aseVo
ltageVc
Vc
VLc +
1.2
5
+
1.25 +
0.7
5
+
0.2
5
-0
.25
-0
.75
-1.251.04 1.13 1.22 1.31 1.4 1.49 -1
.251
.03 1
.12
8 1
.22
6 1
.32
4 1
.42
2 1
.52
Time(sec) Tim
e(sec)
Fig. 13. The simulation results when the system subjected to 3- phase fault disturbance
A COORDINATED CAPACITIVE COMPENSATION AND
TUNED ARM FILTER
Fig 13. Proposed novel tri loop error-driven, error -scaled Tri-loop
dynamic feed back controller.
Developed By Dr. Sharaf
Simulation Results For SSCC/TAF Scheme
Fig 14. the p.u. load voltage at bus 4, terminal voltage at bus 2, total load current iL and the induction load current
when the system subjected to 3 phase fault at bus 2
Fig 15. The Power Transfer levels P& Q without and with SSCC&TAF
Fig 16. Comparison of the load voltage, load current and %THD voltage and
current without and with (SSCC & TAF)
Renewable Energy
The research will investigate the use of renewable dispersed energy system
(wind-small hydro, hybrid scheme) and resulting grid interface problems
and need for effective mitigative FACTS-based solution. Both stand-alone
and grid connect wind energy conversion will be studied
CONCLUSION
The research investigates FACTS topologies & novel control strategies for
voltage stability enhancement, T.L power flow control and harmonic/ SSR
mode stabilization of an interconnected AC system.