8086/88 Hardware and Bus Structure

• We will focus now on the 8086/88 Hard-

ware and pin functions – later we will re-
view characteristics of other Intel µP and
the Motorola family.

• Basic signals of a µP and bus are as follows:

µP Interface A0
A1
.
CLOCK . addr
RESET Buffers .
Latches A18
Decoders A19
Logic
D0
INTERRUPT addr D1
data .
READY/WAIT
ctrl . data
.
D14
D15
BUS MRDC
STATUS MWTC ctrl
IORD
IOWT

1
 • Both the 8086 and the 8088 are 40-pin
Dual In-line Package (DIP) chips.

• 8086 – 16-bit µP and a 16-bit data bus

• 8088 – 16-bit µP and a 8-bit data bus

• 8086 has M/IO, 8088 has IO/M

• Pin 34 is also different: 8086 BHE/S, 8088

has SSO

See page 307, Fig 9-1. Note that on 8088,

IO/M should be IO/M

2
General Characteristics

Power:
8086 +5V ± 10%, 360mA (80C86 10mA)
8088 +5V ± 10%, 340mA (80C86 10mA)

Temp:

32◦F - 180◦F (not suitable for outdoors)

CMOS version -40◦F - 255◦F (MIL spec)

Clock Frequency:

normally 5MHz. SDK86, 2.5MHz or 5MHz.

3
DC characteristics

• Must understand V-A characteristics of I/O

pins in order to connect to the outside
world.

Input characteristics

• compatible with stander logic-level compo-

nents
logic 0 0.8V max, ±10µA max
logic 1 2.0V min, ±10µA max

• The input current is very small – gates of

MOSFETs, so current represents leakage.

4
Output characteristics

• logic 1 voltage level is compatible with most

logic families, but logic 0 is not.
logic 0 0.45V max, 2.0mA max
logic 1 2.0V min, 400 µA max
(Most logic families have logic 0 max 0.4V)

• No more than 10 loads per output without

buffering.

• If more than 10 loads are attached to any

bus pin, then the entire 8086/8088 must
be buffered.

5
Pin Connections (8086)

AD15 − AD0

• Multiplexed address/data bus.

• lines carry address bits A15 − A0 whenever

ALE (Address Latch Enable) is logic 1.

• lines carry address bits D15 − D0 whenever

ALE is logic 0.

• Note: 8088 only multiplexes D7 − D0 be-

cause it uses an 8-bit data bus.

6
A19 /S6 − A16S3

• multiplexed address/status bits.

• lines carry address bits A19 − A16 whenever

ALE is logic 1.

• lines carry status bits S6 −S3 whenever ALE

is logic 0.

7
S6 always logic zero (not used).

S5 matches state of I flag bit (interrupt)

S4, S3 Segment being accessed during current

bus cycle.
S4 S3 Function
0 0 Extra Segment (ES)
0 1 Stack Segment (SS)
1 0 Code Segment (CS)
1 1 Data Segment (DS)

Note: These status lines could be de-

coded/latched to address four sep-
arate 1M banks of memory. (Split
I/D)

8
RD Data bus reception when low.

WR µP is outputting data.

M/IO (8086) indicates a memory address (‘1’),

or an I/O address (‘0’).

DT/T Data transmit/receive. Data bus is trans-

mitting (‘1’), or receiving (‘0’) (for control-
ling bi-directional bus drivers).

9
DEN Data bus enable – used to activate ex-
ternal buffers/transceivers.

BHE/S7 Bus high enable

• used to enable D15 − D8 in an 8086 dur-

ing a 16-bit read/write.

• Multiplexed with S7, which is not used

(always 1).

• latched with ALE.

10
Both the 8086 and the 8088 have two modes
of operation:

1. Minimum Mode: connect MN/MX to +5V

(directly).

• similar to 8085 operation.

• all control signals for memory and I/O

are generated by the µP. (RD, M/IO,
D/R, DEN, ALE, INTA)

2. Maximum Mode: connect MN/MX to ground

(directly).

• dropped by Intel beginning with the 80286.

• must use with co-processor (8087) present.

• some control signals must be generated

externally.

• use with 8288 bus controller.

11
The 8288 Bus Controller

8086 8288
S0 S0 MRDC
S1 S1 MWTC
S2 S2 IORD
DT/R IOWT
DEN INTA
ALE

8282
STB
OE
addr/data
addr

8286
T

OE data

See §9.2, pp311-313

12
The following signals are typically generated
with an 8284A Clock Generator. See §9.5, pp
324-325.

Clock Clock.

Reset Reset.

Ready Wait states for slow memory.

13
8284A Clock Generator

• Used with 8086/88 to generate the clock,

reset and ready signals.

• General use for clock and reset is shown on

next slide.

F/C Frequency/crystal select.

1 external clock
0 crystal (X1-X2 provides timing).

CSYNC Only used with external clock, oth-

erwise grounded.

• Clock controller is also used for wait states

(covered later).

• 10K pullup? 0.5mA sink. (debouncing!)

14
 8284 8086
5MHz
X1 CLK CLK
15MHz ÷3
X2
Vcc F/C

10k CSYNC
RESET RESET
RES
10µF

To reset
other devices

15
 Decoding Bus Control Signal

• In “max mode” use 8288 bus controller to

generate MRDC, MWTC, IORC, IOWC.

• In “min mode” (and for other processors)

it is sometimes better to decode the avail-
able signals.

M/IO
MRDC

RD
MWTC

=
WR
IORC

IOWC

16
Bus Timing

• 8086 and 8088 bus cycles consume four

system clock periods (T-states), T1, T2,
T3 and T4.

• At 5MHz, each T-state is 200nS, therefore

a bus cycle is 800nS.

• Semi-synchronous bus control allows insert-

ing of wait states (Tw), also 200nS, be-
tween T3 and T4 which allows access to
slow memory and I/O devices

Text says Tw inserted between T2 and

T3, but the Intel manual says between
T3 and T4).

17
Bus Cycles

• Most processors are very similar in I/O and

memory access operations.

18
 WRITE Cycle
ONE BUS CYCLE
T1 T2 T3 T4

CLK

ADDRESS
/DATA

ALE

WR

19
 READ Cycle
ONE BUS CYCLE
T1 T2 T3 T4

CLK

ADDRESS
/DATA

ALE

RD

20
1. T1: Address, ALE, DT/R, IO/M.

2. T2: RD, WR, DEN, data on the bus (for

write).

3. At the end of T2 (middle of T3), µP sam-

ples the READY input.

(a) while READY = 0; do

(b) insert Tw.

4. For read cycles, data bus is sampled at the

end of T3.

5. All bus signals are deactivated.

Normal memory access time is 400nS.

Slower devices will need at lest on wait
state which will give 660nS.

21
Wait states with the 8284A
CS from memory devices
X1 RDY 1
15MHz ÷3
Vcc X2

10k 8284A QAQBQCQDQE QF QGQH

RES CLK 74LS164

10µF RESET
CLR SI
READY

Vcc

READY

RESET
CLK
RD
WR
INTA

8086

22
 • 74LS164 is a 8-bit serial shift register.

• Jumper shown generates 1 wait state.

Bus Latching and Buffering

• Latches are used to demultiplex the ad-

dress/data and address/status lines and com-
monly have output buffers for driving ex-
ternals leads.

• Buffers are used to drive external loads,

and to isolate component when disabled.

23
Three-state Buffer (Tri-state buffer)

In Out

Control

• When enabled by the control line, output

follows input.

• When disabled, output is a very high impedance

which prevents the output from driving or
loading connected circuits.

• When disabled, the outputs are said to be

floating.

• In effect, it is like a switch.

24
Bidirectional buffers (transceivers)

B A

Direction
Enable

DIR Action
0 B→A
1 A→B
EX: 74LS245 octal bus transceiver.

25
Latches (D-type flip-flops)

D Q

• When enable is high, Q follows D.

• When enable goes low, Q maintains (latches)

state of D.

• Eg: 74LS373 (latched on falling edge).

• 74LS374 (latched on rising edge)

26
A Fully Buffered 8086
M/IO In OUT M/IO

RD ’244 RD
WR WR
OE

BHE/S7 In OUT BHE

A19 /S6 -A16 /S3 D ’373 Q A19 -A16
4 4
G OE

8 In OUT
8
AD15 -AD8 D ’373 Q A15 -A8

G OE

8 In OUT
8
AD7 -AD0 D ’373 Q A7 -A0

G OE

ALE

In OUT
8
D ’245 Q D15-D8
8086 G DIR
In OUT 8
D ’245 Q D7 -D0

G DIR

DEN
DT/R

27