VERY LARGE SCALE INTEGRATION[VLSI]

Topic:

VERILOG HDL

B.TECH (ECE)
by

E.Hari Krishna(08BEC113)

SUBMITTED TO : Mr.RAJEEV PANKAJ NEELAPATI

SCHOOL OF ELECTRONICS ENGINEERING

(SENSE)

VIT
UNIVERSITY
(Estd. U/s 3 of UGC Act 1956)

Vellore – 632014, Tamil Nadu, India

www. vit.ac.in

NOVEMBER , 2010
 8 X 3 ENCODER

TRUTH TABLE:

Ip[0 Ip[1 Ip[2 Ip[3 Ip[4 Ip[5 Ip[6 Ip[7 Op[0 Op[1 Op[2]
] ] ] ] ] ] ] ] ] ]
0 0 0 0 0 0 0 1 0 0 0
0 0 0 0 0 0 1 0 0 0 1
0 0 0 0 0 1 0 0 0 1 0
0 0 0 0 1 0 0 0 0 1 1
0 0 0 1 0 0 0 0 1 0 0
0 0 1 0 0 0 0 0 1 0 1
0 1 0 0 0 0 0 0 1 1 0
1 0 0 0 0 0 0 0 1 1 1

VERILOG HDL CODE:

module enco(ip,op);

input [7:0] ip;

output[2:0] op;

reg [2:0] op;

always@(ip)

begin

case(ip)

8'b00000001: op=3'b000;

8'b00000010: op=3'b001;

8'b00000100: op=3'b010;

8'b00001000: op=3'b011;

8'b00010000: op=3'b100;

8'b00100000: op=3'b101;

8'b01000000: op=3'b110;

8'b10000000: op=3'b111;

endcase

end

endmodule
TESTBENCH CODE:

module jhvb_v;
// Inputs
reg [7:0] ip;
// Outputs
wire [2:0] op;
// Instantiate the Unit Under Test (UUT)
enco uut (.ip(ip), .op(op));
initial begin
// Initialize Inputs
ip=8'b10000000;
#10 ip=8'b01000000;
#20 ip=8'b00100000;
#30 ip=8'b00010000;
#80 ip=8'b00001000;
#50 ip=8'b00000100;
#90 ip=8'b00000010;
#30 ip=8'b00000001;
end
initial
$monitor ($time," enco_input = %b enco_output = %b",ip,op);
endmodule
OUTPUT:-
0 enco_input = 10000000 enco_output = 111
10 enco_input = 01000000 enco_output = 110
30 enco_input = 00100000 enco_output = 101
60 enco_input = 00010000 enco_output = 100
140 enco_input = 00001000 enco_output = 011
190 enco_input = 00000100 enco_output = 010
280 enco_input = 00000010 enco_output = 001
310 enco_input = 00000001 enco_output = 000

TIMING DIAGRAM/ SCREENSHOTS:

 4 X 2 PRIORITY ENCODER

TRUTH TABLE:
Ip[0] Ip[1] Ip[2] Ip[3] Op[0] Op[1]
1 X X X 0 0
0 1 X X 0 1
0 0 1 X 1 0
0 0 0 1 1 1

VERILOG HDL CODE:

module prior_enco(op,ip);

input [3:0]ip;

output reg [1:0]op;

always @(ip)

begin

casex (ip)

4'b1xxx :op=2'b00;

4'b01xx :op=2'b01;

4'b001x :op=2'b10;

4'b0001 :op=2'b11;

endcase

end

endmoduleTESTBENCH CODE:

module pri_test_v;

// Inputs

reg [3:0] ip;

// Outputs

wire [1:0] op;

// Instantiate the Unit Under Test (UUT)

prior_enco uut (.op(op), .ip(ip));

initial begin

// Initialize Inputs

// Wait 100 ns for global reset to finish

 ip=4'b0001;

#10 ip=4'b0110;

#10 ip=4'b0010;

#10 ip=4'b0101;

#10 ip=4'b0110;

#10 ip=4'b0111;

#10 ip=4'b1000;

#10 ip=4'b1001;

// Add stimulus here

end

initial

$monitor ($time," input=%b output = %b",ip,op);

endmodule

OUTPUT:

0 input=0001 output = 11

10 input=0110 output = 01

20 input=0010 output = 10

30 input=0101 output = 01

40 input=0110 output = 01

50 input=0111 output = 01

60 input=1000 output = 00

70 input=1001 output = 00

TIMING DIAGRAM:
 3 X 8 DECODER

TRUTH TABLE:
Ip[0] Ip[1] Ip[2] Op[0] Op[1] Op[2] Op[3] O[4] Op[5] Op[6] Op[7]

0 0 0 0 0 0 0 0 0 0 1
0 0 1 0 0 0 0 0 0 1 0
0 1 0 0 0 0 0 0 1 0 0
0 1 1 0 0 0 0 1 0 0 0
1 0 0 0 0 0 1 0 0 0 0
1 0 1 0 0 1 0 0 0 0 0
1 1 0 0 1 0 0 0 0 0 0
1 1 1 1 0 0 0 0 0 0 0

VERILOG HDL CODE:

module decoder(ip,op);
input [2:0]ip;
output [7:0]op;
reg [7:0]op;
always@(ip)
begin
case(ip)
3'b000:op=8'b00000001;
3'b001:op=8'b00000010;
3'b010:op=8'b00000100;
3'b011:op=8'b00001000;
3'b100:op=8'b00010000;
3'b101:op=8'b00100000;
3'b110:op=8'b01000000;
3'b111:op=8'b10000000;
endcase
end
endmodule

TESTBENCH CODE:

module fcv_v;

// Inputs
reg [2:0] ip;
// Outputs
wire [7:0] op;
// Instantiate the Unit Under Test (UUT)
decoder uut (.ip(ip),
.op(op));

initial begin

ip=3'b000;
#10 ip=3'b001;
#10 ip=3'b010;
#10 ip=3'b011;
#10 ip=3'b100;
#10 ip=3'b101;
#10 ip=3'b110;
#10 ip=3'b111;

end

initial

$monitor ($time," input = %b output = %b",ip,op);

Endmodule

OUTPUT:
0 input = 000 output = 10000000
10 input = 001 output = 01000000
20 input = 010 output = 00100000
30 input = 011 output = 00010000
40 input = 100 output = 00001000
50 input = 101 output = 00000100
60 input = 110 output = 00000010
70 input = 111 output = 00000001
TIMING DIAGRAM:
 4 BIT RIPPLE CARRY ADDER

CIRCUIT DIAGRAM:

VERILOG HDL CODE:

//define a 1-bit full adder

module fulladd(sum,c_out,a,b,c_in);
//i/0 port declaration
input a,b,c_in;
output sum,c_out;
//internal nets
wire s1,c1,c2;
//instantiate logic gate primitives
xor(s1,a,b);
and(c1,a,b);
xor(sum,s1,c_in);
and(c2,s1,c_in);
xor(c_out,c2,c1);
 endmodule
//define a 4-bit full adder
module fulladd4(sum,c_out,a,b,c_in);
//i/o port declarations
input [3:0]a,b;
input c_in;
output [3:0]sum;
output c_out;
//internal nets
wire c1,c2,c3;
//instantiate 4-bit full adder
fulladd fa0(sum[0],c1,a[0],b[0],c_in);
fulladd fa1(sum[1],c2,a[1],b[1],c1);
fulladd fa2(sum[2],c3,a[2],b[2],c2);
fulladd fa3(sum[3],c_out,a[3],b[3],c3);

endmodule

TESTBENCH CODE:

module nvbn_v;

// Inputs
reg [3:0] a;
reg [3:0] b;
reg c_in;

// Outputs
wire [3:0] sum;
wire c_out;

// Instantiate the Unit Under Test (UUT)

fulladd4 uut (
.sum(sum),
.c_out(c_out),
.a(a),
.b(b),
.c_in(c_in)
);

initial begin
 // Initialize Inputs
$monitor($time,"a=%b,b=%b,c_in=%b,c_out=%b,sum=%b
\n",a,b,c_in,--c_out,sum);
end

// Add stimulus here

initial begin
a=4'd0;b=4'd0;c_in=1'b0;
#10 a=4'd3;b=4'd4;
#10 a=4'd2;b=4'd5;
#10 a=4'd9;b=4'd9;
#10 a=4'd10;b=4'd15;
#10 a=4'd10;b=4'd5;c_in=1'b1;
end
endmodule

OUTPUT:

0 a=0000,b=0000,c_in=0,--c_out=0,sum=0000
10 a=0011,b=0100,c_in=0,--c_out=0,sum=0111
20 a=0010,b=0101,c_in=0,--c_out=0,sum=0111
30 a=1001,b=1001,c_in=0,--c_out=1,sum=0010
40 a=1010,b=1111,c_in=0,--c_out=1,sum=1001
50 a=0000,b=0101,c_in=1,--c_out=1,sum=0000

TIMING DIAGRAM:
 8 X 1 MULTIPLEXER

TRUTH TABLE:

s0 s1 s2 O
0 0 0 i0
0 0 1 i1
0 1 0 i2
0 1 1 i3
1 0 0 i4
1 0 1 i5
1 1 0 i6
1 1 1 i7

VERILOG HDL CODE:

module mux(o,i,s);

input [7:0]i;

input [2:0]s;

output reg o;

always @(i or s)

begin

case (s)

3'b000 : o=i[0];

3'b001 : o=i[1];

3'b010 : o=i[2];

3'b011 : o=i[3];

3'b100 : o=i[4];

3'b101 : o=i[5];
3'b110 : o=i[6];

3'b111 : o=i[7];

endcase

end

endmodule

TESTBENCH CODE:
module mutb_v;

// Inputs

reg [7:0] in;

reg [2:0] sel;

// Outputs

wire out;

// Instantiate the Unit Under Test (UUT)

muxx uut (.out(out),

.in(in),

.sel(sel) );

initial begin

// Initialize Inputs

i=8'b10110010;

s=3'b000;

#10 s=3'b001;

#40 s=3'b010;

#10 s=3'b011;

#30 s=3'b100;

#80 s=3'b101;

#10 s=3'b110;

#20 s=3'b111;

end

initial

$monitor ($time,"input = %b s = %b output = %b",in,s,o)

 Endmodule

OUTPUT:

0 input = 10110010 s = 000 output = 0

10 input = 10110010 s = 001 output = 1

50 input = 10110010 s = 010 output = 0

60 input = 10110010 s = 011 output = 0

90 input = 10110010 s = 100 output = 1

170 input = 10110010 s = 101 output = 1

180 input = 10110010 s = 110 output = 0

200 input = 10110010 s = 111 output = 1

TIMING DIAGRAM:
 1 X 8 DE-MULTIPLEXER

TRUTH TABLE:

s0 s1 s2 I0 I1 I2 I3 I4 I5 I6 I7
0 0 0 I 0 0 0 0 0 0 0
0 0 1 0 I 0 0 0 0 0 0
0 1 0 0 0 I 0 0 0 0 0
0 1 1 0 0 0 I 0 0 0 0
1 0 0 0 0 0 0 I 0 0 0
1 0 1 0 0 0 0 0 I 0 0
1 1 0 0 0 0 0 0 0 I 0
1 1 1 0 0 0 0 0 0 0 I

VERILOG CODE:
module demux(out,in,sel);
input in;
input [2:0]sel;
output reg [7:0]out;
always @(in or out)
begin
out=8'b0;
case (sel)
3'b000 : out[0]=in;
3'b001 : out[1]=in;
3'b010 : out[2]=in;
3'b011 : out[3]=in;
3'b100 : out[4]=in;
3'b101 : out[5]=in;
3'b110 : out[6]=in;
3'b111 : out[7]=in;
endcase
end
endmodule

TESTBENCH CODE:
module demux_v;

// Inputs

reg in;

reg [2:0] sel;

// Outputs

wire [7:0] out;

// Instantiate the Unit Under Test (UUT)

demux uut (

.out(out),

.ip(ip),

.sel(sel) );

initial begin

// Initialize Inputs

in=1'b1;

sel=3'b000;

#10 sel=3'b001;

#20 sel=3'b010;

#30 sel=3'b011;

#40 sel=3'b100;

#50 sel=3'b101;

#60 sel=3'b110;

#70 sel=3'b111;

end
initial

$monitor ($time," input = %b sel = %b output = %b",in,sel,out);

endmodule

OUTPUT:
0 input = 1 sel = 000 output = 00000001

10 input = 1 sel = 001 output = 00000010

30 input = 1 sel = 010 output = 00000100

60 input = 1 sel = 011 output = 00001000

100 input = 1 sel = 100 output = 00010000

150 input = 1 sel = 101 output = 00100000

210 input = 1 sel = 110 output = 01000000

280 input = 1 sel = 111 output = 10000000

TIMING DIAGRAM:
 D FLIP FLOP (POSITIVE EDGE)

TRUTH TABLE:

D Q Output
0 0 Low
1 1 High

VERILOG HDL CODE:

module d_ff(q,d,clk,reset);
output reg q;
input d,clk,reset;
always @(posedge reset or posedge clk)
if(reset)
q<=1'b0;
else
q<=d;
endmodule

TESTBENCH CODE:

module d_ff_t_v;

// Inputs
reg d;
reg clk;
reg reset;

// Outputs
 wire q;

// Instantiate the Unit Under Test (UUT)

dff uut (
.q(q),
.d(d),
.clk(clk),
.reset(reset)
);

initial begin
// Initialize Inputs
d = 0;
clk = 0;
reset = 0;
// Add stimulus here

#10 reset = 1;
#10 reset =0;
#10 d = 1;
#10 d = 0;
#10 d = 0;
#10 d = 1;
#10 d = 1;

end
always
#10 clk = ~clk;
endmodule

TIMING DIAGRAM:
 SHIFT REGISTER (SISO)

CIRCUIT DIAGRAM:

TRUTH TABLE:

CLK i0 i1 i2 i3
1 1 1 1 0
2 0 1 1 1
3 0 0 1 1
4 0 0 0 1

VERILOG HDL CODE:

module siso(q,clk,i);
output reg [3:0] q;
input clk,i;
always @(posedge clk)
begin
q[0] <=i;
q[1] <=q[0];
q[2] <=q[1];
q[3] <=q[2];
end
endmodule

TESTBENCH CODE:
module siso_t_v;

// Inputs
reg clk;
reg i;

// Outputs
wire [3:0] q;

// Instantiate the Unit Under Test (UUT)

siso uut (
.q(q),
.clk(clk),
.i(i)
);

initial begin
// Initialize Inputs
clk = 0;
i = 0;
// Add stimulus here
#20 in = 1;
#20 in = 1;
#20 in = 1;
#20 in = 0
end
always
#10 clk = ~clk;
endmodule
TIMING DIAGRAM:

MODULO-10 COUNTER
TRUTH TABLE:

a0 b0 c0 d0 a1 b1 c1 d1
0 0 0 0 0 0 0 1
0 0 0 1 0 0 1 0
0 0 1 0 0 0 1 1
0 0 1 1 0 1 0 0
0 1 0 0 0 1 0 1
0 1 0 1 0 1 1 0
0 1 1 0 0 1 1 1
0 1 1 1 1 0 0 0
1 0 0 0 1 0 0 1
1 0 0 1 0 0 0 0

STATE DIAGRAM:
VERILOG CODE:

module mod_ten (q,clk,reset);

output [3:0] q;
input clk,reset;
reg [3:0] q;
always @(posedge clk)
begin
if(reset)
q=0;
else
if(q==9)
q = 0;
else
q = q+1;
end
endmodule
TESTBENCH CODE:
module mod_ten_t_v;
// Inputs
reg clk;
reg reset;
// Outputs
wire [3:0] q;
// Instantiate the Unit Under Test (UUT)
counter uut (
.q(q),
.clk(clk),
 .reset(reset)
);
initial begin
// Initialize Inputs
clk = 0;
reset = 0;
// Add stimulus here
#10 reset = 1;
#10 reset = 0;
end
always
#10 clk = ~clk;
Endmodule

TIMING DIAGRAM: