ASSIGNMENT

DLD_LAB
SUBMITTED TO: SIR FAIQ

SUBMITTED BY: Asfand yar zahid

ROLL # : 6656

National University of
Modern Languages

Verilog Full Adder

Truth Table

A B Cin Cout Sum

0 0 0 0 0

0 0 1 0 1

0 1 0 0 1

0 1 1 1 0

1 0 0 0 1

1 0 1 1 0

1 1 0 1 0

1 1 1 1 1

Example

An example of a 4-bit adder is shown below, which accepts two binary numbers through
the signals a and b.
 An adder is a combinational circuit. Therefore Verilog can model it using a continuous
assignment with assign or an always block with a sensitivity list that comprises all
inputs.

1. module fulladder (  input [3:0] a,  
2.                   input [3:0] b,  
3.                   input c_in,  
4.                   output c_out,  
5.                   output [3:0] sum);  
6.   
7.    assign {c_out, sum} = a + b + c_in;  
8. endmodule  

Below code shows the uses an always block which gets executed whenever any of its
inputs change value.

1. module fulladder (  input [3:0] a,  
2.                   input [3:0] b,  
3.                   input c_in,  
4.                   output reg c_out,  
5.                   output reg [3:0] sum);  
6.   
7.     always @ (a or b or c_in) begin  
8.     {c_out, sum} = a + b + c_in;  
9.   end  
10. endmodule  

Hardware Schematic
1. module tb_fulladd;  
2.     // 1. Declare testbench variables  
3.    reg [3:0] a;  
4.    reg [3:0] b;  
5.    reg c_in;  
6.    wire [3:0] sum;  
7.    integer i;  
8.   
9.     // 2. Instantiate the design and connect to testbench variables  
10.    fulladd  fa0 ( .a (a),  
11.                   .b (b),  
12.                   .c_in (c_in),  
13.                   .c_out (c_out),  
14.                   .sum (sum));  
15.   
16.     // 3. Provide stimulus to test the design  
17.    initial begin  
18.       a <= 0;  
19.       b <= 0;  
20.       c_in <= 0;  
21.   
22.       $monitor ("a=0x%0h b=0x%0h c_in=0x%0h c_out=0x%0h sum=0x%0h", a, b, 
c_in, c_out, sum);  
23.   
24.         // Use a for loop to apply random values to the input  
25.       for (i = 0; i < 5; i = i+1) begin  
26.          #10 a <= $random;  
27.              b <= $random;  
28.                  c_in <= $random;  
29.       end  
30.    end  
31. endmodule