EXPERIMENT NO.

AIM:- Write VHDL code to design the 2:1,4:1,8:1 multiplexer

Requirements:-Xilinx window

PROCEDURE:-

A) VHDL code for 2:1 mux:-

Library ieee;
Use ieee.std_logic_1164.all;
Entity mux2_1 is port (a,b,sel:in std_logic;y:out std_logic);
End mux2_1;
Artitechture beh of mux2_1 is begin
process(a,b,sel)begin
case cell is
when '0'=>y<=a;
when '1'=>y<=b;
when others=>null;
end case;
end process;
end beh;
B) VHDL code for 4:1 mux:-

Library ieee;
Use ieee.std_logic_1164.all;
Entity mux4_1 is port (a,b,c,d:in std_logic;shell:in
std_logic_vector(1down to 0);y:out std_logic);
End mux4_1;
Artitechture beh of mux4_1 is begin
process(a,b,c,d,sel)begin
case cell is
when '00'=>y<=a;
when '01'=>y<=b;
when '10'=>y<=c;
when others=>y<=d;
end case;
end process;
end beh;
C) VHDL code for 8:1 mux:-
Library ieee;
Use ieee.std_logic_1164.all;
Entity mux8_1 is port (a,b,c,d,e,f,g,h:in std_logic;shell:in
std_logic_vector(2down to 0);y:out std_logic);
End mux8_1;
Artitechture beh of mux8_1 is begin
process(a,b,c,d,e,f,g,h,sel)begin
case cell is
when '000'=>y<=a;
when '001'=>y<=b;
when '010'=>y<=c;
when '011'=>y<=d;
when '100'=>y<=e;
when '101'=>y<=f;
when '110'=>y<=g;
when others=>y<=h;
end case;
end process;
end beh;