Name

EE 541

FINAL REPORT Spring 2012 (Take home, due May 2, 2012 by 5:00 PM, Room 214 or 209 EE West)

Answer each question on a separate page, single-sided. Your answer cannot exceed one typed page (including figures). Type single-space, font 12, Times New Roman, margins 1 inch top, bottom, left, right. Each problem is worth 4 pts. Base your answers on the course notes and any supplemental source of information available. Make sure you identify source of the information you use (consecutive numbers in square brackets) including complete www addresses if using web based sources. List references on the 9th, and 10th if needed, (counting cover page). This is an individual assignment.

1. We have covered in our discussion several enhancement techniques which keep 193 nm 2. 3. 4. 5. 6. 7.
photolithography work. One not covered is concerned with multiple pattering technology. Explain this method in details. In our discussion we were focused on pattern definition using top-down process. Described principles of the process producing the same pattern using bottom up process. Explain principles of two the most common end-point detection methods conventionally used in etch tools. Consider metals used as gate contacts in conjunction with high-k gate dielectrics. Discuss selection criteria and deposition method(s) used. Consider CMP process using Cu as a material to be removed (e.g. damescene process). Discuss what and how CMP process parameters are used to control Cu removal rate. Explain the purpose and discuss techniques used in advanced IC manufacturing to deposit tungsten. Halo implantation is an important element of the advanced CMOC processes. Explain its purpose and how it is being implemented.