Notation Meaning reg integer register (%r0{%r31) subscript denotes instruction eld (e.g.

, reg rd ) const unsigned integer value subscript denotes size in bits (e.g., const 22) disp signed integer displacement subscript denotes size in bits (e.g., disp 22) siconst 2's complement signed integer value subscript denotes size in bits (e.g., siconst 30) address reg rs1 reg rs1 + reg rs2 reg rs1 + siconst 13 reg rs1 ; siconst 13 siconst 13 siconst 13 + reg rs1 regaddr reg rs1 reg rs1 + reg rs2 label an instruction label asi address space identi er (0 to 255) Name %r0{%r31 %g0{%g7 %o0{%o7 %l0{%l7 %i0{%i7 %fp %sp %asr1{%ars31 %psr %tbr %y
31:28

Notation

ISEM Reference Card (Integer Unit)

Assembler Syntax
operation operation a
29:25 31:30 24:19

Load Instructions

Instruction Formats
11 11 rd rd op3 op3

address ], reg rd regaddr ]asi , reg rd

18:14

rs1 rs1

13

0 1

12:5

asi rs2 siconst13

4:0

Operations
operation ldsb ldsh ldub lduh ld ldd ldstub swap

Registers

%r0 always holds the 32-bit integer value 0. %psr has the following structure: %tbr has the following structure:
Trap base address
31:12

Meaning integer registers global regs (%r0{%r7) output regs (%r8{%r15) local regs (%r16{%r23) input regs (%r24{%r31) frame pointer (%i6) stack pointer (%o6) ancillary state registers processor status register trap base register multiply/divide register
19:14 13 12

Assembler Syntax
31:30

SETHI Instructions

op3 001001 001010 000001 000010 000000 000011 001101 001111

operation (alt. space) ldsba ldsha lduba lduha lda ldda ldstuba swapa

op3 011001 011010 010001 010010 010000 010011 011101 011111

Instruction 24:22 Format 29:25

00 rd 100

sethi const 22, reg rd sethi %hi(const ), reg rd

const22
21:0

Assembler Syntax
7 6 5 4:0 31:30 29:25 24:19

Arithmetic and Logical Instructions

18:14 13 12:5 4:0

impl

27:24

ver

23 22 21 20

n z v c reserved EC EF PIL S PS ET CWP trap type

11:4

11:8

Instruction Formats
10 10 rd rd op3 op3

operation reg rs1 , reg rs2 , reg rd operation reg rs1 , siconst 13, reg rd
rs1 rs1 0 unused (zero) rs2 siconst13 1

0000

3:0

Assembler Syntax
31:30 29:25 24:19

Store Instructions
18:14 13 12:5 4:0

Operations
operation add addx and andn or orn udiv umul sdiv smul sub subx taddcc tsubcc xor xnor

Instruction Formats
11 11 rd rd op3 op3

operation reg rd , address ] operation a reg rd , regaddr ]asi

rs1 rs1 0 1 asi rs2 siconst13

op3 000000 001000 000001 000101 000010 000110 001110 001010 001111 001011 000100 001100 100000 100001 000011 000111

Operations
operation stb sth st std

op3 000101 000110 000100 000111

operation (alt. space) stba stha sta stda

op3 010101 010110 010100 010111

operation addcc addxcc andcc andncc mulscc orcc orncc udivcc umulcc sdivcc smulcc subcc subxcc taddcctv tsubcctv xorcc xnorcc

op3 010000 011000 010001 010101 100100 010010 010110 011110 011010 011111 011011 010100 011100 100010 100011 010011 010111

Assembler Syntax
31:30 29:25 24:19

Shift Instructions
18:14 13 12:5 4:0

Instruction Formats
10 10 rd rd op3 op3

operation reg rs1 , reg rs2 , reg rd operation reg rs1 , const 5, reg rd
rs1 rs1 0 unused (zero) 1 unused (zero) rs2 const5

Assembler Syntax
31:30 29:25 24:19

Restore and Save Instructions

18:14 13 12:5 4:0

Instruction Formats
10 10 rd rd op3 op3

operation reg rs1 , reg rs2 , reg rd operation reg rs1 , siconst 13, reg rd
rs1 rs1 0 unused (zero) rs2 siconst13 1

Operations
operation sll sra srl

Assembler Syntax
operation label operation ,a label
010

Branch Instructions
21:0

op3 100101 100111 100110

Operations

operation op3 restore 111101 save 111100

Assembler Syntax
31:30 29 28:25 24:19

Trap Instructions
18:14 13 12:5 4:0

Instruction 24:22 Format 31:30 29 28:25

00 a cond

Instruction Formats
10 r cond 10 r cond 111010 111010

operation reg rs1 , reg rs2 , reg rd operation reg rs1 , siconst 13, reg rd
rs1 rs1 0 unused (zero) rs2 siconst13 1

disp22

Operations
operation bn be (bz) ble bl bleu bcs (blu) bneg bvs

Assembler Syntax
31:30

Jump and Link Instructions

29:25

cond 0000 0001 0010 0011 0100 0101 0110 0111

operation ba bne (bnz) bg bge bgu bcc (bgeu) bpos bvc

cond 1000 1001 1010 1011 1100 1101 1110 1111

Operations
operation tn te (tz) tle tl tleu tcs (tlu) tneg tvs nop

Instruction Formats
10 10 rd rd 111000 111000
24:19

jmpl address , reg rd

Assembler Syntax
12:5 4:0 31:30

The NOP Instruction

00000 100

cond 0000 0001 0010 0011 0100 0101 0110 0111

operation ta tne (tnz) tg tge tgu tcc (tgeu) tpos tvc

cond 1000 1001 1010 1011 1100 1101 1110 1111

18:14

rs1 rs1

13

0 unused (zero) rs2 siconst13 1

Instruction 24:22 Format 29:25

00

0000000000000000000000

21:0

Assembler Syntax
rett address
00000 00000
29:25 31:30

Return from Trap Instructions

111001 111001
24:19 18:14

Assembler Syntax
unimp const 22
000
31:30 4:0

The UNIMP Instruction

const22
21:0

Instruction Formats
10 10

Instruction 24:22 Format 29:25

00 reserved

rs1 rs1

13

0 unused (zero) rs2 siconst13 1

12:5

Assembler Syntax
call label
31:30

Call and Link Instructions

disp30
29:0

Assembler Syntax
stbar
31:30

The STBAR Instruction

00000 101000 01111
18:14

Instruction Format 29:25 24:19

10

Instruction Format
01

unused (zero)

13:0

Assembler Syntax
rd statereg , rd
rd
31:30

Read State Register Instructions

op3
18:14

Instruction Format 29:25 24:19

10

rs1

unused (zero)

13:0

Register Encodings
state register %y %asr1{%asr31 %psr %wim %tbr

Assembler Syntax
31:30 29:25 24:19

Write State Register Instructions

18:14 13 12:5 4:0

op3 101000 101000 101001 101010 101011

rs1 0 1{31 reserved reserved reserved

Instruction Formats
10 10 rd rd op3 op3

wr reg rs1 , reg rs2 , statereg wr reg rs1 , siconst 13, statereg
rs1 rs1 rs2 0 unused (zero) siconst13 1

Register Encodings
state register %y %asr1{%asr31 %psr %wim %tbr

Assembler Syntax
ush address
29:25 31:30

FLUSH Instructions
111011 111011
24:19

op3 110000 110000 110001 110010 110011

rd 0 1{31 reserved reserved reserved

Synthetic instruction bclr rs , rd bclr rs , siconst 13 bset rs , rd bset siconst 13 , rd btst rs 1, rs 2 btst rs , siconst 13 btog rs , rd btog rs , siconst 13 call address clr rd clrb address ] clrh address ] clr address ] cmp rs 1, rs 2 cmp rs , siconst 13 dec rd dec siconst 13 , rd deccc rd deccc siconst 13 , rd inc rd inc siconst 13 , rd inccc rd inccc siconst 13 , rd jmp address mov rs , rd mov siconst 13 , rd mov statereg , rd mov rs , statereg mov siconst 13 , statereg neg rs , rd neg rd not rd not rs , rd restore save ret retl set iconst , rd

Synthetic Instructions

Instruction Formats
10 unused 10 unused

18:14

rs1 rs1

13

0 unused (zero) rs2 siconst13 1

12:5

4:0

tst

rs

Implementation andn rd , rs , rd andn rs , siconst 13 , rd or rd , rs , rd or rd , siconst 13 , rd andcc rs 1 , rs 2, %g0 andcc rs , siconst 13 , %g0 xor rd , rs , rd xor rs , siconst 13 , rd jmpl address , %g0 or %g0, %g0, rd stb %g0, address ] sth %g0, address ] st %g0, address ] subcc rs 1 , rs 2, %g0 subcc rs , siconst 13 , %g0 sub rd , 1, rd sub rd , siconst 13 , rd subcc rd , 1, rd subcc rd , siconst 13 , rd add rd , 1, rd add rd , siconst 13 , rd addcc rd , 1, rd addcc rd , siconst 13 , rd jmpl address , %g0 or %g0, rs , rd or %g0, siconst 13 , rd rd statereg , rd wr %g0, rs , statereg wr %g0, siconst 13 , statereg sub %g0, rs , rd sub %g0, rd , rd xnor rd , %g0, rd xnor rs , %g0, rd restore %g0, %g0, %g0 save %g0, %g0, %g0 jmpl %i7+8, %g0 jmpl %o7+8, %g0 or %g0, iconst , rd |or | sethi %hi(iconst ), rd |or | sethi %hi(iconst ), rd or rd , %lo(iconst ), rd orcc %g0, rs , %g0

.align .ascii .asciz .byte .data .global .half .include .skip .text .word 0 1 2 3

Assembler Directives
n

"string " , "string "]* "string " , "string "]* 8-bitval , 8-bitval ]*
label , label ]* 16-bitval , 16-bitval ]* " lename "
n

ISEM Traps

32-bitval , 32-bitval ]*

terminate program putchar( %r8 ) blocking getchar( %r8 ) nonblocking getchar( %r8 )