UNIVERSITY

OF REGINA MIPS CARD [david.gerhard@uregina.ca] Rev 1.6 Nov 2020

Name Mnem Fmt Category Opcode Funct Category Fmt Example Operation Notes
Add add R ALU-R 000000 100000 ALU-R R add rd, rs, rt R[rd] = R[rs]+R[rt] Opcode extended by funct
Add Immediate addi I ALU-I 001000 ALU-I I addi rt, rs, imm R[rt] = R[rs]+se(imm) Sign-extend if signed; zero-pad if unsigned
Add Unsigned Immediate addiu I ALU-I 001001 Shift-R R sll rd, rt, shamt R[rd] = R[rt]≪shamt Shift amount is 5 bit unsigned, (0..32)
Add Unsigned addu R ALU-R 000000 100001 Shift-V R sllv rd, rt, rs R[rd] = R[rt]≪R[rs] Shift amount is bottom 5 bits of rs
Subtract sub R ALU-R 000000 100010 Set-R R slt rd, rs, rt if (R[rs]<R[rt]) R[rd]=1; else R[rd]=0
Unsigned Subtract subu R ALU-R 000000 100011 Set-I I slt rt, rs, imm if (R[rs]<se(imm)) R[rt]=1; else R[rt]=0 Sign-extend if signed; zero-pad if unsigned
Bitwise AND and R ALU-R 000000 100100 Branch I/P beq rs, rt, label if (R[rs]==R[rt]) PC+=4+se(imm≪2) If condition fails, PC remains at PC+4
Bitwise AND Immediate andi I ALU-I 001100 Jump-J J j label PC = pc[31-27]:label[26-2]:[00] $ra=PC+4 if using “and link”
Bitwise NOR nor R ALU-R 000000 100111 Jump-R R jr rs PC = R[rs] $ra=PC+4 if using “and link”
Bitwise OR or R ALU-R 000000 100101 lw rt, imm(rs) R[rt] = M[R[rs]+se(imm)] If unsigned, zero-pad immediate offset. If loading a
L/S I sw rt, imm(rs) M[R[rs]+se(imm)] = R[rt] byte or halfword, zero-pad rt.
Bitwise OR Immediate ori I ALU-I 001101
Bitwise XOR xor R ALU-R 000000 100110 mul rs, rt [hi:lo] = R[rs] * R[rt]
Mul/Div R div rs, rt lo=R[rs]/R[rt]; hi=R[rs]%R[rt] mfhi and mflo retrieve results to register file
Bitwise XOR Immeidate xori I ALU-I 001110
Shift Left Logical sll R Shift-R 000000 000000

Common Pseudoinstructions
Shift Right Logical srl R Shift-R 000000 000010 Name Mnem Function (I format) Opcode code** Name Mnem operands Example Code
Shift Right Arithmetic sra R Shift-R 000000 000011 Branch < zero bltz if ([rs]<[0]) PC←PC+* 000001 00000 Branch if less than blt
Shift Left Logical Var. sllv R Shift-V 000000 000100 Branch < zero, if ([rs]<[0]) PC←PC+* Branch if greater than bgt slt $at,rs,rt
bltzal 000001 10000 rs, rt, label bne $at,$0,lbl
Shift Right Logical Var. srlv R Shift-V 000000 000110 and link $ra = PC+4 Branch if less or equal ble
Shift Right Arith. Var. srav R Shift-V 000000 000111 Branch ≥ zero bgez if ([rs]≥[0]) PC←PC+* 000001 00001 Branch if greater/equal bge
Branch ≥ zero, if ([rs]≥[0]) PC←PC+* bltu
Set Less Than slt R Set-R 000000 101010 bgezal 000001 10001
and link $ra = PC+4 bgtu sltu $at,rs,rt
Set Less Than Immediate slti I Set-I 001010 unsigned branch rs, rt, label bne $at,$0,lbl
Branch > zero bgtz if ([rs]>[0]) PC←PC+* 000111 bleu
Set Less Than Uns. Imm. sltiu I Set-I 001011
Branch ≤ zero blez if ([rs]≤[0]) PC←PC+* 000110 bgeu
Set Less Than Unsigned sltu R Set-R 000000 101011 *PC←PC+: PC+=4+se(imm≪2) **rt field, bits 20-16 Branch if equal zero beqz beq rs,$0,lbl
Branch if Equal beq I Branch 000100 rs, label
Floating Point instructions (FR format, even regs only) Branch if not equal zero bnez bne rs,$0,lbl
Branch if Not Equal bne I Branch 000101
Mnem Function opcode ex func Move move rd, rs addu rd, $0, rs
Jump j J Jump-J 000010
add.s 010001 010000 000000 3 operand Multiply mul mult rs,rt; mflo rd
Jump and Link jal J Jump-J 000011 rd, rs, rt
sub.s Single precision 010001 010000 000001 3 operand divide div div rs,rt; mflo rd
Jump Register jr R Jump-R 000000 001000
mul.s F[fd] = F[fs] + F[ft] 010001 010000 000010 Load Immediate li rt, value ori $rt,s e(imm)
Jump and Link Register jalr R Jump-R 000000 001001
div.s 010001 010000 000011 lui $at,imm[31:16]
Load Byte lb I L/S 100000 Load Address la rt, label ori $rt,$at,imm[15:0]
Load Byte Unsigned lbu I L/S 100100 add.d Double precision 010001 010001 000000
sub.d F[fd]:F[fd+1] 010001 010001 000001 addi $sp,$sp,-4
Load Halfword lh I L/S 100001 Push register push rt sw rt, 0($sp)
Load Halfword Unsigned lhu I L/S 100101 mul.d = F[fs]:F[fs+1] 010001 010001 000010
div.d + F[ft]:F[ft+1] 010001 010001 000011 lw rt, 0($sp)
Load Upper Immediate lui I L/S 001111 Pop register pop rt addi $sp,$sp,4
Load Word lw I L/S 100011 Rotate Left rol slr $at,rt,32-shamt
Store Byte sb I L/S 101000 lwc1 Load copr 1 I format, as lw/sw 0x31 rd, rt, shamt sll rd,rt,shamt
lwc1 rf, imm(rs) rt = rf Rotate Right ror
Store Halfword sh I L/S 101001 swc1 Store copr 1 0x39 or rd, rd, $at
Store Word sw I L/S 101011 Rotate Left Variable rolv
rd, rt, rs
Divide div R Mul/Div 000000 011010 Register File Rotate Right Variable rorv
Divide Unsigned divu R Mul/Div 000000 011011
Multiply mult R Mul/Div 000000 011000 Number Name Use Save Service $v0 Arg/Result Directive function (label:)
Multiply Unsigned multu R Mul/Div 000000 011001 $0 $zero zero value - print_int 1 $a0=integer .data Store in data segment
Move from LO Register mflo R R[rd]=lo 000000 010010 $1 $at assembler temp (res) - print_float 2 $f12=float .text Store in code segment
Move from HI Register mfhi R R[rd]=hi 000000 010000 .ascii Store in ascii format
$2 - $3 $v0 - $v1 return values no print_double 3 $f12=double
System Call (syscall) R 000000 001100 .asciiz ascii, null-terminate
$4 - $7 $a0 - $a3 arguments yes print_string 4 $a0=string .space n Store n bytes of space
000000 00000 00000 00000 00000 000000 $8 - $15 $t0 - $t7 temporary no read_int 5 $v0 ← int .byte Store int as bytes
31 - 26 25 - 21 20 - 16 15 - 11 10 - 6 5 - 0 read_float 6 $f0 ← float .half Store int as halfwords
$16 - $23 $s0 - $s7 saved yes
R opcode rs rt rd shamt funct read_double 7 $f0 ← float .word Store int as words
I opcode rs rt immediate $24 - $25 $t8 - $t9 temporary no
read_string 8 $a0=buffer .single Store fp in words
J opcode pseudo-direct $26 - $27 $k0 - $k1 OS kernel (reserved) -
FR opcode ex ft fs fd funct alloc memory 9 $a1=length
$a0=amount .double Store fp in double
$28 $gp global pointer yes .align n Reset word boundary
FI opcode ex ft immediate exit 10
$29 $sp stack pointer yes
R oooo ooss ssst tttt dddd dhhh hhff ffff $30 $fp frame pointer yes 0 1 2 3 4 5 6 7 8 9 A B C D E F
I oooo ooss ssst tttt iiii iiii iiii iiii $31 $ra return address yes 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
J oooo oopp pppp pppp pppp pppp pppp pppp