Finite State Machines

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State Machine Concepts

State, current state, next state, state registers IFL, OFL, Moore outputs, Mealy outputs Transition tables
With output dont cares (Xs) With input dont cares (-s)

State graphs
And their correspondence to TTs

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Counters as State Machines

A counter is a finite state machine
Where the state encodings are significant
1001 1000 0000 0001 0010

0111

0011

Q0 Q1 Q2 Q3

7 Segment Decoder

0110 0101

0100

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State Machines
A state machine is a sequential circuit which progresses through a series of states in reponse to inputs
The output values are usually significant The state encodings are usually not significant
Unlike with counters

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State Encodings
In this machine, the state encodings dont matter The output values do

Event1

Event1 Output1

Event2 Output2

Output3

Notice the alternate notation for X and outputs

Event2

Event3

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A State Machine Controller for a Photocopier

Buttons Lamps

Timers

Inputs

Finite State Machine

Outputs

Motors

Switches

Display 1) FSM receives inputs from copier 2) FSM generates control outputs in response 3) States help it remember where it is in the copy process
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A Sequence Detector FSM

Xin

S0
Xin

Because the encodings dont matter, we will use symbolic state names

S3

S1
Xin

Xin

Xin

S2

Xin

What does this machine do?

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A Sequence Detector FSM

Xin

It is called a sequence detector.

S0
Xin

It has 1 input (Xin) and one output (Z)

S3

S1
Xin

Xin

Xin

S2

Xin

It detects the sequence 0..1..1 on the input. When detected, output Z is asserted.
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A Sequence Detector FSM

Xin

As long as Xin=1, we stay in state S0

S0
Xin

1..1..1..1..1..

S3

S1
Xin

Xin

Xin

S2

Xin

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A Sequence Detector FSM

Xin

When Xin=0, we go to state S1

S0
Xin

1..1..1..1..1..0..

S3

S1
Xin

Xin

Xin

S2

Xin

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A Sequence Detector FSM

Xin

As long as Xin=0, we stay in state S1

S0
Xin

1..1..1..1..1..0..0..0..0..

S3

S1
Xin

Xin

Xin

S2

Xin

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A Sequence Detector FSM

Xin

When Xin=1, we go to state S2

S0
Xin

1..1..1..1..1..0..0..0..0..1..

S3

S1
Xin

Xin

Xin

S2

Xin

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A Sequence Detector FSM

Xin

If Xin=1 again, we go to state S3

S0
Xin

1..1..1..1..1..0..0..0..0..1..1

S3

S1
Xin

Xin

Xin

SUCCESS! Raise the Z output

Xin

S2

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A Sequence Detector FSM

Xin

Once we enter state S3, we never leave

S0
Xin

S3

S1
Xin

Xin

Xin

S2

Xin

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A Sequence Detector FSM

Xin

What if we dont see the second Xin=1?

S0
Xin

1..1..1..1..1..0..0..0..0..1..0..

S3

S1
Xin

Xin

Xin

S2

Xin

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Implementing the Sequence Detector FSM

1. 2. 3. 4. Create symbolic Transition Table Assign state encoding Create conventional Transition Table Do standard implementation steps
Xin CS 0 1 0 1 0 1 S0 S0 S1 S1 S2 S2 S3 NS Z S1 S0 S1 S2 S1 S3 S3 0 0 0 0 0 0 1

Xin Q1 Q0 N1 N0 Z 0 1 0 1 0 1 0 0 0 0 1 1 1 0 0 1 1 0 0 1 0 0 0 1 0 1 1 1 0 1 0 1 1 1 0 0 0 0 0 0 1

S0 = 00 S1 = 01 S2 = 10 S3 = 11 State Assignment
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Symbolic TT

Conventional TT
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Sequence Detector Implementation

N1 = Q1Q0 + XinQ1 + XinQ0 N0 = Xin + Q1 Z = Q1Q0
Q1 Q0 Q1 Xin Xin Q0 N1 Z Q1

D Q

CLK Q0

Xin Q1

N0

D Q

CLK
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A Problem With the Sequence Detector

This FSM only detects first occurrence of 011 on input Here is a timing diagram
actual screenshot from a simulation

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Improved Sequence Detector

This starts over each time 011 is detected
Xin

S0
Xin Xin Xin

S3
Xin

S1
Xin

Xin

S2
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Xin
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Improved Detector Timing Diagram

Z=1 any time state is S3 Looking at Xin, does it look like Z is a cycle late? How could we make Z output a cycle earlier?

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Mealy Version of Sequence Detector

Xin

Output is asserted during the second 1 of the 011 sequence

S0
Xin Xin Xin

S3
Xin / Y

S1
Xin

Xin

S2

Xin

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Mealy Version Timing Diagram

Note how Mealy output follows input during state S2 Output is a cycle earlier than in Moore machine it appears in S2 rather than in S3

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Simplified Mealy Sequence Detector

A characteristic of Mealy state machines is they often require fewer states than Moore state machines Here is simplified but basically equivalent FSM

Xin

S0
Xin

Xin / Y

S1
Xin

Xin

S2
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Xin

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Example FSMs
Two Car Wash Controllers

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Basic Car Wash FSM Operation

1. 2. 3. 4. Wait for a token to be inserted Reset timer Turn on water pump until timer expires Start over This assumes existence of:
Token acceptance mechanism Timer Digitally-controlled water pump
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Basic Car Wash FSM SG

TOKEN

Wait for token

S_IDLE

TOKEN

Clear timer
S_TOKEN

TDONE

CLRT

SPRAY

S_SPRAY

Spray car while waiting for timer to expire

TDONE
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TOKEN TDONE 0 1 0 1

CS

NS

CLRT SPRAY 0 0 1 0 0 0 0 0 1 1

S_IDLE S_IDLE S_IDLE S_TOKEN S_TOKEN S_SPRAY S_SPRAY S_SPRAY S_SPRAY S_IDLE

TOKEN TDONE Q1 Q0 N1 N0 CLRT SPRAY 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 X 0 1 0 X 0 1 1 X 0 1 0 X 0 0 0 X 0 0 0 X 1 0 0 X 1 0 0 X 0 1 0 X 0 1 0 X 0 1 0 X 0 1 0 X 0 0 1 X 0 0 1 X 0 0 1 X 0 0 1 X

TOKEN TDONE 0 1 0 1

Q1 Q0 00 00 01 10 10

N1 N0 00 01 10 10 00

CLRT SPRAY 0 0 1 0 0 0 0 0 1 1

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Basic Car Wash Implementation

SPRAY Q0 Q1 TDONE CLK TOKEN Q1 Q0 N0 CLRT Q0 N1

D Q

Q1

D Q

CLK

This is what you get from a K-map solution

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Simplified State Graph

TOKEN

Clear timer while waiting for a token and eliminate a state

CLRT

S_IDLE

TDONE

TOKEN
TOKEN TDONE 0 1 0 1 CS NS CLRT SPRAY 1 1 0 0 0 0 1 1 S_IDLE S_IDLE S_IDLE S_SPRAY S_SPRAY S_SPRAY S_SPRAY S_IDLE

SPRAY

S_SPRAY

TDONE
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Simplified Car Wash Implementation

State Encoding: S_IDLE = 0, S_SPRAY = 1 NS = CSTOKEN + CSTDONE CLRT = CS SPRAY = CS

CS TOKEN CS TDONE

CS NS

D Q

SPRAY CLRT

CLK

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A Fancy Car Wash Controller

Two types of washes:
Regular wash (spray only) = 1 token Deluxe wash (spray, soap, spray) = 2 tokens

Customer:
Inserts 1 token and pushes START for Regular Inserts 2 tokens for Deluxe

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TOKEN

S0
T1DONE TOKEN

Straightforward process to write transition table and reduce to gates

TOKEN START CLRT1

S1

START

TOKEN START

T1DONE

S4 SPRAY
SPRAY, CLRT2 T2DONE T1DONE

S2

T1DONE

S3 SOAP, CLRT1

Creativity in FSM design is designing the initial state graph

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T2DONE

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Enhancements to Fancy Controller

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TOKEN

S0 ACCEPTCOIN
T1DONE CLRT1, ACCEPTCOIN TOKEN

There is no way to cause coinbox to refuse tokens. Coins inserted after wash commences are presumably kept by the machine.

TOKEN START

S1

START

TOKEN START

T1DONE

S4 SPRAY
SPRAY, CLRT2 T2DONE

S2

T1DONE

T1DONE

S3 SOAP, CLRT1

Lets add an ACCEPTCOIN output to control when coinbox will accept tokens
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T2DONE

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TOKEN

S0 ACCEPTCOIN
T1DONE ACCEPTCOIN CLRT1 TOKEN

If customer pushes START at precisely the same time as he inserts another TOKEN, the FSM will take the token, but deliver a Regular Wash.

TOKEN START

S1

START

TOKEN START

T1DONE

S4 SPRAY
SPRAY, CLRT2 T2DONE

S2

T1DONE

T1DONE

S3 SOAP, CLRT1

That is, START has precedence over TOKEN

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T2DONE

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TOKEN

S0 ACCEPTCOIN
T1DONE ACCEPTCOIN CLRT1 TOKEN

This changes the precedence so the machine wont steal the second token, but will give a deluxe wash in this case.

TOKEN START

S1

STARTTOKEN

TOKEN

T1DONE

S4 SPRAY
SPRAY, CLRT2 T2DONE

S2

T1DONE

T1DONE

S3 SOAP, CLRT1

T2DONE

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Completeness and Conflict Revisited

State S1 is a typical problem spot Carefully analyze the state graph to ensure no conflicts exist and that all cases covered.

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Resetting State Machines

Ability to reset the FSM is essential for most systems Always include a reset capability
Add CLR signal to state graph Use flip flops with reset/set inputs Either method will work

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Another Example
An Electronic Key Lock

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Example: Electronic Key Lock

1) 2) 3) 4) 5) There are 10 keypads 0-9 The unlock sequence is 7..8..9 When a pad is pushed, the signal for that number is asserted When any of the keypads are pushed a PUSHED signal is asserted If you push a number out of sequence, you get an error indicator and you get to start over 6) After three wrong tries, you must wait hour before trying again 7) If you entered the correct sequence, the lock unlocks. 8) Once the lock has opened, nothing happens until it is manually locked again. Inputs: Keypads signals 0-9 PUSHED signal ECNT3 (error count = 3) WAITDONE LOCKED
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Outputs: INC CLRCNTR CLRTIMER ERROR UNLOCK

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LOCKED

D
LOCKED/ CLRCNTR PUSHED PUSHED PUSHED PUSHED9/ UNLOCK

A
Start

PUSHED7

PUSHED8

WAITDONE/ CLRCNTR ECNT3

PUSHED7/ INC

PUSHED8/ INC PUSHED9/ INC

F
WAITDONE

ECNT3/ CLRTIMER

ERROR

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LOCKED

Lets create the transition table

LOCKED/ CLRCNTR

D
PUSHED PUSHED9/ UNLOCK PUSHED PUSHED8

PUSHED

A Start

PUSHED7

WAITDONE/ CLRCNTR

PUSHED7/ PUSHED8/ INC INC PUSHED9/ ECNT3 INC

WAITDONE

F
A A A B B B C C C D D E E F F

ECNT3/ CLRTIMER

E
0 0 0 0 0 0 0 0 1 0 0 0 1

ERROR

PUSHED 7 8 9 ECNT3 WAITDONE LOCKED STATE NEXTSTATE INC ERROR CLRCNTR CLRTIMER UNLOCK 0 1 1 0 1 1 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 A E B B E C C E D D A A F F A 0 1 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0

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Now lets expand State A

PUSHED 7 8 9 ECNT3 WAITDONE LOCKED STATE NEXTSTATE INC ERROR CLRCNTR CLRTIMER UNLOCK 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

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This is going to get ugly fast

7 inputs + 3 state bits = 1024 rows in TT Can you do a 10-variable K-map? There is a technique called One-Hot state machines we can use instead (future lecture) We could also use behavioral Verilog

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