ICS 211 Computer organization and Architecture (Assignment 2) 1.

Imagine you are on the design team for a new 16-bit processor. The ISA for the processor includes specifications for: 16 general-purpose registers. 8 ALU instructions that take two input register operands and write a result into a third output register operand. 4 branch instructions that take an input register operand and an 8-bit immediate offset. 2 memory access instructions that take two input register operands and one output register operand. 2 memory access instructions that take one input register operand, one output register operand and a 4-bit immediate offset. a. Devise an instruction encoding for the processor, taking care to explain any advantages and disadvantages of your design. b. Draw a block diagram of the basic components within this processor, explain the function of each one and how they are connected together.

2. a) It has been suggested that in designing a new processor, a pipelined approach should be used instead of a multi-cycle approach. Explain how and why a pipelined design would improve performance; draw a data-path block diagram to describe which components fit into which pipeline stages and why. b) In the context of pipelined processor design, explain the meaning of the following terms and give examples of each: i. Structural dependency. ii. Control dependency. iii. Data dependency. c) A pipelined processor might stall when such dependencies are encountered; the performance is decreased as a result. Explain how the three types of dependency listed above can be avoided so that stalls are minimized. d) In a pipelined processor design, branches can cause control dependencies that stall the processor until resolved. There are several options for dealing with this problem; select two of the three options below and describe how they work: i. Branch delay slot. ii. Predicated execution. iii. Branch prediction. For each option, your answer should explain how the scheme works, how it reduces the performance impact, and the trade-off between complexity and performance for the programmer and/or in the hardware.