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University of Engineering and Technology, Lahore Department of Electrical Engineering

EE 230: Analog Electronic Circuits Common Base Amplifier Design Assignment
1- Common Base Amplifier Design
Design and breadboard a VDB Common Base amplifier meeting the following requirements: VCC = +15 V. Rin in the range of 40-60 . Be careful while measuring Rin in the lab. Use the same procedure as was used in the common base experiment. In this case use an Rsig = 56 for measurement. VB (DC base to ground voltage) 4V Maximum vout swing 8 Vpk-pk RL =

Assume = 100. RTH = ( x RE)/10. Using input coupling and base to ground capacitors of 100uF and 10uF respectively. Use 5% standard resistors. Write down your design in the space provided below. Also draw the circuit diagram showing all the component values. Also label the diagram with the node numbers that have been assigned during simulation. In the lab you will be asked to connect your circuit and show the output to the Lab Instructor. Note that this is an INDIVIDUAL design assignment.

2- Design Simulation
Simulate your design in WinSpice. Use 5% standard resistors during simulation. Note down the calculated and simulated values in Table 1. Use the following BJT model .MODEL 2N3904 NPN (Is=6.734f Xti=3 Eg=1.11 Vaf=74.03 Bf=416.4 Ne=1.259 Ise=6.734f Ikf=66.78m Xtb=1.5 Br=.7371 Nc=2 Isc=0 Ikr=0 Rc=1 Cjc=3.638p Mjc=.3085 Vjc=.75 Fc=.5 Cje=4.493p Mje=.2593 Vje=.75 Tr=239.5n Tf=301.2p Itf=.4 Vtf=4 Xtf=2 Rb=10)

3- What to Submit?
This handout Printout of SPICE code Printout of TRAN analysis Printout of AC analysis Printout of OP analysis

You may copy & paste multiple plots on a single page

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Design:

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Circuit diagram:

Rin (calc.) ()

Rin (sim.) ()

VB(calc.) (V)

VB (sim.) (V)

Max. o/p swing(calc.) (Vpk-pk)

Max. o/p swing(sim.) (Vpk-pk)

Table 1

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