JHXXX M/B LA-4241P Schematic Block Diagrams and Notes

A
ZZZ1
PJP1
PJP1
PCB
14W_DCIN
15W_DCIN
14W_45@
15W_45@
12/21 Add PJP1 for DCIN Cable on 45 Level

One for 14W DCIN , PN: DC301001Y00
Another for 15W DCIN , PN: DC301001V00
Compal Confidential
JHXXX Schematics Document
Intel Penryn Processor with Cantiga + DDRII + ICH9M

(With nVIDIA MXM/B)
2008-04-24
REV: 0.4
3
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
A
Title
Cover Page
Size
B
Date:
Document Number
Rev
0.4
ai
2008/8/18
Deciphered Date
JHXXX M/B LA-4241P Schematic
he
x
2007/08/18
Issued Date
Compal Electronics, Inc.
Compal Secret Data
Security Classification
nf
@
ho
tm
ai
l.c
om
Thursday, April 24, 2008
Sheet
of
49
Compal Confidential
Model Name : JHXXX
File Name : LA-4241P
Intel Penryn Processor
Fan Control
Thermal Sensor
Clock Generator
ADT7421
ICS9LPRS387
page 4
page 4
uPGA-478 Package
page 16
page 4,5,6
FSB
667/800MHz
H_A#(3..35)
H_D#(0..63)
LVDS
LCD Conn.
page 18
Memory BUS(DDRII)
Intel Cantiga
HDMI
page 25
CRT
page 19
MXM II VGA/B
page 14,15
BANK 0, 1, 2, 3
page 7,8,9,10,11,12,13
DMI
X4 mode
page 17
200pin DDRII-SO-DIMM X2
1.8V DDRII 533/667
uFCBGA-1329
PCI-Express
Dual Channel
USB conn x3
TO I/O/Bpage
Bluetooth
Conn page
35
CMOS Camera
34
Finger Print
Conn page 40
page 40
PCI-Express
Intel ICH9-M
3.3V 48MHz
USB
3.3V 24.576MHz/48Mhz
HD Audio
BGA-676
S-ATA
page 20,21,22,23
New Card MINI Card x3

WLAN,
Socket
page 31
TV-Tuner
Robson
port 0
LAN(GbE)
GMCH HDA
Card Reader
RTL8111C/8102E
page 8
MDC 1.5
Conn
page 40
HDA Codec
ALC268
page 36
JMB385
page 30
page 28
page 26
3 in 1
socket
RJ45
page 29
S-ATA HDD
Conn. page 24
S-ATA ODD
Conn. page 24
Audio AMP
page 37
LPC BUS
page 26
RTC CKT.
ENE KB926
page 21
Power On/Off CKT.
Function/B
Power USB/B
page 33
page 35
DC/DC Interface CKT.

page 41
Power Circuit DC/DC

4
page 44
Int.KBD
Touch Pad
page 34
USB I/O Conn.

CIR
LID SW
Debug port
page 33
BIOS
SCREW
page 39
page 34
page 35
page 41,42,43,45
46,47,48
CHARGER
page 32
TPM
LED
2007/08/18
Issued Date
Compal Secret Data
page 40
2008/8/18
Deciphered Date
A
Title
Block Diagrams
Size
B
Date:
Document Number

Sheet
Friday, April 11, 2008

E
of
49
Rev
0.4
Voltage Rails
Power Plane
Description
S1
S3
VIN
Adapter power supply (19V)
N/A
N/A
S5
N/A
B+
AC or battery power rail for power circuit.
N/A
N/A
N/A
1
+CPU_CORE
Core voltage for CPU
ON
OFF
OFF
+0.9VS ( Actual +0.9V )
0.9V switched power rail for DDR terminator
ON
ON
OFF
+1.05VS
1.05V switched power rail
ON
OFF
OFF
+1.5VS
ON
OFF
OFF
+1.8V
1.8V power rail for DDR
ON
ON
OFF
+1.8VS
ON
OFF
OFF
+3VALW
3.3V always on power rail
ON
ON
ON*
+3VS
ON
OFF
OFF
+5VALW
5V always on power rail
ON
ON
ON*
+5VS
5V switched power rail
ON
OFF
OFF
Device
Address
Device
Address
+VSB
VSB always on power rail
ON
ON
ON*
Smart Battery
0001 011X b
ADI ADM1032
1001 100X b
+RTCVCC
RTC power
ON
ON
ON
EEPROM(24C16/02)
1010 000X b
NVIDIA NB8X
EC SM Bus1 address
EC SM Bus2 address
ICH9M SM Bus address

2
STATE
SIGNAL
SLP_S1# SLP_S3# SLP_S4# SLP_S5#
+VALW
+V
+VS
Clock
HIGH
HIGH
HIGH
HIGH
ON
ON
ON
ON
S1(Power On Suspend)
LOW
HIGH
HIGH
HIGH
ON
ON
ON
LOW
S3 (Suspend to RAM)
LOW
LOW
HIGH
HIGH
ON
ON
OFF
OFF
S4 (Suspend to Disk)
LOW
LOW
LOW
HIGH
ON
OFF
OFF
OFF
S5 (Soft OFF)
LOW
LOW
LOW
LOW
ON
OFF
OFF
OFF
Full ON
ID1
ID0
JHT00 ( 00@ )
R361
R357
JHT01 ( 01@ )
R361
R355
JHL90 ( 10@ )
R360
R357
JHL91 ( 11@ )
R360
R355
Clock Generator
(ICS9LPRS325AKLFT_MLF72)
1101 001Xb
DDR DIMM0
1010 000Xb
DDR DIMM1
1010 010Xb
SKU ID Table
Vcc
Rb
3.3V +/- 5%
47K +/- 5%
Board ID
Rb
NA
47K(RB@)
47K(RB@)
47K(RB@)
47K(RB@)
47K(RB@)
47K(RB@)
47K(RB@)
47K(RB@)
47K(RB@)
47K(RB@)
47K(RB@)
1
2
3
4
5
6
7
8
9
10
11
12
MIC ID Table
R
R585 Single MIC
R583 Array MIC
Address
Rb~ R470
Ra~ R472
PROJECT ID Table
3
Device
Structure
SINGLE@
DUAL@
R472
R472
R472
R472
R472
4.7K_0402_5%
H_14_C@
10K_0402_5%
H_14_MP@
18K_0402_5%
H_15_B@
27K_0402_5%
H_15_C@
39K_0402_5%
H_15_MP@
R472
R472
R472
R472
R472
56K_0402_5%
L_14_B@
82K_0402_5%
L_14_C@
120K_0402_5%
L_14_MP@
220K_0402_5%
L_15_B@
470K_0402_5%
L_15_C@
Ra
4.7K +/- 5%
4.7K +/- 5%
10K +/- 5%
18K +/- 5%
27K +/- 5%
39K +/- 5%
56K +/- 5%
82K +/- 5%
120K +/- 5%
220K +/- 5%
470K +/- 5%
NA
V AD_BID min
0 V
0.274 V
0.553V
0.849V
1.129 V
1.415 V
1.712 V
2.020V
2.303 V
2.670 V
2.972 V
3.135 V
V AD_BID typ
0 V
0.300 V
0.578 V
0.913V
1.204 V
1.496 V
1.794 V
2.097 V
2.371 V
2.719 V
3.000 V
3.300 V
Ra BOM Structure
H_14_B@
H_14_C@
H_14_MP@
H_15_B@
H_15_C@
H_15_MP@
L_14_B@
L_14_C@
L_14_MP@
L_15_B@
L_15_C@
NA for L_15_MP
V AD_BID max
0 V
0.328 V
0.628 V
0.981 V
1.282 V
1.579 V
1.876 V
2.173 V
2.437 V
2.765 V
3.026 V
3.465 V
A
Title
Notes List
Size
B
Date:
Document Number
Rev
0.4
ai
2008/8/18
Deciphered Date
he
x
2007/08/18
Issued Date
Compal Secret Data
nf
@
ho
tm
ai
l.c
om
Sheet
of
49
Place close to CPU with stub length <200 mils

Should we mount this?
+1.05VS
EMI Recommend
Which to follow?
D
TCK
TDI
TMS
TRST#
PREQ#
H_A#[3..35]
<7> H_A#[3..35]
H_REQ#[0..4]
<7> H_REQ#[0..4]
H_RS#[0..2]
<7> H_RS#[0..2]
JCPU1A
K3
H2
K2
J3
L1
<7> H_ADSTB#1
Y2
U5
R3
W6
U4
Y5
U1
R4
T5
T3
W2
W5
Y4
U2
V4
W3
AA4
AB2
AA3
V1
DEFER#
DRDY#
DBSY#
BR0#
REQ[0]#
REQ[1]#
REQ[2]#
REQ[3]#
REQ[4]#
A[17]#
A[18]#
A[19]#
A[20]#
A[21]#
A[22]#
A[23]#
A[24]#
A[25]#
A[26]#
A[27]#
A[28]#
A[29]#
A[30]#
A[31]#
A[32]#
A[33]#
A[34]#
A[35]#
ADSTB[1]#
A20M#
FERR#
IGNNE#
<21>
<21>
<21>
<21>
D5
C6
B4
A3
STPCLK#
LINT0
LINT1
SMI#
M4
N5
T2
V3
B2
C3
D2
D22
D3
F6
RSVD[01]
RSVD[02]
RSVD[03]
RSVD[04]
RSVD[05]
RSVD[06]
RSVD[07]
RSVD[08]
RSVD[09]
RSVD[10]
H5
F21
E1
H_DEFER# <7>
H_DRDY# <7>
H_DBSY# <7>
F1
H_BR0# <7>
LOCK#
H4
RESET#
RS[0]#
RS[1]#
RS[2]#
TRDY#
C1
F3
F4
G3
G2
AD4
AD3
AD1
AC4
AC2
AC1
AC5
AA6
AB3
AB5
AB6
C20
H_PREQ#
R11
54.9_0402_1%
H_IERR#
R12
56_0402_5%
ITP_TMS
R13
54.9_0402_1%
ITP_TDI
R14
54.9_0402_1%
H_PROCHOT#
R15
56_0402_5%
ITP_TCK
R16
54.9_0402_1%
ITP_TRST#
R17
54.9_0402_1%
U1
+3VS
C1
0.1U_0402_16V4Z
1
2
H_INIT# <21>
H_LOCK# <7>
H_RESET#
H_RS#0
H_RS#1
H_RS#2
LM95245CIMMX NOPB MSOP 8P

NS@
H_RESET# <7>
C2
H_TRDY# <7>
U1
2200P_0402_50V7K
2
H_HIT# <7>
H_HITM# <7>
R19
H_PREQ#
ITP_TCK
ITP_TDI
VDD
THERMDA
D+
THERMDC
D- ALERT/THERM2
THERM
R20
+3VS
0_0402_5%
NS@
ITP_TMS
ITP_TRST#
ITP_DBRESET#
1/29 change to EMC1402 pn
EMC1402
H_IERR#
G6
E4
BPM[0]#
BPM[1]#
BPM[2]#
BPM[3]#
PRDY#
PREQ#
TCK
TDI
TDO
TMS
TRST#
DBR#
CRB
54.9_1%
54.9_1%
54.9_1%
54.9_1%
54.9_1%
R18
2
10K_0402_5%
EC_SMB_CK2 <17,32>
EC_SMB_DA2 <17,32>
GND
2
R706
1
10K_0402_5%
+3VS
ADT7421ARMZ-REEL_MSOP8
SMSC@
Address:100_1100
0_0402_5%
NS@
SCLK
SDATA
FAN1 Conn
ITP_DBRESET# <22>
H_PROCHOT# <48>
THERMAL
D21
A24
B25
PROCHOT#
THERMDA
THERMDC
C7
THERMTRIP#
H_PROCHOT#
THERMDA_R
THERMDC_R
1
R705
R19
R20
SMSC@ 100_0402_5%
SMSC@ 100_0402_5%
2
0_0402_5%
THERMDA
THERMDC
+5VS
C3
H_THERMTRIP# <8,21>
+5VS
10U_0805_10V4Z
2
A6
A5
C4
H_ADS# <7>
H_BNR# <7>
H_BPRI# <7>
D20
B3
ICH
<21> H_A20M#
<21> H_FERR#
<21> H_IGNNE#
H1
E2
G5
IERR#
INIT#
HIT#
HITM#
ADDR GROUP 1
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_A#32
H_A#33
H_A#34
H_A#35
ADS#
BNR#
BPRI#
CONTROL
H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
H_ADSTB#0
A[3]#
A[4]#
A[5]#
A[6]#
A[7]#
A[8]#
A[9]#
A[10]#
A[11]#
A[12]#
A[13]#
A[14]#
A[15]#
A[16]#
ADSTB[0]#
XDP/ITP SIGNALS
J4
L5
L4
K5
M3
N2
J1
N3
P5
P2
L2
P4
P1
R1
M1
ADDR GROUP 0
<7>
H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
Checklist
55_5%
55_5%
55_1%
55_5%
x
U2
CLK_CPU_BCLK <16>
CLK_CPU_BCLK# <16>
<32>
EN_FAN1
+VCC_FAN1
1 R815
2 EN_FAN1_R
330_0402_5%
A22
A21
BCLK[0]
BCLK[1]
1
2
3
4
C769
VEN
VIN
VO
VSET
GND
GND
GND
GND
D1
BAS16_SOT23-3
8
7
6
5
H CLK
G990P11U_SOP8
D2
1
BAS16_SOT23-3
Layout Note:
THERMDA&THERMDC Trace / Space = 10 / 10 mil
THERMDA_R&THERMDC_R Trace / Space = 10 / 10 mil
0.047U_0402_16V7K
C4
10U_0805_10V4Z
2
1
+3VS
C5
1000P_0402_50V7K
1
2
H_STPCLK#
H_INTR
H_NMI
H_SMI#
RESERVED
R21
10K_0402_5%
Merom Ball-out Rev 1a

CONN@
40mil
JP7
+VCC_FAN1
<32> FAN_SPEED1
C6
1000P_0402_50V7K
1
2
3
1
2
3
4
5
GND
GND
2
ACES_85205-03001
CONN@
Compal Secret Data
2007/08/18
Issued Date
Deciphered Date
2008/08/18
5
Title
Penryn (1/3)
Size
B
Date:
Document Number

Sheet
1
of
49
Rev
0.4
H_D#[0..63]
H_D#[0..63]
JCPU1C
<7>
+CPU_CORE
JCPU1B
<7> H_DSTBN#0
<7> H_DSTBP#0
<7> H_DINV#0
+1.05VS
R22
1K_0402_1%
<7> H_DSTBN#1
<7> H_DSTBP#1
<7> H_DINV#1
Trace Close CPU < 0.5'

2
R28
2K_0402_1%
2
2
C8
1
2
@
0.1U_0402_16V4Z
GTL_REF0
TEST1
1 @ 1K_0402_5%
TEST2
1 @ 1K_0402_5%
TEST3
@
T1
PAD
TEST4
TEST5
@
PAD
T2
TEST6
@
PAD
T3
AD26
C23
D25
C24
AF26
AF1
A26
GTLREF
TEST1
TEST2
TEST3
TEST4
TEST5
TEST6
B22
B23
C21
<16> CPU_BSEL0
<16> CPU_BSEL1
<16> CPU_BSEL2
BSEL[0]
BSEL[1]
BSEL[2]
D[32]#
D[33]#
D[34]#
D[35]#
D[36]#
D[37]#
D[38]#
D[39]#
D[40]#
D[41]#
D[42]#
D[43]#
D[44]#
D[45]#
D[46]#
D[47]#
DSTBN[2]#
DSTBP[2]#
DINV[2]#
Y22
AB24
V24
V26
V23
T22
U25
U23
Y25
W22
Y23
W24
W25
AA23
AA24
AB25
Y26
AA26
U22
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
D[48]#
D[49]#
D[50]#
D[51]#
D[52]#
D[53]#
D[54]#
D[55]#
D[56]#
D[57]#
D[58]#
D[59]#
D[60]#
D[61]#
D[62]#
D[63]#
DSTBN[3]#
DSTBP[3]#
DINV[3]#
AE24
AD24
AA21
AB22
AB21
AC26
AD20
AE22
AF23
AC25
AE21
AD21
AC22
AD23
AF22
AC23
AE25
AF24
AC20
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63
DATA GRP 2
D[16]#
D[17]#
D[18]#
D[19]#
D[20]#
D[21]#
D[22]#
D[23]#
D[24]#
D[25]#
D[26]#
D[27]#
D[28]#
D[29]#
D[30]#
D[31]#
DSTBN[1]#
DSTBP[1]#
DINV[1]#
COMP[0]
COMP[1]
COMP[2]
COMP[3]
R26
U26
AA1
Y1
DPRSTP#
DPSLP#
DPWR#
PWRGOOD
SLP#
PSI#
E5
B5
D24
D6
D7
AE6
MISC
H_DSTBN#2 <7>
H_DSTBP#2 <7>
H_DINV#2 <7>
H_DSTBN#3 <7>
H_DSTBP#3 <7>
H_DINV#3 <7>
COMP0
COMP1
COMP2
COMP3
R23
R25
R27
R29
1
1
1
1
27.4_0402_1%
54.9_0402_1%
27.4_0402_1%
54.9_0402_1%
2
2
2
2
H_DPRSTP# <8,21,48>
H_DPSLP# <21>
H_DPWR# <7>
H_PWRGOOD <21>
H_CPUSLP# <7>
H_PSI# <48>
H_PWRGOOD
H_CPUSLP#

CONN@
TRACE CLOSELY CPU < 0.5'

COMP0, COMP2 layout : Width 18mils and Space 25mils (27.4Ohms)
COMP1, COMP3 layout : Width 4mils and Space 25mils (55Ohms)
H_PSI#
layout note: Route TEST3 & TEST5 traces on ground referenced layer to the TPs
CPU_BSEL
CPU_BSEL2
CPU_BSEL1
CPU_BSEL0
166
200
266
C739
H_DPRSTP#
C762
1
1
2 @ 100P_0402_50V8J
2
A7
A9
A10
A12
A13
A15
A17
A18
A20
B7
B9
B10
B12
B14
B15
B17
B18
B20
C9
C10
C12
C13
C15
C17
C18
D9
D10
D12
D14
D15
D17
D18
E7
E9
E10
E12
E13
E15
E17
E18
E20
F7
F9
F10
F12
F14
F15
F17
F18
F20
AA7
AA9
AA10
AA12
AA13
AA15
AA17
AA18
AA20
AB9
AC10
AB10
AB12
AB14
AB15
AB17
AB18
VCC[001]
VCC[002]
VCC[003]
VCC[004]
VCC[005]
VCC[006]
VCC[007]
VCC[008]
VCC[009]
VCC[010]
VCC[011]
VCC[012]
VCC[013]
VCC[014]
VCC[015]
VCC[016]
VCC[017]
VCC[018]
VCC[019]
VCC[020]
VCC[021]
VCC[022]
VCC[023]
VCC[024]
VCC[025]
VCC[026]
VCC[027]
VCC[028]
VCC[029]
VCC[030]
VCC[031]
VCC[032]
VCC[033]
VCC[034]
VCC[035]
VCC[036]
VCC[037]
VCC[038]
VCC[039]
VCC[040]
VCC[041]
VCC[042]
VCC[043]
VCC[044]
VCC[045]
VCC[046]
VCC[047]
VCC[048]
VCC[049]
VCC[050]
VCC[051]
VCC[052]
VCC[053]
VCC[054]
VCC[055]
VCC[056]
VCC[057]
VCC[058]
VCC[059]
VCC[060]
VCC[061]
VCC[062]
VCC[063]
VCC[064]
VCC[065]
VCC[066]
VCC[067]
VCC[068]
VCC[069]
VCC[070]
VCC[071]
VCC[072]
VCC[073]
VCC[074]
VCC[075]
VCC[076]
VCC[077]
VCC[078]
VCC[079]
VCC[080]
VCC[081]
VCC[082]
VCC[083]
VCC[084]
VCC[085]
VCC[086]
VCC[087]
VCC[088]
VCC[089]
VCC[090]
VCC[091]
VCC[092]
VCC[093]
VCC[094]
VCC[095]
VCC[096]
VCC[097]
VCC[098]
VCC[099]
VCC[100]
AB20
AB7
AC7
AC9
AC12
AC13
AC15
AC17
AC18
AD7
AD9
AD10
AD12
AD14
AD15
AD17
AD18
AE9
AE10
AE12
AE13
AE15
AE17
AE18
AE20
AF9
AF10
AF12
AF14
AF15
AF17
AF18
AF20
VCCP[01]
VCCP[02]
VCCP[03]
VCCP[04]
VCCP[05]
VCCP[06]
VCCP[07]
VCCP[08]
VCCP[09]
VCCP[10]
VCCP[11]
VCCP[12]
VCCP[13]
VCCP[14]
VCCP[15]
VCCP[16]
G21
V6
J6
K6
M6
J21
K21
M21
N21
N6
R21
R6
T21
T6
V21
W21
VCCA[01]
VCCA[02]
B26
C26
VID[0]
VID[1]
VID[2]
VID[3]
VID[4]
VID[5]
VID[6]
AD6
AF5
AE5
AF4
AE3
AF3
AE2
VCCSENSE
AF7
VCCSENSE
VSSSENSE
AE7
VSSSENSE

CONN@
470P_0402_50V7K
+CPU_CORE
D
330u
ESR 9m ohm
Package(L*W*H)7.3*4.3*1.8
Rating 2.5V
C
+1.05VS
1
+ C7
330U_D2E_2.5VM_R9
20mils
+1.5VS
1
CPU_VID0
CPU_VID1
CPU_VID2
CPU_VID3
CPU_VID4
CPU_VID5
CPU_VID6
1
R30
C9
C10
10U_0805_10V4Z
2
0.01U_0402_16V7K
2
100_0402_1%
+CPU_CORE
VCCSENSE <48>
VSSSENSE <48>
R31
<48>
<48>
<48>
<48>
<48>
<48>
<48>
2
100_0402_1%
Place PU and PD within 1 inch of CPU (CRB recommend)

Route VCCSENSE and VSSSENSE traces at 27.4 Ohms with 50 mils spacing.
For 6 layer
Z=27.4 ohm
VCCSENSE, VSSSENSE/ 14mils (MS),
16mils (SL) width, 7mils space, 25mils
space to other signals Mismatch =25mils.
Place these 2 resisters closk to CPU pins within 500 mils

A
Compal Secret Data

2007/08/18
Issued Date
Deciphered Date
2008/08/18
5
Title
Penryn (2/3)
Size
B
Date:
Document Number
ai
nf
@
ho
tm
ai
l.c
om
Length matching within 25 mils (Compal Common Design)

Trace width/space/other is 20/7/25

he
x
Width=4 mil ,
Spacing: 15mil
(55Ohm)
R24
R26
N22
K25
P26
R23
L23
M24
L22
M23
P25
P23
P22
T24
R24
L25
T25
N25
L26
M26
N24
DATA GRP 1
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
D[0]#
D[1]#
D[2]#
D[3]#
D[4]#
D[5]#
D[6]#
D[7]#
D[8]#
D[9]#
D[10]#
D[11]#
D[12]#
D[13]#
D[14]#
D[15]#
DSTBN[0]#
DSTBP[0]#
DINV[0]#
DATA GRP 3
E22
F24
E26
G22
F23
G25
E25
E23
K24
G24
J24
J23
H22
F26
K22
H23
J26
H26
H25
DATA GRP 0
H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
Sheet
of
49
Rev
0.4
330u
ESR 9m ohm
Rating 2.5V
+CPU_CORE
JCPU1D
A4
A8
A11
A14
A16
A19
A23
AF2
B6
B8
B11
B13
B16
B19
B21
B24
C5
C8
C11
C14
C16
C19
C2
C22
C25
D1
D4
D8
D11
D13
D16
D19
D23
D26
E3
E6
E8
E11
E14
E16
E19
E21
E24
F5
F8
F11
F13
F16
F19
F2
F22
F25
G4
G1
G23
G26
H3
H6
H21
H24
J2
J5
J22
J25
K1
K4
K23
K26
L3
L6
L21
L24
M2
M5
M22
M25
N1
N4
N23
N26
P3
VSS[001]
VSS[002]
VSS[003]
VSS[004]
VSS[005]
VSS[006]
VSS[007]
VSS[008]
VSS[009]
VSS[010]
VSS[011]
VSS[012]
VSS[013]
VSS[014]
VSS[015]
VSS[016]
VSS[017]
VSS[018]
VSS[019]
VSS[020]
VSS[021]
VSS[022]
VSS[023]
VSS[024]
VSS[025]
VSS[026]
VSS[027]
VSS[028]
VSS[029]
VSS[030]
VSS[031]
VSS[032]
VSS[033]
VSS[034]
VSS[035]
VSS[036]
VSS[037]
VSS[038]
VSS[039]
VSS[040]
VSS[041]
VSS[042]
VSS[043]
VSS[044]
VSS[045]
VSS[046]
VSS[047]
VSS[048]
VSS[049]
VSS[050]
VSS[051]
VSS[052]
VSS[053]
VSS[054]
VSS[055]
VSS[056]
VSS[057]
VSS[058]
VSS[059]
VSS[060]
VSS[061]
VSS[062]
VSS[063]
VSS[064]
VSS[065]
VSS[066]
VSS[067]
VSS[068]
VSS[069]
VSS[070]
VSS[071]
VSS[072]
VSS[073]
VSS[074]
VSS[075]
VSS[076]
VSS[077]
VSS[078]
VSS[079]
VSS[080]
VSS[081]
VSS[082]
VSS[083]
VSS[084]
VSS[085]
VSS[086]
VSS[087]
VSS[088]
VSS[089]
VSS[090]
VSS[091]
VSS[092]
VSS[093]
VSS[094]
VSS[095]
VSS[096]
VSS[097]
VSS[098]
VSS[099]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]
VSS[159]
VSS[160]
VSS[161]
VSS[162]
VSS[163]

CONN@
+CPU_CORE
2 x 330uF(9mOhm/3)
P6
P21
P24
R2
R5
R22
R25
T1
T4
T23
T26
U3
U6
U21
U24
V2
V5
V22
V25
W1
W4
W23
W26
Y3
Y6
Y21
Y24
AA2
AA5
AA8
AA11
AA14
AA16
AA19
AA22
AA25
AB1
AB4
AB8
AB11
AB13
AB16
AB19
AB23
AB26
AC3
AC6
AC8
AC11
AC14
AC16
AC19
AC21
AC24
AD2
AD5
AD8
AD11
AD13
AD16
AD19
AD22
AD25
AE1
AE4
AE8
AE11
AE14
AE16
AE19
AE23
AE26
A2
AF6
AF8
AF11
AF13
AF16
AF19
AF21
A25
AF25
1
C11
2 x 330uF(9mOhm/3)
C12
C13
@
+
+
C14
C15
@
330U_D2E_2.5VM_R9
2
2
330U_D2E_2.5VM_R9
330U_D2E_2.5VM_R9
330U_D2E_2.5VM_R9
2
2
330U_D2E_2.5VM_R9
South Side Secondary
+ C16
@
330U_D2E_2.5VM_R9
2
North Side Secondary
+CPU_CORE
C17
C18
C19
C20
C21
C22
C23
C24
10U_0805_6.3V6M
10U_0805_6.3V6M
10U_0805_6.3V6M
10U_0805_6.3V6M
2
2
2
2
2
2
2
2
10U_0805_6.3V6M
10U_0805_6.3V6M
10U_0805_6.3V6M
10U_0805_6.3V6M
(Place these capacitors on South side,Secondary Layer)

+CPU_CORE
C25
C26
C27
C28
C29
C30
C31
C32
10U_0805_6.3V6M
10U_0805_6.3V6M
10U_0805_6.3V6M
10U_0805_6.3V6M
2
2
2
2
2
2
2
2
10U_0805_6.3V6M
10U_0805_6.3V6M
10U_0805_6.3V6M
10U_0805_6.3V6M
(Place these capacitors on North side,Secondary Layer)

+CPU_CORE
1
1
1
1
1
1
1
C34
C35
C36
C37
C38
C39
C40
@
@
10U_0805_6.3V6M
10U_0805_6.3V6M
10U_0805_6.3V6M
10U_0805_6.3V6M
2
2
2
2
2
2
2
2
10U_0805_6.3V6M
10U_0805_6.3V6M
10U_0805_6.3V6M
10U_0805_6.3V6M
C33
(Place these capacitors on South side,Primary Layer)

+CPU_CORE
C41
C42
C43
@
C44
C45
C46
C47
@
C48
10U_0805_6.3V6M
10U_0805_6.3V6M
10U_0805_6.3V6M
10U_0805_6.3V6M
2
2
2
2
2
2
2
2
10U_0805_6.3V6M
10U_0805_6.3V6M
10U_0805_6.3V6M
10U_0805_6.3V6M
B
(Place these capacitors on North side,Primary Layer)
+CPU-CORE
Decoupling
SPCAP,Polymer
MLCC 0805 X5R
C,uF
ESR, mohm
ESL,nH
1.8nH/6
6X330uF
9m ohm/6
32X22uF
3m ohm/32
0.6nH/32
32X10uF
3m ohm/32
0.6nH/32
+1.05VS
C49
C50
C51
C52
C53
C54
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
2
2
2
2
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
A
(Place these capacitors inside socket cavity in 2 row on North side Secondary)
Compal Secret Data
2007/08/18
Issued Date
Deciphered Date
2008/8/18
5
Title
Penryn (3/3)
Size
B
Date:
Document Number

Sheet
1
of
49
Rev
0.4
Change U3 from SA00001P900 to SA00001P930

3/4 Change U3 from SA00001P930 to SA00002JT10 (B0 to B2)
H_D#0
H_D#1
H_D#2
H_D#3
H_D#4
H_D#5
H_D#6
H_D#7
H_D#8
H_D#9
H_D#10
H_D#11
H_D#12
H_D#13
H_D#14
H_D#15
H_D#16
H_D#17
H_D#18
H_D#19
H_D#20
H_D#21
H_D#22
H_D#23
H_D#24
H_D#25
H_D#26
H_D#27
H_D#28
H_D#29
H_D#30
H_D#31
H_D#32
H_D#33
H_D#34
H_D#35
H_D#36
H_D#37
H_D#38
H_D#39
H_D#40
H_D#41
H_D#42
H_D#43
H_D#44
H_D#45
H_D#46
H_D#47
H_D#48
H_D#49
H_D#50
H_D#51
H_D#52
H_D#53
H_D#54
H_D#55
H_D#56
H_D#57
H_D#58
H_D#59
H_D#60
H_D#61
H_D#62
H_D#63
+1.05VS
R32
221_0402_1%
H_SWING
width=10mil
1
R33
C55
0.1U_0402_16V4Z
100_0402_1%
Near C5 pin
H_RCOMP
R34
width / space =10mil / 20mil
24.9_0402_1%
F2
G8
F8
E6
G2
H6
H2
F6
D4
H3
M9
M11
J1
J2
N12
J6
P2
L2
R2
N9
L6
M5
J3
N2
R1
N5
N6
P13
N8
L7
N10
M3
Y3
AD14
Y6
Y10
Y12
Y14
Y7
W2
AA8
Y9
AA13
AA9
AA11
AD11
AD10
AD13
AE12
AE9
AA2
AD8
AA3
AD3
AD7
AE14
AF3
AC1
AE3
AC3
AE11
AE8
AG2
AD6
H_SWING
H_RCOMP
+1.05VS
C5
E3
H_D#_0
H_D#_1
H_D#_2
H_D#_3
H_D#_4
H_D#_5
H_D#_6
H_D#_7
H_D#_8
H_D#_9
H_D#_10
H_D#_11
H_D#_12
H_D#_13
H_D#_14
H_D#_15
H_D#_16
H_D#_17
H_D#_18
H_D#_19
H_D#_20
H_D#_21
H_D#_22
H_D#_23
H_D#_24
H_D#_25
H_D#_26
H_D#_27
H_D#_28
H_D#_29
H_D#_30
H_D#_31
H_D#_32
H_D#_33
H_D#_34
H_D#_35
H_D#_36
H_D#_37
H_D#_38
H_D#_39
H_D#_40
H_D#_41
H_D#_42
H_D#_43
H_D#_44
H_D#_45
H_D#_46
H_D#_47
H_D#_48
H_D#_49
H_D#_50
H_D#_51
H_D#_52
H_D#_53
H_D#_54
H_D#_55
H_D#_56
H_D#_57
H_D#_58
H_D#_59
H_D#_60
H_D#_61
H_D#_62
H_D#_63
H_SWING
H_RCOMP
Layout Note:
H_RCOMP / H_VREF / H_SWING
trace width and spacing is 10/20
R35
<4> H_RESET#
<5> H_CPUSLP#
H_RESET#
H_CPUSLP#
C12
E11
H_VREF
A11
B11
1K_0402_1%
R36
C56
width:spacing=10mil:20mil
@
0.1U_0402_16V4Z
(<0.5")
H_CPURST#
H_CPUSLP#
H_A#_3
H_A#_4
H_A#_5
H_A#_6
H_A#_7
H_A#_8
H_A#_9
H_A#_10
H_A#_11
H_A#_12
H_A#_13
H_A#_14
H_A#_15
H_A#_16
H_A#_17
H_A#_18
H_A#_19
H_A#_20
H_A#_21
H_A#_22
H_A#_23
H_A#_24
H_A#_25
H_A#_26
H_A#_27
H_A#_28
H_A#_29
H_A#_30
H_A#_31
H_A#_32
H_A#_33
H_A#_34
H_A#_35
A14
C15
F16
H13
C18
M16
J13
P16
R16
N17
M13
E17
P17
F17
G20
B19
J16
E20
H16
J20
L17
A17
B17
L16
C21
J17
H20
B18
K17
B20
F21
K21
L20
H_A#3
H_A#4
H_A#5
H_A#6
H_A#7
H_A#8
H_A#9
H_A#10
H_A#11
H_A#12
H_A#13
H_A#14
H_A#15
H_A#16
H_A#17
H_A#18
H_A#19
H_A#20
H_A#21
H_A#22
H_A#23
H_A#24
H_A#25
H_A#26
H_A#27
H_A#28
H_A#29
H_A#30
H_A#31
H_A#32
H_A#33
H_A#34
H_A#35
H_ADS#
H_ADSTB#_0
H_ADSTB#_1
H_BNR#
H_BPRI#
H_BREQ#
H_DEFER#
H_DBSY#
HPLL_CLK
HPLL_CLK#
H_DPWR#
H_DRDY#
H_HIT#
H_HITM#
H_LOCK#
H_TRDY#
H12
B16
G17
A9
F11
G12
E9
B10
AH7
AH6
J11
F9
H9
E12
H11
C9
H_ADS#
H_ADSTB#0
H_ADSTB#1
H_BNR#
H_BPRI#
H_BR0#
H_DEFER#
H_DBSY#
CLK_MCH_BCLK
CLK_MCH_BCLK#
H_DPWR#
H_DRDY#
H_HIT#
H_HITM#
H_LOCK#
H_TRDY#
H_DINV#_0
H_DINV#_1
H_DINV#_2
H_DINV#_3
J8
L3
Y13
Y1
H_DINV#0
H_DINV#1
H_DINV#2
H_DINV#3
H_DSTBN#_0
H_DSTBN#_1
H_DSTBN#_2
H_DSTBN#_3
L10
M7
AA5
AE6
H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3
H_DSTBP#_0
H_DSTBP#_1
H_DSTBP#_2
H_DSTBP#_3
L9
M8
AA6
AE5
H_DSTBP#0
H_DSTBP#1
H_DSTBP#2
H_DSTBP#3
H_REQ#_0
H_REQ#_1
H_REQ#_2
H_REQ#_3
H_REQ#_4
B15
K13
F13
B13
B14
H_REQ#0
H_REQ#1
H_REQ#2
H_REQ#3
H_REQ#4
H_RS#_0
H_RS#_1
H_RS#_2
B6
F12
C8
H_RS#0
H_RS#1
H_RS#2
H_AVREF
H_DVREF
<4>
U3
965PM
PM@
3/4 Change U3 PM@ from SA00001ZO30

to SA00002JJ00 (B0 to B2)
H_ADS# <4>
H_ADSTB#0 <4>
H_ADSTB#1 <4>
H_BNR# <4>
H_BPRI# <4>
H_BR0# <4>
H_DEFER# <4>
H_DBSY# <4>
CLK_MCH_BCLK <16>
CLK_MCH_BCLK# <16>
H_DPWR# <5>
H_DRDY# <4>
H_HIT# <4>
H_HITM# <4>
H_LOCK# <4>
H_TRDY# <4>
H_DINV#0
H_DINV#1
H_DINV#2
H_DINV#3
H_DSTBN#0
H_DSTBN#1
H_DSTBN#2
H_DSTBN#3
<5>
<5>
<5>
<5>
<5>
<5>
<5>
<5>
H_DSTBP#0 <5>
H_DSTBP#1 <5>
H_DSTBP#2 <5>
H_DSTBP#3 <5>
H_REQ#[0..4]
H_RS#[0..2]
<4>
<4>
CANTIGA ES_FCBGA1329
GM@
2K_0402_1%
H_A#[3..35]
U3A
H_D#[0..63]
HOST
<5>
Compal Secret Data

Deciphered Date
2008/8/18
5
Title
Cantiga (1/7)-GTL
Size
B
Date:
Document Number
Rev
0.4
ai
2007/08/18
Issued Date

he
x
nf
@
ho
tm
ai
l.c
om
Sheet
of
49
SM_RCOMP_VOH
R43
3.01K_0402_1%
C57
C59
2.2U_0603_6.3V6K
0.01U_0402_16V7K
C60
C58
2.2U_0603_6.3V6K
0.01U_0402_16V7K
AY21
RSVD20
BG23
BF23
BH18
BF18
RSVD22
RSVD23
RSVD24
RSVD25
<16> MCH_CLKSEL0
<16> MCH_CLKSEL1
<16> MCH_CLKSEL2
MCH_CLKSEL0
MCH_CLKSEL1
MCH_CLKSEL2
MCH_CFG_5
MCH_CFG_6
MCH_CFG_7
Use VGATE for GMCH_PWROK

VGATE
1
R52 @
ICH_PWROK 1
R53
<16,22,48> VGATE
<22,32> ICH_PWROK
GMCH_PWROK
2
0_0402_5%
2
0_0402_5%
MCH_CFG_12
MCH_CFG_13
MCH_CFG_16
MCH_CFG_19
MCH_CFG_20
CFG_0
CFG_1
CFG_2
CFG_3
CFG_4
CFG_5
CFG_6
CFG_7
CFG_8
CFG_9
CFG_10
CFG_11
CFG_12
CFG_13
CFG_14
CFG_15
CFG_16
CFG_17
CFG_18
CFG_19
CFG_20
CFG
MCH_CFG_9
MCH_CFG_10
T25
R25
P25
P20
P24
C25
N24
M24
E21
C23
C24
N21
P21
T21
R20
M20
L21
H21
P29
R28
T28
R57
R58
PM_BMBUSY#
H_DPRSTP#
PM_EXTTS#0
PM_EXTTS#1
R61
R63
R64
2 0_0402_5%
2 0_0402_5%
1
1
100_0402_5%
2 0_0402_5%
2 0_0402_5%
PM_BMBUSY#_R R29
PM_DPRSTP#_R
B7
PM_EXTTS#0
N33
PM_EXTTS#1
P32
GMCH_PWROK AT40
MCH_RSTIN#
AT11
THERMTRIP#_R
T20
DPRSLPVR_R
R32
PM_SYNC#
PM_DPRSTP#
PM_EXT_TS#_0
PM_EXT_TS#_1
PWROK
RSTIN#
THERMTRIP#
DPRSLPVR
DDRA_CLK0
DDRA_CLK1
DDRB_CLK0
DDRB_CLK1
SA_CK#_0
SA_CK#_1
SB_CK#_0
SB_CK#_1
AR24
AR21
AU24
AV20
DDRA_CLK0#
DDRA_CLK1#
DDRB_CLK0#
DDRB_CLK1#
SA_CKE_0
SA_CKE_1
SB_CKE_0
SB_CKE_1
BC28
AY28
AY36
BB36
DDRA_CKE0
DDRA_CKE1
DDRB_CKE0
DDRB_CKE1
SA_CS#_0
SA_CS#_1
SB_CS#_0
SB_CS#_1
BA17
AY16
AV16
AR13
DDRA_SCS0#
DDRA_SCS1#
DDRB_SCS0#
DDRB_SCS1#
SA_ODT_0
SA_ODT_1
SB_ODT_O
SB_ODT_1
BD17
AY17
BF15
AY13
DDRA_ODT0
DDRA_ODT1
DDRB_ODT0
DDRB_ODT1
SM_RCOMP
SM_RCOMP#
BG22
BH21
SMRCOMP
SMRCOMP#
SM_RCOMP_VOH
SM_RCOMP_VOL
BF28
BH28
SM_RCOMP_VOH
SM_RCOMP_VOL
SM_VREF
SM_PWROK
SM_REXT
SM_DRAMRST#
AV42
AR36
BF17
BC36
SM_PWROK
SM_REXT
DPLL_REF_CLK
DPLL_REF_CLK#
DPLL_REF_SSCLK
DPLL_REF_SSCLK#
B38
A38
E41
F41
CLK_DREF_96M
CLK_DREF_96M#
CLK_DREF_SSC
CLK_DREF_SSC#
PEG_CLK
PEG_CLK#
F43
E43
CLK_MCH_3GPLL
CLK_MCH_3GPLL#
<14>
<14>
<15>
<15>
CLK_DREF_96M#
CLK_DREF_96M
<14>
<14>
<15>
<15>
CLK_DREF_SSC
<14>
<14>
<15>
<15>
<14>
<14>
<15>
<15>
For Cantiga
DMI_RXN_0
DMI_RXN_1
DMI_RXN_2
DMI_RXN_3
AE41
AE37
AE47
AH39
DMI_RXP_0
DMI_RXP_1
DMI_RXP_2
DMI_RXP_3
AE40
AE38
AE48
AH40
DMI_ITX_MRX_P0
DMI_ITX_MRX_P1
DMI_ITX_MRX_P2
DMI_ITX_MRX_P3
DMI_TXN_0
DMI_TXN_1
DMI_TXN_2
DMI_TXN_3
AE35
AE43
AE46
AH42
DMI_MTX_IRX_N0
DMI_MTX_IRX_N1
DMI_MTX_IRX_N2
DMI_MTX_IRX_N3
DMI_TXP_0
DMI_TXP_1
DMI_TXP_2
DMI_TXP_3
AD35
AE44
AF46
AH43
DMI_MTX_IRX_P0
DMI_MTX_IRX_P1
DMI_MTX_IRX_P2
DMI_MTX_IRX_P3
GFX_VID_0
GFX_VID_1
GFX_VID_2
GFX_VID_3
GFX_VID_4
B33
B32
G33
F33
E33
GFX_VR_EN
C34
2
1
MCH_TSATN#_EC <32>
C
2 2
B
330_0402_5%
MCH_TSATN#
R81
2
B
E
R76
54.9_0402_1%
Q1
MMBT3904_SOT23-3
@
Q2
MMBT3904_SOT23-3
@
H_DPRSTP#
80.6_0402_1%
80.6_0402_1%
SM_VREF
2 10K_0402_1%
2 499_0402_1%
CFG5
R49
1
C61
CLK_DREF_96M <16>
CLK_DREF_96M# <16>
CLK_DREF_SSC <16>
CLK_DREF_SSC# <16>
+1.8V
CFG6
1K_0402_1%
R51
CFG7
1K_0402_1%
Layout Note:
SM_VREF trace
width and spacing
is 20/20.
CLK_MCH_3GPLL <16>
CLK_MCH_3GPLL# <16>
CFG9
CFG10
SM_PWROK: Pull L for DDR2

Driven by platform for DDR3
DMI_ITX_MRX_N0
DMI_ITX_MRX_N1
DMI_ITX_MRX_N2
DMI_ITX_MRX_N3
<22>
<22>
<22>
<22>
DMI_ITX_MRX_P0
DMI_ITX_MRX_P1
DMI_ITX_MRX_P2
DMI_ITX_MRX_P3
<22>
<22>
<22>
<22>
DMI_MTX_IRX_N0
DMI_MTX_IRX_N1
DMI_MTX_IRX_N2
DMI_MTX_IRX_N3
<22>
<22>
<22>
<22>
DMI_MTX_IRX_P0
DMI_MTX_IRX_P1
DMI_MTX_IRX_P2
DMI_MTX_IRX_P3
<22>
<22>
<22>
<22>
011 = 667MT/s FSB 000 = 1066MT/s FSB

010 = 800MT/s FSB
0 = DMI x 2
1 = DMI x 4 * (Default)
0 = The ITPM Host Interface is enabled
1 = The ITPM Host Interface is disabled *
0 = AMT Firmware will use TLS
cipher suite with no confidentiality
1 = AMT Firmware will use TLS
cipher suite with confidentiality
0 = Lane Reversal Enable
1 = Normal Operation * (Default)
0 = PCIE Loopback Enable
(Default)
1 = Disable *
00 = Reserved
01 = XOR Mode Enabled
10 = All Z Mode Enabled
11 = Normal Operation * (Default)
0 = Dynamic ODT Disabled
1 = Dynamic ODT Enabled * (Default)
CFG[2:0]
CFG[13:12]
CFG16
(Default)
CFG19
CFG20
(PCIE/SDVO select)
SDVO_CTRLDATA
0 = Normal Operation
*(Default)
1 = DMI Lane Reversal Enable
0 = Only PCIE or SDVO is operational.
(Default)
1 = PCIE/SDVO are operating simu.
0 = No SDVO Device Present * (Default)
MCH_CFG_12
R56
MCH_CFG_13
R59
MCH_CFG_16
R60
MCH_CFG_10
R62
MCH_CFG_6
DDPC_CTRLCLK
DDPC_CTRLDATA
SDVO_CTRLCLK
SDVO_CTRLDATA
CLKREQ#
ICH_SYNC#
N28
M28
G36
E36
K36
H36
HDMICLK_NB
HDMIDAT_NB
MCH_CLKREQ#
TSATN#
B12
MCH_TSATN#
CL_VREF
MCH_CFG_7
1K_0402_1%
CL_RST#0 <22>
R67
Add follow CRB

Change R from 4.02K to 2.21K following CRB
ICH_PWROK
R65
R66
CL_CLK0 <22>
CL_DATA0 <22>
2
@ 2.21K_0402_1%
2
@ 2.21K_0402_1%
2
@ 2.21K_0402_1%
2
@ 2.21K_0402_1%
2
@ 2.21K_0402_1%
2
@ 2.21K_0402_1%
2
@ 2.21K_0402_1%
2
@ 2.21K_0402_1%
R55
+1.05VS
1 = SDVO Device Present
R54
10/22 intel recommend 2.21K

iTPM spec use 10K
ME
Strap Pin Table
CFG[19:18] have internal pull down

+1.8V
MCH_CFG_9
AH37
AH36
AN36
AJ35
AH34
0_0402_5%
MCH_CFG_5
CL_CLK
CL_DATA
CL_PWROK
CL_RST#
CL_VREF
0_0402_5%
R68
511_0402_1%
MCH_CFG_19
C62
HDMICLK_NB <25>
0.1U_0402_16V4Z
HDMIDAT_NB <25>
2
MCH_CLKREQ# <16>
MCH_ICH_SYNC# <22>
R69
@ 4.02K_0402_1%
R70
@ 4.02K_0402_1%
R73
10K_0402_5%
R74
10K_0402_5%
+3VS
MCH_CFG_20
PM_EXTTS#0
+3VS
PM_EXTTS#1
GM@
PM_DPRSLPVR_D
MISC
R71
R72
1K_0402_5% 1K_0402_5%
@
+1.05VS
HDA
+3VS
NC_1
NC_2
NC_3
NC_4
NC_5
NC_6
NC_7
NC_8
NC_9
NC_10
NC_11
NC_12
NC_13
NC_14
NC_15
NC_16
NC_17
NC_18
NC_19
NC_20
NC_21
NC_22
NC_23
NC_24
NC_25
NC_26
NC
+3VS
BG48
BF48
BD48
BC48
BH47
BG47
BE47
BH46
BF46
BG45
BH44
BH43
BH6
BH5
BG4
BH3
BF3
BH2
BG2
BE2
BG1
BF1
BD1
BC1
F1
A47
0_0402_5%
CFG[17:3] have internal pull up
0.1U_0402_16V4Z
DMI_ITX_MRX_N0
DMI_ITX_MRX_N1
DMI_ITX_MRX_N2
DMI_ITX_MRX_N3
0_0402_5%
80 Ohm
<14>
<14>
<15>
<15>
20mil
1
1
2
PM@
2
PM@
2
PM@
2
PM@
SM_DRAMRST# would be
needed for DDR3 only
R45
R46
R48
R50
1
R37
1
R40
1
R41
1
R42
CLK_DREF_SSC#
<17,20,26,28,30,40> PLT_RST_BUF#
<4,21> H_THERMTRIP#
<22,48> PM_DPRSLPVR_D
1
1
PM
<22>
<5,21,48>
<14>
<15>
GRAPHICS VID
DMI
CLK
R39
1K_0402_1%
RSVD15
RSVD16
RSVD17
RSVD
SM_RCOMP_VOL
B31
B2
M1
AP24
AT21
AV24
AU20
SA_CK_0
SA_CK_1
SB_CK_0
SB_CK_1
R38
1K_0402_1%
DDR CLK/ CONTROL/
+1.8V
RSVD1
RSVD2
RSVD3
RSVD4
RSVD5
RSVD6
RSVD7
RSVD8
RSVD9
RSVD10
RSVD11
RSVD12
RSVD13
RSVD14
COMPENSATION
U3B
M36
N36
R33
T33
AH9
AH10
AH12
AH13
K12
AL34
AK34
AN35
AM35
T24
1
C760
1
C761
2
470P_0402_50V7K
2
470P_0402_50V7K
HDA_BCLK
HDA_RST#
HDA_SDI
HDA_SDO
HDA_SYNC
B28
B30
B29
C29
A28
GMCH_HDA_BITCLK
GMCH_HDA_RST#
MCH_HDA_SDIN
GMCH_HDA_SDOUT
GMCH_HDA_SYNC
R78
1 GM@
2 33_0402_5%
GMCH_HDA_BITCLK <10>
GMCH_HDA_RST# <10>
GMCH_HDA_SDIN2 <10>
GMCH_HDA_SDOUT <10>
GMCH_HDA_SYNC <10>
HDMICLK_NB
R80
HDMIDAT_NB
R83
2
@ 0_0402_5%
2
@ 0_0402_5%
When ICH9M VCCHDA and VCCSUSHDA tie to 3V, don't stuff these resisters (follow CRB)
2007/08/18
Issued Date
Compal Secret Data
2008/8/18
Deciphered Date
3
Title
Cantiga (2/7)-DMI/DDR
Size Document Number
Custom
Rev
0.4
Date:
Sheet

1
of
49
DDRA_SDQ[0..63]
<15> DDRB_SDM[0..7]
DDRA_SMA[0..14]
<15> DDRB_SMA[0..14]
DDRB_SDQ[0..63]
DDRB_SDM[0..7]
DDRB_SMA[0..14]
GM@
U3E
SA_BS_0
SA_BS_1
SA_BS_2
BD21
BG18
AT25
DDRA_SBS0 <14>
DDRA_SBS1 <14>
DDRA_SBS2 <14>
SA_RAS#
SA_CAS#
SA_WE#
BB20
BD20
AY20
DDRA_SRAS# <14>
DDRA_SCAS# <14>
DDRA_SWE# <14>
SA_DM_0
SA_DM_1
SA_DM_2
SA_DM_3
SA_DM_4
SA_DM_5
SA_DM_6
SA_DM_7
AM37
AT41
AY41
AU39
BB12
AY6
AT7
AJ5
DDRA_SDM0
DDRA_SDM1
DDRA_SDM2
DDRA_SDM3
DDRA_SDM4
DDRA_SDM5
DDRA_SDM6
DDRA_SDM7
SA_DQS_0
SA_DQS_1
SA_DQS_2
SA_DQS_3
SA_DQS_4
SA_DQS_5
SA_DQS_6
SA_DQS_7
AJ44
AT44
BA43
BC37
AW12
BC8
AU8
AM7
DDRA_SDQS0
DDRA_SDQS1
DDRA_SDQS2
DDRA_SDQS3
DDRA_SDQS4
DDRA_SDQS5
DDRA_SDQS6
DDRA_SDQS7
SA_DQS#_0
SA_DQS#_1
SA_DQS#_2
SA_DQS#_3
SA_DQS#_4
SA_DQS#_5
SA_DQS#_6
SA_DQS#_7
AJ43
AT43
BA44
BD37
AY12
BD8
AU9
AM8
DDRA_SDQS0#
DDRA_SDQS1#
DDRA_SDQS2#
DDRA_SDQS3#
DDRA_SDQS4#
DDRA_SDQS5#
DDRA_SDQS6#
DDRA_SDQS7#
SA_MA_0
SA_MA_1
SA_MA_2
SA_MA_3
SA_MA_4
SA_MA_5
SA_MA_6
SA_MA_7
SA_MA_8
SA_MA_9
SA_MA_10
SA_MA_11
SA_MA_12
SA_MA_13
SA_MA_14
BA21
BC24
BG24
BH24
BG25
BA24
BD24
BG27
BF25
AW24
BC21
BG26
BH26
BH17
AY25
DDRA_SMA0
DDRA_SMA1
DDRA_SMA2
DDRA_SMA3
DDRA_SMA4
DDRA_SMA5
DDRA_SMA6
DDRA_SMA7
DDRA_SMA8
DDRA_SMA9
DDRA_SMA10
DDRA_SMA11
DDRA_SMA12
DDRA_SMA13
DDRA_SMA14
DDRB_SDQ0
DDRB_SDQ1
DDRB_SDQ2
DDRB_SDQ3
DDRB_SDQ4
DDRB_SDQ5
DDRB_SDQ6
DDRB_SDQ7
DDRB_SDQ8
DDRB_SDQ9
DDRB_SDQ10
DDRB_SDQ11
DDRB_SDQ12
DDRB_SDQ13
DDRB_SDQ14
DDRB_SDQ15
DDRB_SDQ16
DDRB_SDQ17
DDRB_SDQ18
DDRB_SDQ19
DDRB_SDQ20
DDRB_SDQ21
DDRB_SDQ22
DDRB_SDQ23
DDRB_SDQ24
DDRB_SDQ25
DDRB_SDQ26
DDRB_SDQ27
DDRB_SDQ28
DDRB_SDQ29
DDRB_SDQ30
DDRB_SDQ31
DDRB_SDQ32
DDRB_SDQ33
DDRB_SDQ34
DDRB_SDQ35
DDRB_SDQ36
DDRB_SDQ37
DDRB_SDQ38
DDRB_SDQ39
DDRB_SDQ40
DDRB_SDQ41
DDRB_SDQ42
DDRB_SDQ43
DDRB_SDQ44
DDRB_SDQ45
DDRB_SDQ46
DDRB_SDQ47
DDRB_SDQ48
DDRB_SDQ49
DDRB_SDQ50
DDRB_SDQ51
DDRB_SDQ52
DDRB_SDQ53
DDRB_SDQ54
DDRB_SDQ55
DDRB_SDQ56
DDRB_SDQ57
DDRB_SDQ58
DDRB_SDQ59
DDRB_SDQ60
DDRB_SDQ61
DDRB_SDQ62
DDRB_SDQ63
A
MEMORY
SYSTEM
SA_DQ_0
SA_DQ_1
SA_DQ_2
SA_DQ_3
SA_DQ_4
SA_DQ_5
SA_DQ_6
SA_DQ_7
SA_DQ_8
SA_DQ_9
SA_DQ_10
SA_DQ_11
SA_DQ_12
SA_DQ_13
SA_DQ_14
SA_DQ_15
SA_DQ_16
SA_DQ_17
SA_DQ_18
SA_DQ_19
SA_DQ_20
SA_DQ_21
SA_DQ_22
SA_DQ_23
SA_DQ_24
SA_DQ_25
SA_DQ_26
SA_DQ_27
SA_DQ_28
SA_DQ_29
SA_DQ_30
SA_DQ_31
SA_DQ_32
SA_DQ_33
SA_DQ_34
SA_DQ_35
SA_DQ_36
SA_DQ_37
SA_DQ_38
SA_DQ_39
SA_DQ_40
SA_DQ_41
SA_DQ_42
SA_DQ_43
SA_DQ_44
SA_DQ_45
SA_DQ_46
SA_DQ_47
SA_DQ_48
SA_DQ_49
SA_DQ_50
SA_DQ_51
SA_DQ_52
SA_DQ_53
SA_DQ_54
SA_DQ_55
SA_DQ_56
SA_DQ_57
SA_DQ_58
SA_DQ_59
SA_DQ_60
SA_DQ_61
SA_DQ_62
SA_DQ_63
DDR
AJ38
AJ41
AN38
AM38
AJ36
AJ40
AM44
AM42
AN43
AN44
AU40
AT38
AN41
AN39
AU44
AU42
AV39
AY44
BA40
BD43
AV41
AY43
BB41
BC40
AY37
BD38
AV37
AT36
AY38
BB38
AV36
AW36
BD13
AU11
BC11
BA12
AU13
AV13
BD12
BC12
BB9
BA9
AU10
AV9
BA11
BD9
AY8
BA6
AV5
AV7
AT9
AN8
AU5
AU6
AT5
AN10
AM11
AM5
AJ9
AJ8
AN12
AM13
AJ11
AJ12
DDRA_SDQS0
DDRA_SDQS1
DDRA_SDQS2
DDRA_SDQS3
DDRA_SDQS4
DDRA_SDQS5
DDRA_SDQS6
DDRA_SDQS7
DDRA_SDQS0#
DDRA_SDQS1#
DDRA_SDQS2#
DDRA_SDQS3#
DDRA_SDQS4#
DDRA_SDQS5#
DDRA_SDQS6#
DDRA_SDQS7#
<14>
<14>
<14>
<14>
<14>
<14>
<14>
<14>
<14>
<14>
<14>
<14>
<14>
<14>
<14>
<14>
AK47
AH46
AP47
AP46
AJ46
AJ48
AM48
AP48
AU47
AU46
BA48
AY48
AT47
AR47
BA47
BC47
BC46
BC44
BG43
BF43
BE45
BC41
BF40
BF41
BG38
BF38
BH35
BG35
BH40
BG39
BG34
BH34
BH14
BG12
BH11
BG8
BH12
BF11
BF8
BG7
BC5
BC6
AY3
AY1
BF6
BF5
BA1
BD3
AV2
AU3
AR3
AN2
AY2
AV1
AP3
AR1
AL1
AL2
AJ1
AH1
AM2
AM3
AH3
AJ3
SB_DQ_0
SB_DQ_1
SB_DQ_2
SB_DQ_3
SB_DQ_4
SB_DQ_5
SB_DQ_6
SB_DQ_7
SB_DQ_8
SB_DQ_9
SB_DQ_10
SB_DQ_11
SB_DQ_12
SB_DQ_13
SB_DQ_14
SB_DQ_15
SB_DQ_16
SB_DQ_17
SB_DQ_18
SB_DQ_19
SB_DQ_20
SB_DQ_21
SB_DQ_22
SB_DQ_23
SB_DQ_24
SB_DQ_25
SB_DQ_26
SB_DQ_27
SB_DQ_28
SB_DQ_29
SB_DQ_30
SB_DQ_31
SB_DQ_32
SB_DQ_33
SB_DQ_34
SB_DQ_35
SB_DQ_36
SB_DQ_37
SB_DQ_38
SB_DQ_39
SB_DQ_40
SB_DQ_41
SB_DQ_42
SB_DQ_43
SB_DQ_44
SB_DQ_45
SB_DQ_46
SB_DQ_47
SB_DQ_48
SB_DQ_49
SB_DQ_50
SB_DQ_51
SB_DQ_52
SB_DQ_53
SB_DQ_54
SB_DQ_55
SB_DQ_56
SB_DQ_57
SB_DQ_58
SB_DQ_59
SB_DQ_60
SB_DQ_61
SB_DQ_62
SB_DQ_63
GM@
SB_BS_0
SB_BS_1
SB_BS_2
BC16
BB17
BB33
DDRB_SBS0 <15>
DDRB_SBS1 <15>
DDRB_SBS2 <15>
SB_RAS#
SB_CAS#
SB_WE#
AU17
BG16
BF14
DDRB_SRAS# <15>
DDRB_SCAS# <15>
DDRB_SWE# <15>
SB_DM_0
SB_DM_1
SB_DM_2
SB_DM_3
SB_DM_4
SB_DM_5
SB_DM_6
SB_DM_7
AM47
AY47
BD40
BF35
BG11
BA3
AP1
AK2
DDRB_SDM0
DDRB_SDM1
DDRB_SDM2
DDRB_SDM3
DDRB_SDM4
DDRB_SDM5
DDRB_SDM6
DDRB_SDM7
SB_DQS_0
SB_DQS_1
SB_DQS_2
SB_DQS_3
SB_DQS_4
SB_DQS_5
SB_DQS_6
SB_DQS_7
AL47
AV48
BG41
BG37
BH9
BB2
AU1
AN6
DDRB_SDQS0
DDRB_SDQS1
DDRB_SDQS2
DDRB_SDQS3
DDRB_SDQS4
DDRB_SDQS5
DDRB_SDQS6
DDRB_SDQS7
SB_DQS#_0
SB_DQS#_1
SB_DQS#_2
SB_DQS#_3
SB_DQS#_4
SB_DQS#_5
SB_DQS#_6
SB_DQS#_7
AL46
AV47
BH41
BH37
BG9
BC2
AT2
AN5
DDRB_SDQS0#
DDRB_SDQS1#
DDRB_SDQS2#
DDRB_SDQS3#
DDRB_SDQS4#
DDRB_SDQS5#
DDRB_SDQS6#
DDRB_SDQS7#
SB_MA_0
SB_MA_1
SB_MA_2
SB_MA_3
SB_MA_4
SB_MA_5
SB_MA_6
SB_MA_7
SB_MA_8
SB_MA_9
SB_MA_10
SB_MA_11
SB_MA_12
SB_MA_13
SB_MA_14
AV17
BA25
BC25
AU25
AW25
BB28
AU28
AW28
AT33
BD33
BB16
AW33
AY33
BH15
AU33
DDRB_SMA0
DDRB_SMA1
DDRB_SMA2
DDRB_SMA3
DDRB_SMA4
DDRB_SMA5
DDRB_SMA6
DDRB_SMA7
DDRB_SMA8
DDRB_SMA9
DDRB_SMA10
DDRB_SMA11
DDRB_SMA12
DDRB_SMA13
DDRB_SMA14
U3D
DDRA_SDQ0
DDRA_SDQ1
DDRA_SDQ2
DDRA_SDQ3
DDRA_SDQ4
DDRA_SDQ5
DDRA_SDQ6
DDRA_SDQ7
DDRA_SDQ8
DDRA_SDQ9
DDRA_SDQ10
DDRA_SDQ11
DDRA_SDQ12
DDRA_SDQ13
DDRA_SDQ14
DDRA_SDQ15
DDRA_SDQ16
DDRA_SDQ17
DDRA_SDQ18
DDRA_SDQ19
DDRA_SDQ20
DDRA_SDQ21
DDRA_SDQ22
DDRA_SDQ23
DDRA_SDQ24
DDRA_SDQ25
DDRA_SDQ26
DDRA_SDQ27
DDRA_SDQ28
DDRA_SDQ29
DDRA_SDQ30
DDRA_SDQ31
DDRA_SDQ32
DDRA_SDQ33
DDRA_SDQ34
DDRA_SDQ35
DDRA_SDQ36
DDRA_SDQ37
DDRA_SDQ38
DDRA_SDQ39
DDRA_SDQ40
DDRA_SDQ41
DDRA_SDQ42
DDRA_SDQ43
DDRA_SDQ44
DDRA_SDQ45
DDRA_SDQ46
DDRA_SDQ47
DDRA_SDQ48
DDRA_SDQ49
DDRA_SDQ50
DDRA_SDQ51
DDRA_SDQ52
DDRA_SDQ53
DDRA_SDQ54
DDRA_SDQ55
DDRA_SDQ56
DDRA_SDQ57
DDRA_SDQ58
DDRA_SDQ59
DDRA_SDQ60
DDRA_SDQ61
DDRA_SDQ62
DDRA_SDQ63
MEMORY
<14> DDRA_SMA[0..14]
SYSTEM
<14> DDRA_SDM[0..7]
D
<15> DDRB_SDQ[0..63]
DDRA_SDM[0..7]
DDR
<14> DDRA_SDQ[0..63]
DDRB_SDQS0
DDRB_SDQS1
DDRB_SDQS2
DDRB_SDQS3
DDRB_SDQS4
DDRB_SDQS5
DDRB_SDQS6
DDRB_SDQS7
<15>
<15>
<15>
<15>
<15>
<15>
<15>
<15>
DDRB_SDQS0#
DDRB_SDQS1#
DDRB_SDQS2#
DDRB_SDQS3#
DDRB_SDQS4#
DDRB_SDQS5#
DDRB_SDQS6#
DDRB_SDQS7#
<15>
<15>
<15>
<15>
<15>
<15>
<15>
<15>
Compal Secret Data

Deciphered Date
2008/8/18
5
Title
Cantiga (3/7)-DDRII
Size
B
Date:
Document Number
ai
2007/08/18
Issued Date

he
x
nf
@
ho
tm
ai
l.c
om
Sheet
of
49
Rev
0.4
U3C
<18> GMCH_LCD_CLK
<18> GMCH_LCD_DATA
<18> GMCH_ENVDD
D
C63
2
@ 100P_0402_50V8J
R86
GMCH_TZCLKGMCH_TZCLK+
GMCH_TXCLKGMCH_TXCLK+
GMCH_TZCLKGMCH_TZCLK+
GMCH_TXCLKGMCH_TXCLK+
C41
C40
B37
A37
LVDSA_CLK#
LVDSA_CLK
LVDSB_CLK#
LVDSB_CLK
<18> GMCH_TZOUT0<18> GMCH_TZOUT1<18> GMCH_TZOUT2-
GMCH_TZOUT0GMCH_TZOUT1GMCH_TZOUT2-
H47
E46
G40
A40
LVDSA_DATA#_0
LVDSA_DATA#_1
LVDSA_DATA#_2
LVDSA_DATA#_3
<18> GMCH_TZOUT0+
<18> GMCH_TZOUT1+
<18> GMCH_TZOUT2+
<18> GMCH_TXOUT0<18> GMCH_TXOUT1<18> GMCH_TXOUT2<18> GMCH_TXOUT0+
<18> GMCH_TXOUT1+
<18> GMCH_TXOUT2+
GMCH_TZOUT0+
GMCH_TZOUT1+
GMCH_TZOUT2+
H48
D45
F40
B40
LVDSA_DATA_0
LVDSA_DATA_1
LVDSA_DATA_2
LVDSA_DATA_3
GMCH_TXOUT0GMCH_TXOUT1GMCH_TXOUT2-
A41
H38
G37
J37
LVDSB_DATA#_0
LVDSB_DATA#_1
LVDSB_DATA#_2
LVDSB_DATA#_3
GMCH_TXOUT0+
GMCH_TXOUT1+
GMCH_TXOUT2+
B42
G38
F37
K37
LVDSB_DATA_0
LVDSB_DATA_1
LVDSB_DATA_2
LVDSB_DATA_3
R88
R89
R90
2 150_0402_1%
2 150_0402_1%
2 150_0402_1%
1
1
1
GMCH_TV_COMPS
GMCH_TV_LUMA
GMCH_TV_CRMA
R91
<19> GMCH_CRT_G
R93
CRT_IREF
CRT_VSYNC
GM@ 30_0402_5%
10/22 follow CRB and Checklist

recommend use 30 Ohm (SD028300A80)
Common design recommend H/VSYNC width=8 mil
2 2.2K_0402_5%
GMCH_LCD_CLK
R103 1 GM@
2 2.2K_0402_5%
GMCH_LCD_DATA
R105 1 GM@
2 10K_0402_5%
LCTLB_DATA
R107 1 GM@
2 10K_0402_5%
LCTLA_CLK
R92
PCIE_GTX_C_MRX_N0
PCIE_GTX_C_MRX_N1
PCIE_GTX_C_MRX_N2
PCIE_GTX_C_MRX_N3
PCIE_GTX_C_MRX_N4
PCIE_GTX_C_MRX_N5
PCIE_GTX_C_MRX_N6
PCIE_GTX_C_MRX_N7
PCIE_GTX_C_MRX_N8
PCIE_GTX_C_MRX_N9
PCIE_GTX_C_MRX_N10
PCIE_GTX_C_MRX_N11
PCIE_GTX_C_MRX_N12
PCIE_GTX_C_MRX_N13
PCIE_GTX_C_MRX_N14
PCIE_GTX_C_MRX_N15
PEG_RX_0
PEG_RX_1
PEG_RX_2
PEG_RX_3
PEG_RX_4
PEG_RX_5
PEG_RX_6
PEG_RX_7
PEG_RX_8
PEG_RX_9
PEG_RX_10
PEG_RX_11
PEG_RX_12
PEG_RX_13
PEG_RX_14
PEG_RX_15
H43
J44
L43
L41
N40
P47
N43
T42
U42
Y42
W47
Y37
AA42
AD36
AC48
AD40
PCIE_GTX_C_MRX_P0
PCIE_GTX_C_MRX_P1
PCIE_GTX_C_MRX_P2
PCIE_GTX_C_MRX_P3
PCIE_GTX_C_MRX_P4
PCIE_GTX_C_MRX_P5
PCIE_GTX_C_MRX_P6
PCIE_GTX_C_MRX_P7
PCIE_GTX_C_MRX_P8
PCIE_GTX_C_MRX_P9
PCIE_GTX_C_MRX_P10
PCIE_GTX_C_MRX_P11
PCIE_GTX_C_MRX_P12
PCIE_GTX_C_MRX_P13
PCIE_GTX_C_MRX_P14
PCIE_GTX_C_MRX_P15
PEG_TX#_0
PEG_TX#_1
PEG_TX#_2
PEG_TX#_3
PEG_TX#_4
PEG_TX#_5
PEG_TX#_6
PEG_TX#_7
PEG_TX#_8
PEG_TX#_9
PEG_TX#_10
PEG_TX#_11
PEG_TX#_12
PEG_TX#_13
PEG_TX#_14
PEG_TX#_15
J41
M46
M47
M40
M42
R48
N38
T40
U37
U40
Y40
AA46
AA37
AA40
AD43
AC46
PCIE_MTX_GRX_N0
PCIE_MTX_GRX_N1 C65
1
PCIE_MTX_GRX_N2
PCIE_MTX_GRX_N3 C67
1
PCIE_MTX_GRX_N4
PCIE_MTX_GRX_N5 C69
PCIE_MTX_GRX_N6
PCIE_MTX_GRX_N7 C71
PCIE_MTX_GRX_N8
PCIE_MTX_GRX_N9 C73
PCIE_MTX_GRX_N10
PCIE_MTX_GRX_N11 C75
PCIE_MTX_GRX_N12
PCIE_MTX_GRX_N14
PEG_TX_0
PEG_TX_1
PEG_TX_2
PEG_TX_3
PEG_TX_4
PEG_TX_5
PEG_TX_6
PEG_TX_7
PEG_TX_8
PEG_TX_9
PEG_TX_10
PEG_TX_11
PEG_TX_12
PEG_TX_13
PEG_TX_14
PEG_TX_15
J42
L46
M48
M39
M43
R47
N37
T39
U36
U39
Y39
Y46
AA36
AA39
AD42
AD46
PCIE_MTX_GRX_P0
PCIE_MTX_GRX_P1 C81
1
PCIE_MTX_GRX_P2
PCIE_MTX_GRX_P3 C83
1
PCIE_MTX_GRX_P4
PCIE_MTX_GRX_P5 C85
1
PCIE_MTX_GRX_P6
PCIE_MTX_GRX_P7 C87
1
PCIE_MTX_GRX_P8
PCIE_MTX_GRX_P9 C89
1
PCIE_MTX_GRX_P10
PCIE_MTX_GRX_P11 C91
1
PCIE_MTX_GRX_P12
1
PCIE_MTX_GRX_P14
1
J28
CRT_RED
G29
CRT_IRTN
H32
J32
J29
E29
CRT_DDC_CLK
CRT_DDC_DATA
CRT_HSYNC
CRT_TVO_IREF
R93
49.9_0402_1%
PCIE_MTX_C_GRX_N[0..15]
0_0402_5%
PM@
0_0402_5%
GM@
PCIE_GTX_C_MRX_N[0..15]
PCIE_GTX_C_MRX_P[0..15] <17>
Routing notice:
GM@
R87
PCIE_GTX_C_MRX_P3
2 0_0402_5%
NB
TMDS_B_HPD# <25>
Ext VGA
R
CH7318
2
2
1
2
2
2
2
2
2
2
2
2
C64
1
0.1U_0402_10V7K
C66
1
0.1U_0402_10V7K
C68
PM@ 0.1U_0402_10V7K
C70
PM@ 0.1U_0402_10V7K
C72
PM@ 0.1U_0402_10V7K
C74
PM@ 0.1U_0402_10V7K
C76
PM@ 0.1U_0402_10V7K
C78
PM@ 0.1U_0402_10V7K
C80
1
0.1U_0402_10V7K
C82
1
0.1U_0402_10V7K
C84
PM@ 0.1U_0402_10V7K
C86
PM@ 0.1U_0402_10V7K
C88
PM@ 0.1U_0402_10V7K
C90
PM@ 0.1U_0402_10V7K
C92
PM@ 0.1U_0402_10V7K
C94
PM@ 0.1U_0402_10V7K
2
2
1
2
2
2
0.1U_0402_10V7K PCIE_MTX_C_GRX_N0
PCIE_MTX_C_GRX_N1
0.1U_0402_10V7K PCIE_MTX_C_GRX_N2
PCIE_MTX_C_GRX_N3
PM@ 0.1U_0402_10V7K PCIE_MTX_C_GRX_N4
PCIE_MTX_C_GRX_N5
PCIE_MTX_C_GRX_N7
PCIE_MTX_C_GRX_N9
PCIE_MTX_C_GRX_N11
PCIE_MTX_C_GRX_N13
PCIE_MTX_C_GRX_N15
0.1U_0402_10V7K PCIE_MTX_C_GRX_P0
PCIE_MTX_C_GRX_P1
0.1U_0402_10V7K PCIE_MTX_C_GRX_P2
PCIE_MTX_C_GRX_P3
PM@ 0.1U_0402_10V7K PCIE_MTX_C_GRX_P4
PCIE_MTX_C_GRX_P5
PCIE_MTX_C_GRX_P7
PCIE_MTX_C_GRX_P9
PCIE_MTX_C_GRX_P11
PCIE_MTX_C_GRX_P13
PCIE_MTX_C_GRX_P15
PCIE_MTX_C_GRX_N0
PCIE_MTX_C_GRX_N1
PCIE_MTX_C_GRX_N2
PCIE_MTX_C_GRX_N3
<17,25>
<17,25>
<17,25>
<17,25>
PCIE_MTX_C_GRX_P0
PCIE_MTX_C_GRX_P1
PCIE_MTX_C_GRX_P2
PCIE_MTX_C_GRX_P3
<17,25>
<17,25>
<17,25>
<17,25>
RP60
Reserved for 1.5V level shift circuit

+3.3VS
2 PM@ 0_0402_5%
GMCH_LCD_CLK
R100 1
2 PM@ 0_0402_5%
GMCH_LCD_DATA
R102 1
2 PM@ 0_0402_5%
LCTLB_DATA
R104 1
2 PM@ 0_0402_5%
LCTLA_CLK
R106 1
2 PM@ 0_0402_5%
GMCH_CRT_CLK
R108 1
2 PM@ 0_0402_5%
GMCH_CRT_DATA
R109 1
0_0402_5%
TV_DCONSEL_0
R110 1
0_0402_5%
TV_DCONSEL_1
C748
+1.5VS
C747
HDA_BITCLK_NB
HDA_RST_NB#
HDA_SDOUT_NB
HDA_SYNC_NB
5
6
7
8
HDA_SDIN2
1 R786
2 GMCH_HDA_SDIN2
0_0402_5%
4
3
2
1
GMCH_HDA_BITCLK
GMCH_HDA_RST#
GMCH_HDA_SDOUT
GMCH_HDA_SYNC
0_0804_8P4R_5%
0.1U_0402_16V4Z
@ 2
0.1U_0402_16V4Z
@ 2
U67
<21>
<21>
<21>
<21>
<21>
HDA_BITCLK_NB
HDA_RST_NB#
HDA_SDOUT_NB
HDA_SYNC_NB
HDA_SDIN2
HDA_BITCLK_NB
HDA_RST_NB#
HDA_SDOUT_NB
HDA_SYNC_NB
HDA_SDIN2
16
15
14
13
12
11
10
9
VCCB
VCCA
CLK_OUT CLK_IN
CMD_B
CMD_A
B0
A0
B1
A1
B2
A2
B3
A3
GND
OE
1
2
3
4
5
6
7
8
R787
1
2 10K_0402_5%
GMCH_HDA_BITCLK
GMCH_HDA_RST#
GMCH_HDA_SDOUT
GMCH_HDA_SYNC
GMCH_HDA_SDIN2
Deciphered Date
+1.5VS
Compal Secret Data

2007/08/18
GMCH_HDA_BITCLK <8>
GMCH_HDA_RST# <8>
GMCH_HDA_SDOUT <8>
GMCH_HDA_SYNC <8>
GMCH_HDA_SDIN2 <8>
FXL2SD106BQX_DQFN16_2P5X3P5~D
@
2008/8/18
5
PCIE_GTX_C_MRX_N[0..15] <17>
PCIE_GTX_C_MRX_P[0..15]
Issued Date
PM@
PCIE_MTX_C_GRX_P[0..15] <17,25>
1.02K_0402_1%
PM@
PCIE_MTX_C_GRX_N[0..15] <17,25>
PCIE_MTX_C_GRX_P[0..15]
U67 pn is SA00002CT00 for 030 used
0_0402_5%
+1.05VS_PEG
CRT_VSYNC
R85
C97
@
R91
CRT_GREEN
R98
R99
R101 1 GM@
CRT_BLUE
L29
C96
@
+3VS
E28
H44
J46
L44
L40
N41
P48
N44
T43
U43
Y43
Y48
Y36
AA43
AD37
AC47
AD39
TV_DCONSEL_0
TV_DCONSEL_1
G28
PEG_RX#_0
PEG_RX#_1
PEG_RX#_2
PEG_RX#_3
PEG_RX#_4
PEG_RX#_5
PEG_RX#_6
PEG_RX#_7
PEG_RX#_8
PEG_RX#_9
PEG_RX#_10
PEG_RX#_11
PEG_RX#_12
PEG_RX#_13
PEG_RX#_14
PEG_RX#_15
R95
<19> GMCH_CRT_VSYNC
GMCH_CRT_CLK
GMCH_CRT_DATA
CRT_HSYNC
GM@ 30_0402_5%
100P_0402_50V8J
R94
1
GM@ 150_0402_1%
1
GM@ 150_0402_1%
1
GM@ 150_0402_1%
100P_0402_50V8J
<19> GMCH_CRT_CLK
<19> GMCH_CRT_DATA
<19> GMCH_CRT_HSYNC
TV_RTN
PEG_COMP
T37
T36
VGA
R92
<19> GMCH_CRT_R
H24
C31
E32
Conntc to 0 Ohm when use PM chip

<19> GMCH_CRT_B
TVA_DAC
TVB_DAC
TVC_DAC
TV
TV_DCONSEL_0
TV_DCONSEL_1
F25
H25
K25
R492 Close to GMCH < 0.5'
PEG_COMPI
PEG_COMPO
LVDS
LVDS_IBG
LVDS_VBG
LVDS_VREFH
LVDS_VREFL
LVDS_IBG
2
GM@
2.37K_0402_1%
Change to @ state
<18>
<18>
<18>
<18>
C44
B43
E37
E38
LBKLT_EN
LCTLA_CLK
LCTLB_DATA
GMCH_LCD_CLK
GMCH_LCD_DATA
GMCH_ENVDD
2
GM@ 0_0402_5%
GRAPHICS
R84
L_BKLT_CTRL
L_BKLT_EN
L_CTRL_CLK
L_CTRL_DATA
L_DDC_CLK
L_DDC_DATA
L_VDD_EN
PCI-EXPRESS
<18> GMCH_ENBKL
20/25mils
L32
G32
M32
M33
K33
J33
M29
Title
Cantiga (4/7)-VGA/LVDS/TV
Custom
Rev
0.4
Date:
Sheet
1
10
of
49
U3F
+VCC_AXG
+1.8V
1
1
C107
C108
C109
C110
220U_D2_4VM_R15
0.22U_0603_16V7K
0.1U_0402_16V4Z
2
2
2
10U_0805_10V4Z
0.22U_0603_16V7K
VCC_SM: 3300mA
(330UF*1,22UF*2, 0.1UF*1)
+1.8V
330u
ESR 15m ohm
C111
Rating 2.5V
9/14 add for reservation

(IFTXX)
1
1
C112
C113
C114
C115
C116
C117
330U_D2E_2.5VM
10U_0805_10V4Z
1U_0603_10V4Z
2
2
2
2
@ 22U_0805_6.3V6M
4.7U_0805_10V4Z
@ 0.1U_0402_16V4Z
VCC_AXG: 8700mA
(330UF*2,22UF*1, 10UF*1, 1U*1, 0.47U*1, 0.1UF*2)
+VCC_AXG
330u
ESR 15m ohm
C118
Rating 2.5V
1U_0603_10V4Z
@
C119
1
+
C120 1
C121 1
C122
C123
C124 1
C125 1
AE33
AC33
AA33
Y33
W33
V33
U33
AH28
AF28
AC28
AA28
AJ26
AG26
AE26
AC26
AH25
AG25
AF25
AG24
AJ23
AH23
AF23
T32
VCC_13
VCC_14
VCC_15
VCC_16
VCC_17
VCC_18
VCC_19
VCC_20
VCC_21
VCC_22
VCC_23
VCC_24
VCC_25
VCC_26
VCC_27
VCC_28
VCC_29
VCC_30
VCC_31
VCC_32
VCC_33
VCC_34
VCC_35
+1.05VS
C126
R114
330U_D2E_2.5VM
10U_0805_10V4Z
1U_0603_10V4Z
0.1U_0402_16V4Z
GM@ 2
GM@ 2
GM@
GM@ 2
GM@ 2
GM@ 2
GM@
GM@ 2
330U_D2E_2.5VM
10U_0805_10V4Z
0.47U_0603_16V4Z
0.1U_0402_16V4Z
0_0805_5%
PM@
1U_0603_10V4Z
@
Add these caps around PCI-E bus of NB

+1.05VS
C763
0.1U_0402_16V4Z
C764
0.1U_0402_16V4Z
C765
0.1U_0402_16V4Z
C766
0.1U_0402_16V4Z
C767
0.1U_0402_16V4Z
10/05 This is for GM@ (IFTXX)

Remember open stencil at GM@
+1.05VS
VCC_NCTF_1
VCC_NCTF_2
VCC_NCTF_3
VCC_NCTF_4
VCC_NCTF_5
VCC_NCTF_6
VCC_NCTF_7
VCC_NCTF_8
VCC_NCTF_9
VCC_NCTF_10
VCC_NCTF_11
VCC_NCTF_12
VCC_NCTF_13
VCC_NCTF_14
VCC_NCTF_15
VCC_NCTF_16
VCC_NCTF_17
VCC_NCTF_18
VCC_NCTF_19
VCC_NCTF_20
VCC_NCTF_21
VCC_NCTF_22
VCC_NCTF_23
VCC_NCTF_24
VCC_NCTF_25
VCC_NCTF_26
VCC_NCTF_27
VCC_NCTF_28
VCC_NCTF_29
VCC_NCTF_30
VCC_NCTF_31
VCC_NCTF_32
VCC_NCTF_33
VCC_NCTF_34
VCC_NCTF_35
VCC_NCTF_36
VCC_NCTF_37
VCC_NCTF_38
VCC_NCTF_39
VCC_NCTF_40
VCC_NCTF_41
VCC_NCTF_42
VCC_NCTF_43
VCC_NCTF_44
AM32
AL32
AK32
AJ32
AH32
AG32
AE32
AC32
AA32
Y32
W32
U32
AM30
AL30
AK30
AH30
AG30
AF30
AE30
AC30
AB30
AA30
Y30
W30
V30
U30
AL29
AK29
AJ29
AH29
AG29
AE29
AC29
AA29
Y29
W29
V29
AL28
AK28
AL26
AK26
AK25
AK24
AK23
+VCC_AXG
J1
1
VCCSM_LF1
VCCSM_LF2
VCCSM_LF3
VCCSM_LF4
VCCSM_LF5
VCCSM_LF6
VCCSM_LF7
1
C127
PAD-OPEN 3x3m
GM@
2
1
GM@ JOPEN
2
1
J6 GM@ JOPEN
2
1
J7 GM@ JOPEN
J5
C128
C129
C130
C131
C132
GM@
C133
A
om
0.1U_0402_16V4Z
0.22U_0402_6.3V6K
0.47U_0603_16V4Z
1U_0603_10V4Z
2
2
2
2
0.1U_0402_16V4Z
0.22U_0402_6.3V6K
1U_0603_10V4Z
1/25 Change J5, J6, J7 from 43x79 to 43x39
ai
l.c
AV44
BA37
AM40
AV21
AY5
AM10
BB13
2007/08/18
Issued Date
Compal Secret Data
2008/8/18
Deciphered Date
4
nf
@
ho
tm
VCC_SM_LF1
VCC_SM_LF2
VCC_SM_LF3
VCC_SM_LF4
VCC_SM_LF5
VCC_SM_LF6
VCC_SM_LF7
GM@
VCC_1
VCC_2
VCC_3
VCC_4
VCC_5
VCC_6
VCC_7
VCC_8
VCC_9
VCC_10
VCC_11
VCC_12
POWER
GFX NCTF
VCC
220u
ESR 15m ohm
C106
Rating 4V
VCC: 2898.52mA
(220UF*1, 22UF*1, 0.22UF*2, 0.1UF*1)
NCTF
VCC_AXG_SENSE
VSS_AXG_SENSE
+1.05VS
VCC
AJ14
AH14
U3G
AG34
AC34
AB34
AA34
Y34
V34
U34
AM33
AK33
AJ33
AG33
AF33
Title
Cantiga GMCH(5/7)-GTL
Custom
ai
@
@
+1.05VS
Date:
he
x
PAD
PAD
Checklist 220u ESR max 15m ohm

330u ESR max 12m ohm
GFX
T22
T23
VCC_AXG_1
VCC_AXG_2
VCC_AXG_3
VCC_AXG_4
VCC_AXG_5
VCC_AXG_6
VCC_AXG_7
VCC_AXG_8
VCC_AXG_9
VCC_AXG_10
VCC_AXG_11
VCC_AXG_12
VCC_AXG_13
VCC_AXG_14
VCC_AXG_15
VCC_AXG_16
VCC_AXG_17
VCC_AXG_18
VCC_AXG_19
VCC_AXG_20
VCC_AXG_21
VCC_AXG_22
VCC_AXG_23
VCC_AXG_24
VCC_AXG_25
VCC_AXG_26
VCC_AXG_27
VCC_AXG_28
VCC_AXG_29
VCC_AXG_30
VCC_AXG_31
VCC_AXG_32
VCC_AXG_33
VCC_AXG_34
VCC_AXG_35
VCC_AXG_36
VCC_AXG_37
VCC_AXG_38
VCC_AXG_39
VCC_AXG_40
VCC_AXG_41
VCC_AXG_42
W28
V28
W26
V26
W25
V25
W24
V24
W23
V23
AM21
AL21
AK21
W21
V21
U21
AM20
AK20
W20
U20
AM19
AL19
AK19
AJ19
AH19
AG19
AF19
AE19
AB19
AA19
Y19
W19
V19
U19
AM17
AK17
AH17
AG17
AF17
AE17
AC17
AB17
Y17
W17
V17
AM16
AL16
AK16
AJ16
AH16
AG16
AF16
AE16
AC16
AB16
AA16
Y16
W16
V16
U16
VCC
Y26
AE25
AB25
AA25
AE24
AC24
AA24
Y24
AE23
AC23
AB23
AA23
AJ21
AG21
AE21
AC21
AA21
Y21
AH20
AF20
AE20
AC20
AB20
AA20
T17
T16
AM15
AL15
AE15
AJ15
AH15
AG15
AF15
AB15
AA15
Y15
V15
U15
AN14
AM14
U14
T14
POWER
+VCC_AXG
VCC_AXG_NTCF_1
VCC_AXG_NCTF_2
VCC_AXG_NCTF_3
VCC_AXG_NCTF_4
VCC_AXG_NCTF_5
VCC_AXG_NCTF_6
VCC_AXG_NCTF_7
VCC_AXG_NCTF_8
VCC_AXG_NCTF_9
VCC_AXG_NCTF_10
VCC_AXG_NCTF_11
VCC_AXG_NCTF_12
VCC_AXG_NCTF_13
VCC_AXG_NCTF_14
VCC_AXG_NCTF_15
VCC_AXG_NCTF_16
VCC_AXG_NCTF_17
VCC_AXG_NCTF_18
VCC_AXG_NCTF_19
VCC_AXG_NCTF_20
VCC_AXG_NCTF_21
VCC_AXG_NCTF_22
VCC_AXG_NCTF_23
VCC_AXG_NCTF_24
VCC_AXG_NCTF_25
VCC_AXG_NCTF_26
VCC_AXG_NCTF_27
VCC_AXG_NCTF_28
VCC_AXG_NCTF_29
VCC_AXG_NCTF_30
VCC_AXG_NCTF_31
VCC_AXG_NCTF_32
VCC_AXG_NCTF_33
VCC_AXG_NCTF_34
VCC_AXG_NCTF_35
VCC_AXG_NCTF_36
VCC_AXG_NCTF_37
VCC_AXG_NCTF_38
VCC_AXG_NCTF_39
VCC_AXG_NCTF_40
VCC_AXG_NCTF_41
VCC_AXG_NCTF_42
VCC_AXG_NCTF_43
VCC_AXG_NCTF_44
VCC_AXG_NCTF_45
VCC_AXG_NCTF_46
VCC_AXG_NCTF_47
VCC_AXG_NCTF_48
VCC_AXG_NCTF_49
VCC_AXG_NCTF_50
VCC_AXG_NCTF_51
VCC_AXG_NCTF_52
VCC_AXG_NCTF_53
VCC_AXG_NCTF_54
VCC_AXG_NCTF_55
VCC_AXG_NCTF_56
VCC_AXG_NCTF_57
VCC_AXG_NCTF_58
VCC_AXG_NCTF_59
VCC_AXG_NCTF_60
VCC CORE
VCC_SM_36/NC
VCC_SM_37/NC
VCC_SM_38/NC
VCC_SM_39/NC
VCC_SM_40/NC
VCC_SM_41/NC
VCC_SM_42/NC
SM
BA36
BB24
BD16
BB21
AW16
AW13
AT13
VCC
VCC_SM_1
VCC_SM_2
VCC_SM_3
VCC_SM_4
VCC_SM_5
VCC_SM_6
VCC_SM_7
VCC_SM_8
VCC_SM_9
VCC_SM_10
VCC_SM_11
VCC_SM_12
VCC_SM_13
VCC_SM_14
VCC_SM_15
VCC_SM_16
VCC_SM_17
VCC_SM_18
VCC_SM_19
VCC_SM_20
VCC_SM_21
VCC_SM_22
VCC_SM_23
VCC_SM_24
VCC_SM_25
VCC_SM_26
VCC_SM_27
VCC_SM_28
VCC_SM_29
VCC_SM_30
VCC_SM_31
VCC_SM_32
VCC_SM_33
VCC_SM_34
VCC_SM_35
VCC SM LF
AP33
AN33
BH32
BG32
BF32
BD32
BC32
BB32
BA32
AY32
AW32
AV32
AU32
AT32
AR32
AP32
AN32
BH31
BG31
BF31
BG30
BH29
BG29
BF29
BD29
BC29
BB29
BA29
AY29
AW29
AV29
AU29
AT29
AR29
AP29
Sheet
11
of
49
Rev
0.4
VCCA_HPLL
AE1
VCCA_MPLL
VCCA_LVDS: 13.2mA
(1000PF*1)
J48
VCCA_LVDS
J47
VSSA_LVDS
VCCA_PEG_BG: 0.414mA
(0.1UF*1)
C148
+1.05VS_A_PEGPLL
VCCA_PEG_PLL:
1
C151
L5 1
2
MBK1608221YZF_0603
1
1
2
R123
1_0402_1%
10U_0805_10V4Z
1
C155
1
2
R124
0_0603_5%
220U_D2_4VM_R15
2
C156
C157
C158
C159
720mA
AR20
AP20
AN20
AR17
AP17
AN17
AT16
AR16
AP16
+1.05VS_A_SM_CK
VCCA_SM_CK: 24mA
(22UF*1, 2.2UF*1,0.1UF*1)
R128
0_0402_5%
PM@
C162
C167
@
2.2U_0603_6.3V6K
C163
0.1U_0402_16V4Z
2
2
10U_0805_10V4Z
NO_STUFF
26mA
VCCA_SM_CK_1
VCCA_SM_CK_2
VCCA_SM_CK_3
VCCA_SM_CK_4
VCCA_SM_CK_5
VCCA_SM_CK_NCTF_1
VCCA_SM_CK_NCTF_2
VCCA_SM_CK_NCTF_3
VCCA_SM_CK_NCTF_4
VCCA_SM_CK_NCTF_5
VCCA_SM_CK_NCTF_6
VCCA_SM_CK_NCTF_7
VCCA_SM_CK_NCTF_8
VCCD_HDA: 50mA
(0.1UF*1)
Also power for internal

Thermal Sensor
Please check Power

source if want
support IAMT
0.1U_0402_16V4Z
2
2
0.022U_0402_16V7K
0.1U_0402_16V4Z
2
VCC_HDA
to A32
35mA
+1.5VS_TVDAC
M25
+1.5VS_QDAC
L28
VCCD_QDAC
AF1
VCCD_HPLL
VCCD_TVDAC
copy G913CF_SOT23-5
Footprint
Close to AF1
Vin Vout
SHDN
1
C707
2 GND SET
@
G916T1UF
1U_0402_6.3V4Z
2
+1.5VS_LDO
R681 0_0402_5%
VCCD_QDAC: 48.363mA
(0.1UF*1, 0.01UF*1)
L9
1
2
MBK1608221YZF_0603
180Ohm@100MHz C186
R679 2K_0402_1%
C710
@
4.7U_0805_10V4Z
C187
0.1U_0402_16V4Z
2
2
0.01U_0402_16V7K
R680 10K_0402_1%
+1.05VS_A_PEGPLL
1
C179
Close to
VCCD_PEG_PLL: 50mA
(0.1UF*1)
+1.5VS
U36 @
1mA
157.2mA
+1.5VS_QDAC
1
R137
0_0402_5%
GM@
50mA
AA47
VCCD_PEG_PLL
AA47
60.31mA
M38
L37
0.1U_0402_16V4Z
2
+1.8V
+3VS
B22
B21
A21
VCC_AXF_1
VCC_AXF_2
VCC_AXF_3
VCCD_LVDS_1
VCCD_LVDS_2
BF21
BH20
BG20
BF20
VCC_SM_CK_1
VCC_SM_CK_2
VCC_SM_CK_3
VCC_SM_CK_4
1
2
R122
0_0603_5%
+1.05VS
C153
1U_0402_6.3V4Z
1
2
L6
MBK1608121YZF_0603
+1.8V
C160
1
2
1
2
R125
C161
1_0402_1% 10U_0805_10V4Z
0.1U_0402_16V4Z
+1.8V_TX_LVDS
+1.8V_TX_LVDS: 118.8mA
(22UF*1, 1000PF*1)
0.1uH 20%
1
L7
1
K47
VCC_TX_LVDS
105.3mA
C35
B35
A35
VCC_HV_1
VCC_HV_2
VCC_HV_3
VCC_HV: 105.3mA
(0.1UF*1)
1
CRB use 0.1uH, should we?

+3VS
0.1U_0402_16V4Z
1
1
456mA
C171
1
2
R135
0_0805_5%
C177
0.47U_0603_16V4Z
+1.8V_LVDS GM@
C181
220u
ESR 15m ohm
Rating 6.3V
+1.05VS_PEG
0.1U_0402_16V4Z
VTTLF_CAP1
A8
VTTLF_CAP2
L1
AB2 VTTLF_CAP3
C180
+1.05VS
+ C173
C172
+1.05VS_DMI
VCC_DMI: 456mA
(0.1UF*1)
VTTLF1
VTTLF2
VTTLF3
1
2
R733
0_0805_5%
1
2
R130
0_0805_5%
2
2
2
10U_0805_10V4Z
4.7U_0805_10V4Z
220U_V_6.3VM_R15
AH48
AF48
AH47
AG47
VCC_DMI_1
VCC_DMI_2
VCC_DMI_3
VCC_DMI_4
Please check Power

source if want
support IAMT
C170
+1.05VS_PEG: 1782mA +1.05VS_PEG

(220UF*1, 22UF*1, 4.7UF*1)
V48
U48
V47
U47
U46
VCC_PEG_1
VCC_PEG_2
VCC_PEG_3
VCC_PEG_4
VCC_PEG_5
2
+1.8V
GM@ MBK1608121YZF_0603
R129
C168
C169
PM@
GM@
GM@
0_0402_5% 1000P_0402_50V7K 10U_0805_10V4Z
2
2
CRB have reserved another filter for +VCC_DMI

separated from +1.05VS_PEG, should we?
C182
0.47U_0603_16V4Z
2
2
0.47U_0603_16V4Z
C185
GM@
2
1U_0402_6.3V4Z
R138
0_0402_5%
PM@
TV+CRT use Ivccd_qdac = 0.5u+0.5u =1mA
VCCD_LVDS: 60.31mA
(1UF*1)
2007/08/18
Issued Date
+3VS
@
10_0603_5%
CH751H-40PT_SOD323-2
Compal Secret Data
R139
D3
+1.05VS
Deciphered Date
2008/8/18
4
C184
C178
1
1
2
R136
1
0_0603_5% C183
+1.5VS
PEG
A32
C176
Close
GM@
0.1U_0402_16V4Z
2
VCCA_TV_DAC_1
VCCA_TV_DAC_2
50mA
+1.05VS
+1.5VS_TVDAC
0.47U_0603_16V4Z
VCC_SM_CK: 124mA
( 10UF*1,0.1UF*1) 1uH 30%
1782mA
DMI
1
2
R132
0_0603_5%
R134
GM@
0_0402_5%
PM@
B24
A24
VCCD_HPLL: 157.2mA (0.1UF*1)
VCCD_TVDAC: 58.696mA
(0.1UF*1, 0.01UF*1)
C145
+1.8V_SM_CK
118.8mA
VTTLF
+1.5VS_HDA
+1.5VS
C152
@
10U_0805_6.3V6M
Please check Power

source if want
support IAMT
VCC_AXF: 321.35mA
(10UF*1, 1UF*1)
+1.05VS_AXF
79mA
+3VS_TV_CRT_DAC
R133
0_0402_5%
PM@
C141
321.35mA
+3VS_TV_CRT_DAC
L8
1
2
MBK1608221YZF_0603
180Ohm@100MHz GM@
1
1
C174
C175
GM@
GM@
0.1U_0402_16V4Z
2
2
0.01U_0402_16V7K
C140
220U_D2_4VM_R15
4.7U_0805_10V4Z
2
2
2
4.7U_0805_10V4Z
2.2U_0603_6.3V6K
POWER
VCCA_SM_1
VCCA_SM_2
VCCA_SM_3
VCCA_SM_4
VCCA_SM_5
VCCA_SM_6
VCCA_SM_7
VCCA_SM_8
VCCA_SM_9
AP28
AN28
AP25
AN25
AN24
AM28
AM26
AM25
AL25
AM24
AL24
AM23
AL23
VCCA_TV_DAC: 40mA (0.1UF*1,

0.01UF*1 for each DAC)
C139
124mA
1
2
R126
0_0603_5%
0.1U_0402_16V4Z
VCCA_SM:
(22UF*2, 4.7UF*1, 1UF*1)
+3VS_DACBG
1
2
R131
0_0603_5%
GM@
VCCA_PEG_PLL
(10UF*1,0.1UF*1)
22U_0805_6.3V6M
4.7U_0805_10V4Z
2
2
2
2
@
10U_0805_10V4Z
1U_0402_6.3V4Z
Please check Power

source if want
support IAMT
+1.05VS
AA48
50mA
Close to Ball A25
+3VS
0.414mA
VCCA_PEG_BG
1
C138
+1.05VS
+1.05VS
1
2
R127
0_0603_5%
1
1
1
C164
C165
C166
GM@
GM@
GM@
GM@
0.1U_0402_16V4Z
10U_0805_10V4Z
2
2
2
0.01U_0402_16V7K
13.2mA
50mA
+1.05VS_A_SM
VCCA_DAC_BG: 2.6833333mA
(0.1UF*1, 0.01UF*1)
139.2mA
AD48
0.1U_0402_16V4Z
2
C154 2
Please check Power

source if want
support IAMT
24mA
VTT: 852mA
(270UF*1, 4.7UF*2, 2.2UF*1, 0.47UF*1)
1
R121
0_0402_5%
PM@
1
C144
GM@
1000P_0402_50V7K
2
+VCCA_PEG_BG
R119
0_0603_5%
1
2
64.8mA
VTT
1
2
AD1
+1.05VS_MPLL
+1.8V_TX_LVDS
Please check Power

source if want
support IAMT
Close to Ball A26, B27
+3VS_TV_CRT_DAC
+1.05VS_HPLL
R118
@ 0_0603_5%
1
2
+1.5VS
+3VS_CRTDAC
1
2
R120
0_0603_5%
1
1
GM@
C149
C150
GM@
GM@
0.1U_0402_16V4Z
2
2
0.01U_0402_16V7K
220u
ESR 15m ohm
Rating 4V
VCCA_DPLLB
AXF
+3VS
+3VS_TV_CRT_DAC
VCCA_DPLLA
L48
HV
10U_0805_10V4Z
VCCA_CRT_DAC: 73mA (0.1UF*1, 0.01UF*1)
F47
PLL
C147
TV
VSSA_DAC_BG
220u
ESR 15m ohm
Rating 4V
2
1
10uH 10%
0.1U_0402_16V4Z
A PEG A LVDS
VCCA_DAC_BG
B25
+3VS_DACBG
SM CK
R116
1_0603_1%
A25
0.1U_0402_16V4Z
10U_0805_10V4Z
201005-548
1
1
+
C142
C143
R117
C706
GM@
GM@
@
PM@
220U_D2_4VM_R15
+1.05VS_DPLLA
2
2
2
0_0402_5%
+1.05VS_DPLLB
L4 1
2 @
10U_FLC-453232-100K_0.25A_10%
1
5mA
A SM
C146
+1.05VS_DPLLB
U13
T13
U12
T12
U11
T11
U10
T10
U9
T9
U8
T8
U7
T7
U6
T6
U5
T5
V3
U3
V2
U2
T2
V1
U1
VTT_1
VTT_2
VTT_3
VTT_4
VTT_5
VTT_6
VTT_7
VTT_8
VTT_9
VTT_10
VTT_11
VTT_12
VTT_13
VTT_14
VTT_15
VTT_16
VTT_17
VTT_18
VTT_19
VTT_20
VTT_21
VTT_22
VTT_23
VTT_24
VTT_25
VCCA_CRT_DAC_1
VCCA_CRT_DAC_2
HDA
L3 1
2
MBK1608121YZF_0603
VCCA_MPLL: 139.2mA
(22UF*1, 0.1UF*1)
B27
A26
+3VS_CRTDAC
D TV/CRT
120Ohm@100MHz
Please check Power

source if want GM@ L56
1
2
support IAMT
MBK1608121YZF_0603
+1.05VS
852mA
73mA
LVDS
+1.05VS_MPLL
VCCA_DPLLA
VCCA_DPLLB: 64.8mA
(220UF*1, 0.1UF*1)
U3H
Please check Power

source if want
support IAMT
D
4.7U_0805_10V4Z
2
2
0.1U_0402_16V4Z
220u
ESR 15m ohm
Rating 4V
C135
0.1U_0402_16V4Z
10U_0805_10V4Z
10uH 10% 201005-548
1
1
+
GM@ L55 1
C137
R115
C705
2 C136
GM@
PM@
GM@
MBK1608121YZF_0603 @
220U_D2_4VM_R15
2
2
2
0_0402_5%
NO_STUFF
(4.7UF*1, 0.1UF*1)
L1 1
2 @
10U_FLC-453232-100K_0.25A_10%
1
+1.05VS
220u
ESR 15m ohm
Rating 4V
CRT
+1.05VS_DPLLA
+1.05VS_HPLL
L2 1
2
+1.05VS
MBK1608121YZF_0603
1
C134
VCCA_HPLL: 24mA
Checklist 220u ESR max 15m ohm
A CK
Title
Custom
Rev
JHXXX M/B LA-4241P Schematic 0.4
Date:
Sheet
Monday, April 21, 2008

1
12
of
49
GM@
VSS
AM36
AE36
P36
L36
J36
F36
B36
AH35
AA35
Y35
U35
T35
BF34
AM34
AJ34
AF34
AE34
W34
B34
A34
BG33
BC33
BA33
AV33
AR33
AL33
AH33
AB33
P33
L33
H33
N32
K32
F32
C32
A31
AN29
T29
N29
K29
H29
F29
A29
BG28
BD28
BA28
AV28
AT28
AR28
AJ28
AG28
AE28
AB28
Y28
P28
K28
H28
F28
C28
BF26
AH26
AF26
AB26
AA26
C26
B26
BH25
BD25
BB25
AV25
AR25
AJ25
AC25
Y25
N25
L25
J25
G25
E25
BF24
AD12
AY24
AT24
AJ24
AH24
AF24
AB24
R24
L24
K24
J24
G24
F24
E24
BH23
AG23
Y23
B23
A23
AJ6
BG21
L12
AW21
AU21
AP21
AN21
AH21
AF21
AB21
R21
M21
J21
G21
BC20
BA20
AW20
AT20
AJ20
AG20
Y20
N20
K20
F20
C20
A20
BG19
A18
BG17
BC17
AW17
AT17
R17
M17
H17
C17
VSS_199
VSS_200
VSS_201
VSS_202
VSS_203
VSS_204
VSS_205
VSS_206
VSS_207
VSS_208
VSS_209
VSS_210
VSS_211
VSS_212
VSS_213
VSS_214
VSS_215
VSS_216
VSS_217
VSS_218
VSS_219
VSS_220
VSS_221
VSS_222
VSS_223
VSS_224
VSS_225
VSS_226
VSS_227
VSS_228
VSS_229
VSS_230
VSS_231
VSS_232
VSS_233
BA16
VSS_235
AU16
AN16
N16
K16
G16
E16
BG15
AC15
W15
A15
BG14
AA14
C14
BG13
BC13
BA13
VSS_237
VSS_238
VSS_239
VSS_240
VSS_241
VSS_242
VSS_243
VSS_244
VSS_245
VSS_246
VSS_247
VSS_248
VSS_249
VSS_250
VSS_251
VSS_252
AN13
AJ13
AE13
N13
L13
G13
E13
BF12
AV12
AT12
AM12
AA12
J12
A12
BD11
BB11
AY11
AN11
AH11
VSS_255
VSS_256
VSS_257
VSS_258
VSS_259
VSS_260
VSS_261
VSS_262
VSS_263
VSS_264
VSS_265
VSS_266
VSS_267
VSS_268
VSS_269
VSS_270
VSS_271
VSS_272
VSS_273
Y11
N11
G11
C11
BG10
AV10
AT10
AJ10
AE10
AA10
M10
BF9
BC9
AN9
AM9
AD9
G9
B9
BH8
BB8
AV8
AT8
VSS_275
VSS_276
VSS_277
VSS_278
VSS_279
VSS_280
VSS_281
VSS_282
VSS_283
VSS_284
VSS_285
VSS_286
VSS_287
VSS_288
VSS_289
VSS_290
VSS_291
VSS_292
VSS_293
VSS_294
VSS_295
VSS_296
VSS
VSS NCTF
U3J
VSS_100
VSS_101
VSS_102
VSS_103
VSS_104
VSS_105
VSS_106
VSS_107
VSS_108
VSS_109
VSS_110
VSS_111
VSS_112
VSS_113
VSS_114
VSS_115
VSS_116
VSS_117
VSS_118
VSS_119
VSS_120
VSS_121
VSS_122
VSS_123
VSS_124
VSS_125
VSS_126
VSS_127
VSS_128
VSS_129
VSS_130
VSS_131
VSS_132
VSS_133
VSS_134
VSS_135
VSS_136
VSS_137
VSS_138
VSS_139
VSS_140
VSS_141
VSS_142
VSS_143
VSS_144
VSS_145
VSS_146
VSS_147
VSS_148
VSS_149
VSS_150
VSS_151
VSS_152
VSS_153
VSS_154
VSS_155
VSS_156
VSS_157
VSS_158
VSS_159
VSS_160
VSS_161
VSS_162
VSS_163
VSS_164
VSS_165
VSS_166
VSS_167
VSS_168
VSS_169
VSS_170
VSS_171
VSS_172
VSS_173
VSS_174
VSS_175
VSS_176
VSS_177
VSS_178
VSS_179
VSS_180
VSS_181
VSS_182
VSS_183
VSS_184
VSS_185
VSS_186
VSS_187
VSS_188
VSS_189
VSS_190
VSS_191
VSS_192
VSS_193
VSS_194
VSS_195
VSS_196
VSS_197
VSS_198
VSS_199
AH8
Y8
L8
E8
B8
AY7
AU7
AN7
AJ7
AE7
AA7
N7
J7
BG6
BD6
AV6
AT6
AM6
M6
C6
BA5
AH5
AD5
Y5
L5
J5
H5
F5
BE4
VSS_327
VSS_328
VSS_329
VSS_330
VSS_331
VSS_332
VSS_333
VSS_334
VSS_335
VSS_336
VSS_337
VSS_338
VSS_339
VSS_340
VSS_341
VSS_342
VSS_343
VSS_344
VSS_345
VSS_346
VSS_347
VSS_348
VSS_349
VSS_350
BC3
AV3
AL3
R3
P3
F3
BA2
AW2
AU2
AR2
AP2
AJ2
AH2
AF2
AE2
AD2
AC2
Y2
M2
K2
AM1
AA1
P1
H1
VSS_351
VSS_352
VSS_353
VSS_354
U24
U28
U25
U29
AF32
AB32
V32
AJ30
AM29
AF29
AB29
U26
U23
AL20
V20
AC19
AL17
AJ17
AA17
U17
VSS_SCB_1
VSS_SCB_2
VSS_SCB_3
VSS_SCB_4
VSS_SCB_5
BH48
BH1
A48
C1
A3
GM@
VSS_297
VSS_298
VSS_299
VSS_300
VSS_301
VSS_302
VSS_303
VSS_304
VSS_305
VSS_306
VSS_307
VSS_308
VSS_309
VSS_310
VSS_311
VSS_312
VSS_313
VSS_314
VSS_315
VSS_316
VSS_317
VSS_318
VSS_319
VSS_320
VSS_321
VSS_322
VSS_323
VSS_324
VSS_325
VSS_NCTF_1
VSS_NCTF_2
VSS_NCTF_3
VSS_NCTF_4
VSS_NCTF_5
VSS_NCTF_6
VSS_NCTF_7
VSS_NCTF_8
VSS_NCTF_9
VSS_NCTF_10
VSS_NCTF_11
VSS_NCTF_12
VSS_NCTF_13
VSS_NCTF_14
VSS_NCTF_15
VSS_NCTF_16
VSS SCB
VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9
VSS_10
VSS_11
VSS_12
VSS_13
VSS_14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_21
VSS_22
VSS_23
VSS_24
VSS_25
VSS_26
VSS_27
VSS_28
VSS_29
VSS_30
VSS_31
VSS_32
VSS_33
VSS_34
VSS_35
VSS_36
VSS_37
VSS_38
VSS_39
VSS_40
VSS_41
VSS_42
VSS_43
VSS_44
VSS_45
VSS_46
VSS_47
VSS_48
VSS_49
VSS_50
VSS_51
VSS_52
VSS_53
VSS_54
VSS_55
VSS_56
VSS_57
VSS_58
VSS_59
VSS_60
VSS_61
VSS_62
VSS_63
VSS_64
VSS_65
VSS_66
VSS_67
VSS_68
VSS_69
VSS_70
VSS_71
VSS_72
VSS_73
VSS_74
VSS_75
VSS_76
VSS_77
VSS_78
VSS_79
VSS_80
VSS_81
VSS_82
VSS_83
VSS_84
VSS_85
VSS_86
VSS_87
VSS_88
VSS_89
VSS_90
VSS_91
VSS_92
VSS_93
VSS_94
VSS_95
VSS_96
VSS_97
VSS_98
VSS_99
NC
U3I
AU48
AR48
AL48
BB47
AW47
AN47
AJ47
AF47
AD47
AB47
Y47
T47
N47
L47
G47
BD46
BA46
AY46
AV46
AR46
AM46
V46
R46
P46
H46
F46
BF44
AH44
AD44
AA44
Y44
U44
T44
M44
F44
BC43
AV43
AU43
AM43
J43
C43
BG42
AY42
AT42
AN42
AJ42
AE42
N42
L42
BD41
AU41
AM41
AH41
AD41
AA41
Y41
U41
T41
M41
G41
B41
BG40
BB40
AV40
AN40
H40
E40
AT39
AM39
AJ39
AE39
N39
L39
B39
BH38
BC38
BA38
AU38
AH38
AD38
AA38
Y38
U38
T38
J38
F38
C38
BF37
BB37
AW37
AT37
AN37
AJ37
H37
C37
BG36
BD36
AK15
AU36
NC_26
NC_27
NC_28
NC_29
NC_30
NC_31
NC_32
NC_33
NC_34
NC_35
NC_36
NC_37
NC_38
NC_39
NC_40
NC_41
NC_42
E1
D2
C3
B4
A5
A6
A43
A44
B45
C46
D47
B47
A46
F48
E48
C48
B48
A
Compal Secret Data

Deciphered Date
2008/8/18
5
Title
Custom
ai
2007/08/18
Issued Date
Date:
he
x
nf
@
ho
tm
ai
l.c
om
13
Sheet
1
of
49
Rev
0.4
+1.8V
11/12 Change to HEL80's
+1.8V
+1.8V
JDIMM1
DDRA_SDQ2
DDRA_SDQ3
D
DDRA_SDQ8
DDRA_SDQ9
DDRA_SDQS1#
DDRA_SDQS1
<9> DDRA_SDQS1#
<9> DDRA_SDQS1
DDRA_SDQ10
DDRA_SDQ11
DDRA_SDQ16
DDRA_SDQ17
DDRA_SDQS2#
DDRA_SDQS2
<9> DDRA_SDQS2#
<9> DDRA_SDQS2
DDRA_SDQ18
DDRA_SDQ19
DDRA_SDQ24
DDRA_SDQ25
DDRA_SDM3
EC_TX_P80_DATA
<15,32> EC_TX_P80_DATA
DDRA_SDQ26
DDRA_SDQ27
DDRA_CKE0
<8> DDRA_CKE0
EC_RX_P80_CLK
DDRA_SBS2
<15,32> EC_RX_P80_CLK
<9> DDRA_SBS2
DDRA_SMA12
DDRA_SMA9
DDRA_SMA8
DDRA_SMA5
DDRA_SMA3
DDRA_SMA1
DDRA_SMA10
DDRA_SBS0
DDRA_SWE#
<9> DDRA_SBS0
<9> DDRA_SWE#
DDRA_SCAS#
DDRA_SCS1#
<9> DDRA_SCAS#
<8> DDRA_SCS1#
DDRA_ODT1
<8> DDRA_ODT1
DDRA_SDQ32
DDRA_SDQ33
DDRA_SDQS4#
DDRA_SDQS4
<9> DDRA_SDQS4#
<9> DDRA_SDQS4
DDRA_SDQ34
DDRA_SDQ35
DDRA_SDQ40
DDRA_SDQ41
B
DDRA_SDM5
DDRA_SDQ42
DDRA_SDQ43
DDRA_SDQ48
DDRA_SDQ49
EC_RX_P80_CLK
R144 1
2 0_0402_5%
EC_RX_P80_CLK_R
<15> EC_RX_P80_CLK_R
DDRA_SDQS6#
DDRA_SDQS6
<9> DDRA_SDQS6#
<9> DDRA_SDQS6
DDRA_SDQ50
DDRA_SDQ51
DDRA_SDQ56
DDRA_SDQ57
DDRA_SDM7
DDRA_SDQ58
DDRA_SDQ59
D_CK_SDATA
D_CK_SCLK
<15,16> D_CK_SDATA
<15,16> D_CK_SCLK
+3VS
VSS
DQ16
DQ17
VSS
DQS2#
DQS2
VSS
DQ18
DQ19
VSS
DQ24
DQ25
VSS
DM3
NC
VSS
DQ26
DQ27
VSS
CKE0
VDD
NC
BA2
VDD
A12
A9
A8
VDD
A5
A3
A1
VDD
A10/AP
BA0
WE#
VDD
CAS#
NC/S1#
VDD
NC/ODT1
VSS
DQ32
DQ33
VSS
DQS4#
DQS4
VSS
DQ34
DQ35
VSS
DQ40
DQ41
VSS
DM5
VSS
DQ42
DQ43
VSS
DQ48
DQ49
VSS
NC,TEST
VSS
DQS6#
DQS6
VSS
DQ50
DQ51
VSS
DQ56
DQ57
VSS
DM7
VSS
DQ58
DQ59
VSS
SDA
SCL
VDDSPD
VSS
DQ20
DQ21
VSS
NC
DM2
VSS
DQ22
DQ23
VSS
DQ28
DQ29
VSS
DQS3#
DQS3
VSS
DQ30
DQ31
VSS
NC/CKE1
VDD
NC/A15
NC/A14
VDD
A11
A7
A6
VDD
A4
A2
A0
VDD
BA1
RAS#
S0#
VDD
ODT0
NC/A13
VDD
NC
VSS
DQ36
DQ37
VSS
DM4
VSS
DQ38
DQ39
VSS
DQ44
DQ45
VSS
DQS5#
DQS5
VSS
DQ46
DQ47
VSS
DQ52
DQ53
VSS
CK1
CK1#
VSS
DM6
VSS
DQ54
DQ55
VSS
DQ60
DQ61
VSS
DQS7#
DQS7
VSS
DQ62
DQ63
VSS
SA0
SA1
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
DDRA_SDQ4
DDRA_SDQ5
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
R141
+DIMM_VREF
DDRA_SDM0
1K_0402_1%
20mils
DDRA_SDQ6
DDRA_SDQ7
+DIMM_VREF
1
DDRA_SDQ12
DDRA_SDQ13
C188
C189
R142
2
DDRA_SDM1
0.1U_0402_16V4Z
2.2U_0603_6.3V6K
1K_0402_1%
C215
330u
ESR 15m ohm
Rating 2.5V
DDRA_SDQ20
DDRA_SDQ21
R143 1
DDRA_SDM2
2 0_0402_5%
PM_EXTTS#0 <8>
DDRA_SDQS3# <9>
DDRA_SDQS3 <9>
C191
RP1
1
2
DDRA_SMA12
1
DDRA_SMA9
2
RP2
4
3
56_0404_4P2R_5%
DDRA_SMA4
DDRA_SMA2
DDRA_SMA0
DDRA_SMA8
DDRA_SMA5
4
3
56_0404_4P2R_5%
DDRA_SMA3
DDRA_SMA1
DDRA_SBS1 <9>
DDRA_SRAS# <9>
DDRA_SCS0# <8>
DDRA_SDQ36
DDRA_SDQ37
DDRA_SDM4
DDRA_SDQ38
DDRA_SDQ39
DDRA_SDQ44
DDRA_SDQ45
DDRA_SDQS5# <9>
DDRA_SDQS5 <9>
DDRA_SDQ46
DDRA_SDQ47
DDRA_CLK1 <8>
DDRA_CLK1# <8>
DDRA_SMA10
1
DDRA_SBS0
2
RP5
4
3
56_0404_4P2R_5%
DDRA_SWE#
1
DDRA_SCAS#
2
RP6
4
3
56_0404_4P2R_5%
DDRA_SCS1#
1
DDRA_ODT1
2
RP7
4
3
56_0404_4P2R_5%
DDRA_SMA11
1
DDRA_SMA14
2
RP8
4
3
56_0404_4P2R_5%
+0.9VS
DDRA_SMA6
DDRA_SMA7
1
2
4
3
56_0404_4P2R_5%
DDRA_SMA2
DDRA_SMA4
1
2
RP10
4
3
56_0404_4P2R_5%
DDRA_SBS1
DDRA_SMA0
1
2
RP11
4
3
56_0404_4P2R_5%
DDRA_SCS0#
1
DDRA_SRAS#
2
RP12
4
3
56_0404_4P2R_5%
DDRA_SMA13
1
DDRA_ODT0
2
RP13
4
3
56_0404_4P2R_5%
DDRA_SDM6
DDRA_SDQ54
DDRA_SDQ55
DDRA_SDQ60
DDRA_SDQ61
DDRA_SDQS7#
DDRA_SDQS7
DDRA_SDQS7# <9>
DDRA_SDQS7 <9>
DDRA_CKE1
DDRA_SDQ62
DDRA_SDQ63
R146 1
R147 1
0.1U_0402_16V4Z
4
3
56_0404_4P2R_5%
RP9
DDRA_SDQ52
DDRA_SDQ53
C197
1
2
RP4
DDRA_ODT0 <8>
1
2
1
R145
C195
+1.8V
1
RP3
1
C196
+
@
2.2U_0603_6.3V6K
2.2U_0603_6.3V6K
330U_D2E_2.5VM
2
C194
2.2U_0603_6.3V6K
4
3
56_0404_4P2R_5%
DDRA_SMA11
DDRA_SMA7
DDRA_SMA6
DDRA_SDQS5#
DDRA_SDQS5
C193
2.2U_0603_6.3V6K
+0.9VS
DDRA_CKE0
DDRA_SBS2
DDRA_SMA14
DDRA_ODT0
DDRA_SMA13
C192
2.2U_0603_6.3V6K
DDRA_CKE1 <8>
DDRA_SBS1
DDRA_SRAS#
DDRA_SCS0#
+1.8V
DDRA_SDM[0..7]
<9> DDRA_SDM[0..7]
DDRA_SDQ30
DDRA_SDQ31
DDRA_CKE1
Layout Note:
Place near JP34
DDRA_SDQ[0..63]
<9> DDRA_SDQ[0..63]
DDRA_SDQ28
DDRA_SDQ29
DDRA_SDQS3#
DDRA_SDQS3
DDRA_SMA[0..14]
<9> DDRA_SMA[0..14]
DDRA_SDQ22
DDRA_SDQ23
C198
0.1U_0402_16V4Z
C199
0.1U_0402_16V4Z
C200
0.1U_0402_16V4Z
+0.9VS
C201
0.1U_0402_16V4Z
C206
0.1U_0402_16V4Z
C202
0.1U_0402_16V4Z
C203
0.1U_0402_16V4Z
C204
0.1U_0402_16V4Z
C205
0.1U_0402_16V4Z
C207
0.1U_0402_16V4Z
C208
0.1U_0402_16V4Z
C209
0.1U_0402_16V4Z
C210
0.1U_0402_16V4Z
+0.9VS
C211
0.1U_0402_16V4Z
C212
0.1U_0402_16V4Z
C213
0.1U_0402_16V4Z
C702
0.1U_0402_16V4Z
2
56_0402_5%
2 10K_0402_5%
2 10K_0402_5%
Layout Note:
Place these resistor
closely JP35,all
trace length Max=1.5"
Layout Note:
Place one cap close to every 2 pullup
resistors terminated to +0.9VS
0.1U_0402_16V4Z
2.2U_0603_6.3V6K 2
Compal Secret Data
2007/08/18
Issued Date
2008/8/18
Deciphered Date
12/22 Change from 0805 to 0603 (IFTXX)

5
220P_0402_50V7K
2 @
DDRA_CLK0 <8>
DDRA_CLK0# <8>
DIMM1 STD H:5.2mm (BOT)

C214
C190
DDRA_SDQ14
DDRA_SDQ15
FOX_ASOA426-M2RN-7F
CONN@
+3VS
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
VSS
DQ4
DQ5
VSS
DM0
VSS
DQ6
DQ7
VSS
DQ12
DQ13
VSS
DM1
VSS
CK0
CK0#
VSS
DQ14
DQ15
VSS
DDRA_SDQS0#
DDRA_SDQS0
VREF
VSS
DQ0
DQ1
VSS
DQS0#
DQS0
VSS
DQ2
DQ3
VSS
DQ8
DQ9
VSS
DQS1#
DQS1
VSS
DQ10
DQ11
VSS
DDRA_SDQ0
DDRA_SDQ1
<9> DDRA_SDQS0#
<9> DDRA_SDQS0
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
+DIMM_VREF
Title
DDRII-SODIMM1
Size
B
Date:
Document Number
Rev
0.4
Sheet
1
14
of
49
11/12 Change DIMM1 as HEL80's

+1.8V
+1.8V
+DIMM_VREF
JDIMM2
DDRB_SDQ0
DDRB_SDQ1
<9> DDRB_SDQS0#
<9> DDRB_SDQS0
DDRB_SDQS0#
DDRB_SDQS0
DDRB_SDQ2
DDRB_SDQ3
DDRB_SDQ8
DDRB_SDQ9
<9> DDRB_SDQS1#
<9> DDRB_SDQS1
DDRB_SDQS1#
DDRB_SDQS1
DDRB_SDQ10
DDRB_SDQ11
DDRB_SDQ16
DDRB_SDQ17
<9> DDRB_SDQS2#
<9> DDRB_SDQS2
DDRB_SDQS2#
DDRB_SDQS2
DDRB_SDQ18
DDRB_SDQ19
DDRB_SDQ24
DDRB_SDQ25
DDRB_SDM3
EC_TX_P80_DATA
<14,32> EC_TX_P80_DATA
2
DDRB_SDQ26
DDRB_SDQ27
<8> DDRB_CKE0
<14,32> EC_RX_P80_CLK
<9> DDRB_SBS2
DDRB_CKE0
EC_RX_P80_CLK
DDRB_SBS2
DDRB_SMA12
DDRB_SMA9
DDRB_SMA8
DDRB_SMA5
DDRB_SMA3
DDRB_SMA1
<9> DDRB_SBS0
<9> DDRB_SWE#
<9> DDRB_SCAS#
<8> DDRB_SCS1#
<8> DDRB_ODT1
DDRB_SMA10
DDRB_SBS0
DDRB_SWE#
DDRB_SCAS#
DDRB_SCS1#
DDRB_ODT1
DDRB_SDQ32
DDRB_SDQ33
<9> DDRB_SDQS4#
<9> DDRB_SDQS4
DDRB_SDQS4#
DDRB_SDQS4
DDRB_SDQ34
DDRB_SDQ35
DDRB_SDQ40
DDRB_SDQ41
DDRB_SDM5
DDRB_SDQ42
DDRB_SDQ43
DDRB_SDQ48
DDRB_SDQ49
EC_RX_P80_CLK_R
<14> EC_RX_P80_CLK_R
<9> DDRB_SDQS6#
<9> DDRB_SDQS6
DDRB_SDQS6#
DDRB_SDQS6
DDRB_SDQ50
DDRB_SDQ51
DDRB_SDQ56
DDRB_SDQ57
DDRB_SDM7
DDRB_SDQ58
DDRB_SDQ59
<14,16> D_CK_SDATA
<14,16> D_CK_SCLK
D_CK_SDATA
D_CK_SCLK
+3VS
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
VREF
VSS
DQ0
DQ1
VSS
DQS0#
DQS0
VSS
DQ2
DQ3
VSS
DQ8
DQ9
VSS
DQS1#
DQS1
VSS
DQ10
DQ11
VSS
VSS
DQ16
DQ17
VSS
DQS2#
DQS2
VSS
DQ18
DQ19
VSS
DQ24
DQ25
VSS
DM3
NC
VSS
DQ26
DQ27
VSS
CKE0
VDD
NC
BA2
VDD
A12
A9
A8
VDD
A5
A3
A1
VDD
A10/AP
BA0
WE#
VDD
CAS#
NC/S1#
VDD
NC/ODT1
VSS
DQ32
DQ33
VSS
DQS4#
DQS4
VSS
DQ34
DQ35
VSS
DQ40
DQ41
VSS
DM5
VSS
DQ42
DQ43
VSS
DQ48
DQ49
VSS
NC,TEST
VSS
DQS6#
DQS6
VSS
DQ50
DQ51
VSS
DQ56
DQ57
VSS
DM7
VSS
DQ58
DQ59
VSS
SDA
SCL
VDDSPD
VSS
DQ4
DQ5
VSS
DM0
VSS
DQ6
DQ7
VSS
DQ12
DQ13
VSS
DM1
VSS
CK0
CK0#
VSS
DQ14
DQ15
VSS
VSS
DQ20
DQ21
VSS
NC
DM2
VSS
DQ22
DQ23
VSS
DQ28
DQ29
VSS
DQS3#
DQS3
VSS
DQ30
DQ31
VSS
NC/CKE1
VDD
NC/A15
NC/A14
VDD
A11
A7
A6
VDD
A4
A2
A0
VDD
BA1
RAS#
S0#
VDD
ODT0
NC/A13
VDD
NC
VSS
DQ36
DQ37
VSS
DM4
VSS
DQ38
DQ39
VSS
DQ44
DQ45
VSS
DQS5#
DQS5
VSS
DQ46
DQ47
VSS
DQ52
DQ53
VSS
CK1
CK1#
VSS
DM6
VSS
DQ54
DQ55
VSS
DQ60
DQ61
VSS
DQS7#
DQS7
VSS
DQ62
DQ63
VSS
SAO
SA1
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
DDRB_SDQ4
DDRB_SDQ5
DDRB_SMA[0..14]
<9> DDRB_SMA[0..14]
DDRB_SDM0
DDRB_SDQ6
DDRB_SDQ7
C216
C217
DDRB_SDQ[0..63]
<9> DDRB_SDQ[0..63]
2.2U_0603_6.3V6K
DDRB_SDM[0..7]
<9> DDRB_SDM[0..7]
0.1U_0402_16V4Z
1
DDRB_SDQ12
DDRB_SDQ13
DDRB_SDM1
DDRB_CLK0 <8>
DDRB_CLK0# <8>
DDRB_SDQ14
DDRB_SDQ15
330u
ESR 15m ohm
Rating 2.5V
DDRB_SDQ20
DDRB_SDQ21
R148 1
DDRB_SDM2
0_0402_5%
2
PM_EXTTS#1 <8>
DDRB_SDQ22
DDRB_SDQ23
Layout Note:
Place near JP35
+1.8V
DDRB_SDQ28
DDRB_SDQ29
DDRB_SDQS3#
DDRB_SDQS3
+0.9VS
DDRB_SDQ30
DDRB_SDQ31
DDRB_CKE1
C223 +
@
330U_D2E_2.5VM
2.2U_0603_6.3V6K
2.2U_0603_6.3V6K
2.2U_0603_6.3V6K 2
2.2U_0603_6.3V6K
2.2U_0603_6.3V6K
C218
DDRB_SDQS3# <9>
DDRB_SDQS3 <9>
DDRB_CKE1 <8>
DDRB_CKE0
DDRB_SBS2
1
2
RP14
4
3
56_0404_4P2R_5%
DDRB_SMA12
DDRB_SMA9
1
2
RP15
4
3
56_0404_4P2R_5%
DDRB_SMA8
DDRB_SMA5
1
2
RP16
4
3
56_0404_4P2R_5%
DDRB_SMA3
DDRB_SMA1
1
2
RP17
4
3
56_0404_4P2R_5%
DDRB_SMA10
DDRB_SBS0
1
2
RP18
4
3
56_0404_4P2R_5%
DDRB_SWE#
DDRB_SCAS#
1
2
RP19
4
3
56_0404_4P2R_5%
DDRB_SCS1#
DDRB_ODT1
1
2
RP20
4
3
56_0404_4P2R_5%
DDRB_SMA11
DDRB_SMA14
1
2
RP21
4
3
56_0404_4P2R_5%
DDRB_SMA6
DDRB_SMA7
1
2
RP22
4
3
56_0404_4P2R_5%
DDRB_SMA2
DDRB_SMA4
1
2
RP23
4
3
56_0404_4P2R_5%
DDRB_SBS1
DDRB_SMA0
1
2
RP24
4
3
56_0404_4P2R_5%
DDRB_SCS0#
DDRB_SRAS#
1
2
RP25
4
3
56_0404_4P2R_5%
DDRB_SMA13
DDRB_ODT0
1
2
RP26
4
3
56_0404_4P2R_5%
DDRB_CKE1
1
R149
C219
C220
C221
C222
DDRB_SMA11
DDRB_SMA7
DDRB_SMA6
+1.8V
C224
DDRB_SMA4
DDRB_SMA2
DDRB_SMA0
DDRB_SBS1
DDRB_SRAS#
DDRB_SCS0#
DDRB_ODT0
DDRB_SMA13
DDRB_SBS1 <9>
DDRB_SRAS# <9>
DDRB_SCS0# <8>
DDRB_ODT0 <8>
DDRB_SDQ36
DDRB_SDQ37
C225
C226
C227
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
2
2
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
+0.9VS
C228
DDRB_SDM4
C229
C230
C231
C232
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
2
2
2
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
DDRB_SDQ38
DDRB_SDQ39
DDRB_SDQ44
DDRB_SDQ45
DDRB_SDQS5#
DDRB_SDQS5
DDRB_SDQS5# <9>
DDRB_SDQS5 <9>
DDRB_SDQ46
DDRB_SDQ47
DDRB_SDQ52
DDRB_SDQ53
DDRB_CLK1 <8>
DDRB_CLK1# <8>
DDRB_SDM6
DDRB_SDQ54
DDRB_SDQ55
DDRB_SDQS7# <9>
DDRB_SDQS7 <9>
C234
C235
C236
C237
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
2
2
2
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
+0.9VS
C238
DDRB_SDQ60
DDRB_SDQ61
DDRB_SDQS7#
DDRB_SDQS7
+0.9VS
C233
C239
C240
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
2
2
0.1U_0402_16V4Z
2
56_0402_5%
DDRB_SDQ62
DDRB_SDQ63
R150
R151
1
1
2 10K_0402_5%
2 10K_0402_5%
Layout Note:
Place these resistor
closely JP35,all
trace length Max=1.5"
+3VS
Layout Note:
Place one cap close to every 2 pullup
resistors terminated to +0.9VS
l.c
P-TWO_A5692B-A0G16-P
CONN@
2008/8/18
Deciphered Date
B
Title
DDRII-SODIMM2
Size
B
Date:
Document Number
Rev
ai
2007/08/18
Issued Date
Compal Secret Data
nf
@
ho
tm
ai
Change PCB Footprint
DIMM2 STD H:9.2mm (BOT)
DDRB_SMA14
he
x
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
om
+DIMM_VREF
Sheet
15
of
49
+CLK_VDD
R152
+3VS
+3VS
1
0_0805_5%
C242
C243
C244
C245
C246
C247
R153
2
+1.05VS
C241
R156
10U_0805_10V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
R154
0.1U_0402_16V4Z
2.2K_0402_5%
2.2K_0402_5%
2N7002DW-T/R7_SOT363-6
Q3A
+CLK_VDDSRC
+1.05VS
MCH_CLKSEL0 <8>
10U_0805_10V4Z
C249
0.1U_0402_16V4Z
C250
0.1U_0402_16V4Z
C251
0.1U_0402_16V4Z
C252
0.1U_0402_16V4Z
C253
0.1U_0402_16V4Z
0.1U_0402_16V4Z
+3VS
D_CK_SCLK
Q3B
2N7002DW-T/R7_SOT363-6
11/29 Modify symbol to have additional pin 73
U4
1K_0402_5%
@
<22,30,31> ICH_SMBCLK
10/3 Change symbol

R160
D_CK_SDATA
C254
2
C248
R158
1K_0402_5%
1
2
R159
0_0402_5%
<5> CPU_BSEL0
56_0402_5%
@
1
2
<22,30,31> ICH_SMBDATA
1
0_0805_5%
R157
2.2K_0402_5%
FSA 2
1
R155
1
+CLK_VDD
D_CK_SDATA
10
D_CK_SCLK
CLK_CPU_BCLK
VDDREF
19
D_CK_SDATA <14,15>
D_CK_SCLK <14,15>
VDD48
72
VDDCPU
CPUT0_LPR_F
71
12
VDDPCI
CPUC0_LPR_F
70
CLK_CPU_BCLK#
27
VDDPLL3
CPUT1_LPR_F
68
CLK_MCH_BCLK
CPUC1_LPR_F
67
CLK_MCH_BCLK#
SRCT0_LPR/DOTT_96_LPR
24
R_CLK_DOT
SRCC0_LPR/DOTC_96_LPR
25
R_CLK_DOT#
CLK_CPU_BCLK <4>
CLK_CPU_BCLK# <4>
+1.05VS
SCLK
SDATA
R161
FSB
38
VDDSRC_IO
62
VDDSRC_IO
R167
31
VDDPLL3_IO
27MHz_NonSS/SRCT1_LPR/SE1
28
CLK_PCIE0
0_0402_5%
@
66
VDDCPU_IO
27MHz_SS/SRCC1_LPR/SE2
29
CLK_PCIE0#
23
VDD96_IO
SRCT2_LPR/SATAT_LPR
32
CLK_PCIE_SATA
SRCC2_LPR/SATAC_LPR
33
CLK_PCIE_SATA#
PM_STP_CPU#
<22> PM_STP_CPU#
+1.05VS
PM_STP_PCI#
<22> PM_STP_PCI#
53
CLK_MCH_BCLK <7>
CLK_MCH_BCLK# <7>
R163
R164
R165
R166
1
1
1
1
R169
R170
R171
R172
1
1
1
1
2
2
2
2
GM@
PM@
GM@
PM@
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
2
2
2
2
GM@
@
GM@
@
0_0402_5%
0_0402_5%
0_0402_5%
0_0402_5%
CLK_DREF_96M <8>
CLK_PCIE_VGA <17>
CLK_DREF_96M# <8>
CLK_PCIE_VGA# <17>
2
CLK_DREF_SSC <8>
CLK_27M_VGA <17>
CLK_DREF_SSC# <8>
CLK_27M_VGA# <17>
CLK_PCIE_SATA <21>
CLK_PCIE_SATA# <21>
CPU_STOP#
54
PCI_STOP#
Follow CRB and Checklist
VDDSRC_IO
1
2
VDDSRC
52
+CLK_VDDSRC
MCH_CLKSEL1 <8>
R162
1K_0402_5%
1
2
R168
0_0402_5%
<5> CPU_BSEL1
55
1K_0402_5%
@
1
2
SRCT3_LPR
35
CLK_PCIE_ICH
SRCC3_LPR
36
CLK_PCIE_ICH#
CLK_MCH_3GPLL
CLK_PCIE_ICH
<22>
CLK_PCIE_ICH#
<22>
R175
10K_0402_5%
2
1
1
2
R177
0_0402_5%
<5> CPU_BSEL2
<32> CLK_PCI_EC
1K_0402_5%
@
1
2
MCH_CLKSEL2 <8>
33_0402_5% 1
<40> CLK_PCI_TPM
R176
1K_0402_5%
R179
33_0402_5% 1
FSLC
FSLB
FSLA
CPU
MHz
SRC
MHz
CLKSEL2
CLKSEL1
CLKSEL0
166.6 100
33.3
200
100
33.3
266.6 100
33.3
2 R704
PCI1
13
PCI1
SRCT4_LPR
39
TME
14
PCI2/TME
SRCC4_LPR
40
CLK_MCH_3GPLL#
PCI_TPM
15
PCI3
SRCT6_LPR
57
CLK_PCIE_EXP
SRCC6_LPR
56
CLK_PCIE_EXP#
SRCT7_LPR
61
CLK_PCIE_LAN
SRCC7_LPR
60
CLK_PCIE_LAN#
CLK_PCIE_CARD
33_0402_5% 1
2 R178
27_SEL
16
<20> CLK_PCI_ICH
33_0402_5% 1
2 R180
ITP_EN
17
@ R623
@ R624
R625
<8,22,48> VGATE
<48> CLK_EN#
<22> CK_PWRGD
0_0402_5%
@
2 R174
<35> CLK_PCI_DB
FSC
R173
1
1
1
2 0_0402_5%
2 0_0402_5%
2 0_0402_5%
33_0402_5% 1
2 R181
<22> CLK_ICH_14M
33_0402_5% 1
2 R182
<35> CLK_14M_SIO
33_0402_5% 1
2 R183
X1
CPUT2_ITP_LPR/SRCT8_LPR
X2
CPUC2_ITP_LPR/SRCC8_LPR
63
CLK_PCIE_CARD#
11
NC
CLK_PCIE_WLAN
45
CLK_PCIE_WLAN#
SRCT10_LPR
50
CLK_PCIE_NAND
FSLB/TEST_MODE
FSLC/TEST_SEL/REF0
SRCC10_LPR
51
CLK_PCIE_NAND#
CLK_PCIE_3G
CLK_PCIE_3G#
SRCT11_LPR
SRCC11_LPR
47
For 27_SEL, 0 = Enable DOT96 & SRC1,
69
GNDCPU
1= Enable SRC0 & 27MHz
GNDREF
CR#3
37
For TME, 0 = Overclocking of CPU and SRC allowed
18
GNDPCI
CR#4
41
22
GND48
CR#6
58
30
GND
CR7#
65
26
GND
CR#9
43
34
GNDSRC
CR10#
49
59
GNDSRC
CR#11
46
CR#11
42
GNDSRC
CR#A
21
CR#A
ITP_EN
10K_0402_5%
PM@
27_SEL
10K_0402_5%
@
CLK_PCIE_WLAN# <30>
CLK_PCIE_NAND
CLK_PCIE_3G# <30>
R184 1
2 10K_0402_5%
R186 1
10K_0402_5%
GM@
10K_0402_5%
Issued Date
2007/08/18
R796
2 0_0402_5%
R190 1
R194
1
R799
1
R797
Routing the trace at least 10mil

B
+3VS
LAN_CLKREQ# <28>
CR#9
2008/8/18
Deciphered Date
2 10K_0402_5%
EXP_CLKREQ# <31>
2
0_0402_5%
2 @
0_0402_5%
2 10K_0402_5% +3VS
WLAN_CLKREQ# <30>
2
+3VS
10K_0402_5%
3G_CLKREQ#
SATA_CLKREQ#
3G_CLKREQ# <30>
SATA_CLKREQ# <22>
3G_CLKREQ#
C750
2 @ 100P_0402_50V8J
WLAN_CLKREQ#
C749
100P_0402_50V8J
Compal Secret Data
+3VS
MCH_CLKREQ# <8>
Title
Clock generator-ICS9LPRS387
10K_0402_5%
<BOM Structure>
R197
<30>
CLK_PCIE_3G <30>
Rev:B
R196
<30>
CLK_PCIE_NAND#
ICS9LPRS387AKLFT_MLF72_10x10
R195
<26>
CLK_PCIE_WLAN <30>
TME
CLK_XTAL_OUT
<26>
CLK_PCIE_CARD#
2
R193
10K_0402_5%
@
R192
1
2
+3VS
2
R191
18P_0402_50V8J
44
USB_48MHz/FSLA
FSC
REF1
SRCT9_LPR
Thermal GND
Y1
14.31818MHZ_16PF_DSX840GA
C256
20
FSB
CLK_PCIE_CARD
SRCC9_LPR
REF1
18P_0402_50V8J
CLK_PCIE_LAN# <28>
CLK_XTAL_OUT
73
CLK_XTAL_IN
C255
CLK_PCIE_LAN <28>
64
For ITP_EN, 0 =SRC8/SRC8#; 1 = ITP/ITP#
+3VS
CLK_PCIE_EXP# <31>
1 = Overclocking of CPU and SRC NOT allowed
CK_PWRGD/PD#
48
+3VS
CLK_PCIE_EXP <31>
CLK_XTAL_IN
FSA
CLK_MCH_3GPLL# <8>
PCI_F5/ITP_EN
PCI
MHz
<22> CLK_ICH_48M
PCI4/27_SELECT
CLK_MCH_3GPLL <8>
Size
Document Number

Date:

G
Sheet
16
H
of
49
Rev
0.4
PCIE_MTX_C_GRX_N[0..15]
<10,25> PCIE_MTX_C_GRX_N[0..15]
PCIE_MTX_C_GRX_P[0..15]
<10,25> PCIE_MTX_C_GRX_P[0..15]
9/13 modify this footprint from ACES_88990-2D08_230P to ACES_88990-2D28_230P

12/19 modify this footprint from ACES_88990-2D28_230P to QUASA_CA0330-230N20_230P
0208 : Modify this footprint from QUASA_CA0330-230N20_230P to QUASA_CA0330-230N20_230P-S
12/10 footprint QUASA_CA0330-230N20_230P
JMXM1B
PCIE_GTX_C_MRX_N[0..15]
<10> PCIE_GTX_C_MRX_N[0..15]
PCIE_GTX_C_MRX_P[0..15]
<10> PCIE_GTX_C_MRX_P[0..15]
PCIE_GTX_C_MRX_N1
PCIE_GTX_C_MRX_P1
JMXM1A
1
3
5
7
9
11
13
15
17
19
21
23
B+
PCIE_GTX_C_MRX_N15
PCIE_GTX_C_MRX_P15
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
PCIE_GTX_C_MRX_N14
PCIE_GTX_C_MRX_P14
PCIE_GTX_C_MRX_N13
PCIE_GTX_C_MRX_P13
PCIE_GTX_C_MRX_N12
PCIE_GTX_C_MRX_P12
PCIE_GTX_C_MRX_N11
PCIE_GTX_C_MRX_P11
PCIE_GTX_C_MRX_N10
PCIE_GTX_C_MRX_P10
PCIE_GTX_C_MRX_N9
PCIE_GTX_C_MRX_P9
PCIE_GTX_C_MRX_N8
PCIE_GTX_C_MRX_P8
PCIE_GTX_C_MRX_N7
PCIE_GTX_C_MRX_P7
PCIE_GTX_C_MRX_N6
PCIE_GTX_C_MRX_P6
PCIE_GTX_C_MRX_N5
PCIE_GTX_C_MRX_P5
PCIE_GTX_C_MRX_N4
PCIE_GTX_C_MRX_P4
PCIE_GTX_C_MRX_N3
PCIE_GTX_C_MRX_P3
PCIE_GTX_C_MRX_N2
PCIE_GTX_C_MRX_P2
PWR_SRC
PWR_SRC
PWR_SRC
PWR_SRC
PWR_SRC
PWR_SRC
PWR_SRC
PWR_SRC
GND
GND
GND
GND
1V8RUN
1V8RUN
1V8RUN
1V8RUN
1V8RUN
1V8RUN
1V8RUN
RUNPWROK
5VRUN
GND
GND
GND
PEX_RX15#
PEX_RX15
GND
PEX_RX14#
PEX_RX14
GND
PEX_RX13#
PEX_RX13
GND
PEX_RX12#
PEX_RX12
GND
PEX_RX11#
PEX_RX11
GND
PEX_RX10#
PEX_RX10
GND
PEX_RX9#
PEX_RX9
GND
PEX_RX8#
PEX_RX8
GND
PEX_RX7#
PEX_RX7
GND
PEX_RX6#
PEX_RX6
GND
PEX_RX5#
PEX_RX5
GND
PEX_RX4#
PEX_RX4
GND
PEX_RX3#
PEX_RX3
GND
PEX_RX2#
PEX_RX2
GND
PRSNT2#
PEX_TX15#
PEX_TX15
GND
PEX_TX14#
PEX_TX14
GND
PEX_TX13#
PEX_TX13
GND
PEX_TX12#
PEX_TX12
GND
PEX_TX11#
PEX_TX11
GND
PEX_TX10#
PEX_TX10
GND
PEX_TX9#
PEX_TX9
GND
PEX_TX8#
PEX_TX8
GND
PEX_TX7#
PEX_TX7
GND
PEX_TX6#
PEX_TX6
GND
PEX_TX5#
PEX_TX5
GND
PEX_TX4#
PEX_TX4
GND
PEX_TX3#
PEX_TX3
GND
PEX_TX2#
PEX_TX2
PCIE_GTX_C_MRX_N0
PCIE_GTX_C_MRX_P0
2
4
6
8
10
12
14
16
18
20
22
24
CLK_PCIE_VGA#
CLK_PCIE_VGA
<16> CLK_PCIE_VGA#
<16> CLK_PCIE_VGA
SUSP#
+5VS
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
<8,20,26,28,30,40>
<31,32,41,46,47>
<21>
<21>
<4,32>
<4,32>
<32>
<19>
<19>
<19>
<19>
<21>
<21>
PCIE_MTX_C_GRX_N15
PCIE_MTX_C_GRX_P15
PCIE_MTX_C_GRX_N14
PCIE_MTX_C_GRX_P14
PLT_RST_BUF#
HDA_SYNC_MXM
HDA_BITCLK_MXM
EC_SMB_DA2
EC_SMB_CK2
VGA_THERM#
VGA_CRT_HSYNC
VGA_CRT_VSYNC
VGA_DDC_CLK
VGA_DDC_DATA
HDA_SDIN3
HDA_SDOUT_MXM
HDA_SYNC_MXM
HDA_BITCLK_MXM
VGA_THERM#
VGA_CRT_HSYNC
VGA_CRT_VSYNC
VGA_DDC_CLK
VGA_DDC_DATA
HDA_SDIN3
HDA_SDOUT_MXM
CLK_27M_VGA#
CLK_27M_VGA
VGA_AC_DET
HDA_RST_030
<16> CLK_27M_VGA#
<16> CLK_27M_VGA
<32> VGA_AC_DET
PCIE_MTX_C_GRX_N13
PCIE_MTX_C_GRX_P13
PCIE_MTX_C_GRX_N12
PCIE_MTX_C_GRX_P12
PCIE_MTX_C_GRX_N11
PCIE_MTX_C_GRX_P11
PCIE_MTX_C_GRX_N10
PCIE_MTX_C_GRX_P10
PCIE_MTX_C_GRX_N9
PCIE_MTX_C_GRX_P9
PCIE_MTX_C_GRX_N8
PCIE_MTX_C_GRX_P8
PCIE_MTX_C_GRX_N7
PCIE_MTX_C_GRX_P7
PCIE_MTX_C_GRX_N6
PCIE_MTX_C_GRX_P6
PCIE_MTX_C_GRX_N5
PCIE_MTX_C_GRX_P5
PCIE_MTX_C_GRX_N4
PCIE_MTX_C_GRX_P4
PCIE_MTX_C_GRX_N3
PCIE_MTX_C_GRX_P3
VGA_HDMI_DETECT
VGA_HDMI_CLKVGA_HDMI_CLK+
<25> VGA_HDMI_DETECT
<25> VGA_HDMI_CLK<25> VGA_HDMI_CLK+
VGA_HDMI_TX2VGA_HDMI_TX2+
<25> VGA_HDMI_TX2<25> VGA_HDMI_TX2+
PCIE_MTX_C_GRX_N2
PCIE_MTX_C_GRX_P2
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
145
147
149
151
153
155
157
159
161
163
165
167
169
171
173
175
177
179
181
183
185
187
189
191
193
195
197
199
201
203
205
207
209
211
213
215
217
219
221
223
225
227
229
PEX_RX1#
GND
PEX_RX1
PEX_TX1#
GND
PEX_TX1
PEX_RX0#
GND
PEX_RX0
PEX_TX0#
GND
PEX_TX0
PEX_REFCLK#
PRSNT1#
PEX_REFCLK
TV_C/HDTV_Pr
CLK_REQ#
GND
PEX_RST#
TV_Y/HDTV_Y
RSVD
GND
RSVD
TV_CVBS/HDTV_Pb
SMB_DAT
GND
SMB_CLK
VGA_RED
THERM#
GND
VGA_HSYNC
VGA_GRN
VGA_VSYNC
GND
DDCA_CLK
VGA_BLU
DDCA_DAT
GND
IGP_UCLK#
LVDS_UCLK#
IGP_UCLK
LVDS_UCLK
GND
GND
RSVD
LVDS_UTX3#
RSVD
LVDS_UTX3
RSVD
GND
IGP_UTX2#
LVDS_UTX2#
IGP_UTX2
LVDS_UTX2
GND
GND
IGP_UTX1#
LVDS_UTX1#
IGP_UTX1
LVDS_UTX1
GND
GND
IGP_UTX0#
LVDS_UTX0#
IGP_UTX0
LVDS_UTX0
GND
GND
IGP_LCLK#/DVI_B_CLK#
LVDS_LCLK#
IGP_LCLK/DVI_B_CLK
LVDS_LCLK
DVI_B_HPD/GND
GND
RSVD
LVDS_LTX3#
RSVD
LVDS_LTX3
GND
GND
IGP_LTX2#/DVI_B_TX2#
LVDS_LTX2#
IGP_LTX2/DVI_B_TX2
LVDS_LTX2
GND
GND
LVDS_LTX1#
IGP_LTX1/DVI_B_TX1
LVDS_LTX1
GND
GND
LVDS_LTX0#
IGP_LTX0/DVI_B_TX0
LVDS_LTX0
DVI_A_HPD
GND
DVI_A_CLK#
DDCC_DAT
DVI_A_CLK
DDCC_CLK
GND
LVDS_PPEN
DVI_A_TX2#
LVDS_BL_BRGHT
DVI_A_TX2
LVDS_BLEN
GND
DDCB_DAT
DVI_A_TX1#
DDCB_CLK
DVI_A_TX1
2V5RUN
GND
GND
DVI_A_TX0#
3V3RUN
DVI_A_TX0
3V3RUN
GND
3V3RUN
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
146
148
150
152
154
156
158
160
162
164
166
168
170
172
174
176
178
180
182
184
186
188
190
192
194
196
198
200
202
204
206
208
210
212
214
216
218
220
222
224
226
228
230
PCIE_MTX_C_GRX_N1
PCIE_MTX_C_GRX_P1
PCIE_MTX_C_GRX_N0
PCIE_MTX_C_GRX_P0
VGA_TV_CRMA
@
VGA_TV_LUMA
@
VGA_TV_COMPS
HDA_RST_NB9X#
VGA_CRT_R
PAD
T4
PAD
T5
PAD
T6
VGA_CRT_R <19>
VGA_CRT_G
VGA_CRT_G <19>
VGA_CRT_B
VGA_CRT_B <19>
TXCLKTXCLK+
TXCLK- <18>
TXCLK+ <18>
10/3 for HDMI

SPDIFO
TXOUT2TXOUT2+
SPDIFO <36>
TXOUT2- <18>
TXOUT2+ <18>
TXOUT1TXOUT1+
TXOUT1- <18>
TXOUT1+ <18>
TXOUT0TXOUT0+
TXOUT0- <18>
TXOUT0+ <18>
TZCLKTZCLK+
TZCLK- <18>
TZCLK+ <18>
TZOUT2TZOUT2+
TZOUT2- <18>
TZOUT2+ <18>
TZOUT1TZOUT1+
TZOUT1- <18>
TZOUT1+ <18>
TZOUT0TZOUT0+
TZOUT0- <18>
TZOUT0+ <18>
I2CC_SDA
I2CC_SCL
ENVDD
I2CC_SDA <18>
I2CC_SCL <18>
ENVDD <18>
VGA_ENBKL
VGA_HDMIDAT
VGA_HDMICLK
VGA_ENBKL <18>
VGA_HDMIDAT <25>
VGA_HDMICLK <25>
B
+3VS
10/3 for HDMI
ACES_88990-2D08
ACES_88990-2D08
C260
4.7U_0805_10V4Z
PM@ 2
+5VS
C261
0.1U_0402_16V4Z
2 PM@
SPDIFO
R198 1
GM@
2 0_0402_5%
C263
0.1U_0402_16V4Z
2 PM@
HDA_RST_NB9X#
1
2
R693 NB9X@
0_0402_5%
R693
R694
NB9X
Mount
No stuff
030 NB9X
No stuff
Mount
NB8X
No stuff
No stuff
HDA_RST_MXM#
<21> HDA_RST_MXM#
1
R694 PM@
HDA_RST_030
0_0402_5%
Compal Secret Data

Deciphered Date
2008/8/18
5
Title
MXM Connector
Custom
Rev
ai
2007/08/18
Issued Date
0.4
Date:
he
x
nf
@
ho
tm
ai
om
C257
0.1U_0603_25V7K
PM@
+3VS
l.c
B+
Sheet
17
of
49
LCD POWER CIRCUIT

Routing Diagram
+3VS
+3VALW
+LCDVDD
W=60mils
MXMII Conn.
1
R200
100K_0402_5%
1 2
0.1U_0402_10V7K
2
G
2
R201
D
Q4
SSM3K7002FU_SC70-3
C264
C265
1
100K_0402_5%
LVDS
4.7U_0805_10V4Z
LVDS Bus
NB
R199
300_0603_5%
D
Q5
SI2301BDS_SOT23
Use Daisy chain to route
GM@
2 0_0402_5%
PM@
0_0402_5%
2
<17> ENVDD
R203 1
+LCDVDD
Q6
SSM3K7002FU_SC70-3
2
G
1
R202 1
<10> GMCH_ENVDD
W=60mils
@
R204
100K_0402_5%
C266
4.7U_0805_10V4Z
2
C267
I2CC_SCL
I2CC_SDA
1
2
RP27
1
2
RP28
1
2
RP29
1
2
RP30
1
2
RP31
1
2
RP32
1
2
RP33
1
2
RP34
1
2
RP35
0.1U_0402_16V4Z
TXOUT0+
TXOUT0-
TXOUT1TXOUT1+
LCD/PANEL BD. Conn.

(IFTXX)
TXOUT2TXOUT2+
TXCLK+
TXCLK-
JLVDS1
+3VS
C268
0.1U_0402_16V4Z
+LCDVDD
<17>
<17>
TZOUT0+
TZOUT0-
<17>
<17>
TZOUT1+
TZOUT1-
<17>
<17>
TZOUT2+
TZOUT2-
<17>
<17>
TZCLK+
TZCLK-
L10 2
TZOUT0+
TZOUT0TZOUT1+
TZOUT1TZOUT2+
TZOUT2TZCLK+
TZCLK+LCDVDD_L
(60 MIL)
FBMA-L11-201209-221LMA30T_0805 +3VS
C269
220P_0402_50V7K
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
32
GND1
GND2
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
ACES_88242-3001
CONN@
<EMI>
C271
10U_0805_10V4Z
Follow HEL80's pin definition

1
TXOUT0+ <17>
TXOUT0- <17>
TXOUT1+
TXOUT1-
TZOUT0+
TZOUT0-
TXOUT1+ <17>
TXOUT1- <17>
TXOUT2+
TXOUT2-
TZOUT1+
TZOUT1-
TXOUT2+ <17>
TXOUT2- <17>
TXCLK+
TXCLK-
TZOUT2TZOUT2+
TXCLK+ <17>
TXCLK- <17>
I2CC_SDA
I2CC_SCL
TZCLK+
TZCLK-
I2CC_SDA <17>
I2CC_SCL <17>
Except pin 29
C272
GMCH_LCD_CLK
GMCH_LCD_DATA
0_0404_4P2R_5%
GMCH_TXOUT0+
GMCH_TXOUT00_0404_4P2R_5%
GMCH_TXOUT1GMCH_TXOUT1+
0_0404_4P2R_5%
GMCH_TXOUT2GMCH_TXOUT2+
0_0404_4P2R_5%
GMCH_TXCLK+
GMCH_TXCLK0_0404_4P2R_5%
GMCH_TZOUT0+
GMCH_TZOUT00_0404_4P2R_5%
GMCH_TZOUT1+
GMCH_TZOUT10_0404_4P2R_5%
GMCH_TZOUT2GMCH_TZOUT2+
0_0404_4P2R_5%
GMCH_TZCLK+
GMCH_TZCLK0_0404_4P2R_5%
GMCH_LCD_CLK <10>
GMCH_LCD_DATA <10>
GMCH_TXOUT0+ <10>
GMCH_TXOUT0- <10>
GMCH_TXOUT1- <10>
GMCH_TXOUT1+ <10>
GMCH_TXOUT2- <10>
GMCH_TXOUT2+ <10>
GMCH_TXCLK+ <10>
GMCH_TXCLK- <10>
GMCH_TZOUT0+ <10>
GMCH_TZOUT0- <10>
C
GMCH_TZOUT1+ <10>
GMCH_TZOUT1- <10>
GMCH_TZOUT2- <10>
GMCH_TZOUT2+ <10>
GMCH_TZCLK+ <10>
GMCH_TZCLK- <10>
+3VS
1
C270
220P_0402_50V7K
12/18 modified from

220p @ to 470p mount
by EMI request
INVERTER Conn.
<EMI>
+LCDVDD_L
1
TXOUT0+
TXOUT0-
4
3
GM@
4
3
GM@
4
3
GM@
4
3
GM@
4
3
GM@
4
3
GM@
4
3
GM@
4
3
GM@
4
3
GM@
0208 Add C796 , C797 for EMI
DAC_BRIG
0.1U_0402_16V4Z
JP37
LTCX000G500 footprint is still use ACES_88242-3001
<32>
INVT_PWM
<32>
DAC_BRIG
+INVPWR_B+
INVT_PWM
1
2
3
4
5
6
7
DISPOFF#
DISPOFF#
1
C273
1
C274
1
C275
2 <EMI>
470P_0402_50V7K
2 <EMI>
470P_0402_50V7K
2 <EMI>
470P_0402_50V7K
+3VS
1
MOLEX_53780-0790
CONN@
R205
1
2
R206
2
R207
<10> GMCH_ENBKL
<17> VGA_ENBKL
1
GM@ 0_0402_5%
1
PM@ 0_0402_5%
4.7K_0402_5%
DISPOFF#
ENBKL
ENBKL
<32>
BKOFF#
<32> BKOFF#
D4
2
R208
100K_0402_5%
+INVPWR_B+
L11 2
1
KC FBM-L11-201209-221LMAT_0805
B+
<EMI>
L12 2
1
KC FBM-L11-201209-221LMAT_0805
C276
A
0.1U_0603_50V4Z
C277
<EMI>
A
68P_0402_50V8K
2 @
12/22 Change to SE071680J80
2007/08/18
Issued Date
Compal Secret Data
2008/8/18
Deciphered Date
5
Title
LVDS & DVI Connector

Size
B
Date:
Document Number
Rev
0.4
Sheet

1
18
of
49
Checklist recommend: 2-pole filter on R/G/B signals

C-L-C-L-C
10p - 47 Ohm/100MHz - 22p - 47 Ohm/100MHz - 10p
L13
KC FBM-L11-201209-221LMAT_0805
D5
D6
D7
@
@
@
DAN217_SC59 DAN217_SC59 DAN217_SC59
1
CRT Connector
+5VS
+R_CRT_VCC
D8
12/15 Modified. Note L26~L30 are 0 Ohm resisters

(IFTXX)
Place closed to chipset

R734 1
R209 1
2 PM@ 0_0402_5%
2 GM@ 0_0402_5%
VGA_CRT_R1
<17> VGA_CRT_G
<10> GMCH_CRT_G
R735 1
R210 1
2 PM@ 0_0402_5%
2 GM@ 0_0402_5%
VGA_CRT_G1
<17> VGA_CRT_B
<10> GMCH_CRT_B
R736 1
R211 1
2 PM@ 0_0402_5%
2 GM@ 0_0402_5%
VGA_CRT_B1
0_0603_5%
L16
0_0603_5%
L18
R213
1
C279
R214
150_0402_1%
2
L14
150_0402_1%
C280
2
2
10P_0402_50V8J
C281
C282
2
10P_0402_50V8J
+3VS
CRT_G_1
L17 1
2
FBMA-L10-160808-800LMT_0603
CRT_G_2
CRT_B_1
L19 1
2
FBMA-L10-160808-800LMT_0603
CRT_B_2
C283
C285
6
11
1
7
12
2
8
13
3
9
14
4
10
15
5
1
1
2
2
22P_0402_50V8J
22P_0402_50V8J
22P_0402_50V8J
C284
10P_0402_50V8J
2
C286
10P_0402_50V8J
2
C287
10P_0402_50V8J
1
1
L20
CRT_HSYNC_0
CRT_HSYNC_2
2
FCM1608C-121T_0603
C288
<EMI> 2
100P_0402_50V8J
<EMI>
1
L21
CRT_VSYNC_2
2
FCM1608C-121T_0603
DSUB_12
1
<EMI>
VGA_CRT_HSYNC1
2
PM@ 0_0402_5%
2
GM@ 0_0402_5%
1
10K_0402_5%
U5
OE#
2
R215
5
2
0.1U_0402_16V4Z
1
R737
1
R217
1
R216
2 CRT_HSYNC_1
39_0402_1%
C291
10P_0402_50V8J
<EMI>
TC7SET125FUF_SC70
C292
C290
<EMI>
68P_0402_50V8K
10P_0402_50V8J
2 <EMI>
DSUB_15
2
+CRT_VCC
2
0.1U_0402_16V4Z
1
R218
2 CRT_VSYNC_1
39_0402_1%
D9
<EMI>
DAN217_SC59
@
12/22 Change to SE071680J80

(IFTXX)
CRT_VSYNC_0
TC7SET125FUF_SC70
5
2
68P_0402_50V8K
<EMI>
VGA_CRT_VSYNC1
2
PM@ 0_0402_5%
2
GM@ 0_0402_5%
C293
U6
<10> GMCH_CRT_VSYNC
1
R738
1
R219
<17> VGA_CRT_VSYNC
2
P
1
C294
OE#
Place closed to chipset
16
17
SUYIN_070546FR015S233CR
+CRT_VCC
1
C289
<10> GMCH_CRT_HSYNC
JCRT1
10P_0402_50V8J
C278
0.1U_0402_16V4Z
2
CRT_R_2
150_0402_1%
<17> VGA_CRT_HSYNC
RB491D_SC59-3 1.1A_6VDC_FUSE
1
L15 1
2
FBMA-L10-160808-800LMT_0603
0_0603_5%
W=40mils
R212
CRT_R_1
<17> VGA_CRT_R
<10> GMCH_CRT_R
+L_CRT_VCC 2
+CRT_VCC
W=40mils
F1
D10
<EMI>
DAN217_SC59
@
Add IFTXX
Andy_1102
+5VS
+3VS
1
+CRT_VCC
R220
2.2K_0402_5%
R221
R222
VGA_DDC_DATA <17>
2.2K_0402_5%
Q44A
2N7002DW-T/R7_SOT363-6
DSUB_15
2
R223
1
GM@ 0_0402_5%
GMCH_CRT_DATA <10>
2
R224
1
GM@ 0_0402_5%
GMCH_CRT_CLK <10>
DSUB_12
2.2K_0402_5%
+3VS
3
Q44B
2N7002DW-T/R7_SOT363-6
VGA_DDC_CLK <17>
R225
10/5 Change to SB00000AR00

2
2.2K_0402_5%
+3VS
A
Title
CRT Connector
Size
B
Date:
Document Number
Rev
ai
2008/8/18
Deciphered Date
0.4
he
x
2007/08/18
Issued Date
Compal Secret Data
nf
@
ho
tm
ai
l.c
om
Sheet
19
of
49
+3VS
DMI for ESI-compatible operation

RP40
PCI_REQ#2
PCI_FRAME#
PCI_REQ#1
PCI_DEVSEL#
8
7
6
5
PCI_GNT#1
3/4 Change U7 from SA00002AN10 to SA00002JH00 (A2 to A3)
8.2K_1206_8P4R_5%
U7B
PCI_PLOCK#
PCI_IRDY#
PCI_PIRQD#
PCI_PERR#
8
7
6
5
D11
C8
D9
E12
E9
C9
E10
B7
C7
C5
G11
F8
F11
E7
A3
D2
F10
D5
D10
B3
F7
C3
F3
F4
C1
G7
H7
D1
G5
H6
G1
H3
8.2K_1206_8P4R_5%
+3VS
RP42
1
2
3
4
PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQE#
PCI_SERR#
8
7
6
5
8.2K_1206_8P4R_5%
RP43
1
2
3
4
PCI_PIRQG#
PCI_PIRQH#
PCI_PIRQC#
PCI_PIRQF#
8
7
6
5
8.2K_1206_8P4R_5%
RP44
1
2
3
4
PCI_STOP#
PCI_REQ#3
PCI_TRDY#
PCI_REQ#0
8
7
6
5
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
AD27
AD28
AD29
AD30
AD31
8.2K_1206_8P4R_5%
PCI_PIRQA#
PCI_PIRQB#
PCI_PIRQC#
PCI_PIRQD#
R247
2 1K_0402_5% PCI_GNT#3
@
R250
2 1K_0402_5% PCI_GNT#0
@
2 1K_0402_5%
@
REQ0#
GNT0#
REQ1#/GPIO50
GNT1#/GPIO51
REQ2#/GPIO52
GNT2#/GPIO53
REQ3#/GPIO54
GNT3#/GPIO55
C/BE0#
C/BE1#
C/BE2#
C/BE3#
D8
B4
D6
A5
IRDY#
PAR
PCIRST#
DEVSEL#
PERR#
PLOCK#
SERR#
STOP#
TRDY#
FRAME#
D3
E3
R1
C6
E4
C2
J4
A4
F5
D7
PCIRST#
PCI_DEVSEL#
PCI_PERR#
PCI_PLOCK#
PCI_SERR#
PCI_STOP#
PCI_TRDY#
PCI_FRAME#
PLTRST#
PCICLK
PME#
C14
D4
R2
PLT_RST#
CLK_PCI_ICH
PCI_PME#
Interrupt I/F
PIRQA#
PIRQB#
PIRQC#
PIRQD#
ICH9-M ES_FCBGA676
PIRQE#/GPIO2
PIRQF#/GPIO3
PIRQG#/GPIO4
PIRQH#/GPIO5
PAD
T7
PAD
T8
PCI_IRDY#
Place closely pin D4

CLK_PCI_ICH
R240
10_0402_5%
@
CLK_PCI_ICH <16>
PCI_PME# <32>
C295
10P_0402_50V8J
@
PCI_PIRQE#
PCI_PIRQF#
PCI_PIRQG#
PCI_PIRQH#
H4
K6
F2
G2
+3V_AND1
1
R248
1
R249
1
C296
SPI_CS#1 <22>
R251
J5
E1
J6
C4
PCI
PCI_REQ#0
PCI_GNT#0
PCI_REQ#1
PCI_GNT#1
PCI_REQ#2
PCI_GNT#2
PCI_REQ#3
PCI_GNT#3
F1
G4
B6
A7
F13
F12
E6
F6
1
2
3
4
RP41
PLT_RST#
2
@ 0_0402_5%
2
@ 0_0402_5%
+3VS
+3VALW
2
@ 0.1U_0402_16V4Z
U8
NC7SZ08P5X_NL_SC70-5
@
Y 4
PLT_RST_BUF# <8,17,26,28,30,40>
Low= DMI for ESI-compatible operation

High= Default* (Internal pull-up)
1
2
3
4
Low= A16 swap override Enable

High= Default*
2
0_0402_5%
1
R253
A16 Swap Override Strap

PCI_GNT#3
R252
100K_0402_5%
@
+3V_AND2
Update Footprint
1
R254
1
R255
CRB: GNT#0 and SPI_CS#1 have a weak internal pull up
+3VALW
2
@ 0.1U_0402_16V4Z
U9
NC7SZ08P5X_NL_SC70-5
@
Y 4
PCI_RST# <31,32,35>
Boot BIOS Strap
+3VS
PCIRST#
1
C297
2
@ 0_0402_5%
2
@ 0_0402_5%
PCI_GNT#0
A
SPI_CS#1
Boot BIOS Loaction
SPI
PCI
LPC*
1
R257
2
0_0402_5%
Compal Secret Data
2007/08/18
Issued Date
Deciphered Date
2008/8/18
5
Title
ICH9M(1/4)-PCI
Size
Document Number

Date:
Sheet
1
20
of
49
Rev
0.4
12/7 Modified X4 to SJ100001U00 10ppm

ICH_RTCX1
R263
10M_0402_5%
2
1
OUT
NC
IN
32.768KHZ_12.5P_1TJS125BJ2A251
Need check
GPIO33
20K_0402_5%
GPIO56
1
R278
1
R279
1
R281
1
R282
+1.5VS
HDA_SDIN1
100P_0402_50V8J
<40> HDA_BITCLK_MDC
<40> HDA_SYNC_MDC
<40> HDA_RST_MDC#
<36>
<40>
<10>
<17>
HDA_SDIN0
HDA_SDIN1
HDA_SDIN2
HDA_SDIN3
1
R285
<40> HDA_SDOUT_MDC
PAD
T9
GLAN_COMP
2
24.9_0402_1%
HDA_BITCLK_ICH
2
33_0402_5%
HDA_SYNC_ICH
2
33_0402_5%
HDA_RST_ICH#
2
33_0402_5%
HDA_SDIN0
HDA_SDIN1
HDA_SDIN2
HDA_SDIN3
SATA_LED#
<40> SATA_LED#
SATA HDD
<36> HDA_SYNC_AUDIO
<36> HDA_RST_AUDIO#
<36> HDA_SDOUT_AUDIO
SATA_DTX_C_IRX_N0
SATA_DTX_C_IRX_P0
SATA_ITX_DRX_N0
SATA_ITX_DRX_P0
<24> SATA_DTX_C_IRX_N1
<24> SATA_DTX_C_IRX_P1
HDA_BITCLK_ICH
2
33_0402_5%
HDA_SYNC_ICH
2
33_0402_5%
HDA_RST_ICH#
2
33_0402_5%
HDA_SDOUT_ICH
2
33_0402_5%
1
R288
1
R289
1
R290
1
R291
<36> HDA_BITCLK_AUDIO
INTVRMEN
LAN100_SLP
<17> HDA_SDOUT_MXM
<10> HDA_BITCLK_NB
<10> HDA_SYNC_NB
<10> HDA_RST_NB#
<10> HDA_SDOUT_NB
1
R292
1
R293
1
R294
1
R295
HDA_BITCLK_ICH
2
GM@ 33_0402_5%
HDA_SYNC_ICH
2
GM@ 33_0402_5%
HDA_RST_ICH#
2
GM@ 33_0402_5%
HDA_SDOUT_ICH
2
GM@ 33_0402_5%
Need check
SATA_DTX_C_IRX_N1
SATA_DTX_C_IRX_P1
SATA_ITX_DRX_N1
SATA_ITX_DRX_P1
LAN_RXD0
LAN_RXD1
LAN_RXD2
LAN_TXD_0
LAN_TXD_1
LAN_TXD_2
B10
GPIO56
B28
B27
GLAN_COMPI
GLAN_COMPO
AF6
AH4
HDA_BIT_CLK
HDA_SYNC
GPIO33
R297
1K_0402_5%
@
AF4
AG4
AH3
AE5
HDA_SDIN0
HDA_SDIN1
HDA_SDIN2
HDA_SDIN3
AG5
HDA_SDOUT
AG7
AE8
HDA_DOCK_EN#/GPIO33
HDA_DOCK_RST#/GPIO34
AG8
SATALED#
AJ16
AH16
AF17
AG17
SATA0RXN
SATA0RXP
SATA0TXN
SATA0TXP
AH13
AJ13
AG14
AF14
SATA1RXN
SATA1RXP
SATA1TXN
SATA1TXP
<22>
ICH_TP3
R298
1K_0402_5%
@
<24> SATA_ITX_C_DRX_N0
<24> SATA_ITX_C_DRX_P0
SATA_ITX_C_DRX_P0
1
C303
1
C305
FERR#
AJ26
FERR#
CPUPWRGD
AD22
H_PWRGOOD
IGNNE#
AF25
H_IGNNE#
INIT#
INTR
RCIN#
AE22
AG25
L3
H_INIT#
H_INTR
KB_RST#
NMI
SMI#
AF23
AF24
H_NMI
H_SMI#
STPCLK#
AH27
H_STPCLK#
THRMTRIP#
AG26
THRMTRIP_ICH#
TP12
AG27
SATA4RXN
SATA4RXP
SATA4TXN
SATA4TXP
AH11
AJ11
AG12
AF12
2
2
1
R276
H_DPRSTP# <5,8,48>
H_DPSLP# <5>
H_FERR#
2
56_0402_5%
H_FERR# <4>
H_PWRGOOD <5>
H_IGNNE# <4>
R277
H_INIT# <4>
H_INTR <4>
H_NMI <4>
H_SMI# <4>
H_STPCLK# <4>
R283 1
AH9
AJ9
AE10
AF10
SATA_CLKN
SATA_CLKP
SATARBIAS#
SATARBIAS
AH18
AJ18
AJ7
AH7
+3VS
R308 need to place within 2" of ICH9M

R310 must be place within 2" of R308 w/o stub.
2 54.9_0402_1%
H_THERMTRIP#
2
R284
SATA ODD
SATA5RXN
SATA5RXP
SATA5TXN
SATA5TXP
1 10K_0402_5%
KB_RST# <32>
SATA_DTX_C_IRX_N4
SATA_DTX_C_IRX_P4
SATA_ITX_DRX_N4
SATA_ITX_DRX_P4
T24
T25
T26
T27
1
56_0402_5%
CLK_PCIE_SATA# <16>
CLK_PCIE_SATA <16>
R287 2
+1.05VS
MAINPWON <43,45>
R286
@ 330_0402_5%
1
2 2
B
Q7
E
CLK_PCIE_SATA#
CLK_PCIE_SATA
SATARBIAS
2SC2411K_SOT23
@
H_THERMTRIP#
1 24.9_0402_1%
4mils width less than 500mils
SATA_ITX_DRX_N1
1
C304
SATA_ITX_DRX_P1
1
C306
SATA_ITX_C_DRX_N1
0.01U_0402_16V7K
SATA_ITX_C_DRX_P1
0.01U_0402_16V7K
2
2
SATA_ITX_C_DRX_N1 <24>
SATA_ITX_C_DRX_P1 <24>
Change BATT1 P/N : SP093PA0200 (Panasonic)

SP093MX0000 (MAXELL)
HDA_BITCLK_ICH
C738
100P_0402_50V8J
R630
10_0402_5%
@
9/29 modified to follow ISKAA
C648
10P_0402_50V8J
@
D11
+RTC_BATT
BATT1
R296
+RTCBATT1
2
2
511_0603_1%
1
ML1220T13RE
@
+CHGRTC
1
3
+RTCVCC
BAS40-04_SOT23
Description
RSVD
Enter XOR Chain
Normal Operation
Set PCIE port config bit 1
H_THERMTRIP# <4,8>
PAD @
PAD @
PAD @
PAD @
+1.05VS
C307
0.1U_0402_16V4Z
9/29 Checked. Same as HEL80's
Compal Secret Data
2007/08/18
Issued Date
Deciphered Date
2008/8/18
5
0_0402_5% H_DPRSTP#
0_0402_5% H_DPSLP#
2 SATA_ITX_DRX_N0
0.01U_0402_16V7K
2 SATA_ITX_DRX_P0
0.01U_0402_16V7K
H_DPRSTP#
DPRSTP# R274 1
DPSLP#
R275 1
+3VS
close ICH9
SATA_ITX_C_DRX_N0
XOR Chain Entrance Strap
AJ25
AE23
1 8.2K_0402_5%
GATEA20 <32>
H_A20M# <4>
RTC Battery
Low= Descriptor Security override

High= Default* (Internal pull-up)
HDA_SDOUT
DPRSTP#
DPSLP#
LPC_DRQ0# <35>
R273 2
1
@ 56_0402_5%
1
@ 56_0402_5%
1
56_0402_5%
ICH9-M ES_FCBGA676
ICH_TP3
HDA_SDOUT_ICH
GATEA20
H_A20M#
HDA_RST#
Flash Descriptor Security Override Strap
+3VS
A20GATE
A20M#
N7
AJ27
ai
<17> HDA_RST_MXM#
HDA_BITCLK_ICH
2
PM@ 33_0402_5%
HDA_SYNC_ICH
2
PM@ 33_0402_5%
HDA_RST_ICH#
2
PM@ 33_0402_5%
HDA_SDOUT_ICH
2
PM@ 33_0402_5%
LPC_DRQ0#
H_DPRSTP#
R268
H_DPSLP#
R272
H_FERR#
R270
LPC_FRAME# <32,35,40>
<17> HDA_SYNC_MXM
1
R626
1
R627
1
R628
1
R629
LDRQ0#
LDRQ1#/GPIO23
J3
J1
LAN_RSTSYNC
<17> HDA_BITCLK_MXM
LPC_FRAME#
GLAN_CLK
D13
D12
E13
AE7
2 HDA_SDOUT_ICH
33_0402_5%
@ GPIO33
K3
+1.05VS
om
1
R663
FWH4/LFRAME#
<32,35,40>
<32,35,40>
<32,35,40>
<32,35,40>
l.c
2 GPIO56
10K_0402_5%
1
R675
C751
+3VALW
RTCRST#
SRTCRST#
INTRUDER#
LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
nf
@
ho
tm
close to
SATA_LED#
10K_0402_5%
LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
Title
ICH9M(2/4)-LAN,IDELPC,RTC
Custom
Rev
0.4
ai
K5
K4
L6
K2
Date:
he
x
1
R664
FWH0/LAD0
FWH1/LAD1
FWH2/LAD2
FWH3/LAD3
RTCX1
RTCX2
+RTCVCC
+3VS
U7A
C23
ICH_RTCX2
C24
1
15P_0402_50V8J
ICH_RTCRST#
1
2
A25
R266
ICH_SRTCRST#
F20
1
2
+RTCVCC
R267
SM_INTRUDER#
20K_0402_5%
C22
180K_0402_5%
ICH_INTVRMEN
B22
RAM door
close to RAM door
LAN100_SLP
A22
@
2
1
1
2
J2 @
JOPEN
R271
E25
10K_0603_5%
R662
R661
C300
C301
@
@
C13
1U_0603_10V4Z
0.1U_0402_16V4Z
0_0402_5% 0_0402_5%
1
2
1
2
F14
G13
D14
2
C302
R265
2 LAN100_SLP
330K_0402_5%
NC
LPC
2 ICH_INTVRMEN
330K_0402_5%
CPU
R262
RTC
X1
LAN / GLAN
C299
15P_0402_50V8J
2
1
2 SM_INTRUDER#
1M_0402_5%
IHDA
+RTCVCC
R258
ICH9M Internal VR Enable Strap

(Internal VR for VccSus1.05, VccSus1.5, VccCL1.5)
Low = Internal VR Disabled
ICH_INTVRMEN High = Internal VR Enabled(Default)
ICH9M LAN100 SLP Strap
(Internal VR for VccLAN1.05 and VccCL1.05)
Low = Internal VR Disabled
ICH_LAN100_SLP High = Internal VR Enabled(Default)
SATA
Sheet
21
of
49
<40> SUS_STAT#
<4> ITP_DBRESET#
PM_BMBUSY#
<8> PM_BMBUSY#
GPIO7
<32> EC_LID_OUT#
SATA_CLKREQ#
OCP#
D_ACIN
CR_WAKE#
<16> PM_STP_PCI#
<16> PM_STP_CPU#
SERIRQ
GPIO38
GPIO48
GPIO39
PAD
T12
D12 1
<32,42,44> ACIN
PAD
T14
<26> CR_WAKE#
<16> SATA_CLKREQ#
follow iTPM spec
No Reboot Strap
SB_SPKR
100K_0402_5%
ICH_GPIO57
R329 1
@
2
10K_0402_5%
R330 1
@
2
VRMPWRGD
A20
TP11
AG19
AH21
AG21
A21
C12
C21
AE18
K1
AF8
AJ22
A9
D19
L1
AE19
AG22
AF21
AH24
A8
GPIO1
GPIO6
GPIO7
GPIO8
GPIO12
GPIO13
GPIO17
GPIO18
GPIO20
SCLOCK/GPIO22
GPIO27
GPIO28
SATACLKREQ#/GPIO35
SLOAD/GPIO38
SDATAOUT0/GPIO39
SDATAOUT1/GPIO48
GPIO49
GPIO57/CLGPIO5
M7
AJ24
B21
AH20
AJ20
AJ21
SPKR
MCH_SYNC#
TP3
TP8
TP9
TP10
1
2
CLPWROK
PM_SLP_M#
2
0_0402_5%
Check
1
R325
CK_PWRGD <16>
2
SLP_M#
B16
F24
B19
CL_CLK0 <8>
CL_DATA0
CL_DATA1
F22
C19
CL_DATA0 <8>
CL_VREF0
CL_VREF1
C25
A19
CL_RST0#
CL_RST1#
F21
D18
MEM_LED/GPIO24
GPIO10/SUS_PWR_ACK
GPIO14/AC_PRESENT
WOL_EN/GPIO9
A16
C18
C11
C20
PAD
PM_DPRSLPVR_D
C737 1
100P_0402_50V8J
2 @
ICH_PCIE_WAKE#
C730 1
100P_0402_50V8J
2 @
VGATE
C740 1
100P_0402_50V8J
2 @
ICH_SMBCLK
C741 1
100P_0402_50V8J
2 @
ICH_SMBDATA
C742 1
100P_0402_50V8J
2 @
ICH_PWROK <8,32>
0_0402_5%
CL_CLK0
CL_CLK1
C309
10P_0402_50V8J
@
T13
CL_VREF0_ICH
CL_VREF1_ICH
C
CL_RST#0 <8>
GPIO10
GPIO14
DMI Termination Voltage

GPIO49
Low= Desktop used

High= Mobile* (Internal pull-up)
J29
J28
K27
K26
PERN3
PERP3
PETN3
PETP3
For PCIE LAN
<28>
<28>
<28>
<28>
PCIE_PTX_C_IRX_N4
PCIE_PTX_C_IRX_P4
PCIE_ITX_C_PRX_N4
PCIE_ITX_C_PRX_P4
C317 2
C318 2
1
1
PCIE_PTX_C_IRX_N4
PCIE_PTX_C_IRX_P4
0.1U_0402_10V7K
PCIE_ITX_PRX_N4
PCIE_ITX_PRX_P4
0.1U_0402_10V7K
G29
G28
H27
H26
PERN4
PERP4
PETN4
PETP4
<26>
<26>
<26>
<26>
PCIE_PTX_C_IRX_N5
PCIE_PTX_C_IRX_P5
PCIE_ITX_C_PRX_N5
PCIE_ITX_C_PRX_P5
C319 2
C320 2
1
1
PCIE_PTX_C_IRX_N5
PCIE_PTX_C_IRX_P5
0.1U_0402_10V7K
PCIE_ITX_PRX_N5
PCIE_ITX_PRX_P5
0.1U_0402_10V7K
E29
E28
F27
F26
PERN5
PERP5
PETN5
PETP5
C29
C28
D27
D26
PERN6/GLAN_RXN
PERP6/GLAN_RXP
PETN6/GLAN_TXN
PETP6/GLAN_TXP
follow iTPM spec

<34> ICH_SPI_CLK_R
<34> ICH_SPI_CS0#_R
<20> SPI_CS#1
R345
R346
@
@
15_0402_5%
15_0402_5%
ICH_SPI_CLK
ICH_SPI_CS0#
D23
D24
F23
SPI_CLK
SPI_CS0#
SPI_CS1#GPIO58/CLGPIO6
ICH_SPI_MOSI_R
R348
15_0402_5%
ICH_SPI_MOSI
ICH_SPI_MISO
D25
E23
SPI_MOSI
SPI_MISO
<35> USB_OC#04
ID0
JHT01 ( 01 )
R361
R355
<35> USB_OC#511
JHL90 ( 10 )
R360
R357
<31> CP_PE#
R361
10K_0402_5%
01@
USB_OC#04
USB_OC#1
USB_OC#2
USB_OC#3
R355
10K_0402_5%
01@
USB_OC#6
CP_PE#
USB_OC#8
USB_OC#9
USB_OC#10
USBRBIAS
R360
2
1
R356
22.6_0402_1%
R357
N4
N5
N6
P6
M1
N2
M4
M3
N3
N1
P5
P3
AG2
AG1
OC0#/GPIO59
OC1#/GPIO40
OC2#/GPIO41
OC3#/GPIO42
OC4#/GPIO43
OC5#/GPIO29
OC6#/GPIO30
OC7#/GPIO31
OC8#/GPIO44
OC9#/GPIO45
OC10#/GPIO46
OC11#/GPIO47
V27
V26
U29
U28
DMI_MTX_IRX_N0
DMI_MTX_IRX_P0
DMI_ITX_MRX_N0
DMI_ITX_MRX_P0
DMI1RXN
DMI1RXP
DMI1TXN
DMI1TXP
Y27
Y26
W29
W28
DMI_MTX_IRX_N1
DMI_MTX_IRX_P1
DMI_ITX_MRX_N1
DMI_ITX_MRX_P1
DMI2RXN
DMI2RXP
DMI2TXN
DMI2TXP
AB27
AB26
AA29
AA28
DMI_MTX_IRX_N2
DMI_MTX_IRX_P2
DMI_ITX_MRX_N2
DMI_ITX_MRX_P2
DMI3RXN
DMI3RXP
DMI3TXN
DMI3TXP
AD27
AD26
AC29
AC28
DMI_MTX_IRX_N3
DMI_MTX_IRX_P3
DMI_ITX_MRX_N3
DMI_ITX_MRX_P3
T26
T25
CLK_PCIE_ICH#
CLK_PCIE_ICH
DMI_CLKN
DMI_CLKP
DMI_ZCOMP
DMI_IRCOMP
ICH_SPI_CLK_R
ICH_SPI_CS0#_R
12/13 Modified
by Andy
DMI0RXN
DMI0RXP
DMI0TXN
DMI0TXP
SPI
USB
USBP0N
USBP0P
USBP1N
USBP1P
USBP2N
USBP2P
USBP3N
USBP3P
USBP4N
USBP4P
USBP5N
USBP5P
USBP6N
USBP6P
USBP7N
USBP7P
USBP8N
USBP8P
USBP9N
USBP9P
USBP10N
USBP10P
USBP11N
USBP11P
AF29
AF28
AC5
AC4
AD3
AD2
AC1
AC2
AA5
AA4
AB2
AB3
AA1
AA2
W5
W4
Y3
Y2
W1
W2
V2
V3
U5
U4
U1
U2
DMI_IRCOMP
DMI_MTX_IRX_N0
DMI_MTX_IRX_P0
DMI_ITX_MRX_N0
DMI_ITX_MRX_P0
<8>
<8>
<8>
<8>
RSMRST circuit
DMI_MTX_IRX_N1
DMI_MTX_IRX_P1
DMI_ITX_MRX_N1
DMI_ITX_MRX_P1
<8>
<8>
<8>
<8>
DMI_MTX_IRX_N2
DMI_MTX_IRX_P2
DMI_ITX_MRX_N2
DMI_ITX_MRX_P2
<8>
<8>
<8>
<8>
DMI_MTX_IRX_N3
DMI_MTX_IRX_P3
DMI_ITX_MRX_N3
DMI_ITX_MRX_P3
<8>
<8>
<8>
<8>
R332
0_0402_5%
1
2
<EMI>
Q8
3
1
<32> EC_RSMRST#
@ BAV99DW-7_SOT363
PCIE_PTX_C_IRX_N3
PCIE_PTX_C_IRX_P3
0.1U_0402_10V7K
PCIE_ITX_PRX_N3
PCIE_ITX_PRX_P3
0.1U_0402_10V7K
R357
EC_RSMRST#R
R335
@ 2.2K_0402_5%
D13B
@ MMBT3906_SOT23
1
2
+3VALW
R334
@ 4.7K_0402_5%
D13A @
BAV99DW-7_SOT363
R336
2
B
@ 2.2K_0402_5%
CLK_PCIE_ICH# <16>
CLK_PCIE_ICH <16>
R340 24.9_0402_1%
1
2
USB20_N0
USB20_P0
USB20_N1
USB20_P1
USB20_N2
USB20_P2
USB20_N3
USB20_P3
Within 500 mils
ICH_PWROK
1
R338
2
10K_0402_5%
EC_RSMRST#R
1
R342
2
10K_0402_5%
+1.5VS_PCIE_ICH
USB20_N0
USB20_P0
USB20_N1
USB20_P1
USB20_N2
USB20_P2
USB20_N3
USB20_P3
<35>
<35>
<40>
<40>
<40>
<40>
<30>
<30>
USB20_N5
USB20_P5
USB20_N6
USB20_P6
<35>
<35>
<34>
<34>
USB(IO/B)
FP
CAMERA
WLAN
+3VS
USB20_N5
USB20_P5
USB20_N6
USB20_P6
+3VALW
USB(IO/B)
R349
BT
R350
@
3.24K_0402_1%
3.24K_0402_1%
USB20_N8
USB20_P8
USB20_N8 <30>
USB20_P8 <30>
USB20_N10
USB20_P10
USB20_N11
USB20_P11
USB20_N10
USB20_P10
USB20_N11
USB20_P11
<31>
<31>
<35>
<35>
CL_VREF0_ICH
TV
C323
New Card
0.1U_0402_16V4Z
2
USB(IO/B)
CL_VREF1_ICH
R353
453_0402_1%
1
C324
@
0.1U_0402_16V4Z
2
R354
@
453_0402_1%
A
USBRBIAS
USBRBIAS#
ICH9-M ES_FCBGA676
Within 500 mils

10K_0402_5%
90@
R6
1
1
R361
00@ 10K_0402_5%
R361 1
2 PROJECT_ID1
CLPWROK
C315 2
C316 2
ID1
91@ 10K_0402_5%
R360 1
2
CK_PWRGD
PCIE_PTX_C_IRX_N3
PCIE_PTX_C_IRX_P3
PCIE_ITX_C_PRX_N3
PCIE_ITX_C_PRX_P3
00@ 10K_0402_5%
R357 1
2 PROJECT_ID0
+3VS
R5
PERN2
PERP2
PETN2
PETP2
JHT00 ( 00 )
91@ 10K_0402_5%
R355 1
2
PM_DPRSLPVR_D <8,48>
PBTN_OUT# <32>
D22
L29
L28
M27
M26
+3VS
C308
10P_0402_50V8J
@
IFT use 100 ohm
CK_PWRGD
PCIE_PTX_C_IRX_N2
PCIE_PTX_C_IRX_P2
0.1U_0402_10V7K
PCIE_ITX_PRX_N2
PCIE_ITX_PRX_P2
0.1U_0402_10V7K
<30>
<30>
<30>
<30>
USB_OC#9
USB_OC#6
USB_OC#8
R355
RSMRST#
2
0_0402_5%
1
R317
EC_RSMRST#R
1
1
PCIE_PTX_C_IRX_N2
PCIE_PTX_C_IRX_P2
PCIE_ITX_C_PRX_N2
PCIE_ITX_C_PRX_P2
<34> ICH_SPI_MISO
R360
LAN_RST#
C313 2
C314 2
<30>
<30>
<30>
<30>
<34> ICH_SPI_MOSI_R
JHL91 ( 11 )
PBTN_OUT#
D20
1
1
For Robson
For CardReader
ICH_SPI_MOSI
2
20K_0402_5%
ICH_SPI_MOSI
2
10K_0402_5%
R3
DPRSLPVR
1
R313
PM_BATLOW#
ICH9-M ES_FCBGA676
10K_1206_8P4R_5%
B13
PWRBTN#
T11
PM_SLP_S3# <32>
PM_SLP_S4# <32>
PM_SLP_S5# <32>
BATLOW#
LAN_RST#
PAD
USB_OC#1
USB_OC#2
USB_OC#10
USB_OC#3
RP39
ICH_PWROK
M2
DPRSLPVR/GPIO16
PERN1
PERP1
PETN1
PETP1
C311 2
C312 2
10K_1206_8P4R_5%
R347
G20
N29
N28
P27
P26
For Express Card
RP36
R344
C10
PWROK
PCIE_PTX_C_IRX_N1
PCIE_PTX_C_IRX_P1
0.1U_0402_10V7K
PCIE_ITX_PRX_N1
PCIE_ITX_PRX_P1
0.1U_0402_10V7K
PCIE_PTX_C_IRX_N1
PCIE_PTX_C_IRX_P1
PCIE_ITX_C_PRX_N1
PCIE_ITX_C_PRX_P1
For Wireless LAN
+3VALW
4
3
2
1
WAKE#
SERIRQ
THRM#
S4_STATE#/GPIO26
R310
10_0402_5%
@
U7D
100K_0402_5%
R333 1
ICH_VGATE
2
5
6
7
8
CLKRUN#
D21
Low= Default*
High= "No Reboot"
<31>
<31>
<31>
<31>
ICH_GPIO49
100K_0402_5%
R331 1
@
PM_DPRSLPVR_D
2
4
3
2
1
PM_SLP_S3#
PM_SLP_S4#
PM_SLP_S5#
R309
10_0402_5%
@
CLK_ICH_14M <16>
CLK_ICH_48M <16>
1 2
PM_BATLOW#
STP_PCI#
STP_CPU#
PMSYNC#/GPIO0
CLK_ICH_14M
8.2K_0402_5%
R326 2
1
+3VS
<36> SB_SPKR
<8> MCH_ICH_SYNC#
<21> ICH_TP3
SUS_CLK
2 10K_0402_5%
ICH_PCIE_WAKE#
R327
P1
C16
E16
G17
Place closely pin AC1
CLK_ICH_48M
1K_0402_5%
R324 1
2
A14
E19
SATA_CLKREQ#
GPIO38
GPIO39
GPIO48
ICH_GPIO49
ICH_GPIO57
@
2 1K_0402_5%
SB_SPKR
MCH_ICH_SYNC#
ICH_TP3
SUSCLK
SLP_S3#
SLP_S4#
SLP_S5#
Place closely pin B2
ICH_GPIO57
SMBALERT#/GPIO11
PM_STP_PCI#
PM_STP_CPU#
E20
M5
AJ23
CLK_ICH_14M
CLK_ICH_48M
CLK14
CLK48
10K_0402_5%
2
SINGLE@
R307
MIC_ID
1
2
DUAL@ 10K_0402_5%
R301 1
10K_0402_5%
R709 1
@
2
A17
GPIO18
@ ICH_GPIO20
CR_WAKE#
<26> GPIO18
ITP_DBRESET#
GPIO14
GPIO10
EC_LID_OUT#
EC_SCI#
<32> EC_SCI#
4
3
2
1
M6
L4
H1
AF3
SATA0GP/GPIO21
SATA1GP/GPIO19
SATA4GP/GPIO36
SATA5GP/GPIO37
clocks
PM_BMBUSY#
OCP#
D_ACIN
GPIO7
EC_SMI#
<32> EC_SMI#
RP46
5
6
7
8
SUS_STAT#/LPCPD#
SYS_RESET#
2
1 ICH_VGATE
R316
0_0402_5%
@ ICH_TP11
<8,16,48> VGATE
10K_1206_8P4R_5%
R4
G19
SMB
PROJECT_ID1
PROJECT_ID0
MIC_ID
R308 1
10K_1206_8P4R_5%
RP38
ICH_RI#
5
4
ICH_SMLINK1
6
3
ICH_SMLINK0
7
2
LINKALERT#
8
1
10K_1206_8P4R_5%
SUS_STAT#
ITP_DBRESET#
SMBCLK
SMBDATA
LINKALERT#/GPIO60/CLGPIO4
SMLINK0
SMLINK1
AH23
AF19
AE21
AD20
4
3
2
1
5
6
7
8
RI#
ICH_PCIE_WAKE#
SERIRQ
EC_THERM#
<28,30,31> ICH_PCIE_WAKE#
<32,35,40> SERIRQ
<32> EC_THERM#
RP45
+3VALW
F19
PM_CLKRUN#
<32,40> PM_CLKRUN#
10K_1206_8P4R_5%
5
6
7
8
ICH_RI#
PM_STP_CPU#
10K_0402_5%
R676 1
@
2
10K_0402_5%
R732 1
2
RP37
5
4
6
3
7
2
8
1
G16
A13
E17
C17
B18
Direct Media Interface
PM_STP_PCI#
10K_0402_5%
R305 1
@
2
+3VS
U7C
ICH_SMBCLK
ICH_SMBDATA
LINKALERT#
ICH_SMLINK0
ICH_SMLINK1
PCI - Express
10K_0402_5%
R304 1
@
2
2 2.2K_0402_5%
SATA
GPIO
EC_THERM#
R300 1
12/13 Add
Power MGT
PM_CLKRUN#
8.2K_0402_5%
R311 1
2
2 2.2K_0402_5%
SYS / GPIO
8.2K_0402_5%
R303 1
2
R299 1
+3VALW
MISC
GPIO
Controller Link
+3VS
Internal TPM Strap
10K_0402_5%
90@
SPI_MOSI
Low= Disable
High= iTPM enable by MCH strap*
4
Issued Date
Compal Secret Data
2007/08/18
2008/8/18
Deciphered Date
3
Title
ICH9M(3/4)-USB,GPIO,PCIE
Custom
Rev
0.4
Date:
Sheet

1
22
of
49
646mA
+1.5VS_PCIE_ICH
L23 2
1
KC FBM-L11-201209-221LMAT_0805
1
+1.5VS
10/22 CRB use 330 Ohm@100Mhz,

We use 220 Ohm 3A check!
C337
(220UF*1, 22UF*2, 2.2UF*1)

C335
C336
C338
220U_D2_4VM_R15
10U_0805_10V4Z
2
2
2
10U_0805_10V4Z
2.2U_0603_6.3V6K
+1.5VS_SATAPLL_R
+1.5VS_SATAPLL_ICH
+1.5VS
R367
0_0603_5%
(10UF*1, 1UF*1)
L24 1
2
MBK1608121YZF_0603
C348
(10UF*1, 1UF*1)
C349
10U_0805_10V4Z
2 1U_0402_6.3V4Z
2
47mA
AJ19
C351
1U_0402_6.3V4Z
1342mA
+1.5VS
C355
AC9
10/22 follow common design 0928
VCC1_5_A[18]
VCC1_5_A[19]
VCC1_5_A[20]
G10
G9
VCC1_5_A[21]
VCC1_5_A[22]
AC12
AC13
AC14
VCC1_5_A[23]
VCC1_5_A[24]
VCC1_5_A[25]
11mA
+1.5VS
(0.1UF*1)
11mA
0.1U_0402_16V4Z
(0.1UF*1)
+3VS
C362
1
2
C361
1 +VCCLAN1_05_INT_ICH
0.1U_0402_16V4Z
19mA
2
0.1U_0402_16V4Z
AJ5
VCCUSBPLL
AA7
AB6
AB7
AC6
AC7
VCC1_5_A[26]
VCC1_5_A[27]
VCC1_5_A[28]
VCC1_5_A[29]
VCC1_5_A[30]
A10
A11
VCCLAN1_05[1]
VCCLAN1_05[2]
A12
B12
VCCLAN3_3[1]
VCCLAN3_3[2]
23mA
R372
0_0603_5%
(2.2UF*1,
1
2 +VCC_GLANPLL_ICH
MBK1608121YZF_0603 1
L25
C367
C366
10UF*1) 10U_0805_10V4Z
2
2.2U_0603_6.3V6K
80mA
(4.7UF*1)
A27
VCCGLANPLL
D28
D29
E26
E27
VCCGLAN1_5[1]
VCCGLAN1_5[2]
VCCGLAN1_5[3]
VCCGLAN1_5[4]
A26
+1.5VS_PCIE_ICH
C332
VCCGLAN3_3
R364
0_0603_5%
+1.5VS
(10UF*1, 0.01UF*1)
C333
VCC_DMI
23mA
R366
VCCDMIPLL
VCC_DMI[1]
VCC_DMI[2]
W23
Y23
V_CPU_IO[1]
V_CPU_IO[2]
AB23
AC23
VCC3_3[01]
VCC3_3[02]
VCC3_3[07]
AG29
AJ6
AC10
VCC3_3[03]
VCC3_3[04]
VCC3_3[05]
VCC3_3[06]
AD19
AF20
AG24
AC20
VCC3_3[08]
VCC3_3[09]
VCC3_3[10]
VCC3_3[11]
VCC3_3[12]
VCC3_3[13]
VCC3_3[14]
B9
F9
G3
G6
J2
J7
K7
0_0603_5% +1.05VS
(22UF*1)
4.7U_0805_10V4Z
2
48mA
2mA
+1.05VS
C339
C340
1
C341(4.7UF*1,
0.1UF*2)
4.7U_0805_10V4Z
0.1U_0402_16V4Z
2
2
0.1U_0402_16V4Z
close to AG29
close to AC20
close to G6 308mA
+3VS
VCCHDA
AJ4
VCCSUSHDA
AJ3
C342
C343
C344
C345
C346
C347
(0.1UF*6)
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
2
2
2
2
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
close to AD19
11mA
close to B9
close to K7
+VCC_HDA_ICH
11mA
(0.1UF*1) 1
VCCSUS1_05[1]
VCCSUS1_05[2]
AC8 TP_VCCSUS1_05_ICH_1
F17 TP_VCCSUS1_05_ICH_2
@
@
PAD
PAD
T15
T16
VCCSUS1_5[1]
AD8 TP_VCCSUS1_5_ICH_1
PAD
T17
VCCSUS1_5[2]
F18
VCCSUS3_3[01]
VCCSUS3_3[02]
VCCSUS3_3[03]
VCCSUS3_3[04]
A18
D16
D17
E22
VCCSUS3_3[05]
AF1
PM@
R368
0_0603_5%
GM@
R369
0_0603_5%
0.1U_0402_16V4Z
C350
+3VALW
+3VS
+1.5VS
R671
180_0402_1%
@
(0.1UF*1)
VCCCL1_05
VCCCL1_5
VCCCL3_3[1]
VCCCL3_3[2]
1 GM@
2
R798
0_0402_5%
(0.1UF*1) 1
C353
0.1U_0402_16V4Z
C354
R670
150_0402_1%
@
0.1U_0402_16V4Z
(0.1UF*1, 0.022UF*2)
+3VALW
C356
0.1U_0402_16V4Z
VCCSUS3_3[06]
VCCSUS3_3[07]
VCCSUS3_3[08]
VCCSUS3_3[09]
VCCSUS3_3[10]
VCCSUS3_3[11]
VCCSUS3_3[12]
VCCSUS3_3[13]
VCCSUS3_3[14]
VCCSUS3_3[15]
VCCSUS3_3[16]
VCCSUS3_3[17]
VCCSUS3_3[18]
VCCSUS3_3[19]
VCCSUS3_3[20]
+VCCSUS_HDA_ICH
+VCCSUS1_5_ICH_INT_2
212mA
GLAN POWER
+1.5VS
A
+VCC_GLANPLL_R
+1.5VS_DMIPLL_R
TP_VCCSUS1_5_ICH_1
USB CORE
C360
@
220U_D2_4VM_R15
10U_0805_10V4Z
2
0.01U_0402_16V7K
R29
VCC1_5_A[17]
AC21
C358
0.1U_0402_16V4Z
VCC1_5_A[09]
VCC1_5_A[10]
VCC1_5_A[11]
VCC1_5_A[12]
VCC1_5_A[13]
VCC1_5_A[14]
VCC1_5_A[15]
VCC1_5_A[16]
AC18
AC19
+1.5VS
VCC1_5_A[01]
VCC1_5_A[02]
VCC1_5_A[03]
VCC1_5_A[04]
VCC1_5_A[05]
VCC1_5_A[06]
VCC1_5_A[07]
VCC1_5_A[08]
L22 1
2
MBK1608121YZF_0603
VCCSATAPLL
ATX
1U_0402_6.3V4Z
AC11
AD11
AE11
AF11
AG10
AG11
AH10
AJ10
+1.5VS_DMIPLL_ICH
C334
ARX
AC16
AD15
AD16
AE15
AF15
AG15
AH15
AJ15
+1.5VS
0.1U_0402_16V4Z
2
2
0.1U_0402_16V4Z
T1
T2
T3
T4
T5
T6
U6
U7
V6
V7
W6
W7
Y6
Y7
T7
C357
R671
0.1U_0402_16V4Z
2
0_0402_5%
PM@
+3VALW
C359
4.7U_0805_10V4Z
G22 +VCCCL1_05_INT_ICH
G23 +VCCCL1_5_INT_ICH
A24
B24
+3VS
19mA
1
1
1
C363
C365
C364
(0.1UF*1)
@
@
1U_0402_6.3V4Z
0.1U_0402_16V4Z
2
2
2
0.1U_0402_16V4Z
VSS[001]
VSS[002]
VSS[003]
VSS[004]
VSS[005]
VSS[006]
VSS[007]
VSS[008]
VSS[009]
VSS[010]
VSS[011]
VSS[012]
VSS[013]
VSS[014]
VSS[015]
VSS[016]
VSS[017]
VSS[018]
VSS[019]
VSS[020]
VSS[021]
VSS[022]
VSS[023]
VSS[024]
VSS[025]
VSS[026]
VSS[027]
VSS[028]
VSS[029]
VSS[030]
VSS[031]
VSS[032]
VSS[033]
VSS[034]
VSS[035]
VSS[036]
VSS[037]
VSS[038]
VSS[039]
VSS[040]
VSS[041]
VSS[042]
VSS[043]
VSS[044]
VSS[045]
VSS[046]
VSS[047]
VSS[048]
VSS[049]
VSS[050]
VSS[051]
VSS[052]
VSS[053]
VSS[054]
VSS[055]
VSS[056]
VSS[057]
VSS[058]
VSS[059]
VSS[060]
VSS[061]
VSS[062]
VSS[063]
VSS[064]
VSS[065]
VSS[066]
VSS[067]
VSS[068]
VSS[069]
VSS[070]
VSS[071]
VSS[072]
VSS[073]
VSS[074]
VSS[075]
VSS[076]
VSS[077]
VSS[078]
VSS[079]
VSS[080]
VSS[081]
VSS[082]
VSS[083]
VSS[084]
VSS[085]
VSS[086]
VSS[087]
VSS[088]
VSS[089]
VSS[090]
VSS[091]
VSS[092]
VSS[093]
VSS[094]
VSS[095]
VSS[096]
VSS[097]
VSS[098]
VSS[099]
VSS[100]
VSS[101]
VSS[102]
VSS[103]
VSS[104]
VSS[105]
VSS[106]
VSS[107]
VSS[108]
VSS[109]
VSS[110]
VSS[111]
VSS[112]
VSS[113]
VSS[114]
VSS[115]
VSS[116]
VSS[117]
VSS[118]
VSS[119]
VSS[120]
VSS[121]
VSS[122]
VSS[123]
VSS[124]
VSS[125]
VSS[126]
VSS[127]
VSS[128]
VSS[129]
VSS[130]
VSS[131]
VSS[132]
VSS[133]
VSS[134]
VSS[135]
VSS[136]
VSS[137]
VSS[138]
VSS[139]
VSS[140]
VSS[141]
VSS[142]
VSS[143]
VSS[144]
VSS[145]
VSS[146]
VSS[147]
VSS[148]
VSS[149]
VSS[150]
VSS[151]
VSS[152]
VSS[153]
VSS[154]
VSS[155]
VSS[156]
VSS[157]
VSS[158]
VSS[159]
VSS[160]
VSS[161]
VSS[162]
VSS[163]
VSS[164]
VSS[165]
VSS[166]
VSS[167]
VSS[168]
VSS[169]
VSS[170]
VSS[171]
VSS[172]
VSS[173]
VSS[174]
VSS[175]
VSS[176]
VSS[177]
VSS[178]
VSS[179]
VSS[180]
VSS[181]
VSS[182]
VSS[183]
VSS[184]
VSS[185]
VSS[186]
VSS[187]
VSS[188]
VSS[189]
VSS[190]
VSS[191]
VSS[192]
VSS[193]
VSS[194]
VSS[195]
VSS[196]
VSS[197]
VSS[198]
H5
J23
J26
J27
AC22
K28
K29
L13
L15
L2
L26
L27
L5
L7
M12
M13
M14
M15
M16
M17
M23
M28
M29
N11
N12
N13
N14
N15
N16
N17
N18
N26
N27
P12
P13
P14
P15
P16
P17
P2
P23
P28
P29
P4
P7
R11
R12
R13
R14
R15
R16
R17
R18
R28
T12
T13
T14
T15
T16
T17
T23
B26
U12
U13
U14
U15
U16
U17
AD23
U26
U27
U3
V1
V13
V15
V23
V28
V29
V4
V5
W26
W27
W3
Y1
Y28
Y29
Y4
Y5
AG28
AH6
AF2
B25
VSS_NCTF[01]
VSS_NCTF[02]
VSS_NCTF[03]
VSS_NCTF[04]
VSS_NCTF[05]
VSS_NCTF[06]
VSS_NCTF[07]
VSS_NCTF[08]
VSS_NCTF[09]
VSS_NCTF[10]
VSS_NCTF[11]
VSS_NCTF[12]
A1
A2
A28
A29
AH1
AH29
AJ1
AJ2
AJ28
AJ29
B1
B29
+3VS
Compal Secret Data

2007/08/18
Issued Date
2008/8/18
Deciphered Date
4
(1UF*1, 0.1UF*1)
1mA
ICH9-M ES_FCBGA676
ICH9-M ES_FCBGA676
C368
4.7U_0805_10V4Z
AA26
AA27
AA3
AA6
AB1
AA23
AB28
AB29
AB4
AB5
AC17
AC26
AC27
AC3
AD1
AD10
AD12
AD13
AD14
AD17
AD18
AD21
AD28
AD29
AD4
AD5
AD6
AD7
AD9
AE12
AE13
AE14
AE16
AE17
AE2
AE20
AE24
AE3
AE4
AE6
AE9
AF13
AF16
AF18
AF22
AH26
AF26
AF27
AF5
AF7
AF9
AG13
AG16
AG18
AG20
AG23
AG3
AG6
AG9
AH12
AH14
AH17
AH19
AH2
AH22
AH25
AH28
AH5
AH8
AJ12
AJ14
AJ17
AJ8
B11
B14
B17
B2
B20
B23
B5
B8
C26
C27
E11
E14
E18
E2
E21
E24
E5
E8
F16
F28
F29
G12
G14
G18
G21
G24
G26
G27
G8
H2
H23
H28
H29
om
(0.1UF*1)
0.1U_0402_16V4Z
C330
l.c
C326
Title
ICH9M(4/4)-POWER&GND
Custom
ai
1
2
+ICH_V5REF_SUS
C329
Date:
he
x
10_0402_5%
220u
ESR 15m ohm
Rating 4V
ai
2
D15
VCC1_5_B[01]
VCC1_5_B[02]
VCC1_5_B[03]
VCC1_5_B[04]
VCC1_5_B[05]
VCC1_5_B[06]
VCC1_5_B[07]
VCC1_5_B[08]
VCC1_5_B[09]
VCC1_5_B[10]
VCC1_5_B[11]
VCC1_5_B[12]
VCC1_5_B[13]
VCC1_5_B[14]
VCC1_5_B[15]
VCC1_5_B[16]
VCC1_5_B[17]
VCC1_5_B[18]
VCC1_5_B[19]
VCC1_5_B[20]
VCC1_5_B[21]
VCC1_5_B[22]
VCC1_5_B[23]
VCC1_5_B[24]
VCC1_5_B[25]
VCC1_5_B[26]
VCC1_5_B[27]
VCC1_5_B[28]
VCC1_5_B[29]
VCC1_5_B[30]
VCC1_5_B[31]
VCC1_5_B[32]
VCC1_5_B[33]
VCC1_5_B[34]
VCC1_5_B[35]
VCC1_5_B[36]
VCC1_5_B[37]
VCC1_5_B[38]
VCC1_5_B[39]
VCC1_5_B[40]
VCC1_5_B[41]
VCC1_5_B[42]
VCC1_5_B[43]
VCC1_5_B[44]
VCC1_5_B[45]
VCC1_5_B[46]
VCC1_5_B[47]
VCC1_5_B[48]
VCC1_5_B[49]
+1.05VS
1
C325
U7E
nf
@
ho
tm
0.1U_0402_16V4Z
V5REF_SUS
VCCA3GP
AA24
AA25
AB24
AB25
AC24
AC25
AD24
AD25
AE25
AE26
AE27
AE28
AE29
F25
G25
H24
H25
J24
J25
K24
K25
L23
L24
L25
M24
M25
N23
N24
N25
P24
P25
R24
R25
R26
R27
T24
T27
T28
T29
U24
U25
V24
V25
U23
W24
W25
K23
Y24
Y25
+3VALW
R362
AE1
A15
B15
C15
D15
E15
F15
L11
L12
L14
L16
L17
L18
M11
M18
P11
P18
T11
T18
U11
U18
V11
V12
V14
V16
V17
V18
2mA
VCC1_05[01]
VCC1_05[02]
VCC1_05[03]
VCC1_05[04]
VCC1_05[05]
VCC1_05[06]
VCC1_05[07]
VCC1_05[08]
VCC1_05[09]
VCC1_05[10]
VCC1_05[11]
VCC1_05[12]
VCC1_05[13]
VCC1_05[14]
VCC1_05[15]
VCC1_05[16]
VCC1_05[17]
VCC1_05[18]
VCC1_05[19]
VCC1_05[20]
VCC1_05[21]
VCC1_05[22]
VCC1_05[23]
VCC1_05[24]
VCC1_05[25]
VCC1_05[26]
+ICH_V5REF_SUS
V5REF
220u
ESR 15m ohm
Rating 4V
2
0.1U_0402_16V4Z
VCCRTC
(0.1UF*2)
1634mA
2
1U_0402_6.3V4Z
A6
2mA
CORE
+ICH_V5REF
VCCP_CORE
1
2
1
C328
+ICH_V5REF
2
(0.1UF*1)
C331
1
+5VALW
C327
100_0402_5%
1
D14
PCI
A23
+RTCVCC
R363
U7F
VCCPSUS
(1UF*1, 0.1UF*2)
VCCPUSB
+3VS
+5VS
Sheet

1
23
of
49
Rev
0.4
14W SATA ODD Conn.
+5VS
1
0.1U_0402_16V4Z
1
C369
14W@
C370
14W@
C371
14W@
1000P_0402_50V7K
SATA ODD Conn.
10U_0805_10V4Z
Copy JIWA2 Symbol

JSATA1
SATA_ITX_C_DRX_P1
SATA_ITX_C_DRX_N1
SATA_DTX_IRX_N1
SATA_DTX_IRX_P1
R373 1
2 1K_0402_1%
+5VS
1
2
3
4
5
6
7
GND
A+
AGND
BB+
GND
8
9
10
11
12
13
DP
+5V
+5V
MD
GND
GND
SATA HDD Conn.

2
OCTEK_SLS-13SB1G
SATA_DTX_C_IRX_N1
1
C372
SATA_DTX_IRX_N1
0.01U_0402_16V7K
SATA_DTX_C_IRX_P1
1
C373
SATA_DTX_IRX_P1
0.01U_0402_16V7K
Update FootPrint from

OCTEK_SLS-13SB1G_13P-T to
OCTEK_SLS-13SB1G_13P_RV-T
+5VS
+3VS
0.1U_0402_16V4Z
C374
C375
1000P_0402_50V7K
10U_0805_10V4Z
1
C376
C377
1U_0603_10V4Z
C378
C379
0.1U_0402_16V4Z
2 @
2
10U_0805_10V4Z
15W SATA ODD Conn.

+5VS_ODD
JSATA3
0.1U_0402_16V4Z
3
C381
15W@
C382
15W@
1000P_0402_50V7K
C380
15W@
SATA ODD Conn.
10U_0805_10V4Z
SATA_DTX_C_IRX_N0
1
C383
SATA_DTX_C_IRX_P0
1
C384
SATA_ITX_C_DRX_P0
SATA_ITX_C_DRX_N0
SATA_DTX_IRX_N0
2
3900P_0402_50V7K
SATA_DTX_IRX_P0
2
3900P_0402_50V7K
Copy JIWA2 Symbol
P1
P2
P3
P4
P5
P6
P7
P8
P9
P10
P11
P12
P13
P14
P15
+3VS
JSATA2
SATA_ITX_C_DRX_P1
R374
SATA_ITX_C_DRX_N1
R375
SATA_DTX_IRX_N1
R376
SATA_DTX_IRX_P1
R377
1
15W@
1
15W@
1
15W@
1
15W@
0_0402_5%
SATA_ITX_C_DRX_P1_R
0_0402_5%
SATA_ITX_C_DRX_N1_R
0_0402_5%
SATA_DTX_IRX_N1_R
0_0402_5%
SATA_DTX_IRX_P1_R
SATA_ITX_C_DRX_P1_R
SATA_ITX_C_DRX_N1_R
SATA_DTX_IRX_N1_R
SATA_DTX_IRX_P1_R
R378 1
@
2 1K_0402_1%
+5VS_ODD
1
2
3
4
5
6
7
GND
A+
AGND
BB+
GND
8
9
10
11
12
13
DP
+5V
+5V
MD
GND
GND
+5VS
1
R778
1
R779

OCTEK_SLS-13SB1G_13P-T to
OCTEK_SLS-13SB1G_13P_RV-T
2
15W@ 0_1206_5%
2
15W@ 0_1206_5%
2007/08/18
2008/8/18
Deciphered Date
B
V33
V33
V33
GND
GND
GND
V5
V5
V5
GND
Reserved
GND
V12
V12
GND
V12
GND
23
24
Compal Secret Data
Issued Date
Update Symbol
SP01000G800
FOX_LD2122H-S43_NR
Manually update pin number
+5VS_ODD
GND
A+
AGND
BB+
GND
FOX_LD2122H-S43_NR
CONN@
OCTEK_SLS-13SB1G
+5VS
S1
S2
S3
S4
S5
S6
S7
Title
HDD & ODD Connector

Size
B
Document Number
Rev
0.4
Date:

G
Sheet
24
H
of
49
CH7318C-BF-TR QFN 48P

7318@
U12
Symbol modified pn to
SD034120180.
Never use this symbol
for other platform
OE*
2
11
15
21
26
33
40
46
+VCC3V
R382
VCC3V
VCC3V
VCC3V
VCC3V
VCC3V
VCC3V
VCC3V
VCC3V
2.2K_0402_5%
GM@
1.2K_0402_1%
7318@
3
4
1
2
R388 8101@
430_0402_1%
HPD_SOURCE
<8> HDMIDAT_NB
<8> HDMICLK_NB
C391
0.5P_0402_50V8B
R389
68_0402_5%
C392
0.5P_0402_50V8B
R390
68_0402_5%
C393
0.5P_0402_50V8B
R391
68_0402_5%
0.5P_0402_50V8B
R392
68_0402_5%
ANALOG1(REXT)
HPD_SOURCE
SDA_SOURCE
SCL_SOURCE
GM@
C389
GM@
C390
GM@
0_0603_5%
GM@
Place close pin 33 and 36

R380 2
@
1 0_0402_5%
R383 2 7318@ 1 0_0402_5%
SCL_SINK
28
HDMICLK
SDA_SINK
29
HDMIDAT
+3VS
+5VS_HDMI
Pull high on VGA/B
+3VS
R385
HDMI_DETECT
HPD_SINK
30
DDC_EN
32
R386 2 GM@
R387 2
@
FUNCTION3
FUNCTION4
34
35
R800 2 7318@ 1 4.7K_0402_5% +3VS

R801 2
@
1 0_0402_5%
2.2K_0402_5%
1 4.7K_0402_5% +3VS
1 0_0402_5%
2.2K_0402_5%
HDMIDAT
VGA_DDC_HDMIDAT
PM@
Q10A
2N7002DW-T/R7_SOT363-6
R802 2 7318@ 1 4.7K_0402_5% +3VS

R803 2
@
1 0_0402_5%
HDMICLK
VGA_DDC_HDMICLK
PM@
Q10B
2N7002DW-T/R7_SOT363-6
10/16 change symbol from SC1B411D000 to SC1B411D010
10
ANALOG2
+5VS
HDMI_CLK+
HDMI_CLK-
C395
FUNCTION1
FUCNTION2
GM@
C388
R384
R388
2.2K_0402_5%
GM@
25
C387
DAN217_SC59
@ <EMI>
HDMI_TX0-_R
1
2 2
L46 <EMI> @
<EMI>
1
2 R655 0_0402_5%
1
2 R657 0_0402_5%
<EMI>
+3VS
+3VS
R381
HDMI_TX0- 1
Change U12 from SA00001U900(CH7318A) to

SA00002D700(PS8101T)
Add U12 from SA00001U920(CH7318C)
<EMI>
2 R647 0_0402_5%
2 R649 0_0402_5%
<EMI>
1
1
GM@
HDMI_TX2-_R
C386
1
L45 <EMI> @
GM@
+5VS
HDMI_TX2- 1
C385
D17
0.1U_0402_16V4Z
DAN217_SC59
@ <EMI>
WCM2012F2SF-121T04_0805
HDMI_TX0+ 4
HDMI_TX0+_R
4
3 3
R379
1
+VCC3V
WCM2012F2SF-121T04_0805
HDMI_TX2+ 4
HDMI_TX2+_R
4
3 3
+3VS

0.1U_0402_16V4Z
HDMI_TX1-_R
1
2 2
L44 <EMI> @
<EMI>
1
2 R651 0_0402_5%
1
2 R653 0_0402_5%
<EMI>
HDMICLK
+VCC3V
0.1U_0402_16V4Z
U12
+5VS
0.1U_0402_16V4Z
HDMI_TX1- 1
HDMIDAT
HDMI_CLK-_R
1
2 2
L43 <EMI> @
<EMI>
1
2 R643 0_0402_5%
1
2 R645 0_0402_5%
<EMI>
WCM2012F2SF-121T04_0805
HDMI_TX1+ 4
HDMI_TX1+_R
4
3 3
D16
0.1U_0402_16V4Z
WCM2012F2SF-121T04_0805
HDMI_CLK+_R
4 4
3 3
HDMI_CLK-
HDMI_CLK+
Change L43,L44,L45,L46 from SM070000M00 to

SM070000K00
0.1U_0402_16V4Z
13
14
OUT_D4+
OUT_D4-
IN_D4+
IN_D4-
48
47
IN_D4+
IN_D4-
HDMI_TX2+
HDMI_TX2-
16
17
OUT_D3+
OUT_D3-
IN_D3+
IN_D3-
45
44
IN_D3+
IN_D3-
HDMI_TX1+
HDMI_TX1-
19
20
IN_D2+
IN_D2-
42
41
IN_D2+
IN_D2-
39
38
IN_D1+
IN_D1-
HDMI_TX0+
HDMI_TX0-
OUT_D2+
OUT_D2-
22
23
OUT_D1+
OUT_D1-
1
5
12
18
24
27
31
36
37
43
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
IN_D1+
IN_D1-
1
2
RP47
1
2
RP48
1
2
RP49
1
2
RP50
4
3
GM@
4
3
GM@
4
3
GM@
4
3
GM@
PCIE_MTX_C_GRX_P3
PCIE_MTX_C_GRX_N3
0_0404_4P2R_5%
PCIE_MTX_C_GRX_P0
PCIE_MTX_C_GRX_N0
0_0404_4P2R_5%
1 R807@ 2
0_0805_5%
<10,17>
<10,17>
D18
2
<10,17>
<10,17>
+VCC_HDMI
RB491D_SC59-3
+5VS_HDMI
1
2
F2
1.1A_6VDC_FUSE
PCIE_MTX_C_GRX_P1 <10,17>
PCIE_MTX_C_GRX_N1 <10,17>
0_0404_4P2R_5%
HDMI Connector
PCIE_MTX_C_GRX_P2 <10,17>
PCIE_MTX_C_GRX_N2 <10,17>
0_0404_4P2R_5%
C394
0.1U_0402_16V4Z
JHDMI1
HDMI_HPD
PS8101TQFN48G QFN 48P

8101@
2
Y
R632
100K_0402_5%
HDMIDAT
HDMICLK
C649
0.1U_0402_16V4Z
HDMI_CLK-_R
5
1
A
R811
GM@
0_0402_5%
2
R631
PM@
2.2K_0402_5%
2
P
OE#
C650
0.1U_0402_16V4Z
PM@ 1
1
1
+5VS
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
+3VS
HDMI_DETECT
HDMI_CLK+_R
HDMI_TX0-_R
U35
SN74AHCT1G125GW_SOT353-5
PM@
HDMI_TX0+_R
HDMI_TX1-_R
HDMI_TX1+_R
HDMI_TX2-_R
HDMI_TX2+_R
Inverting level shift for hot-plug detect
20
21
22
23
TYCO_1775040-6
CONN@
Layout Notice:
Need short
+3VS
HP_DET
+5V
DDC/CEC_GND
SDA
SCL
Reserved
CEC
CKGND
CK_shield GND
CK+
GND
D0GND
D0_shield
D0+
D1D1_shield
D1+
D2D2_shield
D2+
Cantiga NB
R810 1 8101@ 2 0_0402_5%
R401
7318@
7.5K_0402_1%
<17> VGA_HDMI_CLK+
<17> VGA_HDMI_CLK<17> VGA_HDMI_TX0+
<17> VGA_HDMI_TX0-
Q11
SSM3K7002FU_SC70-3
7318@
HPD_SOURCE
2
G
Near MXM conn.
R405
7318@
100K_0402_5%
<17> VGA_HDMI_TX1+
<17> VGA_HDMI_TX2<17> VGA_HDMI_DETECT
1
2
RP51
1
2
RP52
1
2
RP53
1
2
RP54
R406 2
1
2
RP59
<17> VGA_HDMIDAT
<17> VGA_HDMICLK
HDMI_CLK+
4
HDMI_CLK3
PM@ 0_0404_4P2R_5%
HDMI_TX0+
4
HDMI_TX03
PM@ 0_0404_4P2R_5%
HDMI_TX1+
4
HDMI_TX13
PM@ 0_0404_4P2R_5%
HDMI_TX2+
4
HDMI_TX23
PM@ 0_0404_4P2R_5%
PM@ 1 0_0402_5%
HDMI_DETECT
VGA_DDC_HDMIDAT
4
VGA_DDC_HDMICLK
3
PM@ 0_0404_4P2R_5%
2008/8/18
Deciphered Date
5
Title
CH7318A&HDMI Connector
Custom
ai
2007/08/18
Issued Date
Date:
he
x
100K follow DG 0.8
Compal Secret Data
If there is 5% resister availble,just change
nf
@
ho
tm
ai
l.c
HDMI Conn.
CH7318
<10> TMDS_B_HPD#
Ext VGA
om
R395
7318@
20K_0402_5%
Sheet
25
of
49
Rev
0.4
SD,MMC,MS muti-function pin define
Active High EN
11/24 Andy
+3VS
2
0_0805_5% 1
C399
10U_0805_10V4Z
SD1_DAT1
MS1_DAT1
MDIO02
SD1_DAT2
VIN
VOUT
VIN/CE VOUT
MS1_DAT2
MDIO03
SD1_DAT3
GND
MS1_DAT3
MDIO04
SD1_CMD
MS1_BS
R410
MDIO05
SD1_CLK
MS1_CLK
150K_0402_5%
@
MDIO06
SD1_WP
1
5
RT9701-PB_SOT23-5
@
C400
0.1U_0402_16V4Z
C397
@
0.1U_0402_16V4Z
3
4
+VCC_3IN1
1
R409
MDIO01
+VCC_3IN1
U13
C398
1U_0603_10V4Z
MS Card
PIN Name
MS1_DAT0
+VCC_OUT
Use 0805 type and over 20 mils

trace width on both side
+VCC_OUT
SD/MMC Card
PIN Name
SD1_DAT0
MDIO
PIN Name
MDIO00
40mil
MDIO07
reserved power circuit
mount JMB suggest
+VCC_3IN1
MDIO08
MMC_DAT4
MS1_DAT4
MDIO09
MMC_DAT5
MS1_DAT5
MDIO10
MMC_DAT6
MS1_DAT6
MDIO11
MMC_DAT7
MS1_DAT7
CR1_LEDN
SD1_LED#
MS1_LED#
CR1_PCTLN
SD1_PCTL#
MS1_PCTL#
CR1_CD0
SD1_CD#
MDIO12
1
R411
2 SDWP#_MMCWP#
10K_0402_5%
1
R412
2 XD_RB#
10K_0402_5%
MDIO13
+1.8VS_CR
20mil
0.1U_0402_16V4Z
1
1
C401
C402
2
10U_0805_10V4Z
C403
Refer JMB suggest 11/14

1
R413 @
MDIO14
2
+1.8VS_CRR
0_0805_5%
C404
2
1000P_0402_50V7K
0.1U_0402_16V4Z
MS1_CD#
CR1_CD1
40 mil
U14
+3VS
1
<16> CLK_PCIE_CARD#
<16> CLK_PCIE_CARD
3
4
<22> PCIE_ITX_C_PRX_N5
<22> PCIE_ITX_C_PRX_P5
9
8
APRXN
APRXP
11
12
APTXN
APTXP
C407
C408
<22> PCIE_PTX_C_IRX_N5
<22> PCIE_PTX_C_IRX_P5
2 0.1U_0402_10V7K
2 0.1U_0402_10V7K
1
1
R414 1
PCIE_PTX_IRX_N5
PCIE_PTX_IRX_P5
2 8.2K_0402_5%
APREXT
12mil,length <250 mil

+3VS
1
R665
38
39
2
0_0402_5%
APCLKN
APCLKP
1
2
PLT_RST_BUF#
1
R673
<22> GPIO18
+3VS
2
0_0402_5%
T19
R415
R416
2 4.7K_0402_5%
2 4.7K_0402_5%
1
1
1
R642
<22> CR_WAKE#
2
@ 0_0402_5%
13
14
PAD
MSCD#_XDCD1
SDCD#_XDCD0#
+VCC_OUT
15
16
17
40 mil
21
5
10
30
DV33
DV33
DV33
DV18
DV18
19
20
44
18
37
MDIO0
MDIO1
MDIO2
MDIO3
MDIO4
MDIO5
MDIO6
MDIO7
MDIO8
MDIO9
MDIO10
MDIO11
MDIO12
MDIO13
MDIO14
48
47
46
45
43
42
41
40
29
28
27
26
25
23
22
NC
NC
NC
34
35
36
APREXT
PCIES_EN
PCIES
JMB385
Change Pin definition for Rev:B

<8,17,20,28,30,40>
APVDD
APV18
TAV33
XRSTN
XTEST
D3E_WAKEN
NC
CR1_CD1N
CR1_CD0N
C651
0.1U_0402_16V4Z
C652
0.1U_0402_16V4Z
C405
0.1U_0402_16V4Z
C406
0.1U_0402_16V4Z
+1.8VS_CR
12mil
SDDATA0_MSDATA0
SDDATA1_MSDATA1
SDDATA2_MSDATA2
SDDATA3_MSDATA3
SDCMD_MSBS
SDCLK_MSCLK
SDWP#_MMCWP#
XD_CLE
C409
2
0.1U_0402_16V4Z
R420 1
2 22_0402_5%
SDCLK
R421 1
2 22_0402_5%
MSCLK
C410
0.1U_0402_16V4Z
Damping need to close to IC

XD_RE#
XD_RB#
XD_ALE
Strap pin for JMicro

+3VS
1
R417
XD_CLE
2
10K_0402_5%
APGND
CR1_PCTLN
200K_0402_5%
24
31
32
33
GND
GND
GND
GND
CR1_LEDN
200K_0402_5%
2
2
1
R418
1
R419
3 in 1 Card Reader
XD_RE#
XD_ALE
JREAD1
+VCC_3IN1
JMB385-LGEZ0A_LQFP48_7X7
B
Rev :B
D66
C701
2
SDCD#_XDCD0#
MSCD#_XDCD1
270P_0402_50V7K
@
SDDATA0_MSDATA0
SDDATA1_MSDATA1
SDDATA2_MSDATA2
SDDATA3_MSDATA3
SDCLK
SDWP#_MMCWP#
SDCMD_MSBS
SDCD#_XDCD0#
SDDATA1_MSDATA1
DAN202UT106_SC70-3
@
MSCLK
MSCD#_XDCD1
SDDATA0_MSDATA0
SDCMD_MSBS
SDDATA3_MSDATA3
SDDATA2_MSDATA2
+1.8V
6
9
10
2
3
7
11
4
1
5
8
VDD_SD
DAT0_SD
DAT1_SD
DAT2_SD
CD/DAT3_SD
CLK_SD
WP_SD
CMD_SD
CD_SD
VSS_SD
VSS_SD
19
13
14
16
18
20
15
17
21
12
22
23
VCC_MS
VCC_MS
SCLK_MS
INS_MS
SDIO_MS
BS_MS
RESERVED_MS
RESERVED_MS
VSS_MS
VSS_MS
GND
GND
PROCO_MDR019-C0-1202
CONN@
2 100K_0402_5% 2
C714
@
0.1U_0402_16V4Z
C713
@
1U_0603_10V4Z
10/17 add for

JMB380
The circuit need reserve for JMB385?
@
Q50
SI2301BDS_SOT23
D
SUSP
<41,47>
R532 1
@
SDCLK
R633
@ 100_0402_5%
W=40mils
C412
@ 100P_0402_50V8J
+1.8VS_CRR
MSCLK
R634
@ 100_0402_5%
2007/08/18
Deciphered Date
2008/8/18
5
C413
@ 100P_0402_50V8J
Compal Secret Data
Issued Date
Title

JMB385 CardReader

Custom
Rev
0.4
Date:
Sheet
1
26
of
49
Compal Secret Data

2008/8/18
Deciphered Date
5
Title

3 in 1 Card Reader Conn

Custom
ai
2007/08/18
Issued Date
Date:
he
x
nf
@
ho
tm
ai
l.c
om
Sheet

1
27
of
49
Rev
0.4
Max 340mA
width > 60mil
SROUT12
R424 8102E@ 0_0603_5%
Length < 200mil to Pin1
AVDD12
FB12
L27
AVDD12
+3VALW
C414
0.1U_0402_16V4Z
8111C@
VDD33
Max 541mA
R426
width > 40mil
0.1U_0402_16V4Z
C415
0.1U_0402_16V4Z
8111C@
R425
0.1U_0402_16V4Z
1
1
C416
C417
8111C@
0_0603_5%
1
2
4.7UH_1008HC-472EJFS-A_5%_1008
1
1
C418
C419
C420
@
22U_0805_6.3V6M
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
VDD33
22U_0805_6.3V6M
8111C@
0_0603_5%
C421
6
5
2
1
2
2
0.1U_0402_16V4Z
4
Q12
SI3445ADV-T1-E3_TSOP6
@
C422
@
22U_0805_6.3V6M
0.1U_0402_16V4Z
Bead current rating:600mA
C423
C424
C425
L28
1
EVDD12
EVDD12
C426
0.1U_0402_16V4Z
1
C722
8102E@
4.7U_0805_10V4Z
2
0.1U_0402_16V4Z
AVDD33
1
C427
8111C@
0.1U_0402_16V4Z
2
8111C@
Inductor=4.7uH,600mA
SHI00004C00
MBK1608121YZF_0603
2
C428
0.1U_0402_16V4Z
R427
0_0603_5%
R428
0_0603_5%
8111C@
width > 40mil

@
R429
R678 1
210K_0402_5%
0_0603_5%
AVDD33
EN_WOL# <32>
C430
Max 340mA
C431
CTRL12
C429
@
0.1U_0402_16V4Z
0.1U_0402_16V4Z
2
2 8111C@
0.1U_0402_16V4Z
For soft start

Andy 11/24
DVDD12
DVDD12
C436
0.1U_0402_16V4Z
1
1
C437
C438
2
0.1U_0402_16V4Z
8111C@
0.1U_0402_16V4Z
R430 8102E@ 0_0603_5%
1
1
1
C440
C441
CTRL12
C439
0.1U_0402_16V4Z
0.1U_0402_16V4Z
0.1U_0402_16V4Z
U15
LAN_CLKREQ#
<16> LAN_CLKREQ#
2
1 PCIE_PTX_IRX_P4
C442
0.1U_0402_10V7K
2
1 PCIE_PTX_IRX_N4
C443
0.1U_0402_10V7K
PCIE_ITX_C_PRX_P4
29
HSOP
30
HSON
23
HSIP
PCIE_ITX_C_PRX_N4
24
HSIN
33
CLKREQB
CLK_PCIE_LAN
26
REFCLK_P
CLK_PCIE_LAN#
27
REFCLK_N
PLT_RST_BUF#
20
PERSTB
R432 1
2 0_0402_5%
<16> CLK_PCIE_LAN
<16> CLK_PCIE_LAN#
<8,17,20,26,30,40> PLT_RST_BUF#
width > 60mil
+3VS
R434 1
R435 1
R436
VDD33
CKREQB
SROUT12
2
1 FB12
C721
0.01U_0402_16V7K
2 8111C@ 0_0402_5% ENSR
2 @ 0_0402_5%
2.49K_0402_1%
RSET
FB12
62
ENSR
64
RSET
ICH_PCIE_WAKE#
19
LANWAKEB
ISOLATEB
36
ISOLATEB
2
1
ISOLATEB
R441
EEDO
EEDI
EESK
EECS
LED3
LED2
LED1
LED0
54
55
56
57
LINK10 R431 1
LINKLED#
ACTIVITY#
MDIP0
MDIN0
MDIP1
MDIN1
MDIP2
MDIN2
MDIP3
MDIN3
3
4
6
7
9
10
12
13
MDI0+
MDI0MDI1+
MDI1MDI2+
MDI2MDI3+
MDI3-
LAN_XTAL_IN
60
LAN_XTAL_OUT
61
CKTAL2
65
EXPOSE_PAD
10/09 change to SJ125P0M200

25
LAN_XTAL_IN
31
LAN_XTAL_OUT
DVDD12
25MHz_20pF_6X25000017
1
C448
27P_0402_50V8J
C449
27P_0402_50V8J
R445 8102E@ 0_0603_5%
15
17
18
34
35
39
40
41
42
2 0_0402_5%
LINKLED# <29>
ACTIVITY# <29>
MDI0+
MDI0MDI1+
MDI1MDI2+
MDI2MDI3+
MDI3-
VDD33
<29>
<29>
<29>
<29>
<29>
<29>
<29>
<29>
VDD33
R433
@
3.6K_0402_5%
EEDI
U16
EECS
EESK
DVDD12
DVDD12
DVDD12
DVDD12
DVDD12
DVDD12
DVDD12
21
32
38
43
49
52
EVDD12
EVDD12
22
28
EVDD12
VDD33
VDD33
VDD33
VDD33
16
37
46
53
VDD33
1
2
3
4
CS
SK
DI
DO
VCC
NC
NC
GND
8
7
6
5
AT93C46-10SI-2.7_SO8
@
C445
@
0.1U_0402_16V4Z
Pin 11,14,32,38,52,59 are NC pins when use 8102E
CKTAL1
EGND
NC
NC
NC
NC
NC
NC
NC
NC
NC
CTRL12
width > 40mil

Length < 200mil
VDDSR
63
AVDD33
AVDD33
2
59
AVDD33
AVDD12
AVDD12
AVDD12
AVDD12
8
11
14
58
AVDD12
IGPIO
OGPIO
50
51
EGND
Y2
EEDO
15K_0402_5%
45
47
48
44
SROUT12
R439
1K_0402_5%
B
EEDO
EEDI/AUX
EESK
EECS
R443 8111C@
0_0603_5%
1
1
VDD33
C446
C447
8111C@
0.1U_0402_16V4Z
22U_0805_6.3V6M 2
8111C@
R448 8111C@ 0_0603_5%

R449 8102E@ 0_0603_5% DVDD12
U15
RTL8111C-GR_QFN64_9X9
8111C@
8102E
8102E@
Compal Secret Data
2007/08/18
Issued Date
Deciphered Date
2008/8/18
5
Title
LAN-RTL8111C/RTL8102E
Custom
Date:
Sheet
1
28
of
49
Rev
0.4
T20
C450 1
C451 1
C452 1
C453 1
2 0.01U_0402_16V7K
2 0.01U_0402_16V7K
8111C@
2 0.01U_0402_16V7K
2 0.01U_0402_16V7K
8111C@
<28>
<28>
MDI0+
MDI0-
<28>
<28>
MDI2+
MDI2-
<28>
<28>
MDI1+
MDI1-
<28>
<28>
MDI3+
MDI3-
V_DAC
MDI0+
MDI0-
1
2
3
4
5
6
7
8
9
10
11
12
MDI2+
MDI2MDI1+
MDI1MDI3+
MDI3-
TCT1
TD1+
TD1TCT2
TD2+
TD2TCT3
TD3+
TD3TCT4
TD4+
TD4-
MCT1
MX1+
MX1MCT2
MX2+
MX2MCT3
MX3+
MX3MCT4
MX4+
MX4-
24
23
22
21
20
19
18
17
16
15
14
13
MCT0
MDO0+
MDO0MCT1
MDO2+
MDO2MCT2
MDO1+
MDO1MCT3
MDO3+
MDO3-
R450 2
1 75_0402_5%
R451 2 8111C@ 1 75_0402_5%

R452 2
1 75_0402_5%
R453 2 8111C@ 1 75_0402_5%
RJ45_PR
GSL5009LF
8111C@
3/4 Change T20 Value from 350uH_GSL5009LF to GSL5009LF

Change T20 P/N fromSP050003T00 to SP050003T10
Lan Conn.
1
2
3
4
5
6
7
8
V_DAC
MDI1+
MDI1-
RD+
RDCT
NC
NC
CT
TD+
TD-
1 <EMI>
470P_0402_50V7K
@
@
1
2
R454
300_0402_5%
2
C454
T21
MDI0+
MDI0V_DAC
RX+
RXCT
NC
NC
CT
TX+
TX-
16
15
14
13
12
11
10
9
MDO0+
MDO0MCT0
<28> ACTIVITY#
ACTIVITY#
JP23
VDD33
12
Amber LED+
LAN_ACT#
11
Amber LED-
10mil
MDO3-
MCT2
MDO1+
MDO1-
NS0013LF
8102E@
Change T21 Value from 350uH_NS0013LF to NS0013LF
MDO3+
PR4+
MDO1-
PR2-
MDO2-
PR3-
MDO2+
PR3+
MDO1+
PR2+
MDO0-
PR1-
MDO0+
PR1+
10mil
<28> LINKLED#
LINKLED#
1
R455
2
C455
2
300_0402_5%
1 <EMI>
470P_0402_50V7K
@
LAN_LINK#
VDD33
10
9
SHLD2
16
SHLD1
15
PR4-
SHLD2
14
SHLD1
13
Green LEDGreen LED+

TYCO_3-440470-4
CONN@
RJ45_PR
C456
1
2 <EMI>
1000P_1206_2KV7K
C457
0.1U_0402_16V4Z
LANGND
C458
4.7U_0805_10V4Z
Compal Secret Data

Deciphered Date
2008/8/18
5
Title

LAN CONNECTOR

Custom
Rev
0.4
ai
2007/08/18
Issued Date
Date:
he
x
nf
@
ho
tm
ai
l.c
om
Sheet
29
of
49
NAND mini Card(Robson support)

+3VS_ROB
Mini-Express Card for TV Tuner

+3VS
+1.5VS_ROB
Use Y topology to place these resisters between JMIN2 and JMIN1
2
1
1
C465
0.01U_0402_16V7K
2 ROBSON@
1
1
1
1
C467
C468
C469
C470
@
@
0.1U_0402_16V4Z
4.7U_0805_10V4Z
4.7U_0805_10V4Z
0.01U_0402_16V7K 0.1U_0402_16V4Z
2 ROBSON@
2
2
2 ROBSON@
2 ROBSON@
C466
1
R788
1
R789
1
R790
1
R791
PCIE_PTX_C_IRX_N2_14
2
14W@ 0_0402_5%
PCIE_PTX_C_IRX_P2_14
2
14W@ 0_0402_5%
PCIE_ITX_C_PRX_N2_14
2
14W@ 0_0402_5%
PCIE_ITX_C_PRX_P2_14
2
14W@ 0_0402_5%
C459
@
4.7U_0805_10V4Z
+1.5VS
C460
0.1U_0402_16V4Z
+3VS_ROB
+3VS_ROB
+3VS_ROB
53
GND1
GND2
54
<34> WLAN_ACTIVE
<34> BT_ACTIVE
1
+3VS
R456
<16> 3G_CLKREQ#
2
15W@ 0_0402_5%
2
15W@ 0_0402_5%
2
15W@ 0_0402_5%
2
15W@ 0_0402_5%
+3VS
PLT_RST_BUF#
PLT_RST_BUF# <8,17,20,26,28,40>
+3VS
Vcc 3.3V +/- 8%

Peak Icc 2750mA
+3VS
with max supply droop 50mA
Average Icc 1000mA
+3VS_ROB
C463
0.1U_0402_16V4Z
C464
0.1U_0402_16V4Z
53
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
GND2
54
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
GND1
+3VS
+1.5VS
MINI2_OFF#
PLT_RST_BUF#
+3VS
ICH_SMBCLK
ICH_SMBDATA
USB20_R_N8
USB20_R_P8
(WWAN_LED#)
WLAN_LED# <40>
2
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
0.1U_0402_16V4Z
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
R458
ROBSON@
R780
0_0805_5%
10K_0402_5%
@
WCM2012F2SF-121T04_0805
USB20_R_N8 4
USB20_N8
4
3 3
MINI2_OFF#
+1.5VS
FOX_AS0B226-S56N-7F
CONN@
2
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
C462
USB20_N8 <22>
+3VS_ROB
<16> CLK_PCIE_NAND#
<16> CLK_PCIE_NAND
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
+1.5VS_ROB
Q13
SSM3K7002FU_SC70-3
ROBSON@
R781
0_0805_5%
2
G
TV_ON#
USB20_R_P8
TV_ON# <32>
ROBSON@
1
2 ROB_CLKREQ#
R457
10K_0402_5%
1
R792
1
R793
1
R794
1
R795
+1.5VS_ROB
C461
@
4.7U_0805_10V4Z
JMIN1
ICH_PCIE_WAKE#
WLAN_ACTIVE
BT_ACTIVE
2 3G_CLKREQ#
10K_0402_5%
<16> CLK_PCIE_3G#
<16> CLK_PCIE_3G
JMIN3
+3VS
FOX_AS0B226-S56N-7F
ROBCONN@
1
L51 <EMI>
1
1
USB20_P8
USB20_P8 <22>
<EMI>
2 R666 0_0402_5%
2 R667 0_0402_5%
<EMI>
Mini-Express Card for WLAN

MINI_VCC
+1.5VS
+3VS
***
L29
JMIN2
USB20_R_P3
USB20_R_N3
@
WCM2012F2SF-121T04_0805
USB20_P3
4 4
3 3
1
1
L59 <EMI>
1
1
USB20_N3
C472
C473
0.1U_0402_16V4Z
WLAN_LED# <40>
Q14
SSM3K7002FU_SC70-3
RF_ON#
01/22 change sw2 P/N DE100000300

2
SW2
1BS003-1211L_3P
100K_0402_5%
+5VS
C476
0.1U_0402_16V4Z
C477
@
4.7U_0805_10V4Z
0.1U_0402_16V4Z
Please place these caps between JMIN1 and JMIN2
ICH_SMBCLK
C757
2 @ 100P_0402_50V8J
ICH_SMBDATA
C758
2 @ 100P_0402_50V8J
Compal Secret Data
2007/08/18
2008/8/18
Deciphered Date
B
11/23 Change SW2 to correct symbol (by Andy)
+3VS
Issued Date
RF_ON# <32>
R463
1
2
G
S
+1.5VS
C475
WLAN_LED#
FOX_AS0B226-S56N-7F
CONN@
0.01U_0402_16V7K
KILL_SW# <32>
MINI_RF_OFF#
C471
C474
@
4.7U_0805_10V4Z
100K_0402_5%
KILL_SW#
10K_0402_5%
USB20_R_N3
USB20_R_P3
MINI_VCC
0.01U_0402_16V7K
+3VALW
R461
R462
ICH_SMBCLK <16,22,31>
ICH_SMBDATA <16,22,31>
<EMI>
2 R808 0_0402_5%
2 R809 0_0402_5%
<EMI>
D21
DAN217_SC59
@
1
ICH_SMBCLK
ICH_SMBDATA
USB20_P3 <22>
USB20_N3 <22>
3
MINI_RF_OFF#
PLT_RST_BUF#
MINI_VCC
54
+3VS
GND2
+3VALW
GND1
Kill SWITCH
53
KC FBM-L11-201209-221LMAT_0805
MINI_VCC
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
CLK_PCIE_WLAN#
CLK_PCIE_WLAN
<16> CLK_PCIE_WLAN#
<16> CLK_PCIE_WLAN
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
ICH_PCIE_WAKE#
WLAN_ACTIVE
BT_ACTIVE
WLAN_CLKREQ#
MINI_VCC
<22,28,31>
<34>
<34>
<16>
ICH_PCIE_WAKE#
WLAN_ACTIVE
BT_ACTIVE
WLAN_CLKREQ#
Title

Mini-Card/Kill SWITCH
Size
Document Number

Date:
Sheet

E
30
of
49
Rev
0.4
+3VS_CARD1
New Card
+1.5VS
C694
2
1 0.1U_0402_16V4Z
+3VS
2
C693
<20,32,35> PCI_RST#
<32,41,46> SYSON
<17,32,41,46,47> SUSP#
2
R635
2
R636
+3VALW
JEXP1
C695
0.1U_0402_16V4Z
U18
12
14
1.5Vin
1.5Vin
1.5Vout
1.5Vout
11
13
+1.5VS_CARD1
3.3Vout
3.3Vout
3
5
+3VS_CARD1
C696
@
4.7U_0805_10V4Z
<22> USB20_N10
<22> USB20_P10
1 0.1U_0402_16V4Z
2
4
17
PCI_RST#
3.3Vin
3.3Vin
AUX_IN
SYSRST#
AUX_OUT
15
OC#
19
SYSON
20
SUSP#
STBY#
NC
10
CPPE#
GND
CP_PE#
1
100K_0402_5%
CP_USB#
1
100K_0402_5%
internal pull high to 3.3Vaux-in

EC need setting at Hi-Z & output Low
SHDN#
CPUSB#
18
RCLKEN
PERST#
C697
+3VALW_CARD1
0.1U_0402_16V4Z
CP_USB#
+1.5VS_CARD1
+1.5VS_CARD1
C689
2
1 0.1U_0402_16V4Z
+3VALW
New Card Socket (Left/TOP)
New Card Power Switch
+3VALW_CARD1
C698
@
4.7U_0805_10V4Z
PERST1#
+3VS_CARD1
<16>
<22>
<16>
<16>
PERST1#
16
7
EXP_CLKREQ#
CP_PE#
EXP_CLKREQ#
CP_PE#
CLK_PCIE_EXP#
CLK_PCIE_EXP
+3VALW_CARD1
R5538D001-TR-F_QFN20_4X4~D
C699
0.1U_0402_16V4Z
C700
@
4.7U_0805_10V4Z
JAQ60
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
GND
USB_DUSB_D+
CPUSB#
RSV
RSV
SMB_CLK
SMB_DATA
+1.5V
+1.5V
WAKE#
+3.3VAUX
PERST#
+3.3V
+3.3V
CLKREQ#
CPPE#
REFCLKREFCLK+
GND
PERn0
PERp0
GND
PETn0
PETp0
GND
27
28
GND1
GND2
29
30
GND3
GND4
SANTA_130810-1
CONN@
Change to GMT PartNumber

SANTA_13181060-5_26P-T to
SANTA_130810-1_26P

SANTA_130810-1_26P to
SANTA_130810-1_26P-S
A
Title
NEW CARD
Size
B
Date:
Document Number
ai
2008/8/18
Deciphered Date
he
x
2007/08/18
Issued Date
Compal Secret Data
nf
@
ho
tm
ai
l.c
om
Sheet
31
of
49
Rev
0.4
+EC_DVCC
PM_CLKRUN#
2
8.2K_0402_5%
+3VALW
2
R483
1
10K_0402_5%
1
R487
2
0_0402_5%
EC_PME#
<20>
PCI_PME#
<33>
+5VALW
KSO[0..15]
KSO[0..15]
<33>
KSI[0..7]
KSI[0..7]
EC_SMB_CK1 L57 1 <EMI> 2 0_0402_5% CLK_GUEST

2
4.7K_0402_5%
EC_SMB_DA1 L58 1 <EMI> 2 0_0402_5% DATA_GUEST
2
4.7K_0402_5%
CLK_GUEST_R
2
10K_0402_5%
DATA_GUEST_R
2
<34,43> EC_SMB_CK1
10K_0402_5%
<34,43> EC_SMB_DA1
ACK_GUEST_R
2
<4,17> EC_SMB_CK2
10K_0402_5%
<4,17> EC_SMB_DA2
1
R490
1
R491
1
R711
1
R712
1
R713
55
56
57
58
59
60
61
62
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
81
82
KSI0/GPIO30
KSI1/GPIO31
KSI2/GPIO32
KSI3/GPIO33
KSI4/GPIO34
KSI5/GPIO35
KSI6/GPIO36
KSI7/GPIO37
KSO0/GPIO20
KSO1/GPIO21
KSO2/GPIO22
KSO3/GPIO23
KSO4/GPIO24
KSO5/GPIO25 Int. K/B
KSO6/GPIO26 Matrix
KSO7/GPIO27
KSO8/GPIO28
KSO9/GPIO29
KSO10/GPIO2A
KSO11/GPIO2B
KSO12/GPIO2C
KSO13/GPIO2D
KSO14/GPIO2E
KSO15/GPIO2F
KSO16/GPIO48
KSO17/GPIO49
EC_SMB_CK1
EC_SMB_DA1
EC_SMB_CK2
EC_SMB_DA2
77
78
79
80
SCL1/GPIO44
SDA1/GPIO45
SCL2/GPIO46
SDA2/GPIO47
BATT_TEMP
BATT_OVP
ADP_I
DAC_BRIG/DA0/GPIO3C
EN_DFAN1/DA1/GPIO3D
IREF/DA2/GPIO3E
DA3/GPIO3F
68
70
71
72
DAC_BRIG
EN_FAN1
IREF
CHGVADJ
PSCLK1/GPIO4A
PSDAT1/GPIO4B
PSCLK2/GPIO4C
PSDAT2/GPIO4D
TP_CLK/PSCLK3/GPIO4E
TP_DATA/PSDAT3/GPIO4F
83
84
85
86
87
88
C503
DAC_BRIG <18>
EN_FAN1 <4>
IREF
<44>
CHGVADJ <44>
CLK_GUEST_R L53 1 @ <EMI> 2 0_0402_5% CLK_GUEST

DATA_GUEST_R L54 1 @ <EMI> 2 0_0402_5% DATA_GUEST
CLK_GUEST <33>
DATA_GUEST <33>
SPIDI/RD#
SPIDO/WR#
SPICLK/GPIO58
SPICS#
119
120
126
128
FRD#SPI_SO
FWR#SPI_SI
SPI_CLK
FSEL#SPICS#
CIR_RX/GPIO40
CIR_RLC_TX/GPIO41
FSTCHG/SELIO#/GPIO50
BATT_CHGI_LED#/GPIO52
CAPS_LED#/GPIO53
BATT_LOW_LED#/GPIO54
SUSP_LED#/GPIO55
SYSON/GPIO56
VR_ON/XCLK32K/GPIO57
AC_IN/GPIO59
73
74
89
90
91
92
93
95
121
127
RCIRRX
MCH_TSATN#_EC
FSTCHG
CHARGE_LED0#
CAPS_LED#
CHARGE_LED1#
PWR_LED#
SYSON
VR_ON
ACIN
EC_RSMRST#/GPXO03
EC_LID_OUT#/GPXO04
EC_ON/GPXO05
EC_SWI#/GPXO06
ICH_PWROK/GPXO06
GPO
BKOFF#/GPXO08
WL_OFF#/GPXO09
GPXO10
GPXO11
100
101
102
103
104
105
106
107
108
EC_RSMRST#
EC_LID_OUT#
EC_ON
TV_ON#
ICH_PWROK
BKOFF#
RF_ON#
BT_ON#
VGA_AC_DET
PM_SLP_S4#/GPXID1
ENBKL/GPXID2
GPXID3
GPXID4
GPXID5
GPXID6
GPXID7
110
112
114
115
116
117
118
PM_SLP_S4#
ENBKL
CIR_DET#
EC_THERM#
SUSP#
PBTN_OUT#
EC_PME#
V18R
124
GPIO
SPI_CS#
SPI_CS#
<34>
SPI_CLK_R
<34>
SPI_SI
2 ACK_GUEST_R
0_0402_5%
FSEL#SPICS#
2
0_0402_5%
SPI_CLK
2
0_0402_5%
FWR#SPI_SI
2
0_0402_5%
R494
SPI_CLK_R
1
R495
SPI_SI
1
R496
XCLKI
XCLKO
R497
XCLKO 1
@
2 XCLKI
20M_0603_5%
PIN
KB926C0
ACES_85205-0400
DBCONN@
1
OSC
OSC
X2
2 10K_0402_5%
CIR_DET#
R731 2
1 10K_0402_5%
P_USB#
R485 2
1 10K_0402_5%
RCIRRX
R489 1
2 10K_0402_5%
SM_KEY#
R672 1
2 10K_0402_5%
PCI_RST#
R256 1
2 100K_0402_5%
C
CLK_GUEST
DATA_GUEST
FRD#SPI_SO <34>
C720
@
22P_0402_50V8J
2 <EMI>
EC_RSMRST#
BEEP#
SYSON
EC_SCI#
EC_THERM#
SERIRQ
RCIRRX <35>
MCH_TSATN#_EC <8>
FSTCHG <44>
CHARGE_LED0# <40>
CAPS_LED# <33>
CHARGE_LED1# <40>
PWR_LED# <33,40>
SYSON <31,41,46>
VR_ON <48>
ACIN
<22,42,44>
C508
C506
C507
@ C505
@ C509
@ C510
@
@
@
ICH_PWROK
PBTN_OUT#
EN_FAN1
EC_ON
ON/OFF#
TV_ON#
100P_0402_50V8J
EC_RSMRST# <22>
EC_LID_OUT# <22>
EC_ON <35>
TV_ON# <30>
ICH_PWROK <8,22>
BKOFF# <18>
RF_ON# <30>
BT_ON# <34>
VGA_AC_DET <17>
PM_SLP_S4# <22>
ENBKL <18>
CIR_DET# <35>
EC_THERM# <22>
SUSP# <17,31,41,46,47>
PBTN_OUT# <22>
C733
C731
C517
BATT_OVP
C519
100P_0402_50V8J
ACIN
C520
100P_0402_50V8J
VR_ON
C521
2 @ 100P_0402_50V8J
ENBKL
C522
2 @ 100P_0402_50V8J
FSTCHG
C734
100P_0402_50V8J
ACK_GUEST
C735
100P_0402_50V8J
ADP_I
C736
2 @ 100P_0402_50V8J
EC_SMB_DA1 C743
2 @ 100P_0402_50V8J
EC_SMB_CK1 C744
2 @ 100P_0402_50V8J
C732
2
C518
4.7U_0805_10V4Z
C524
15P_0402_50V8J
BATT_TEMP
32.768KHZ_12.5PF_Q13MC14610002
Compal Secret Data
2007/08/18
Issued Date
2008/8/18
Deciphered Date
5
C515
C514
@ C516
@
@
100P_0402_50V8J
2
Use KB926C0
R813 1
1
C719
@
22P_0402_50V8J
<EMI> 2
NC
1
2
3
4
NC
EC_TX_P80_DATA
EC_RX_P80_CLK
KB926QFA1 LQFP 128P
GPXOA02
+3VALW
1
2
3
4
JP61
A
C523
15P_0402_50V8J
GPI
XCLK1
XCLK0
1
4
EC DEBUG PORT
122
123
PM_SLP_S3#/GPIO04
PM_SLP_S5#/GPIO07
EC_SMI#/GPIO08
LID_SW#/GPIO0A
SUSP#/GPIO0B
PBTN_OUT#/GPIO0C
GPIO
EC_PME#/GPIO0D
EC_THERM#/GPIO11
FAN_SPEED1/FANFB1/GPIO14
FANFB2/GPIO15
EC_TX/GPIO16
EC_RX/GPIO17
ON_OFF/GPIO18
PWR_LED#/GPIO19
NUMLED#/GPIO1A
AGND
ACK_GUEST 1
R814
EC_TX_P80_DATA
EC_RX_P80_CLK
ON/OFF#
SM_KEY_LED#
NUM_LED#
6
14
15
16
17
18
19
25
28
29
30
31
32
34
36
2 4.7K_0402_5%
69
<33> ACK_GUEST
<34>
<14,15>
<14,15>
<35>
<33>
<33>
SUSP#
2
@ 100P_0402_50V8J
PM_SLP_S3#
PM_SLP_S5#
EC_SMI#
SM_KEY#
2 0_0402_5% ESB_CLK
2 0_0402_5% ESB_DAT
P_USB#
USB2_ON#
FAN_SPEED1
ACK_GUEST_R
EC_TX_P80_DATA
EC_RX_P80_CLK
ON/OFF#
SM_KEY_LED#
NUM_LED#
R477 1
ECAGND
1
C513
PM_SLP_S3#
PM_SLP_S5#
EC_SMI#
SM_KEY#
@L60
@
L60 1 <EMI>
1
C512
@L61
@
L61 1 <EMI>
@
<33> P_USB#
100P_0402_50V8J
<35> USB2_ON#
2
<4> FAN_SPEED1
GND
GND
GND
GND
GND
<22>
<22>
<22>
<33>
CLK_GUEST
DATA_GUEST
11
24
35
94
113
EC_SMB_CK2
2
4.7K_0402_5%
EC_SMB_DA2
2
4.7K_0402_5%
1
C511
@
100P_0402_50V8J
2
TP_DATA
+3VALW
97
98
99
109
SPI Flash ROM
2 4.7K_0402_5%
MB2_ID
MB_ID
SDICS#/GPXOA00
SDICLK/GPXOA01
SDIDO/GPXOA02
SDIDI/GPXID0
SPI Device Interface
R475 1
+5VALW
BATT_TEMP <43>
BATT_OVP <44>
ADP_I
<44>
+3VS
1
R492
1
R493
2
1
2
ECAGND
0.01U_0402_16V7K
POWER_USB_LED#
POWER_USB_LED# <33>
TP_CLK
KB926 SPI STRAP
TP_CLK <34>
TP_DATA
TP_DATA <34> No stuff when use
1
2
KILL_SW# <30>
R637 1
2 0_0402_5%
R488
@
10K_0402_5%
EN_WOL#
EN_WOL# <28>
GPXOA02
ACK_GUEST
R812 1
@
2 0_0402_5%
LID_SW#
LID_SW# <35>
PS2 Interface
SM Bus
TP_CLK
100P_0402_50V8J
63
64
65
66
75
76
INVT_PWM <18>
BEEP# <36>
VGA_THERM# <17>
ACOFF <44>
100P_0402_50V8J
R714
BATT_TEMP/AD0/GPIO38
BATT_OVP/AD1/GPIO39
ADP_I/AD2/GPIO3A
Input
AD3/GPIO3B
AD4/GPIO42
SELIO2#/AD5/GPIO43
DA Output
KSI0
KSI1
KSI2
KSI3
KSI4
KSI5
KSI6
KSI7
KSO0
KSO1
KSO2
KSO3
KSO4
KSO5
KSO6
KSO7
KSO8
KSO9
KSO10
KSO11
KSO12
KSO13
KSO14
KSO15
INVT_PWM
BEEP#
VGA_THERM#
ACOFF
100P_0402_50V8J
+3VS
21
23
26
27
PWM Output
AD
R472
@
0_0402_5%
Ra
2
100P_0402_50V8J
PCICLK
PCIRST#/GPIO05
ECRST#
SCI#/GPIO0E
CLKRUN#/GPIO1D
100P_0402_50V8J
C504
0.1U_0402_16V4Z
<22> EC_SCI#
<22,40> PM_CLKRUN#
12
13
37
20
38
47K_0402_5%
RB@
+5VS
INVT_PWM/PWM1/GPIO0F
BEEP#/PWM2/GPIO10
FANPWM1/GPIO12
ACOFF/FANPWM2/GPIO13
MISC
C501
@
0.1U_0402_16V4Z
100P_0402_50V8J
CLK_PCI_EC
PCI_RST#
EC_RST#
EC_SCI#
@
1
2
R479
0_0402_5%
<20,31,35> PCI_RST#
GA20/GPIO00
KBRST#/GPIO01
SERIRQ#
LFRAME#
LAD3
LAD2
LAD1
LAD0 LPC &
R471
@
0_0402_5%
Rd
100P_0402_50V8J
SERIRQ
LPC_FRAME#
LPC_AD3
LPC_AD2
LPC_AD1
LPC_AD0
SERIRQ
LPC_FRAME#
LPC_AD3
LPC_AD2
LPC_AD1
LPC_AD0
1
2
3
4
5
7
8
10
100P_0402_50V8J
GATEA20
GATEA20
<16> CLK_PCI_EC
R478 1
2
47K_0402_5%
C500
@
0.1U_0402_16V4Z
100P_0402_50V8J
<21>
2
1
D23
@
<22,35,40>
<21,35,40>
<21,35,40>
C502
<21,35,40>
@
2
1
2
1
<21,35,40>
R476
10_0402_5%
<21,35,40>
@ 22P_0402_50V8J
+3VALW
2
0_0402_5%
KB_RST#
KB_RST#
100P_0402_50V8J
<21>
MB_ID
100P_0402_50V8J
1
R474
MB2_ID
VCC
VCC
VCC
VCC
VCC
VCC
U21
R470
Rb
R469
@
100K_0402_5%
RC
67
+3VALW
AVCC
C499
1000P_0402_50V7K
C498
1000P_0402_50V7K
C497
0.1U_0402_16V4Z
C496
0.1U_0402_16V4Z
C495
0.1U_0402_16V4Z
C494
0.1U_0402_16V4Z
1
L32
1
2
FBM-11-160808-601-T_0603
+EC_AVCC
1000P_0402_50V7K
0.1U_0402_16V4Z
1 ECAGND 2
2
FBM-11-160808-601-T_0603
+EC_AVCC
9
22
33
96
111
125
2 FBM-11-160808-601-T_0603
2
1
C492
C493
1
L31
+3VALW
+3VALW
10/12 Add MB2 ID need check
L30
+3VALW
Title

ENE-KB926

Custom
Date:
Sheet
1
32
of
49
Rev
0.4
INT_KBD Conn.
For JHL90
JP43
KSI1
KSI7
KSI6
KSO9
KSI4
KSI5
KSO0
KSI2
KSI3
KSO5
KSO1
KSI0
KSO2
KSO4
KSO7
KSO8
KSO6
KSO3
KSO12
KSO13
KSO14
KSO11
KSO10
KSO15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
GND
GND
KSI[0..7]
For JHT00
KSI[0..7] <32>
KSO[0..15]
KSO[0..15] <32>
JP44
KSI1
KSI7
KSI6
KSO9
KSI4
KSI5
KSO0
KSI2
KSI3
KSO5
KSO1
KSI0
KSO2
KSO4
KSO7
KSO8
KSO6
KSO3
KSO12
KSO13
KSO14
KSO11
KSO10
KSO15
27
26
ACES_88502-2501
CONN@
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
GND
GND
Delete C525~C548 SE071101J80 (100pF)

Add SI102101K80 (CP : 100pF)
(EMI Recommend)
CP1 <EMI>
KSI4
KSI5
KSO0
KSI2
1
2
3
4
CP4 <EMI>
8
7
6
5
KSO6
KSO3
KSO12
KSO13
100P_1206_8P4C_50V8
1
2
3
4
8
7
6
5
100P_1206_8P4C_50V8
CP2 <EMI>
KSI1
KSI7
KSI6
KSO9
1
2
3
4
CP5 <EMI>
8
7
6
5
KSI3
KSO5
KSO1
KSI0
1
2
3
4
100P_1206_8P4C_50V8
100P_1206_8P4C_50V8
CP3 <EMI>
27
26
KSO2
KSO4
KSO7
KSO8
ACES_88502-2501
CONN@
1
2
3
4
CP6 <EMI>
8
7
6
5
KSO14
KSO11
KSO10
KSO15
1
2
3
4
100P_1206_8P4C_50V8
8
7
6
5
8
7
6
5
100P_1206_8P4C_50V8
Function Board Conn.

Power USB Board Conn.
+3VS
+3VALW
+5VS
+5VALW
R817 2
1 0_0603_5%
R816 2
1 0_0603_5%
R805 2
1 0_0603_5%
R806 2
<32>
<32>
<32>
<32>
<32>
B
+5V_SW
1 0_0603_5%
CLK_GUEST
DATA_GUEST
ACK_GUEST
SM_KEY#
SM_KEY_LED#
<32> CAPS_LED#
<32> NUM_LED#
JP48
CLK_GUEST
DATA_GUEST
ACK_GUEST
SM_KEY#
SM_KEY_LED#
CAPS_LED#
NUM_LED#
1
2
3
4
5
6
7
8
9
10
11
12
+5VALW
1
2
3
4
5
6
7
8
9
10
GND
GND
JP62
1
2
3
4
5
6
7
8
ON/OFFBTN#
D_P_USB#
PWR_LED#
POWER_USB_LED#
<35> ON/OFFBTN#
<32,40> PWR_LED#
<32> POWER_USB_LED#
1
2
3
4
5
6
GND
GND
ACES_85201-06051
ACES_85201-1005N
CONN@
+3VALW
C759
2 @ 100P_0402_50V8J
1
ACK_GUEST
R659
10K_0402_5%
D67
D_P_USB#
P_USB#
51_ON#
P_USB#
<32>
51_ON#
<35,42>
DAN202UT106_SC70-3
Compal Secret Data

Deciphered Date
2008/8/18
5
Title
KB/SW/PW Conn
Size
B
Date:
Document Number
Rev
ai
2007/08/18
Issued Date
0.4
Tuesday, April 22, 2008
he
x
nf
@
ho
tm
ai
l.c
om
Sheet
33
of
49
+3VALW +5VALW
2
R521
1 EEPROM_VCC
0_0603_5%
2
R522
1
0_0603_5%
8M SPI ROM
16M SPI ROM
For iTPM+HDCP
+3VALW
For EC+BIOS+VBIOS
EEPROM_VCC
2 EC_SMB_CK1
4.7K_0402_5%
2 EC_SMB_DA1
4.7K_0402_5%
EEPROM_VCC
@
C550 1
2 0.1U_0402_16V4Z
8
7
6
5
<32,43> EC_SMB_CK1
<32,43> EC_SMB_DA1
C551
R525
@
100K_0402_5%
0.1U_0402_16V4Z
C549
@
0.1U_0402_16V4Z
Andy
VCC
WP
SCL
SDA
A0
A1
A2
GND
1
2
3
4
<32>
<32>
SPI_CLK_R
<32>
SPI_SI
SPI_CS#
VCC
VSS
4
<22> ICH_SPI_CS0#_R
HOLD
<22> ICH_SPI_CLK_R
<22> ICH_SPI_MOSI_R
SPI_CLK_R
SPI_SI
AT24C16AN-10SU-2-7_SO8
U22 @
U23
8
SPI_CS#
20mils
20mils
U24 @
12/28 Add
@
1
R523
@
1
R524
SA00001IT00
16Mbit 12/10
+3VALW
EEPROM_VCC
VCC
HOLD
ICH_SPI_CS0#_R
ICH_SPI_CLK_R
ICH_SPI_MOSI_R
VSS
ICH_SPI_MISO_R
@
R526
15_0402_5%
SPI_SO 2
D
Q 2
R527
SST25LF080A_SO8-200mil
1
0_0402_5%
FRD#SPI_SO <32>
R528
@
100K_0402_5%
0206 => change PN to SA00001N800
follow CRB Check

SD028150A80
12/19 change pn to SA00001MP00 ( original part EOL )
ICH_SPI_MISO <22>
SST25LF080A_SO8-200mil
12/25 change back to SA024160140 ( Samples can not on time )
12/15 change from 15 to 0 ohm'
Bluetooth Conn.
To TP/B Conn.
Need to check BT pin definition again!

9/20 modified this block
JP12
+5VS
<32>
<32>
L39 <EMI>
R529
+5VS
+BT_VCC
R530
10K_0402_5%
SWR#
JP42
1
2
3
4
5
6
7
8
9
10
1
2
3
4
5
6
7
8
GND1
GND2
SWL#
+5VS
D25
@
PSOT24C_SOT23
MOLEX_53780-0870
CONN@
C552
0.1U_0402_16V4Z
Update Footprint
15W Use
+3VALW
C553
3
Left Switch
SWL#
SW5
Left Switch
SMT1-05_4P
14W@
3
SMT1-05_4P
15W@
C554
1U_0603_10V4Z
Q19
SI2301BDS_SOT23
W=40mils
+BT_VCC
C557
@
4.7U_0805_10V4Z
SW6
SWR#
Right Switch
6
5
6
5
2
100K_0402_5%
1
R531
BT_ON#
<32>
0.1U_0402_16V4Z
SW4
SWL#
6
5
6
5
14W Use
1
2
3
4
5
6
GND
GND
ACES_85201-06051
BT_ACTIVE
USB20_P6
USB20_N6
BTON_LED
2
G
<30> BT_ACTIVE
<22> USB20_P6
<22> USB20_N6
D
Q18
SSM3K7002FU_SC70-3
WCM2012F2SF-121T04_0805
@
USB20_R_P6
1 <EMI> 2
R638 1
USB20_R_N6
2 0_0402_5%
0_0402_5%
R639
<EMI>
WLAN_ACTIVE
<30> WLAN_ACTIVE
BT_LED#
1
BT_LED#
TP_DATA
TP_CLK
10K_0402_5%
<40>
1
2
3
4
5
6
7
8
SWR#
SWL#
TP_DATA
TP_CLK
SWR#
Right Switch
SMT1-05_4P
14W@
C558
SW7
3
SMT1-05_4P
15W@
0.1U_0402_16V4Z
Issued Date
Compal Secret Data
2007/08/18
Deciphered Date
2008/8/18
Title
BIOS, TP & BT Connector

Size
B
Date:
Document Number

Sheet
34
of
49
Rev
0.4
ON/OFF switch
TOP Side
J3
J4
12/4 Change D14 to correct symbols
1
@ JOPEN
1
@ JOPEN
FOR LPC DEBUG PORT
FOR LPC SIO DEBUG PORT
+3VS
JP54
+3VALW
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Bottom Side
R533
JP57
100K_0402_5%
1
D26
ON/OFFBTN#
<33> ON/OFFBTN#
ON/OFF#
51_ON#
ON/OFF# <32>
51_ON# <33,42>
DAN202UT106_SC70-3
Power Button
C561
D27
CLK_PCI_DB
CLK_PCI_DB <16>
LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
LPC_FRAME#
LPC_AD0 <21,32,40>
LPC_AD1 <21,32,40>
LPC_AD2 <21,32,40>
LPC_AD3 <21,32,40>
LPC_FRAME# <21,32,40>
PCI_RST#
PCI_RST# <20,31,32>
1
ACES_85201-1005N
DBCONN@
C562
@
0.1U_0402_16V4Z
+5VS
+3VS
CLK_14M_SIO <16>
LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
LPC_FRAME#
LPC_DRQ0#
PCI_RST#
LPC_DRQ0# <21>
2 A@
R534
CLK_PCI_DB
SERIRQ
1
10K_0402_5%
SERIRQ <22,32,40>
ACES_85201-2005
DBCONN@
RLZ20A_LL34
2
1000P_0402_50V7K
1
1
2
3
4
5
6
7
8
9
10
11
12
1
2
3
4
5
6
7
8
9
10
GND
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
3ON/OFFBTN#
4
EC_ON
EC_ON
2
G
6
5
<32>
SMT1-05_4P
SW3
A@
R535
Q21
SSM3K7002FU_SC70-3
10K_0402_5%
1
10/09 add for debug

2
CIR
USB IO Conn.
+3VALW
JP51
<32>
<32>
RCIRRX
CIR_DET#
RCIRRX
CIR_DET#
1
2
3
4
+USB_VCCC
5
6
15
26
3
4
JP52
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
ACES_85201-0405
15WCONN@
Change JP51 from 18 pin to 4 pin

11/09 Andy
3
150u
ESR 0.9 ohm
Rating 6.3V
<22>
<22>
USB20_N0
USB20_P0
USB20_N0
USB20_P0
<22>
<22>
USB20_N5
USB20_P5
USB20_N5
USB20_P5
<22>
<22>
USB20_N11
USB20_P11
USB20_N11
USB20_P11
ACES_85201-20051
+USB_VCCC
W=80mils
+USB_VCCC
1
+
2
1
1
C564
@
150U_D_6.3VM
470P_0402_50V7K 2
R537 1
+USB_VCCC
copy LM75CIMMX-3_MSOP8
footprint
2 100K_0402_5%
R468
VDD
U26
OUTPUT
C566
LID_SW# <32>
2
GND
IN
IN
EN#
OUT
OUT
NC
OC
8
7
6
5
10K_0402_5%
R691 0_0402_5%
2
1
USB_OC#04 <22>
USB_OC#511 <22>
G545A2P8U MSOP 8P
4.7U_0805_10V4Z
C567
C568
4
10P_0402_50V8J
<32>
0.1U_0402_16V4Z
2 @
USB2_ON#
om
U25
A3212ELHLT-T_SOT23W-3
A
Title
Power OK/Lid/Front,IO,DB Conn

Size
B
Date:
Document Number
Rev
ai
2008/8/18
Deciphered Date
he
x
2007/08/18
Issued Date
Compal Secret Data
nf
@
ho
tm
ai
1
2
3
4
l.c
0.1U_0402_16V4Z
4
1
GND
C565
+3VALW
+VCC_LID
2
0_0402_5%
10U_0805_10V4Z
11/29 change this symbol's footprint as

ADT7421ARMZ-REEL_MSOP8
+5VALW
1
R536
C768
C563
Lid Switch
+3VALW
Sheet
35
of
49
+3VS_DVDD
C575
C577
@
100P_0402_50V8J
10mil
MIC2_R
<37>
MIC1_R
MIC1_R_L
2
1K_0402_5%
MIC1_R_R
2
1K_0402_5%
C594 1
@
1
R717
1
R718
AMP_LEFT_HP
AMP_RIGHT_HP
MIC2_L
HP_OUT_L
C585 2.2U_0603_6.3V6K
MIC2_C_R
17
MIC2_R
HP_OUT_R
41
23
LINE1_L
NC
45
24
LINE1_R
DMIC_CLK
46
18
CD_L
NC
43
20
CD_R
NC
44
19
CD_GND
MIC1_C_L
21
MIC1_L
MIC1_C_R
22
MIC1_R
12
PCBEEP
C591 2.2U_0603_6.3V6K
C592 2.2U_0603_6.3V6K
2 100P_0402_50V8J
MONO_IN
11
10
5
2
3
13
34
SENSE_A
SENSE_B
SPDIFO
SPDIFO
2
1
R546 PM@ 0_0402_5%
2
1
<22>
SB_SPKR
1 R543
2
10K_0402_5%
1 R804
2
0_0402_5%
MONO_IN_1 1
C582
4
7
DVSS1
DVSS2
R544
SDATA_IN
SDIN0
MONO_OUT
37
LINE1_VREFO
29
GPIO1
31
MIC1_VREFO_L
28
MIC1_VREFO_R
32
MIC2_VREFO
30
VREF
27
JDREF
40
NC
33
AVSS1
AVSS2
26
42
HDA_BITCLK_AUDIO
1
R545
2
33_0402_5%
HDA_SDIN0
Sense Pin
<21>
Impedance
<21>
SENSE A / B
10mil
10mil
10mil
+MIC1_VREFO_L
Need Update Footprint
9/19 Realtek suggest

Add bypass schematic.
Codec Signals
Funnction
39.2K
PORT-A (PIN 39, 41)
HP
20K
PORT-B (PIN 21, 22)
MIC
10K
PORT-C (PIN 23, 24)
LINE IN
5.1K
PORT-D (PIN 35, 36)
LINE OUT
39.2K
PORT-E (PIN 14, 15)
HP
20K
PORT-F (PIN 16, 17)
MIC
10K
PORT-G (PIN 43, 44)
LINE IN
5.1K
PORT-H (PIN 45, 46)
LINE OUT
+MIC1_VREFO_R
+MIC2_VREFO
10mil
ACZ_VREF
ACZ_JDREF
SENSE B
1
R548
20K_0402_1%
ALC268-GR_LQFP48
DGND
R542 1
@
2
Q22
2.4K_0402_5%
@
2SC2411K_SOT23
D28
@
10K_0402_5%
AMP_RIGHT_HP <37>
MONO_IN
2
0.1U_0402_16V4Z
GPIO0
GPIO3
SENSE A
SENSE B
SPDIFO
PCI Beep
AMP_LEFT_HP <37>
HDA_BITCLK_AUDIO
SDATA_OUT
EAPD
2
B
E
AMP_RIGHT <37>
SYNC
48
10_0402_5%
@
C598
1 R541
2
10K_0402_5%
AMP_LEFT <37>
BIT_CLK
RESET#
47
R547
BEEP#
EAPD
<32>
AMP_RIGHT
<21> HDA_SDOUT_AUDIO
AMP_LEFT
36
39
<21> HDA_SYNC_AUDIO
<17>
DVDD
35
LINE_OUT_R
16
<21> HDA_RST_AUDIO#
<37>
DVDD_IO
LINE_OUT_L
NC
0_0402_5%
EC Beep
38
25
NC
15
MIC2_C_L
2/01 Let them floating
MIC1_L
14
2 0.1U_0402_16V4Z
R540
C581
@
4.7U_0805_10V4Z
C589 2.2U_0603_6.3V6K
<37>
+1.5VS
C596
10U_0805_10V4Z
C597
100P_0402_50V8J
<38>
MIC2_R_L
2
1K_0402_5%
MIC2_R_R
2
1K_0402_5%
1
R715
1
R716
AVDD2
AVDD1
U27
MIC2_L
C580
2
2
0.1U_0402_16V4Z
0.1U_0402_16V4Z
<38>
C572 1
+3VS
L35 1
2
FBMA-L11-160808-800LMT_0603
GM@
PM@ 0_0603_5%
C574
R539
C573
10U_0805_10V4Z
R538
@
10K_0402_5%
0_0603_5%
+VDDA
+3VS
10/03 add +1.5VS
+1.5VS_DVDD
40mil
0.1U_0402_16V4Z
L33 1
2
FBMA-L11-160808-800LMT_0603
C571
@
4.7U_0805_10V4Z
L34
2
2
0.1U_0402_16V4Z
+AVDD_AC97
+VDDA
C570
10mil
HD Audio Codec
AGND
15P_0402_50V8J
2 @
SENSE FOR Ext. Mic.
HDA_BITCLK_AUDIO
2
1
R550
SENSE_A
2
20K_0402_1%
10_0402_5%
@
L36
10P_0402_50V8J
2 @
40mil
U28
60mil
+5VS
C599
+5VS_VDDA
0_0603_5%
SENSE FOR Solo Int. Mic.
C600
1
C601
2
3
10U_0805_10V4Z 2
@
1
R551
PAD-OPEN 3x3m
<37> MIC_SENSE
J9
Regulator for CODEC
R549
2 0.1U_0402_16V4Z
IN
OUT
BYP
GND
SHDN
G9191-475T1U_SOT23-5
1
C603
SENSE_B
2
20K_0402_1%
+VDDA
(Max output = 300 mA)
0.01U_0402_16V7K
4.75V
C602
4.7U_0805_10V4Z
2 @
Moat Bridge
10/2 change circuit
SENSE FOR HP
2
R554
SENSE_A
1
39.2K_0402_1%
1
R555
1
R556
2
0_0805_5%
2
0_0805_5%
Compal Secret Data
<37> HP_SENSE
U8 change footprint
Issued Date
2007/08/18
Deciphered Date
2008/8/18
3
Title
<Title>
HD Audio Codec ALC268

Custom
Date:
Sheet
1
36
of
49
Rev
0.4
+MIC1_VREFO_R
+MIC1_VREFO_L
10mil
+5VALW
R557
+5VS
1
C612
1
C613
<36> AMP_LEFT_HP
1
2
R569 0_0402_5%
1
C614
MIC1_L
<36> MIC1_L
C610
<EMI>
220P_0402_50V7K
FOX_JA6333L-B3S0-7F~N
CONN@
R564 1
AMP_RHPIN
2
4.7U_0805_10V4Z
AMP_LHPIN
2
4.7U_0805_10V4Z
AMP_SD#
2
0.47U_0603_16V4Z
INR_A
INL_A
27
/AMP EN
2 100K_0402_5% HP_EN
24
HP EN
4
6
INR_H
INL_H
INR_H
2
39K_0402_5%
INL_H
2
39K_0402_5%
1
R565
1
R566
1
R567
1
C618
C620
AMP_BEEP
2
0_0402_5%
AMP_CP+
AMP_CP2
1U_0603_10V6K
AMP_BIAS
2.2U_0603_6.3V6K
1
0.1U_0402_16V4Z
26
/SD
28
BEEP
12
14
CP+
CP-
25
BIAS
ROUT+
ROUT-
22
21
SPKR+
SPKR-
LOUT+
LOUT-
8
9
SPKL+
SPKL-
HP_R
HP_L
17
18
HP_R
HP_L
CVSS
15
CVSS
VSS
16
GND
PGND
PGND
CGND
GND
2
23
7
13
29
10mil
HEADPHONE
OUT JACK
C619
1U_0603_10V6K
JP64
HP_SENSE
<36> HP_SENSE
5
4
APA2057A_TSSOP28
HP_L
11/28 Modified to X5R
R570
@
0_0402_5%
1
R568
C615
<EMI>
@
0_0402_5%
10P_0402_50V8J2
10
9
8
7
3
6
2
1
C616
<EMI>
IN_A Gain = 10dB (Internal Speaker)

IN_H Gain = 0dB (Headphone)
L49 1
2 <EMI> HPR
KC FBM-L11-160808-121LMT 0603
L50 1
2 <EMI> HPL
KC FBM-L11-160808-121LMT 0603
2
HP_R
9/5 If implement AMP BEEP, Swap C641 and R524.

R524 change from 0 Ohm to 47K
RED
@
D29
PSOT05C-LF-T7 SOT-23-3
<EMI>
Trace width/spacing/other=8/6/50
3
5
AMPL
2 100K_0402_5% AMP_EN#
C617
10
9
8
7
3
6
2
1
3
L47 1
2 <EMI> MIC1_R_1
KC FBM-L11-160808-121LMT 0603
L48 1
2 <EMI> MIC1_L_1
KC FBM-L11-160808-121LMT 0603
1
C611
<EMI>
220P_0402_50V7K
2
MIC1_R
<36> MIC1_R
VDD
19
20
10
PVDD
PVDD
11
JP63
5
AMPR
2
1U_0603_10V4Z
2
1U_0603_10V4Z
R563 1
<36> AMP_RIGHT_HP
2.2K_0402_5%
1U_0603_10V4Z
<36> AMP_LEFT
MIC_SENSE
<36> MIC_SENSE
C607
1
C609
1
C608
<36> AMP_RIGHT
U29
+3VALW
CVDD
fo=1/(2*3.14*R*C)=106Hz
R=1.5K / C= 1uF
HVDD
R560 @ 1.5K_0402_1%
1
2
R562 @ 1.5K_0402_1%
1
2
10U_0805_10V4Z
C606
MICROPHONE
IN JACK
R558
2.2K_0402_5%
1
C605
0.1U_0402_16V4Z
C604
680P_0402_50V7K
W=40mil
10mil
10/2 U6 APA2057A P/N:SA00001QD00
APA2057 SPK/HP Amplifier
FOX_JA6333L-B3S0-7F~N
CONN@
2 10P_0402_50V8J
@
D30
<EMI>
1
11/28 Change to SE080105K80
Trace width/spacing=15/9
GREEN
Add below circuit for APA2057 gain tunning use

1
+5VALW
R571
10K_0402_1%
2
+3VALW
AMP_SD#
2
3
C621
1
0_0402_5%
1
2
R577
0.01U_0402_16V7K
HP_EN
3
C622
22K_0402_1%
0.1U_0402_16V4Z
Q23
2
G
Q24
2
G
EAPD
2 10K_0402_5%
R574
10K_0402_5%
<36> EAPD
R572 1
R573
SSM3K7002FU_SC70-3
1/8 change JSPK1 following JAW91
SSM3K7002FU_SC70-3
JSPK1
3.48
11
3.56
3.62
3.59
12
3.68
3.73
3.70
13
3.80
3.85
3.82
4
3
2
1
6
5
G2
G1
ACES_88266-04001
CONN@
Speaker Conn.
D32
@
PSOT24C_SOT23
<EMI>
ai
l.c
om
D31
@
PSOT24C_SOT23
<EMI>
+5VALW assume equal 5.1V

10 dB ---> 5.1 x 220 / 320 = 3.5
Compal Secret Data
2007/08/18
Issued Date
2008/8/18
Deciphered Date
A
4
3
2
1
nf
@
ho
tm
3.51
SPK_L1SPK_L1+
SPK_R1SPK_R1+
Title
AMP/VR/Audio Jack

Custom
ai
3.45
0_0603_5%
0_0603_5%
0_0603_5%
0_0603_5%
Date:
he
x
10
20mil
<EMI>
<EMI>
<EMI>
<EMI>
Recommended (V)
2
2
2
2
High (V)
1
1
1
1
Low (V)
R580
R578
R581
R579
Gain (dB)
SPKLSPKL+
SPKRSPKR+
Gain= 10dB
Sheet
37
of
49
Rev
0.4
SINGLE INT MIC/DUAL INT MIC

1
+3VS
R723
10K_0402_5%
@
2
0_0402_5%
+MIC2_VREF_R
C723
0.1U_0402_16V4Z
@
R724
27K_0402_5%
@
2/01 Add D52 for INT MIC use( PN:SCD0T05CA20 )

D52 is a modified symbol
2 R582
1
@ 0_0402_5%
+MIC2_VREF_R
D70 DUAL@
1
1 R583
2 DUAL@
2.2K_0402_5%
RLS4148_LL34-2
JMIC1
1
2
GND
GND
3
4
MIC2_L_OUT
C623
<EMI>
1
220P_0402_50V7K
DUAL@
D34
1
2
ACES_88231-02001
DUALCONN@
1
R725
+MIC2_VREFO
+MIC2_VREFO
R585
0_0402_5%
SINGLE@
1
R707
2 <EMI>
0_0402_5%
MIC2_L
1
R708
2 <EMI>
0_0402_5%
MIC2_R
MIC2_L <36>
@
1
2 R586
1
SINGLE@
0_0402_5%
+MIC2_VREF_R
D71 DUAL@
1
1 R587
2
2.2K_0402_5%
RLS4148_LL34-2
JMIC2
1
2
1
2
GND
GND
3
4
MIC2_R_OUT
C625
<EMI>
1
220P_0402_50V7K
MIC2_R <36>
12/21 Place these parts close to CODEC (U7)
ACES_88231-02001
Issued Date
Compal Secret Data
2007/08/18
Deciphered Date
2008/8/18
Title
MIC
Size
B
Date:
Document Number
Rev
0.4

Sheet
38
of
49
11/27 Add screw for layout request
H22
HOLEA
H23
HOLEA
H14
HOLEA
H13
HOLEA
H12
HOLEA
H11
HOLEA
H10
HOLEA
H8
HOLEA
H7
HOLEA
H6
HOLEA
H5
HOLEA
H4
HOLEA
H3
HOLEA
H2
HOLEA
H_3P0
H1
HOLEA
H26
HOLEA
H_3P7
2
H31
HOLEA
H30
HOLEA
H29
HOLEA
H28
HOLEA
H_4P2
2/22 change these from H_3P7 to H_3P8

H32
HOLEA
H27
HOLEA
FD4
@
FD5
@
FD6
@
FD3
@
FD2
@
H20
HOLEA
FD1
H19
HOLEA
H18
HOLEA
M2
HOLEA
M1
HOLEA
H17
HOLEA
H16
HOLEA
H15
HOLEA
2/22 change these from H_3P2 to H_3P3
H25
HOLEA
H24
HOLEA
H21
HOLEA
H9
HOLEA
H_5P0X3P2N
M3
HOLEA
H_5P0X3P2N
M4
HOLEA
M5
HOLEA
H_3P1N
H_5P0X3P2N
Compal Secret Data

2008/8/18
Deciphered Date
A
Title

Screw
Size
Document Number
Rev
0.4
ai
2007/08/18
Issued Date

Date:
he
x
nf
@
ho
tm
ai
l.c
om
H_5P2X3P2N
11/27 Add screw for layout request

4
Sheet

E
39
of
49
Camera Conn
R590 2
+5VS
MDC Conn.
1 0_0603_5%
R591 2
+5VALW
0_0603_5%
20mil
+VCC_MDC
1 R695
PM@
2 0_0402_5%
GM@
2 0_0402_5%
+3V_MDC
1 R697
2 0_0402_5%
JMDC1
<21> HDA_SDOUT_MDC
<21> HDA_SYNC_MDC
HDA_SDOUT_MDC
HDA_SYNC_MDC
SDIN1_MDC
HDA_RST_MDC#
GND1
RES0
IAC_SDATA_OUT
RES1
GND2
3.3V
IAC_SYNC
GND3
IAC_SDATA_IN
GND4
IAC_RESET#
IAC_BITCLK
2
4
6
8
10
12
GND
GND
GND
GND
GND
GND
<21> HDA_RST_MDC#
1
3
5
7
9
11
1 R710
C627
+3VS
+3VS
4.7U_0805_10V4Z
+1.5VS
C628
0.1U_0402_16V4Z
JP3
<22>
<22>
HDA_BITCLK_MDC
1
C629
USB20_N2
USB20_P2
USB20_N2
USB20_P2
R594 1
R595 1
+5V_CAMERA 1
2
3
4
5
6
7
USB20_R_N2
USB20_R_P2
2 0_0402_5%
2 0_0402_5%
HDA_BITCLK_MDC <21>
@
WCM2012F2SF-121T04_0805
4
1
L42
ACES_88266-05001
CAMCONN@
13
14
15
16
17
18
22P_0402_50V8J
2 @
Connector for MDC Rev1.5
1
2
3
4
5
GND1
GND2
ACES_88018-124G
CONN@
+VCC_MDC
+3V_MDC
R593
<21> HDA_SDIN1
HDA_SDIN1
Finger Print board
33_0402_5%
C746
0.1U_0402_16V4Z
2
@
For EMI
1/05 Modified D3 to SCA00000A00
SDIN1_MDC
0.1U_0402_16V4Z
2 @
@
WCM2012F2SF-121T04_0805
D36 @
3
I/O
I/O
VCC
Please add these caps close to JMDC1 as close as possible,
C752
2 @ 100P_0402_50V8J
HDA_SYNC_MDC
C753
2 @ 100P_0402_50V8J
HDA_RST_MDC#
C754
2 @ 100P_0402_50V8J
HDA_SDIN1
C756
2 @ 100P_0402_50V8J
USB20_P1
USB20_N1
<22> USB20_P1
<22> USB20_N1
1
L40
+5VS
GND
PRTR5V0U2X_SOT143
HDA_SDOUT_MDC
2/1 change JP4 pin 6 to +5VS for LTT FP use
0208 Remove D3 , Add D55 (SC300000G00)
C745
JP4
1
2
3
4
5
6
7
8
R640 10_0402_5%2USB20_R_P1
1
2USB20_R_N1
R641 0_0402_5%
+3VS
4.7U_0805_10V4Z
@ 2
C630
ACES_85201-06051
FPCONN@
C631
0.1U_0402_16V4Z
Let C715 close pin 24
Let C724 close pin 10
Copy IFT
+3VS
+3VALW
TPM 1.2
VDD
VDD
VDD
1 LED1
PWR_LED# <32,33>
<21,32,35>
<21,32,35>
<21,32,35>
<21,32,35>
LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
LPC_AD0
LPC_AD1
LPC_AD2
LPC_AD3
26
23
20
17
LAD0
LAD1
LAD2
LAD3
LPCPD#
TESTB1/BADD
TEST1
28
9
8
XTALO
XTALI
14
13
GPIO2
GPIO
2
6
HT-191NB_BLUE_0603
+5VALW
R598
1
2
3.3K_0402_5%
HT-191UD_AMBER_0603
2
1 LED6
1 LED7
Amber
CHARGE_LED0# <32>
21
22
16
27
15
7
LCLK
LFRAME#
LRESET#
SERIRQ
CLKRUN#
PP
GND
GND
GND
GND
R597
3.3K_0402_5%
1
2
CLK_PCI_TPM
CLK_PCI_TPM
LPC_FRAME#
LPC_FRAME#
PLT_RST_BUF#
PLT_RST_BUF#
SERIRQ
SERIRQ
PM_CLKRUN#
PM_CLKRUN#
1
2
R698
4.7K_0402_5%
IN_TPM@
Blue
CHARGE_LED1# <32>
4
11
18
25
+5VALW
<16>
<21,32,35>
<8,17,20,26,28,30>
<22,32,35>
<22,32>
+3VS
TPM
SLB 9635 TT 1.1
HT-191NB_BLUE_0603
TPM_TEST1
R703 1
2
IN_TPM@
R701
4.7K_0402_5%
@
NC
NC
NC
1
3
12
C717
IN_TPM@
15P_0402_50V8J
TPM_XTALI
SLB-9635-TT-1.2_TSSOP28
IN_TPM@
2
R699
@ 10_0402_5%
0_0402_5%
TPM_XTALO
TPM_XTALI
CLK_PCI_TPM
Blue&Amber
R700
4.7K_0402_5%
TPM@
Base I/O Address

0 = 02Eh
1 = 04Eh
*
SUS_STAT#
SUS_STAT# <22>
U32
SATA_LED# <21>
1 LED4
IN_TPM@
R702
10M_0402_5%
2
1
+5VALW
C724
WB_TPM@
1U_0402_6.3V4Z
+3VS
HT-191NB_BLUE_0603
R596
4.3K_0402_5%
1
2
R660
4.3K_0402_5%
1
2
C715
VSB
+5VS
0.1U_0402_16V4Z
TPM@ 2
+3VS
24
19
10
LED
1
2
3
4
5
6
GND
GND
U32
X3
1
IN
NC
OUT
NC
32.768KHZ_12.5P_1TJS125BJ2A251
IN_TPM@
TPM_XTALO
+5VS
+5VS
R599
3.3K_0402_5%
1
2
R600
1
2
3.3K_0402_5%
HT-191UD_AMBER_0603
2
1 LED5
1 LED3
C718
IN_TPM@
15P_0402_50V8J
Amber
WLAN_LED# <30>
C716
@ 15P_0402_50V8J
S IC WPCT200AA0WG TSSOP 28P TPM

WB_TPM@
Blue
BT_LED# <34>
12/7 Modified LED footprint to LED_HT-297UD-CB_4P

12/15 Modified to correct LED symbol!
Issued Date
Compal Secret Data
HT-191NB_BLUE_0603
2007/08/18
Deciphered Date
2008/8/18
Title
MDC/LED/Camera/FP
Size
B
Date:
Document Number
Rev

Sheet
40
of
49
+1.5V TO +1.5VS
+5VALW TO +5VS
+5VALW
+1.5V
+3VALW TO +3VS
+5VS
+3VALW
+3VS
J8
PAD-OPEN 3x3m
2
+1.5VS
U30
U31
SUSP
1
1
Q28
SSM3K7002FU_SC70-3
2
G
C634
AO4468_SO8
C635
8
7
6
5
R602
10U_0805_10V4Z
2
@ 2
1U_0603_10V4Z
Q51A
@
2
5VS_GATE
R604
33K_0402_5%
470_0603_5%
@
470_0603_5%
@
D
D
D
D
S
S
S
G
1
2
3
4
C643
C644
10U_0805_10V4Z
2
@ 2
1U_0603_10V4Z
AO4468_SO8
@
Q51B
@
SUSP
5
2N7002DW-T/R7_SOT363-6
+VSB
C638
1
2
R605
47K_0402_5%
SUSP
0.1U_0603_25V7K
2
G
Q29
SSM3K7002FU_SC70-3
SUSP
2N7002DW-T/R7_SOT363-6
+VSB
C639
0.1U_0603_25V7K
1
2
R612
47K_0402_5%
@
SUSP
2
G
Q35
SSM3K7002FU_SC70-3
@
10U_0805_10V4Z
2
@ 2
1U_0603_10V4Z
R601
C633
U34
1
2
3
4
S
S
S
G
3 1
D
D
D
D
C632
AO4468_SO8
+VSB
8
7
6
5
1
2
3
4
S
S
S
G
D
D
D
D
6 1
8
7
6
5
0.1U_0603_25V7K
2 @
C646
+5VALW
2
+5VALW
2
R613
100K_0402_5%
1
R621
100K_0402_5%
SUSP
Q36
SSM3K7002FU_SC70-3
S
2
G
3
<31,32,46> SYSON
SYSON#
SYSON
1
R622
2
10K_0402_5%
<26,47>
Q43
SSM3K7002FU_SC70-3
1
2
G
<17,31,32,46,47> SUSP#
R614
SUSP
C647
100P_0402_50V8J
10K_0402_5%
2
3/14 Change R16 from 100K to 10K
+1.05VS
SUSP
2N7002DW-T/R7_SOT363-6
Q47A
@
2 SUSP
1
Q48B
@
5
2N7002DW-T/R7_SOT363-6
R619
470_0603_5%
@
1
3
R618
470_0603_5%
@
SUSP
2N7002DW-T/R7_SOT363-6
Q48A
@
2
Q47B
@
+1.8V
R617
470_0603_5%
@
R615
470_0603_5%
@
+0.9VS
+1.5VS
SYSON#
2N7002DW-T/R7_SOT363-6
2008/8/18
A
Title
DC Interface
Size
B
Date:
Document Number
ai
Deciphered Date
Rev
0.4
he
x
2007/08/18
Issued Date
Compal Secret Data
nf
@
ho
tm
ai
l.c
om
Sheet
E
41
of
49
DC301001Y00
PR2
PC5
@ 10K_0402_1% @ 0.01U_0402_25V7K
1
2
1
2
1
2
1
2
PC4
0.022U_0603_50V7K
RTCVREF
1
PR9
10K_0402_1%
PR10
10K_0402_1%
2
1
8
P
Vin Detector
PU2A
LM393DG_SO8
PU2B
LM393DG_SO8
PD2
RLZ4.3B_LL34
<22,32,44>
ACIN
PR6
10K_0402_1%
1
2
PC7
0.1U_0402_16V7K
PR5
10K_0402_1%
2
1
PR4
84.5K_0402_1%
1
PR8
20K_0402_1%
2
1
2
PC6
1000P_0603_50V7K
VS
PR7
22K_0402_1%
1
2
VS
PR3
1M_0402_1%
1
2
VIN
PC3
0.022U_0603_50V7K
PC142
2200P_0402_50V7K
2
1
1
2
PC2
0.01U_0402_50V7K
PJP1
1
VIN
PL1
HCB4532KF-800T90_1812
1
2
ADPIN
PC1
0.01U_0402_50V7K
@ SINGA_2DW-0268-B16
1 1
2 2
3 3
4 4
High 18.764 17.901 17.063

Low 17.745 16.9
16.03
3.3V
VIN
PD3
RLS4148_LL34-2
PD4
RTCVREF
RLS4148_LL34-2
G920AT24U_SOT89-3
1
2
2
1
2
PR17
22K_0402_1%
1
2
<33,35> 51_ON#
VS
PC10
0.22U_1206_25V7K
PR16
100K_0402_1%
GND
CHGRTCP
IN
OUT
PR15
200_0805_5%
2
1
PC9
1U_0805_25V4Z
+CHGRTC
PU3
1
3
PR14
560_0603_5%
2 1
2
PC8
4.7U_0805_10V4Z
PR13
560_0603_5%
PC11
0.1U_0603_25V7K
BATT+
2
1
PR11
68_1206_5%
2
1
PR12
68_1206_5%
3.3V
PQ1
TP0610K-T1-E3_SOT23-3
+1.8VP
PJ1
1
PAD-OPEN 3x3m
2
+1.8V
PJ14
1
PAD-OPEN 3x3m
2
(8A,320mils ,Via NO.= 16)
+5VALWP
PJ2
PAD-OPEN 3x3m
2
+5VALW

4
+3VALWP
PJ5
PAD-OPEN 3x3m
1
2
+0.9VSP
PJ6
PAD-OPEN 3x3m
2
+0.9VS
+3VALW
+VSBP
PJ3
PAD-OPEN 3x3m
2
PJ4
1
+1.05VSP
PAD-OPEN 3x3m
2
+1.05VS
(16A,800mils ,Via NO.= 24)
PJ7
(6A,240mils ,Via NO.=12)
+1.5VP
PAD-OPEN 3x3m
1
2
+VSB
(0.3A,40mils ,Via NO.= 2)
Issued Date
2005/10/17
Deciphered Date
2006/10/17
(6A,240mils ,Via NO.=12)

A
Compal Secret Data
+1.5V
Title
DCIN/DECTOR
Size
B
Date:
Document Number
Rev
0.2
Sheet

D
42
of
49
PJ8
PAD-OPEN 3x3m
2
BATT+
PH1 under CPU botten side :

CPU thermal protection at 89 degree C
Recovery at 70 degree C
PJP2
PR27
78.7K_0603_1%
1
2
PU4A
3 +
PD5
0
-
MAINPWON <21,45>
1SS355TE-17_SOD323-2
<BOM Structure>
PR31
150K_0402_1%
1
2
PR28
2 150K_0402_1%
1
VL
1
PR30
1K_0402_1%
LM358ADR_SO8
<BOM Structure>
PC17
1U_0603_6.3V6M
+3VALWP
1
2
PR29
6.49K_0402_1%
PH1
100K_0603_1%_TH11-4H104FT
1
2
1
2
PC16
1000P_0402_50V7K
EC_SMB_DA1 <32,34>
1
2
PR23
150K_0402_1%
PR24
1 442K_0603_1%
2
1
PR26
100_0402_1%
2
2
1
PR25
100_0402_1%
VL
TM_REF1
EC_SMB_CK1 <32,34>
1
1
PR22
10K_0402_1%
VS
VL
PC14
0.01U_0402_50V7K
PR20
1K_0402_1%
SUYIN_200275MR009G180ZR
@ 100K_0402_5%
@ PR18
100K_0402_5%
+3VALWP
PC13
1000P_0402_50V7K
PR19
+3VALWP
CNT1
CNT2
EC_SMCA
EC_SMDA
TS_A
GND
PC12
1000P_0402_50V7K
PR21
1K_0402_1%
1
2
BATT++
1
2
3
4
5
6
7
8
9
10
11
1
2
3
4
5
6
7
8
9
G1
G2
PC15
0.1U_0603_25V7K
BATT++
DC040003600
BATT_TEMP <32>
PQ2
TP0610K-T1-E3_SOT23-3
1
2
2
1
2
PC18
0.22U_1206_25V7K
2
1
PR32
100K_0402_1%
PR33
22K_0402_1%
1
2
VL
+VSBP
1
PC19
0.1U_0603_25V7K
B+
PQ3
SSM3K7002F_SC59-3
2
G
SPOK
PR35
0_0402_5%
2
PC20
0.1U_0402_16V7K
1
<45>
2
PR34
10K_0402_1%
Deciphered Date
2006/10/17
A
Title
BATTERY CONN. / OTP

Size
B
Date:
Document Number
Rev
0.1
ai
2005/10/17
he
x
Issued Date
Compal Secret Data
nf
@
ho
tm
ai
l.c
om
Sheet
43
of
49
65W, Iadapter=0~3.42A, Current sense=0.015ohm, PR45=110K, CP=3.175A

90W, Iadapter=0~4.74A, Current Sense=0.015ohm, PR45=54.9K, CP=4.303A
ACSET
ACSET
23
PGND
22
LEARN
21
OVPSET
3
2
1
PC37
680P_0603_50V7K
OVPSET
AGND
PC39
0.1U_0402_16V7K
1
2
20
PC40
0.1U_0603_25V7K
PC41
@0.1U_0603_25V7K
VDAC
11
0_0402_5%
19
SE_CHG+
18
SE_CHG-
BAT
17
TP
29
SRSET
16
SRP
SRN
VADJ
VADJ
PC44
0.1U_0603_25V7K
12
ACGOOD#
RHU002N06_SOT323-3
ACGOOD
14
BATDRV
ICHG setting
PR53
2
1
49.9K_0402_1%
IREF
<32>
BATDRV#
13
VREF
SI2301BDS-T1-E3_SOT23-3
ACSET
PQ31
RHU002N06_SOT323-3
PQ30
10
1
PC43
0.1U_0603_25V7K
2
G
PQ9
2
1
PR180
340K_0402_1%
PC42
1U_0603_10V6K
2
G
1
0.1U_0402_16V7K
PR51
100K_0402_1%
PR178
200K_0402_1%
PR179
100K_0402_1%
ACOFF
CELLS
1
1
VREF
<32>
PR50
VREF
PC141
1
2
ACOFF
VREF=3.3V
PR49
54.9K_0402_1%
Fsw : 300KHz
Input UVP : 17.26V
Input OVP : 22.3V
Iadapter=(Vacset/Vvdac)*(0.1/PR36)
VREF
<BOM Structure>
3
2
1
LODRV
Icharge=(Vsrset/Vvdac)*(0.1/PR44)
CP setting
PR48
340K_0402_1%
2
7 ACOP
PC38
0.47U_0603_16V7K
BATT+
AO4466_SO8
PC36
1U_0603_10V6K
PR46
4.7_1206_5%
PQ8
PR47
100K_0402_1%
2
1
PC32
RLS4148_LL34-2
0.1U_0603_25V7K
24
1
PR44
PL2
0.02_2512_1%
10UH_SIL1045RA-100PF_4.5A_30%
1
2
1
4
PD7
2
REGN
5
6
7
8
0_0603_5%
25
PH
5
6
7
8
ACDRV
ACDET
4
2
ACN
ACP
4
5
PC34
10U_1206_25V6M
1 PR181
PC24
10U_1206_25V6M
HIDRV
26
PC23
10U_1206_25V6M
27
PQ7
AO4407_SO8
BATDRV#
PQ6
AO4466_SO8
2
3
PR38
100K_0402_1%
PC33
10U_1206_25V6M
<BOM Structure>
PR45
110K_0402_1%
1
2
1
2
BTST
PR40
2.2_0603_5%
1
2
REGN
PC31
1U_0603_25V6K
PC35
@ 0.01U_0402_25V7K
CHG_PVCC
PC21
0.01U_0402_25V7K
1
1
ACDET
VREF
28
PVCC
3
2
1
2
1
ACDRV
PR42
54.9K_0402_1%
CHGEN
PC30
@0.1U_0603_25V7K
ACN
PC28
0.1U_0805_25V7K
1
2
PU5
1
ACP
RLZ24B_LL34
CHG_B+
JUMP_43X118
PC145
2200P_0402_50V7K
PC29
0.1U_0603_25V7K
PC27
0.1U_0402_16V7K
1
2
PR41
340K_0402_1%
PD6
PJ9
2
4
PR39
100K_0402_1%
2
1
1
PR43
3.3_1210_5%
PC26
0.01U_0402_25V7K
2
1
4
2
1
PC22
0.01U_0603_50V7K
CHGEN#
PR37
3.3_1210_5%
PR36
0.015_2512_1%
4
5
6
7
8
8
7
6
5
1
2
3
B+
PQ5
AO4407_SO8
1
2
3
8
7
6
5
AO4407_SO8
PQ4
VIN
PR55
100K_0402_1%
15
PR54
10_0603_5%
PC45
@0.01U_0402_25V7K
PC46
100P_0402_50V8J
<32>
PR56
0_0402_5%
IADAPT
BQ24751ARHDR_QFN28_5X5
REGN
ADP_I
IREF
VREF
PR60
@ 10K_0402_5%
CHGEN#
ACIN
ACGOOD#
<22,32,42>
FSTCHG
D
PQ11
@ SSM3K7002F_SC59-3
2
G
PQ10
RHU002N06_SOT323-3
2
G
LM358ADR_SO8
<BOM Structure>
PR64
105K_0402_1%
PC49
0.01U_0402_25V7K
Issued Date
Compal Secret Data
2006/05/18
Deciphered Date
2007/05/18
A
<32>
4V
0V
PR62
499K_0402_1%
@ 100K_0402_1%
PR52
100K_0402_1%
4.35V
PR58
100K_0402_1%
PR61
RTCVREF
PC140
@1000P_0402_50V7K
3.3V
Per Cell
PU4B
5
CHGVADJ
0
G
PR59
340K_0402_1%
1
2
8
PR63
10K_0402_1%
2
PC48
0.01U_0402_25V7K
BATT_OVP
<32>
PC47
0.01U_0402_25V7K
BATT-OVP=0.111*BATT+
VREF
3A
4.3K_0402_5%
Current
2.968V
<32> CHGVADJ
BATT+
VADJ
VS
LI-3S :13.50V--BATT-OVP=1.5V
PR57
OVP voltage :
Title
CHARGER
Size
Document Number
Rev
1.0
CHARGER
Date:
Sheet
D
44
of
49
ISL6237_B+
ISL6237_B+
B+
PR65
3
2
1
23
PHASE2
PHASE1
LGATE2
LGATE1
PQ15
AO4712_SO8
FB3
30
32
VL
0.1U_0603_25V7K
LX5
18
DL5
PGND
22
OUT1
10
FB1
11
BYP
SKIP
29
1 2
4
PQ14
AO4712_SO8
OUT2
1
+
Rds=18mOHM
REFIN2
2VREF_ISL6237
2
16
PC64
220U_6.3V_M
DL3
1
PC61
25
PR68
@ PR71
61.9K_0402_1%
2
BST5A 2
@ PR69
2.2_1206_5%
DH5
17
Rds=18mOHM
5
6
7
8
4.7U_0805_6.3V6K
PC57
2
1
PC56
1
2
3
VCC
VIN
LDO
15
BOOT1
PR72
0_0402_5%
1
2
BOOT2
19
PC63
680P_0603_50V8J
LX3
PR74
10K_0402_1%
24
PVCC
UGATE1
0_0603_5%
UGATE2
PC60
0.1U_0603_25V7K
PR66
1 BST3A
0_0603_5%
TP
26
PL4
2
1
4.7UH_SIL104R-4R7PF_5.7A_30%
PC58
1U_0603_10V6K
1
2
33
+5VALWP
8
7
6
5
DH3
3
2
1
PU6
1
2
3
PC62
680P_0603_50V8J
2
1
2
1
PR70
0_0402_5%
+3VALWP
@ PR67
2.2_1206_5%
2
1
PL3
1
2
4.7UH_SIL104R-4R7PF_5.7A_30%
1
2
3
1U_0603_10V6K
PC55
0.1U_0603_25V7K
PC53
4.7U_1206_25V6K
2
1
PQ13
AO4466_SO8
VL
PC52
4.7U_1206_25V6K
2
1
5
6
7
8
PQ12
AO4466_SO8
PC54
2200P_0402_50V7K
2
1
2
0_0603_5%
8
7
6
5
PC51
2200P_0402_50V7K
2
1
1
PC50
4.7U_1206_25V6K
2
1
PAD-OPEN 3x3m
2
PC150
2200P_0402_25V7K
PJ10
1
PC59
220U_6.3V_M
FB5
VFB=0.7V
REF
PC65 0.22U_0603_10V7K
LDOREFIN
Rds(on) = 18m ohm(max) ; Rds(on) = 15m ohm(typical)
4
14
EN_LDO
POK1
13
EN1
ILIM1
GND
21
TON
2
1
NC
5
SPOK
<43>
PR79
12
ILM1
31
ILIM2
330K_0402_1%
1
ILIM2
1
330K_0402_1%
ISL6237IRZ-T_QFN32_5X5
Rds(on) = 18m ohm(max) ; Rds(on) = 15m ohm(typical)

PR84
0_0402_5%
5VALWP
Imax=4.9A
Ipeak=7A
Iocp=10.146A
PC139
1U_0603_10V6K
PC68
0.047U_0402_16V7K
2
1
PQ29
TP0610K-T1-E3_SOT23-3
PC67
0.047U_0603_16V7K
@ PR86
47K_0402_1%
EN2
PR85
0_0402_5%
2
1
VL
2VREF_ISL6237
28
2
1
PR81
@ 0_0402_5%
POK2
0_0402_5%
1
0_0402_5%
2
PR80
27
<21,43> MAINPWON
NC
PC66
0.22U_0603_25V7K
2VREF_ISL6237
1
20
PR77
100K_0402_1%
1
2
PR78
200K_0402_5%
1
2
VS
PR82
0_0402_5%
PZD1
RLZ5.1B_LL34
3.3VALWP
Imax=5.59A
Ipeak=7.85A
Iocp=10.133A
@ PR75
2
PR76
1
PD8
2
1SS355TE-17_SOD323-2
4
Deciphered Date
2006/10/17
A
Title
+5VALWP/+3VALWP
Custom
Date:
Rev
0.1
ai
2005/10/17
he
x
Issued Date
Compal Secret Data
nf
@
ho
tm
ai
l.c
om
Sheet
45
of
49
2.2_0603_1%
PR87
+5VALWP
PC70
1U_0402_6.3V6K
PC69
1U_0402_6.3V6K
PR88
1
+5VALWP
2.2_0603_1%
ISL6228_B+
2 PR89
ISL6228_B+
1
JUMP_43X118
1
2
PJ11
2
B+
PC71
0.1U_0603_25V7K
PC72
0.1U_0603_25V7K
2 PR90
10_0603_1%
ISL6228_B+
10_0603_1%
PC147
2200P_0402_25V7K
2
1
1
2
FB1
PGOOD2
28
2
VIN2
3
VCC2
VCC1
29
PR98
1
8.2K_0402_1%
+5VALWP
1
GND_T
FSET2
PR97
VIN1
FB_1.5
34K_0402_1%
PR92
18.2K_0402_1%
@
0_0402_5%
PGOOD1
1 PR94
PR96
FSET1
PC74
1000P_0402_50V7K
PR91
22K_0402_1%
PR95
PC75
2
1
PR93
22K_0402_1%
3.3K_0402_5%
1000P_0402_50V7K
PC73
1000P_0402_50V7K
+5VALWP
0_0402_5%
3.3K_0402_5%
PR99
1000P_0402_50V7K
16.5K_0402_1% PR100
PC76
2
1
1
2
ISL6228_B+
PR101
VO_1.5
VO_1.8
26
VO2
EN2
24
OCSET_1.8
PR105
0_0402_5%
1
2
PC80
ISL6228HRTZ-T_QFN28_4X4
12
PHASE1
0.022U_0402_16V7K
LX_1.8
23
PHASE2
PR108
22
UGATE2
DH_1.8-1
1
2
0_0603_5%
5
6
7
8
21
20
19
18
17
16
15
1.5VP
Imax=2.89A
Ipeak=4.13A
Iocp=8.2A
BST_1.8 1
2
+5VALWP
2.2_0603_5%
PC87
1U_0402_6.3V6K
+1.8VP
1
+
DCR 10 mOHM
PC86
220U_6.3V_M
2
4
0.1U_0402_16V7K
3
2
1
2
PC89
1U_0402_6.3V6K
0_0402_5%
PL6
1.8UH_SIL104R-1R8PF_9.5A_30%
PQ19
AO4712_SO8
PC88
PR109
+5VALWP
PC83
2
PR106
12.1K_0402_1%
BOOT2
PVCC2
LGATE2
BOOT1
PGND2
1BST_1.5 14
PR107
2.2_0603_5%
PGND1
1
2
3
1 2
LGATE1
UGATE1
0.1U_0402_16V7K
DH_1.5-113
PQ17
AO4466_SO8
4
3
2
1
8
7
6
5
@ 0.01U_0402_25V7K
ISL6228_B+
SYSON <31,32,41>
25
PC82
4.7U_1206_25V6K
OCSET2
PU7
EN1
11
PC85
PQ18
AO4712_SO8
PC81
4.7U_1206_25V6K
1.5V_EN
PR104
2
PC146
1000P_0402_50V7K
Rds=18mOHM
12.1K_0402_1%
0_0603_5%
LX_1.5
DCR 10 mOHM
OCSET1
PC84
220U_6.3V_M
10
5
6
7
8
8
7
6
5
OCSET_1.5
PQ16
AO4466_SO8
1.8UH_SIL104R-1R8PF_9.5A_30%
PR102
1
2
3
PL5
1
FB2
34K_0402_1%
DH_1.5-21
+1.5VP
FB_1.8
27
DH_1.8-2
PR103
8.2K_0402_1%
VO1
PVCC1
PC77
0.022U_0402_16V7K
1
2
PC79
4.7U_1206_25V6K
PC78
4.7U_1206_25V6K
2
1
<17,31,32,41,47> SUSP#
Rds=18mOHM
2
DL_1.5
PR177
PR110
0_0402_5%
2
1
1.5V_EN
PC90
0.01U_0402_25V7K
@
<31,32,41> SYSON
DL_1.8
1.8VP
Imax=6.09A
Ipeak=8.7A
Iocp=12.1A
VFB=0.6V
Issued Date
Compal Secret Data
2005/10/17
2006/10/17
Deciphered Date
1.5VP/1.8VP
5
Title

Custom
Date:
Rev
0.1
Sheet
1
46
of
49
PJ12
2
B+
D
6268_B+
For discrete
JUMP_43X118
DH_1.05-1
6268_1.05V
PR112
4.7U_1206_25V6K
0_0603_5%
2
DH_1.05-2
PC93
1 PR113
10K_0402_1%
2.2_0603_5%
+5VS
BOOT_1.05V
PR114
0_0603_5%
PR119=>11.5K
0.1U_0402_16V7K
5
6
7
8
PC92
4.7U_1206_25V6K
1
PC91
2
PR111
PC149
3300P_0402_50V7K
PR115
0_0603_5%
VIN
16
BOOT
UG
15
PC95
6268_1.05V
VCC
2.2U_0603_6.3V6K
LG_1.05V
13
LG
PL7
1.8UH_SIL104R-1R8PF_9.5A_30%
1
2
PGND
12
+1.05VSP
+1.05VSP
ISEN
11
PR117
4.7_1206_5%
5
6
7
8
PC96
2.2U_0603_6.3V6K
PR116
4.7_0603_5%
1
2 6268_1.05V
14
PVCC
0.1U_0603_25V7K
PQ20
AO4466_SO8
1.05VSP
Imax=14.56A
Ipeak=20.4A
Iocp=24.5A
3
2
1
PHASE
GND
PGOOD
1
@
PU500
PC94
PR118
10
FB_1.05V
PC500
0.01U_0402_25V7K
PR122
57.6K_0402_1%
PR120
2.37K_0402_1%
PC98
680P_0603_50V7K
3
2
1
ISL6268CAZ-T_SSOP16
Rds=18mOHM
PR123
3K_0402_1%
2
PC100
22P_0402_50V8J
PR121
49.9K_0402_1%
PC97
330U_D2_2.5VY_R15M
2
1
PR119
19.1K_0402_1%
PQ21
AO4712_SO8
ISEN_1.05V
1
VO
FB
PC99
0.1U_0402_16V7K
@
FSET
EN
0_0402_5%
COMP
<17,31,32,41,46> SUSP#
PC97=>220UF/15m,
PHASE_1.05V
PC102
6800P_0402_25V7K
VFB=0.6V
B
PJ13
JUMP_43X118
+1.8V
NC
VREF
NC
VOUT
NC
TP
PR124
1K_0402_1%
PR125
1
S
+0.9VSP
1
3
1
2
PC106
10U_0805_10V4Z
A
om
l.c
ai
PC105
0.1U_0402_16V7K
Issued Date
Compal Secret Data
2005/10/17
2006/10/17
Deciphered Date
Title
1.05VSP/0.9VSP
5
nf
@
ho
tm
PR126
1K_0402_1%

Custom
Date:
Rev
ai
PQ22
SSM3K7002F_SC59-3
he
x
PC107
0.1U_0402_16V7K
1
@
2
G
PC104
1U_0603_6.3V6M
APL5331KAC-TRL_SO8
0_0402_5%
1
2
<26,41> SUSP
+3VALWP
1
VCNTL
GND
PC103
10U_0805_10V4Z
VIN
2
1
PU9
1
Sheet
0.1
47
of
49
12
FB2
NC
25
220P_0402_50V7K
20_0402_5%
2
PR175 1K_0402_1%
VCC_PRM
PC137
0.22U_0603_10V7K
1
2
PC113
220U_25V_M
PC112
10U_1206_25V6M
2
1
PC111
10U_1206_25V6M
2
1
PR146
10K_0402_1%
2
1
3.65K_0805_1%
1 2
PR144
PC116
PC144
1000P_0402_50V7K
4.7_1206_5%
680P_0603_50V8J
PR145
2
1
3
2
1
D
D
D
D
5
6
7
8
3
2
1
5
6
7
8
PR158
1 2
D
D
D
D
G
S
S
S
4
3
2
1
4
3
2
1
D
D
D
D
5
6
7
8
PC128
1
2
0.22U_0603_10V7K
VCC_PRM
ISEN2
+CPU_B+
2.61K_0402_1%
1
2
PR171
PR176 4.02K_0402_1%
PC136 0.1U_0402_16V7K
1
2
1_0402_5%
PR164 @ 0_0603_5%
1
2
1
2
PR172 0_0402_5%
PC135 180P_0402_50V8J
1
2
PR173
VSSSENSE
PR174
<5>
11K_0402_1%
20_0402_5%
<BOM Structure>PR160
VSUM
PC133
0.018U_0603_50V7J
PC134
0.018U_0603_50V7J
PR170
0_0402_5%
PR169
+CPU_CORE
PC132 0.018U_0603_50V7J
1
2
VSUM
PQ28
SI4856DY-T1-E3_SO8
+5VS
PC131
0.1U_0603_25V7K
PR168 1K_0402_1%
PC125
680P_0603_50V8J
PL10
10KB_0603_5%_ERTJ1VR103J
PH3
PR166 1
PR157
4.7_1206_5%
PR163 1_0603_5%
PC127
1U_0402_6.3V6K
PR167
10_0603_5%
1
2
1
1K_0402_1%
PC130 1000P_0402_50V7K
1
2
G
S
S
S
ISEN1
24
ISEN2
23
22
VDD
GND
21
VSUM
VIN
20
19
DFB
VO
18
17
DROOP
1
2
0.36UH_MPC1040LR36_24A_20%
2
PQ27
SI4856DY-T1-E3_SO8
PU10
<BOM Structure>
ISEN1
ISEN2
2
UGATE_CPU2-2
26
+CPU_B+
27
BOOT2
UGATE2
FB
COMP
11
PHASE_CPU2
PR154
UGATE_CPU2-1 1
2
0_0603_5%
BOOT_CPU2
1
2
1
2
PR155
PC123
2.2_0603_5%
0.22U_0603_10V7K
PC120
10U_1206_25V6M
10
PQ26
SI7686DP-T1-E3_SO8
LGATE_CPU2
+CPU_CORE
PR147
1_0402_5%
<BOM Structure>
PR159
10K_0402_1%
2
1
28
PR162
@ 0_0402_5%
PR165
PC143
2200P_0402_50V7K
PL9
LGATE_CPU1
3.65K_0805_1%
29
PHASE2
PQ24
SI4856DY-T1-E3_SO8
PGND2
VW
PR161 97.6K_0402_1% PC126 470P_0402_50V7K

1
2
2
1
+
2
PR148 @ 0_0603_5%
1
2
PC117
1
2
VCC_PRM
ISEN1
0.22U_0603_10V7K
VSUM
OCSET
5
6
7
8
ISL6262ACRZ-T_QFN48_7X7
B+
0.36UH_MPC1040LR36_24A_20%
2
1
PC119
10U_1206_25V6M
2
1
SOFT
G
S
S
S
30
PHASE_CPU1
4
3
2
1
31
NTC
D
D
D
D
PVCC
LGATE2
VR_TT#
G
S
S
S
LGATE1
32
UGATE_CPU1-1
4
3
2
1
33
PC124 1000P_0402_50V7K
<5> VCCSENSE
PC110
10U_1206_25V6M
2
1
1
34
PGND1
255_0402_1%
1
PC109
2.2U_0603_6.3V6K
2
1
PC108
0.022U_0402_16V7K
2
1
PHASE1
RBIAS
13
<5>
37
VID0
38
VID1
PMON
RTN
13K_0402_1%
1
2
1
2
1000P_0402_50V7K PC122
PR156 6.81K_0402_1%
1
2
PC129
<5>
PR139
PR138
PR137
39
VID2
40
VID3
42
41
VID4
VID5
44
46
43
VID6
45
48
47
3V3
36
35
16
PC118
0.015U_0402_16V7K 0.022U_0603_50V7K PC121
1
2
<5>
<5>
<5>
CPU_VID0
<5>
CPU_VID1
<5>
CPU_VID2
<32>
CPU_VID3
CPU_VID4
PR136
PR135
PR134
PR132
1
2
BOOT1
15
@ 100K_0603_1%_TH11-4H104FT
1
2
PR153
1
2
0_0603_5%
PR143
UGATE1
VSEN
PSI#
VDIFF
<4> H_PROCHOT#
PR151 0_0402_5%
1
2
PR152 @ 4.22K_0402_1% PH2
1
2 1
2.2_0603_5%
0.22U_0603_10V7K
UGATE_CPU1-2
PR141
PC115
BOOT_CPU1 1
2
1
2
PGOOD
PL8
HCB4532KF-800T90_1812
1
2
PQ23
SI7686DP-T1-E3_SO8
PQ25
SI4856DY-T1-E3_SO8
1
2
PR149
@ 0_0402_5%
1
2
PR150
147K_0402_1%
VR_TT#
PMON
C
DPRSTP#
H_PSI#
14
<5>
DPRSLPVR
<8,16,22> VGATE
+CPU_B+
PC114
1U_0603_6.3V6M
1
PR140
499_0402_1%
1.91K_0402_1%
PR142
49
+3VS
+3VS
0_0402_5%
2
CLK_EN#
PR131
1
1
0_0402_5%
2
1
0_0402_5%
2
1
0_0402_5%
2
1
0_0402_5%
2
1
0_0402_5%
2
1
0_0402_5%
2
1
0_0402_5%
2
1
0_0402_5%
PR130 @ 0_0402_5%
1
2
CLK_EN#
GND
<16>
0_0402_5%
2
VR_ON
<5,8,21> H_DPRSTP#
PR127
1_0603_5%
0_0402_5%
2
1
PR129
1
PR133
PR128
<8,22> PM_DPRSLPVR_D
CPU_VID5
VR_ON
CPU_VID6
+5VS
PC138 0.22U_0402_6.3V6K
2
1
2005/10/17
Issued Date
Compal Secret Data
Deciphered Date
2006/10/17
5
Title
+CPU_CORE
Custom
Date:
Rev
0.1
Sheet
1
48
of
49
page
Reason for change
Modify list
Add original ACIN detector fun,and del TI fun.
ADD PR6, Del PQ11, PR61
Change PC28 to 0.1U for common design
PC28
Change PR16,PR32 & PR77 to 1% for common part
PR16 & PR32 & PR77
Change PC55 to 0.1U_0603 for common design
PC55
Add PC139 for 3/5V 2nd source
PC139
Change PQ21 to AO4712 and PL7 to 1.8UH for cost
PQ21 & PL7
Change PC12 and PC13 to 0402 for source suggest
PC12 & PC13
Change PR176 to 4.02K for load line
PR176
Change 1.05V VIN from 5valwp to 5VS. reduse S3 power loss

Del PR83 for extra pull-high R
Add cpu_core boost and sunnber for EMI request
Add PR141,PR144,PC116,PR155,PR157 &PC125
Add 1.05VSP boost and sunnber for EMI request
Add PR113,PR117 &PC98
Fixed CV mode
Add PR56,Del PR57&PR60
Adjust 1.05V to 1.074 for HW request
Modify PR120 to 2.37K
Adjust 1.5V to 1.527 for HW request
Modify PR93
DVT
to 22K
Del PR73 for fix 3V in 2nd source

Add PQ30,PQ31, PR178,PR179,PR180,PC141
Prevent ACOP protection by charger
Modify PQ10 to SOT322
Layout limit
Modify 1.5V to susp#
Add PR177, Del PR170
Modify PR36 to 0.015 for rating & change PR45 to 100K

Modify PL9 & PL10 form NEC to TOKO
Modify PR108 to 2.2 for EMI request
B
PVT
Fix 5valwp, so del PR71, change PR72 to 0
Change PC103 & PC106 to Y5 type for costdown

Change PC8
to Y5V type for costdown
nf
@
ho
tm
ai
l.c
om
Title
he
x
Date:
5
ai
<Title>
Size
Document Number
Custom<Doc>
Sheet
Rev
<RevCode>
49
of
49

JHXXX M/B LA-4241P Schematic Block Diagrams and Notes

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JHXXX M/B LA-4241P Schematic Block Diagrams and Notes

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12/21 Add PJP1 for DCIN Cable on 45 Level

Intel Penryn Processor with Cantiga + DDRII + ICH9M

JHXXX M/B LA-4241P Schematic

Compal Electronics, Inc.

Compal Secret Data

Thursday, April 24, 2008

Intel Penryn Processor

1.8V DDRII 533/667

New Card MINI Card x3

Power On/Off CKT.

DC/DC Interface CKT.

Power Circuit DC/DC

USB I/O Conn.

Compal Electronics, Inc.

Compal Secret Data

JHXXX M/B LA-4241P Schematic

Friday, April 11, 2008

Adapter power supply (19V)

AC or battery power rail for power circuit.

Core voltage for CPU

+0.9VS ( Actual +0.9V )

0.9V switched power rail for DDR terminator

1.05V switched power rail

1.5V switched power rail

1.8V power rail for DDR

1.8V switched power rail

3.3V always on power rail

3.3V switched power rail

5V always on power rail

5V switched power rail

VSB always on power rail

ICH9M SM Bus address

SLP_S1# SLP_S3# SLP_S4# SLP_S5#

JHXXX M/B LA-4241P Schematic

Compal Electronics, Inc.

Compal Secret Data

Thursday, April 24, 2008

Place close to CPU with stub length <200 mils

LM95245CIMMX NOPB MSOP 8P

1/29 change to EMC1402 pn

Merom Ball-out Rev 1a

Compal Electronics, Inc.

Compal Secret Data

JHXXX M/B LA-4241P Schematic

Trace Close CPU < 0.5'

Merom Ball-out Rev 1a

TRACE CLOSELY CPU < 0.5'

Merom Ball-out Rev 1a

Place PU and PD within 1 inch of CPU (CRB recommend)

Place these 2 resisters closk to CPU pins within 500 mils

Compal Electronics, Inc.

Compal Secret Data

Length matching within 25 mils (Compal Common Design)

JHXXX M/B LA-4241P Schematic

Merom Ball-out Rev 1a

South Side Secondary

North Side Secondary

(Place these capacitors on South side,Secondary Layer)

(Place these capacitors on North side,Secondary Layer)

(Place these capacitors on South side,Primary Layer)

(Place these capacitors on North side,Primary Layer)

VCCA_CRT_DAC: 73mA (0.1UF1, 0.01UF1)