Circuite log

&LUFXLWHOH ORJLFH FRPELQD LRQDOH ILJ  VXQW FRQVLGHUDWH

ordin zero circXLWH I U

FRPELQD LL ORJLFH DOH VHPQDOHORU GH LQWUDUH UHOD LD  H[LVWkQG QXPDL DWkWD WLPS FkW VHPQDOHOH GH LQWUDUH H[LVW  /D FLUFXLWHOH ORJLFH VHFYHQ LDOH FOV FRQVLGHUDWH LHLULORU GHSLQGH QX QXPDL GH VWDUHD DFWXDO DOH FLUFXLWXOXL 'LQ DFHVW PRWLY VH VSXQH F

circuite cu memorie.
6FKHPD EORF D XQXL FLUFXLW ORJLF VHFYHQ LDO HVWH SUH]HQWDW vQ ILJ  vQ FDUH

am notat cu x1, x2, , xn LQWU ULOH SULQFLSDOH FX \1, y2, , ym LHLULOH SULQFLSDOH FX q1, q2, ,ql VW ULOH LQWHUQH SUH]HQWH DOH FLUFXLWXOXL L FX T1, q2, ,ql - VW ULOH
LQWHUQH XUP WRDUH DOH DFHVWXLD

,QWU UL

principale

([SUHVLLOH LHLULORU L VW ULORU XUP WRDUH DOH XQXL FLUFXLW ORJLF VHFYHQ LDO vQ IXQF LH GH LQWU UL L VW ULOH SUH]HQWH SRW IL VFULVH DVWIHO

  

137

CAPITOLUL 5

&LUFXLWH

ORJLFH VHFYHQ LDOH

sisteme digitale de
(OH VXQW

DYkQG

FD

HOHPHQW

UHSUH]HQWDWLY

SRDUWD

ORJLF

HOHPHQWDU 

PHPRULH L VH FDUDFWHUL]HD]

SULQ IDSWXO F

VHPQDOHOH GH LHLUH VXQW

sisteme de ordin , starea

ORJLFH VHFYHQ LDOH VXQW

D LQWU ULORU GDU L GH VW ULOH DQWHULRDUH FLUFXLWHOH

x1 2 x n

y1 y2 ym q1 q2
W

,HLUL

principale

q1 q2 2 ql C.L.C

q1 q2

ql

ql

C.L.S.

)LJ  6FKHPD EORF D XQXL FLUFXLW ORJLF VHFYHQ LDO

138

Capitolul 5

(5.1) automat Mealy. n cazul n care yk QX GHSLQGH GHFkW GH LQWU ULOH [1, x2, , xn VSXQHP F UHOD LLOH  DVWIHO PRGLILFDWH GHILQHVF XQ automat de tip Moore. 6W ULOH XUP Woare qi GHYLQ SUH]HQWH GXS XQ LQWHUYDO GH WLPS GHWHUPLQDW GH ntrzierile W1 W2  Wl, special introduse n circuit. 'DF W1 W2 Wl VSXQHP F c.l.s. este de tip asincron LDU GDF
Q DFHDVW IRUP  UHOD LLOH  GHILQHVF XQ WLPS W1 W2 W OD FRPDQGD XQXL LPSXOV GH WDFW VSXQHP F F Wl W GHFL PRGLILFDUHD VW ULORU DUH ORF GXS XQ DFHODL LQWHUYDO GH

yk=yk(x1, x2, , xn, q1, q2, , ql); qi= qi(x1, x2, , xn, q1, q2, , ql).

c.l.s. este de tip sincron.

LHLU

6H REVHUY

WUHFHUHD GH OD VLVWHPH GH RUGLQXO ]HUR FOF OD FHOH GH RUGLQ

VXSHULRU FOV VH IDFH SULQ LQWURGXFHUHD XQRU UHDF LL FDUH FRQIHU R DXWRQRPLH SDU LDO  OD OLPLW

WRWDO

 ID

GH LQWU UL GHFL FDOLWDWHD GH

ilor circuitului memorie.

5.1. Circuite basculante bistabile SR

UHDF LL vQWU VW

Circuitele basculante bistabile SR (CBB-65 VH RE LQ SULQ LQWURGXFHUHD XQHL -un sistem elementar de RUGLQ ]HUR 6LVWHPXO DVWIHO RE LQXW HVWH GH RUGLQ  CBB-65 SRW IL UHDOL]DWH vQ YDULDQWD DVLQFURQ  VLQFURQ VDX 0DVWHU-Slave" SkQ-sclav).

5.1.1. Circuitul basculant bistabil SR asincron

Circuitul basculant bistabil SR asincron, cunoscut - datorit SURSULHW LORU VDOH de a memora - L VXE GHQXPLUHD GH latch ] YRU SRDWH IL UHDOL]DW FX 125-uri sau cu NAND-uri.

5.1.1.1. Circuitul basculant bistabil SR asincron realizat cu NOR-uri

GLQ ILJ  L WDEHOXO GH WUDQ]L LH ORJLF

Circuitul basculant bistabil SR asincron realizat cu NOR-uri prezLQW VFKHPD tab. 5.1, n care s-a notat cu indice n - valoarea SUH]HQW L FX n+1 - YDORDUHD ORJLF YLLWRDUH
([SUHVLD LHLULL 4 D FLUFXLWXOXL SRDWH IL RE LQXW GLQ VFKHPD GLQ ILJ 

astfel:
Q n +1 = Sn + R n + Q n = Sn + R n Q n .
(OLPLQkQG QHJD LD vQ DPELL PHPEUL DL UHOD LHL  RE LQHP

(5.2) (5.3)
XWLOL]DUHD GLDJUDPHL 9. GLQ

Q n +1 = S n + R n Q n .
8Q DOW PRG GH D RE LQH H[SUHVLD  vO UHSUH]LQW ILJ  vQ ORFD LLOH F UHLD DX IRVW WUHFXWH YDORULOH ORJ

ice ale lui Qn+1.

Circuite log

&RPSOHWDUHD

WUDQ]L LH WDE  DVWIHO

- pentru SnRn = 00, Qn+1=Qn SULPD OLQLH D WDEHOXOXL GH WUDQ]L LH GHFL YDORULOH logice ale lui Qn se trec n coloana SnRn = 00 a diagramei VK; - pentru SnRn=01(10), Qn+1=0(1) indiferent de valorile lui Qn L ORFD LLOH GLQ
FRORDQD D GRXD D SDWUD D GLDJUDPHL 9. VH FRPSOHWHD] FX 

deci s-DU DMXQJH OD VLWXD LD LQDGPLVLELO

Q n +1 = Q n +1 = 0 .

- pentru SnRn

  
ORFD LLORU GLDJUDPHL V D

139

I FXW

LQkQG

VHDPD

GH

WDEHOXO

GH

R S P1 P2 Q R Q

Q
D 6FKHPD ORJLF

Q b) Schema bloc

Fig. 5.2. CBB-SR asincron, varianta NOR

7DE 7DEHO GH WUDQ]L LH DO

CBB-SR asincron, varianta NOR

Sn 0 0 1 1
SnRn 00 Qn 0 1 0 1

Rn 0 1 0 1

Qn+1 Qn 0 1 x

01 0 0
R n Qn

11 x x

10 1 1 Sn

Fig. 5.3. Diagrama VK pentru CBB-SR asincron - varianta NOR

 LHLULOH FHORU GRX

SRU L VXQW IRU DWH VLPXOWDQ vQ  ORJLF

vQ FDUH

(5.4)

140
'LQ DFHVW PRWLY FRPELQD LD GH LQWUDUH 6n

Capitolul 5

ORJLF

VXSOLPHQWDU  LDU vQ ORFD LLOH FRUHVSXQ] WRDUH DOH WDE  L GLDJUD Q XUPD PLQLPL] ULL VH RE LQH UHOD LD  'HQXPLULOH 6 6(7 L 5 5(6(7 DOH LQWU ULORU ODWFK

Rn

 HVWH LQWHU]LV

GH RELFHL SULQ

mei VK din

ILJ  VH SXQH VHPQXO

[  VSHFLILF ORFD LLORU vQ FDUH IXQF LD HVWH QHGHILQLW 

GLQ OLPED HQJOH]

L DX VHPQLILFD LLOH U REVHUY P F

ntr-DGHY
DFWLYDW WHDUV

L vQ PHPRULD HOHPHQWDU

Similar, pentru SnRn : Qn+1=0.

 LQWUDUHD GH WHUJHUH 5n HVWH DFWLYDW FX XXULQ

-ului SR asincron provin nscriere, respectiv WHUJHUH. SHQWUX 6nRn=10, intrarea de nscriere Sn este VH vQVFULH  ORJLF GHFL 4n+1=1.
L PHPRULD HVWH SHQWUX SULPHOH  OLQLL DOH WDE 

5HOD LD  VH YHULILF

5.1.1.2. Circuitul basculant bistabil SR asincron realizat cu NAND-uri Schema circuitului basculant bistabil SR asincron realizat cu NAND-uri este
SUH]HQWDW vQ ILJ  LDU WDEHOXO GH WUDQ]L LH HVWH WDE 

P1

P2

S
Q

Q
D VFKHPD ORJLF

Q
b) schema bloc

Fig.5.4. CBB-SR asincron, varianta NAND

7DE 7DEHO GH WUDQ]L LH DO &%%

-SR asincron, varianta NAND

1 1 0 0

1 0 1 0

Pe schema din fig. 5.4 putem scrie:

Q n +1 = Sn R n Q n = Sn + R n Q n ,

Qn+1 Qn 0 1 x

Circuite log

UHOD LH LGHQWLF

cu NOR-uri.
$FHHDL UHOD LH VH RE LQH L vQ XUPD PLQLPL] ULL IXQF LHL ORJLFH 4n+1

ajutorul diagramei VK din fig. 5.5.

Sn R n 00 Qn

,QGLIHUHQW GH YDULDQWD GH LPSOHPHQWDUH DGRSWDW  &%% 65 DVLQFURQ SUH]LQW

XUP WRDUHOH

DFHOHDL SHQWUX

vQVFULHUHD GLFWHD] LPSUHYL]LELO 

Exemplu: Tranzi LD
SRU LOH 31

ILJ  vQ RULFDUH GLQ FHOH GRX LHLUL YRU IL IRU DWH vQ  4

YD RE LQH XQ  ORJLF OD LHLUHD LHLUHD 4 (YLGHQW GDF DOH LHLULORU VH LQYHUVHD] 

5.1.2. Circuitul basculant bistabil SR sincron

&LUFXLWXO DG XJDUHD D GRX EDVFXODQW ELVWDELO 65 VLQFURQ VH RE LQH GLQ FHO DVLQFURQ SULQ SRU L  L  YDOLGDELOH GH XQ LPSXOV GH WDFW ILJ  L  &%%

)XQF LRQDUHD FHORU GRX

H[SOLFDUHD IXQF LRQ ULL FLUFXLWXOXL GLQ ILJ  D 2EVHUY P F SHQWUX

a lui S

pentru CLK = 1  LQWU ULOH DFHVWXLD YRU IL 6nRn  5.1, Qn+1=Qn L LHLULOH YRU U PkQH QHVFKLPEDWH

65 YRU DYHD DFFHV OD LQWU ULOH &%% 65 DVLQFURQ DF LRQkQG FRQIRUP WDE 

Cnd CLK = 0  SRU LOH  L  YRU IL YDOLGDWH L LQWU -

  
FX UHO  RE LQXW

141
vQ FD]XO FLUFXLWXOXL EDVFXODQW ELVWDELO 65 UHDOL]DW

cu

01 1 1

11 0 1

10 0 0
R nQn

0 1

x x

Sn

Fig. 5.5. Diagrama VK pentru CBB-SR asincron, varianta NAND

deficiHQ H:
VHPQDOH DQXPLWH FDUH LQGLF DOH PRGXO

cum
DLE

vQ

FDUH

WUHEXLH VWDUHD

VH

IDF HVWH

L PRPHQWXO

cnd WUHEXLH V

ORF DFHDVWD FLUFXLWXOXL LHLULORU

WUDQ]L LL

LQWU ULORU





D LQWU ULORU SRDWH DGXFH LHLULOH 4

 YDOLGkQG SULQ LQWHUPHGLXO OHJ WXULORU GH UHDF LH  L DGPL kQG F FHHD FH GHWHUPLQ

VW UL SRVLELOH $VWIHO SHQWUX 6n

DOH &%% GLQ

Rn=11, ambele

, P2. Aplicnd acum SnRn

DSOLF P DFHHDL VXSR]L LH SHQWUX SRDUWD 32

Q

SRDUWD 31 HVWH PDL UDSLG  VH

SULQ UHDF LH

- un 0 logic la , valorile logice

-SR sincrone fiind siPLODU

 QH YRP OLPLWD OD

CLK = 1  SRU LOH  L 

VXQW LQKLEDWH L RULFH PRGLILFDUH U

R nu va afecta CBB-ul SR asincrRQ IRUPDW GLQ SRU LOH  L  QWU-DGHY

L FRQIRUP SULPHL OLQLL GLQ WDE

ULOH

S R , transformate n

142
3HQWUX R IXQF LRQDUH VLQFURQ GLFWHD] D FLUFXLWXOXL HVWH QHFHVDU FD

Capitolul 5

CLK = 0 , care
QXPDL GXS FH

cnd V

VH H[HFXWH FRPHQ]LOH GDWH GH LQWU ULOH

S RV

DSDU

acestea s-au stabilizat. Modificarea lui S R

vQ LQWHUYDOXO GH WLPS vQ FDUH SRU LOH GH D FLUFXLWXOXL 'LQ

LQWUDUH  L  VXQW GHVFKLVH FRQGXFH OD R IXQF LRQDUH DVLQFURQ

DFHVW PRWLY VXQW QHFHVDUH FRQGL LL UHVWULFWLYH SHQWUX UHOD LD GH WLPS GLQWUH

CLK

S R. S CLK
R

3 S 1 2

4 R S CLK R Q

Q
b) schema bloc

a) schema ORJLF

Fig. 5.6. CBB-SR sincron, varianta NOR

CLK

4 S CLK R

S
1 2

R
Q

Q
b) schema bloc

D VFKHPD ORJLF

Fig. 5.7. CBB-SR sincron, varianta NAND

&LUFXLWXO GLQ ILJ  IXQF LRQHD] GDW

DFWLY SH SDOLHUXO VXSHULRU  ORJLF DO LPSXOVXOXL GH WDFW

5.1.3. Circuitul basculant bistabil SR Master-Slave

'XS UHSUH]LQW FXP UHLHVH GLQ ILJ  FLUFXLWXO EDVFXODQW ELVWDELO 65 0DVWHU HVWH SUH]HQWDW R H[WHQVLH VHULH D ELVWDELOXOXL 65 VLQFUR

ILJ  6FKHPD ORJLF &/. L

CLK - vQ ILJ  E L F

S CLK R

)XQF LRQDUH

n intervalul (1)-
L GH 6/$9(

0 L GH WUDQVIHU 6 6 VXQW EORFDWH LDU 0$67(5 XO HVWH L]RODW DWkW GH LQWU UL FkW

n intervalul (2)- &/.

vQ FRQWLQXDUH L]RODW ID

QVFULH vQ 0$67(5 SRU LOH 6 6 ILLQG EORFDWH  CLK = 0 ), bistabilul SLAVE este
GH 0$67(5 VLWXD LD GLQ LQWHUYDOXO 

n intervalul (3)- VH UHSHW

Q VIkULW GXS L]RODW ID WUDQVIHU vQ 6/$9( vQVFULHUHD

HUD L]RODW DWkW GH LQWU UL FkW L GH 6/$9( PRPHQWXO  SRU LOH 0 0 VXQW EORFDWH 0$67(5

&RQFOX]LRQkQG

momentul (3 SRVLELO FKLDU SH IURQWXO GHVFUHVF

 "  !  #    

Circuite log

143
VLPLODU LPSXOVXO GH WDFW ILLQG GH DFHDVW

-Slave n implementat cu NAND-uri (v.

vQ ILJ  D LDU GLDJUDPHOH LPSXOVXULORU

SM M QM

RM
QM

SS CLK RS S QS QS

Fig. 5.8. CBB-SR-MS - Schema bloc

Y GLDJUDPHOH E L F GLQ ILJ  SRU LOH GH LQWUDUH 0

 L SRU LOH 0 0 VXQW YDOLGDWH LDU LQIRUPD LD VH

-(2) cnd MASTER-ul -ul

GH

GH LQWU UL LDU SRU LOH 6 6 VXQW YDOLGDWH L LQIRUPD LD GLQ 0$67(5 VH LQIRUPD LHL vQ 0$67(5 DUH ORF vQDLQWH

WRU DO &/. LDU WUDQVIHUXO HL vQ

144
6/$9( L GHFL OD LHLUH DUH ORF GXS PRPHQWXO  GHFL SH

Capitolul 5
DFHODL IURQW

GHVFUHVF WRU DO &/.

CLK

R
3RU L

3M

4M

intrare CBB-SR MASTER sincron

1M

2M

CBB-SR MASTER asincron

CLK

3RU L

transfer 3S 4S CBB-SR SLAVE asincron CBB-SR SLAVE sincron

a)

1S

2S

Q CLK "1" b) "0"

(2) (3) (1) (4)

CLK "1" c) "0" (2) (3) t

 E F GLDJUDPH

(1)

(4)

Fig. 5.9. CBB-SR-MS: a) scKHP

3ULQ XUPDUH SHQWUX vQVFULHUHD I U QHFHVDU FD DFHDVWD V U PkQ VWDELO

intervalului (3)-(4).
'HL UHDOL]HD] R PXOW PDL EXQ VHSDUD LH vQWUH QX HOLPLQ FDUH V

PRGLILFH LQIRUPD LD PHPRUDW  &%%

SRVLELOLWDWHD DSDUL LHL WUDQ]L LLORU QHGHWHUPLQDWH Y WDE  L 

Evident, se pot construi CBB-SR-06 impulsului de tact.

5.2. Circuite basculante bistabile de tip D

&LUFXLWHOH EDVFXODQWH ELVWDELOH GH WLS ' SRW IL UHDOL]DWH vQ YDULDQWD DVLQFURQ  VLQFURQ L 0DVWHU

5.2.1. Circuitul basculant bistabil de tip D asincron

Circuitul basculant bistabil de tip D DVLQFURQ ILJ  VH RE LQH GLQWU-un CBB-65 DVLQFURQ ILJ  WDE  VDX ILJ  WDE  SULQ DWDDUHD XQXL LQYHUVRU
vQ VFRSXO HOLPLQ ULL VW ULORU QHGHWHUPLQDWH

'DWRULW

D n = S n = R n  RE LQkQGX-se tabelul 5.3.

7DE  7DEHOXO GH WUDQ]L LH DO &%% GH WLS '

 "  !  #    
HURUL D LQIRUPD LHL vQ &%% OD LQWUDUH XQ LQWHUYDO L GH WLPS vQ

Circuite log

145

-SR-MS, este
MXUXO VH WUHEXLH V

cnd

cum

-SR-06

GH]DYDQWDMXO UHSUH]HQWDW GH D

FRPXWH SH WUDQ]L LD SR]LWLY

-Slave.

S Q

Fig. 5.10. Circuitul basculant bistabil de tip D asincron

LQYHUVRUXOXL GLQ WDEHOXO  U PkQ QXPDL OLQLLOH  L  SHQWUX FDUH

Dn

Sn
1 0

Rn

Qn x x

Qn+1 1 0

146
'HRDUHFH UHSHW SUDFWLF LQVWDQWDQHX OD LHLUH FHHD FH L VH DSOLF LQWHUHV SUDFWLF

Capitolul 5
OD LQWUDUH Y

WDE  FLUFXLWXO QX SUH]LQW

5.2.2. Circuitul basculant bistabil de tip D sincron

9DULDQWHOH GH &%% WLS ' VLQFURQ SHUH]HQWDWH vQ ILJ  L  DX IRVW RE LQXWH SULQ DWDDUHD FkWH GLQ ILJ  L 

unui inversor circuitelor basculante bistabile SR sincrone

D

CLK S
Q

D
Q

CLK
Q

D PRGXO GH RE LQHUH

E VFKHPD EORF

Fig. 5.11. CBB-D sincron comandat de palierul inferior al CLK D CLK S Q R D Q CLK

D PRGXO GH RE LQHUH

E VFKHPD EORF

Fig. 5.12. CBB-D sincron comandat de palierul superior al CLK

&D L vQ FD]XO &%% 65 VLQFURQ SHQWUX D UHDOL]D R FRPXWDUH VLQFURQL]DW

GH

&/. HVWH QHFHVDU FD LQIRUPD LD GH OD LQWUDUHD ' V

VH PRGLILFH vQ DIDUD SDOLHUXOXL  SHQWUX ILJ  vQ

activ al impulsului de tact ( CLK = 0

SHQWUX ILJ  L &/. U PkQ

WLPSXO SDOLHUXOXL UHVSHFWLY DFHDVWD WUHEXLQG V DFWLY DO LPSXOVXOXL GH &/. GHFODQD] ELVWDELO L SHUPLWH FLWLUHD DFHVWHLD OD LHLUH

VWDELO  $SDUL LD SDOLHUXOXL

RSHUD LXQHD GH vQVFULHUH D LQIRUPD LHL vQ

,QWHUYDOXO ELVWDELOXOXL L

. De fapt, denumirea de bistabil de tip D, provine din englezescul DELAY=ntrziere. D XQXLD GLQ FHOH GRX ODWFK-uri de Q ILJ  DP UHSUH]HQWDW VFKHPD ORJLF WLS ' D FkWH  EL L ILHFDUH GLQ VWUXFWXUD FLUFXLWXOXL LQWHJUDW &'%  LDU vQ WDE  IXQF LRQDUHD ODWFK-ului respectiv.
D E (CLK)

WHPSRUL]DUH FRPDQGDW

)LJ 

Autorizare date Blocare date

%LVWDELOXO GH WLS ' VLQFURQ

1 1 0
DUH

0 1 x
QXPHURDVH

0 1 Qn
DSOLFD LL

1 0 Qn
SUDFWLFH GLQWUH FDUH

amintim: latch-ul adresabil, memoria RAM, etc.

5.2.2.1. Latch-ul adresabil Latch-XO DGUHVDELO ILJ  UHSUH]LQW basculant bistabil (latch-XOXL GH WLS ' VLQFURQ
R H[WHQVLH

paralel a circuitului

GLQ ILJ  L VH FRPSXQH GLQ 

DVWIHO GH FLUFXLWH ELVWDELOH L XQ GHFRGLILFDWRU GH DGUHV 

 "  !  #    
GH WLPS VFXUV vQ vQWUH PRPHQWXO SRDWH DSDUL LHL IL FLWLW LQIRUPD LHL OD LHLUH OD PRPHQWXO FDUH DFHDVWD UHSUH]LQW SULQ &/.

Circuite log

147
LQWUDUHD R

Q0
6FKHPD ORJLF D ODWFK

Q0 -ului de tip D din structura CI - CDB 475

7DE 

([SOLFDWLY SHQWUX IXQF LRQDUHD ODWFK

-ului de tip D din fig. 5.13

,HLUL

Mod operare

,QWU

UL

En

Dn

Qn+1

Qn

148

Capitolul 5

A B C

DCD 7 ...

_ E

CLK

DIN

CLK
Q

CLK
Q

CLK
Q

Q7

Q1

Q0

Fig. 5.14. Latch-ul adresabil

OD LQWU ULOH

Datele de intrare DIN sosesc ntr-R PDQLHU VHULDO  ILHFDUH ELW ILLQG GLVWULEXLW D ale celor 8 latch-XUL VLQFURQH &RPELQD LD ORJLF D OLQLLORU GH DGUHV $ % & DFWLYHD] XQD GLQ OLQLLOH GH LHLUH DOH GHFRGLILFDWRUXOXL VHOHFWkQG DVWIHO ODWFK-ul
D IL vQVFULV LQIRUPD LD vQ WLPSXO SDOLHUXOXL DFWLY DO LPSXOVXOXL GH D F WUH XQ DOW ELVWDELO DPG ODWFK

vQ FDUH XUPHD] OLQLLORU GH DGUHV vQVFULV

&/. (YLGHQW XUP WRUXO ELW GH LQIRUPD LH YD IL GLULMDW GH F WUH FRPELQD LD ORJLF 2EVHUY P F

-ul adresabil este de fapt o memorLH vQ FDUH LQIRUPD LD HVWH

IL FLWLW LQWHJUDO OD LHLULOH FHORU  ELVWDELOH 3ULQ

ELW FX ELW SXWkQG vQV

urmare, latch-XO DGUHVDELO SRDWH IL SULYLW L FD XQ FRQYHUWRU VHULH-paralel. Latch-XO DGUHVDELO UHDOL]HD] R EXQ VHSDUD LH vQWUH unde, cnd L cum trebuie V VH vQVFULH LQIRUPD LD $VWIHO FRPELQD LD ORJLF D OLQLLORU GH DGUHV VWDELOHWH unde
vQ FH ELVWDELO XUPHD] D IL vQVFULV V LQIRUPD LD LPSXOVXO &/. GLFWHD] PRPHQWXO

cnd

DLE

ORF vQVFULHUHD LDU YDORDUHD ORJLF

VWDELOHWH PRGXO

cum XUPHD]

VH PRGLILFH LQIRUPD LD GLQ ELVWDELOXO VHOHFWDW

D ILHF UXL ELW GLQ FRPSRQHQ D 'IN

5.2.2.2. Memoria RAM

SUH]LQW

Memoria RAM (Random Acces Memory = memoria cu acces aleator) VFKHPD GLQ ILJ  L SRDWH IL RE LQXW GLQ ODWFK-ul adresabil prin
QLYHOXUL GH GHFRGLILFDUH L PHPRUDUH D XQXL DO WUHLOHD QLYHO 5$0 FXSULQGH GRX UHJLPXUL GH OXFUX L DQXPH )XQF LRQDUHD PHPRULHL

DG XJDUHD OD FHOH GRX

de multiplexare. nscrierea L citirea LQIRUPD LHL Regimul de nscriere VH UHDOL]HD] este inhibat.

SHQWUX

WE = 0 (Write Enable = autorizare

GH vQVFULHUH VLWXD LH vQ FDUH GHFRGLILFDWRUXO HVWH DFWLYDW vQ WLPS FH PXOWLSOH[RUXO

&RPELQD LD ORJLF FDUH XUPHD] 'XS

LHLUH DOH GHFRGLILFDWRUXOXL VHOHFWkQG DVWIHO XQD GLQ FHOH  HSXL]DUHD WXWXURU FHORU 

DGUHV  XQ QXP U GH  vQVFULL vQ FHOH 

Regimul de citire VH UHDOL]HD] SHQWUX WE = 1  este activat, iar decodificatorul este inhibat.
&RPELQD LD ORJLF FRQ LQXW WUHEXLH V DLE D OLQLLORU GH DGUHV DFFHV OD LHLUHD 08; GH PHPRULH FX

3XWHP DVWIHO DYHD DFFHV SUDFWLF LQVWDQWDQHX OD LQIRUPD LD VWRFDW

din cele 2n
YD

FRUHVSXQ] WRDUH D OLQLLORU GH DGUHV 

Baleierea aleatoare (n orice ordine) a tuturor celor 2n FRPELQD LL GH DGUHV  n SHUPLWH R FLWLUH VHULDO  vQWU-R RUGLQH RDUHFDUH D FRQ LQXWXOXL WXWXURU FHORU 

ORFD LL GH PHPRULH

5.2.3. Circuitul basculant bistabil D Master-Slave

Circuitul basculant bistabil D Master-6ODYH
YDULDQW 65 GLQ GRX VH RE LQH FD L RPRORJXO V X vQ L FRPDQGDWH vQ ELVWDELOH ' VLQFURQH FRQHFWDWH vQ FDVFDG

contratimp de impulsul de CLK. Q IXQF LH GH WLSXO de bistabile D sincrone din care este constituit, bistabilul D Master-Slave poate comuta fie pe frontul anterior, fie pe cel posterior al impulsului de CLK.

 "  !  #    

Circuite log

149

Adrese n n

DCD 1 din 2 n 2 n

_ E

WE

DIN

n 2 CELULE DE MEMORIE 2n MUX DOUT Fig. 5.15. Memoria RAM _ E

linii de celule de memorare n D VH vQVFULH ELWXO GH LQIRUPD LH VRVLW SH OLQLD GH GDWH 'IN.
n n
FRPELQD LL ORJLFH SRVLELOH DOH OLQLLORU GH

D FHORU

OLQLL GH DGUHV

YD DFWLYD XQD GLQ FHOH 

EL L VRVL L SH LQWUDUHD VHULDO

ORFD LL DOH PHPRULHL 5$0

GH GDWH 'IN

se vor afla deja

VLWXD LH vQ FDUH PXOWLSOH[RUXO

YD VHOHFWD ORFD LD GH PHPRULH DO F UHL

-ului.
vQ RULFDUH ORJLFH DSOLF ULL FRPELQD LHL

FHOXOH

FRQGL LD

150

Capitolul 5
'LQWUH FHOH PDL IUHFYHQWH DSOLFD LL DOH VDOH PHQ LRQ P UHJLVWUHOH UHJLVWUXO GH

deplasare serie, paralel, combinat, universal, etc.

5.2.3.1. Registrul de deplasare serie Registrul de deplasare serie, fig. 5.16, este format din 4 bistabili de tip D Master-Slave.
DIN D0 Q0 D1 Q1 D2 Q2 D3 Q3 DOUT

CLK CLK
)LJ 

CLK

CLK

CLK

6FKHPD JHQHUDO

D XQXL UHJLVWUX GH GHSODVDUH VHULH

n timpul funF LRQ ULL ODWFK-urile de tip master sunt deschise simultan pentru CLK=0, cele de tip slave ILLQG vQFKLVH Q WLPSXO WUDQ]L LHL GLQ  vQ  D VHPQDOXOXL GH CLK, latch-urile master VH EORFKHD] LDU FHOH slave VH GHVFKLG L SULPHVF LQIRUPD LD din master. Se rHPDUF IDSWXO F vQ QLFL XQ PRPHQW QX H[LVW R FDOH GHVFKLV vQWUH
LQWUDUHD L LHLUHD UHJLVWUXOXL 3H ED]D VFKHPHL GLQ ILJ  SXWHP VFULH XUP WRDUHOH UHOD LL

DOUT =Q3 =D3 =Q2n-1=D2n-2=Q1n-2=D1n-3=Q0n-3=D0n-4=DINn-4

6H REVHUY F GH LQIRUPD LD 'IN DMXQJH OD LHLUHD UHJLVWUXOXL GXS GHSODVDUH FD]XO SRW IL FRQVWUXLWH DWkW vQ YDULDQWH

n-1

(5.5)
 LPSXOVXUL GH FkW L vQ VH

tact.
5HJLVWUHOH YDULDQWH PLQLP SRDW VWDWLFH R GLQDPLFH Q VWUXFWXULORU GLQDPLFH YD WUHEXL LPSXV IUHFYHQ D VHPQDOXOXL GH FHDV SHQWUX FD GDWHOH vQVFULVH vQ FHOXOHOH GH PHPRUDUH V

UHJHQHUD VLJXU SULQ WUDQVIHUXO vQ FHOXOHOH XUP WRDUH

6HULDO $FFHV 0HPRU\5HJLVWHU (OH VXQW FRQVWUXLWH SHQWUX XQ QXP U DVXSUD QXP UXOXL GH FRQH[LXQL H[WHUQH DOH LQWHJUDWXOXL

Registrele de deplasare serie pot fi utilizate ca memorii cu acces serie (SAR foarte mare de

EL L FUHWHUHD QXP UXOXL GH FHOXOH GH PHPRUDUH QHDYkQG QLFL XQ IHO GH LPSOLFD LL

5.2.3.2. Registrul paralel Registrul paralel (de stocare, tampon) prezentat n fig. 5.17, este format din 4
ELVWDELOL GH WLS ' DF LRQD L VLQFURQ GH XQ WDFW FRPXQ Q PRPHQWXO DSOLF ULL WDFWXOXL FXYkQWXO ELQDU GH  EL L SUH]HQW OD LQWU ULOH ,0, I1, I2, I3 HVWH vQVFULV vQ FHOH  FHOXOH GH PHPRULH L SRDWH IL FLWLW OD LHLULOH 40, Q1, Q2, Q 3. )XQF LD SULQFLSDO DQXPLWH FRQILJXUD LL ELQDUH vQ VFRSXO XQXL DFFHV XRU OD HOH vQ YHGHUHD SUHOXFU ULL

D XQXL DVWIHO GH UHJLVWUX HVWH DFHHD GH D VWRFD WHPSRUDU

Registrul paralel este memoria zonHORU digital de prelucrare a datelor.

5.2.3.3. Registrul combinat

&HOH GRX WLSXUL GH UHJLVWUH WUDWDWH PDL VXV VXQW XWLOL]DWH vQ DSOLFD LL vQ FDUH

transferul datelor se face fie numai paralel, fie numai serie. Registrele combinate
SHUPLW WUHFHUHD GH OD WUDQVIHUXO SDUDOHO OD FHO VHULH L LQYHUV Q ILJ  SUH]HQW P XQ UHJLVWUX FRPELQDW SDUDOHO GH  EL L

S/P

CLK Q0
)LJ 

 "  !  #    

Circuite log

151

I3 CLK CLK D Q CLK

I2

I1

I0

D Q

CLK

D Q

CLK

D Q

Q3
)LJ 

Q2

Q1
D XQXL UHJLVWUX SDUDOHO

Q0

6FKHPD JHQHUDO

GH

YLWH]

PD[LP

GLQWU

-un sistem

-serie sau serie-paralel)

I3

SI

I0

I1

I2

D CLK Q CLK

D Q CLK

D Q CLK

D Q

Q1
6FKHPD JHQHUDO

Q2
D XQXL UHJLVWUX FRPELQDW

Q3 (SO)

152

Capitolul 5

Pentru 63
OD LQWU ULOH FHORU 63 

 VXQW YDOLGDWH SRU LOH  L GDWHOH GH LQWUDUH ,0 ELVWDELOH  VXQW QF UFDUHD SDUDOHO  DUH ORF vQ

PRPHQWXO

, I1, I2, I3 au acces

DSOLF ULL UHDOL]HD] R

impulsului de CLK.
3HQWUX YDOLGDWH SRU LOH DVWIHO vQFkW UHJLVWUXO

deplasare serie a datelor de la stnga la dreapta, cu cte un bit pentru fiecare impuls de CLK. 5HJLVWUXO SRDWH IXQF LRQD FD XQ FRQYHUWRU SDUDOHO-serie, datele fiind introduse SDUDOHO OD LQWU ULOH ,0, I1, I2, I3 L ILLQG H[WUDVH VHULH OD LHLUHD 62 6HULDl Output) a circuitului. n regim de convertor serie-SDUDOHO GDWHOH VH LQWURGXF GH R PDQLHU VHULDO OD LQWUDUHD 6, 6HULDO ,QSXW L VXQW H[WUDVH SDUDOHO OD LHLULOH 40, Q1, Q2, Q3.
 5HJLVWUXO XQLYHUVDO ELGLUHF LRQDO GH  EL L

Registrul uniYHUVDO ELGLUHF LRQDO GH  EL L 61  ILJ  DFRSHU toate variantele de registre prezentate anterior.
&DUDFWHULVWLFLOH WDEHOXO GH IXQF LRQDUH IXQF LRQDOH DOH DFHVWXL WLS GH UHJLVWUX VXQW

SUDFWLF vQ

SUH]HQWDWH

- tab. 5.5.
I1(4) I2(5) I3(6) LI(7)

S0(9)

RI(2) I0(3)

S1(10)

CLK CL

CLK CL

CLK CL

CLK CL

CLK(11)
CL(1)

Q0(15) (LO)
)LJ 

Q1(14)

Q2(13)

Q3(12) (RO)

5HJLVWUXO XQLYHUVDO ELGLUHF LRQDO GH  EL L 61 

&LUFXLWXO LQWHJUDW 61  SUH]LQW FHOH GRX

GRPHQLXO GH DSOLFDELOLWDWH )XQF LRQDUHD VLQFURQ

WDEHOXO GH IXQF LRQDUH GDWHOH SRW IL LQWURGXVH L GHSODVDWH GH OD VWkQJD OD GUHDSWD GH OD GUHDSWD OD VWkQJD VDX LQWURGXVH SDUDOHO vQF UFkQG VLPXOWDQ vQ UHJLVWUX WR L FHL  EL L 'DF UHJLVWUX VXQW S VWUDWH 7HUPLQDOHOH 5, 5LJKW ,QSXW L /, /HIW ,QSXW VXQW LQWU UL VHULDOH SHQWUX GHSODVDUHD OD GUHDSWD UHVSHFWLY OD VWkQJD D GDWHORU L QX LQWHUIHUHD] vQ DPEHOH LQWU UL GH VHOHF LH 60 L 61

nici un IHO FX RSHUD LXQHD GH vQF

,QWU ULOH GH VHOHF LH L GH GDWH WUHEXLH V

GH WLPS vQDLQWHD DSDUL LHL IURQWXOXL SR]LWLY DO &/. HOH GHYHQLQG DFWLYH QXPDL GXS

acest moment.
Tab. 5.5. Tabelul de fXQF LRQDUH DO UHJLVWUXOXL XQLYHUVDO 61 

Mod de operare
WHUJHUH

Hold Deplasare la stnga Deplasare la dreapta

QF UFDUH

paralel

+ QLYHO GH WHQVLXQH ULGLFDW K LGHP VWDELOLW DQWHULRU WUDQ]L LHL /H a CLK; L = niveO GH WHQVLXQH FRERUkW O LGHP VWDELOLW DQWHULRU WUDQ]L LHL /H a CLK; in(qn VW ULOH LQWU ULORU VDX LHLULORU VWDELOLWH DQWHULRU WUDQ]L LHL /H a CLK; X = indiferent; WUDQ]L LH /H a CLK. 1RW  E 7UDQ]L LD +/ D LQWU ULORU 60 L 61 trebuie s VH SURGXF QXPDL vQ WLPS &/. HVWH + SHQWUX RSHUD LL FRQYHQ LRQDOH

&LUFXLWHOH EDVFXODQWH ELVWDELOH GH WLS 65 L ' IDF SDUWH GLQ VLVWHPHOH GH RUGLQXO , 1H RFXS P vQ FRQWLQXDUH GH DOWH GRX 2 VHFYHQ DSOLFDW WLSXUL GH ELVWDELOH 7 L -. FDUH SUH]HQWkQG OD LHLUH XQ FkWH R UHDF LH VXSOLPHQWDU  VXQW FRQVLGHUDWH VLVWHPH GH RUGLQXO ,, OD LQWUDUHD XQRU DVWIHO GH VLVWHPH JHQHUHD] U VSXQV SDU LDO FRUHODW FX DFHDVWD L SXWHUQLF LQIOXHQ DW GH VHFYHQ HOH DQWHULRDUH

prin starea n care s-a aflat sistemul vQDLQWH GH DSOLFDUHD VHFYHQ HL
Q SDUDOHO FX HYROX LD LHLULORU HYROXHD] ID GH LQWU UL ILLQG FRQIHULW L VWDUHD DXWRQRPLD SDU LDO HYROX LH SDUDOHO  D LHLULORU WRFPDL GH DFHDVW

 "  !  #    
FRPHQ]L ORJLFH VSHFLDOH FDUH D FLUFXLWXOXL HVWH GHWHUPLQDW FXP UH]XOW LQWU UL GH VHOHF LH D PRGXOXL GH OXFUX 60 L 61 'XS UFDUH SDUDOHO D GDWHORU ,QWU UL ,HLUL

Circuite log

153

-i sporesc
GH L GLQ

sunt n stare "jos", datele existente n

VH VWDELOL]H]H FX XQ DQXPLW LQWHUYDO

CLK X X

CL
L H H H H H H

S1 X l(b) h h l(b) l(b) h

S0 X l(b) l(b) l(b) h h h

RI X X X X l h X

LI X X l h X X X

In X X X X X X in

Q0 L q0 q1 q1 L H i0

Q1 L q1 q2 q2 q0 q0 i1

Q2 L q2 q3 q3 q1 q1 i2

Q3 L q3 L H q2 q2 i3

FH

154

Capitolul 5

5.3. Circuite basculante bistabile de tip T

Circuitul basculant
ELVWDELO GH WLS 7 VH RE LQH GLQWU

-un bistabil D prin

LQWURGXFHUHD XQHL UHDF LL VXSOLPHQWDUH LHLUH LQWUDUH DSOLFDW

SULQ LQWHUPHGLXO XQXL

FLUFXLW ORJLF FRPELQD LRQDO HOHPHQWDU ILJ 

CLK CLK D Q Q

Q
D PRGXO GH RE LQHUH

b) schema bloc

Fig. 5.20. Circuitul basculant bistabil de tip T sincron

7DE  7DEHOXO GH WUDQ]L LH DO FLUFXLWXOXL EDVFXODQW ELVWDELO GH WLS 7

Tn 0 1

Qn+1 Qn Qn

'LQ WDEHOXO GH WUDQ]L LH WDE  VH SRDWH GHGXFH H[SUHVLD IXQF LHL GH LHLUH

Q n +1 = Q n Tn + Q n Tn = Q n T .
%LVWDELOXO 7

(5.6) -

GLQ ILJ  QX vQGHSOLQHWH IXQF LD GH PHPRULH SURSLX ]LV

FXP HVWH FD]XO ELVWDELOHORU 65 L ' DYkQG XQ FRPSRUWDPHQW GHILQLW DWkW GH LQWUDUH FkW L GH VWDUHD vQ FDUH VH DIO  (O HVWH FHO PDL VLPSOX VLVWHP DXWRPDW L HVWH XWLOL]DW VSUH H[HPSOX OD FRQVWUXLUHD QXP U WRDUHORU DVLQFURQH

5.4. Circuite basculante bistabile de tip JK

5HDPLQWLP IDSWXO F ELVWDELOXO ' D DS UXW FD XUPDUH D QHFHVLW LL GH D vQO WXUD WUDQ]L LLOH QHGHWHUPLQDWH DOH ELVWDELOHORU 65 $FHODL HIHFW GH HOLPLQDUH D WUDQ]L LLORU

QHGHWHUPLQDWH VH SRDWH RE LQH SULQ LQWURGXFHUHD GH UHDF LL VXSOLPHQWDUH vQ VWUXFWXULOH

SR.

2.5.1. Circuitul basculant bistabil JK asincron

%LVWDELOXO -. DVLQFURQ ILJ  SRDWH IL RE LQX SULQ LQWURGXFHUHD XQHL UHDF LL

'LQ ILJ  VH SRDWH GHGXFH VXFFHVLY IXQF LD GH LHLUH D FLUFXLWXOXL

Sn = J n Qn ; R n = K n Qn ;
Q n +1 = K n Q n + (J n Qn + Q n ) = (K n Q n )(J n Qn + Q n ) = = (K n + Qn )(J n Qn + Q n ) = K n J n Qn + K n Q n + J n Qn ;

Q n +1 = J n Qn + K n Q n .
LQkQG VHDPD GH UHO  L WDEHOXO GH WUDQ]L LH DO SXWHP DOF WXL WDE 

' 1 % 0(& % 2 ' ) & ' '

Circuite log

155

t din bistabilul SR asincron

Fig. 5.21. Schema circuitului basculant bistabil JK asincron

(5.7) (5.8)

(5.9) &%%-SR asincron, tab. 5.1,

Tab. 5

7DEHOXO GH WUDQ]L LH DO &%%

-JK asincron

Jn 0 0 1 1

Kn 0 1 0 1

Sn 0 0
Qn Qn

Rn 0 Qn 0 Qn

Qn+1 Qn 0 1
Qn

156
6H REVHUY RVFLOHD] F SHQWUX -n

Capitolul 5

=Kn

 VH RE LQH OD LHLUH

Q n +1 = Q n , decL

LHLULOH

SHUPDQHQW vQWUH  L  ORJLF

5.4.2. Circuitul basculant bistabil JK sincron

Schema CBB--.
VLQFURQ ILJ  VH RE LQH GLQ FHD SUHFHGHQW SULQ LQWURGXFHUHD XQHL ERUQH VXSOLPHQWDUH SHQWUX WDFW LDU WDEHOXO GH WUDQ]L LH HVWH WDE 

.8.

CLK

Fig. 5.22. Schema circuitului basculant bistabil JK sincron

7DE  7DEHOXO GH WUDQ]L LH DO FLUFXLWXOXL EDVFXODQW ELVWDELO -. VLQFURQ

Jn 0 1 0 1 x 0 1 0
6H REVHUY F

Kn 0 0 1 1 x 0 0 1

CLK 0 1 0 1 0 1 0 1 0 1 1

Qn+1 Qn 1 0

)XQF LRQDUH VLQFURQ

Qn
Qn 1 0 Circuit blocat
)XQF LRQDUH DVLQFURQ

SULQ OHJDUHD vPSUHXQ 

D LQWU ULORU - L . VH RE LQH XQ ELVWDELO GH GLQWU

tip T care, pentru Jn=Kn=Tn impulsului de CLK.

EDVFXOHD]

-o stare n alta la comanda

5.4.3. Circuitul basculant bistabil JK Master-Slave

Bistabilul JK-06
VH RE LQH SULQ FRQHFWDUHD vQ FDVFDG D GRX &%%

VLQFURQH WUDQVIHUXO LQIRUPD LHL vQ VHF LXQHD

al impulsuluL GH &/. 7DEHOXO GH WUDQ]L LH HVWH WRW WDE 

 1XP U WRUXO DVLQFURQ  FLUFXLWH EDVFXODQWH ELVWDELOH -.

1XP U WRUXO DVLQFURQ ILJ  XWLOL]HD]

Master-Slave, n regim de circuit basculant bistabil de tip T: Jn=Kn=Tn=1.

CLK 1

CLK T _ Q Q 20 A0

$FHVW FLUFXLW VH FDUDFWHUL]HD]

DVXSUD WXWXURU ELVWDELOHORU GH WLS 7 FL QXPDL DVXSUD SULPXOXL LHLULOH ILHF UXL ELVWDELO

fiind conectate la intrarea de CLK a bistabilului XUP

0 CLK A0 A1 A2 A3 1 2 3 4 5 6 7 8 9

' 1 % 0(& % 2 ' ) & ' '

Circuite log

157

-JK

slave

DYkQG ORF SH IURQWXO GHVFUHVF WRU

CLK T _ Q Q 21 A1

CLK T _ Q Q 22 A2

CLK _ Q

T Q 23 A3

Fig.  6FKHPD QXP

U WRUXOXL DVLQFURQ

SULQ IDSWXO F

LPSXOVXO GH &/. QX DF LRQHD] WRU

10

11

12

13 14

15 t t t t t

)LJ  'LDJUDPHOH GH VHPQDO DOH QXP U WRUXOXL DVLQFURQ

158

Capitolul 5
Q SOXV WRDWH LQWU ULOH 7 DOH ELVWDELOHORU ILLQG SHUPDQHQW FRQHFWDWH OD  ORJLF

YDORDUHD

ORJLF

LHLULL

ILHF UXL

ELVWDELO

VH

PRGLILF

SH

IURQWXO

QHJDWLY

DO

impulsurilor primite pe intrarea de CLK, v. fig.5.24.

5.5. Conversia circuitelor basculante bistabile

Q QXPHURDVH DSOLFD LL HVWH QHFHVDU XWLOL]DUHD XQXL DQXPLW WLS GH &%% SUDFWLF ILLQG GLVSRQLELO XQ DOWXO Q DFHVWH FRQGL LL GH PDUH DMXWRU VXQW HFXD LLOH

loJLFH GH OHJ WXU GLQWUH GLIHULWH tabelului comparativ, tab. 5.9.

WLSXUL GH ELVWDELOOH UHOD LL FH VH SRW RE LQH SH ED]D

Tab. 5.9. Tabel comparativ al diferitelor tipuri de CBB Tip CBB SR SnRn Tabelul de DGHY r 00 01 10 11 Qn+1 Qn 0 1 ? Dn 0 1 D Qn+1 0 1 Tn 0 1 T Qn+1 Qn JnKn 00 01 10 11 JK Qn+1 Qn 0 1

Qn

Qn

(FXD LLOH

Qn+1
Qn +1

Sn+ R n Qn Rn+ Sn Qn

D n = Sn = R n D n = Sn = R n

Tn Qn+Tn Qn Tn Qn +TnQn

J n Q n + K n Qn

logice

J n Qn +KnQn

5.5.1. Conversia n T
Pentru realizarea conversiei JKT sau D7 5.25.
T X CLK Fig. 5.25. Conversia n T: punerea problemei
3HQWUX DFHDVWD VH FRQVWUXLHWH WDEHOXO DMXW WRU  DVWIHO vQ SULPHOH GRX FRORDQH VH WUHF WRDWH FRPELQD LLOH ORJLFH SRVLELOH DOH LQWU ULL 7 n L VW ULL 4n WUHEXLH J VLW UHOD LD GLQWUH LQWUDUHD 7 D ELVWDELOXOXL VLPXODW L LQWU ULOH -. VDX ' DOH ELVWDELOXOXL GLVSRQLELO

- fig.

CBB JK sau D

ELVWDELOXOXL VLPXODW vQ XUP WRDUHOH GRX L 'n FRPSOHWDWH QXPDL GXS

Qn+1 a bistabilului simulat.

Tab. 5.10. Explicativ pentru realizarea conversiilor n T

face porniQG

&RPSOHWDUHD FX YDORULOH ORJLFH FRUHVSXQ] WRDUH D FRORDQHORU -n D WDE 

VWXGLHUH DWHQW

$VWIHO VLWXD LD 4n=0, Qn+1  VH RE LQH JnKn [ XQGH SULQ [ vQ HOHJHP LQGLIHUHQW JnKn=00 sau 10, deci JnKn [ DPG 6LPLODU VH SURFHGHD] FX FRORDQD OXL 'n. 2 GDW 9. SHQWUX IXQF LLOH GH LHLUH -n

&X DFHVWH UH]XOWDWH VFKHPD JHQHUDO

din fig. 5.27.

T CLK J CLK K Q Q T CLK D Q CLK Q b) DT Q

' 1 % 0(& % 2 ' ) & ' '

FRORDQH

Circuite log

159

WUHFHUHD vQ XOWLPD FRORDQ

YDORULOH ORJLFH DOH LQWU ULORU -n

D YDORULORU ORJLFH DOH LHLULL

Kn

Tn 0 0 1 1

Qn 0 1 0 1

J nK n 0x x0 1x x1

Dn 0 1 1 0

Qn+1 0 1 1 0 Kn
L 'n

se
R

GH OD YDORULOH ORJLFH DOH VW ULL SUH]HQWH L YLLWRDUH 4n L 4n+1 GXS DWXQFL FkQG -n 4n  L

4n+1

Kn=00 sau 01, deci  VH RE LQH FkQd

FRPSOHWDW WDE  VH SRDWH WUHFH OD VLQWH]  FRQVWUXLQG GLDJUDPHOH

, Kn L 'n - fig. 5.26.

Tn Qn 0 x x 1 0 1 Tn Qn 0 1 0 0 1 1 1 0

Tn

Qn 0 1

0 0 1

1 x x

0 1

a) Jn=Tn
)LJ 

b) Kn=Tn

c)Dn=Tn Q n + Tn Qn=TnQn

6LQWH]D IXQF LLORU GH LHLUH DOH EORFXOXL ; GLQ ILJ 

GLQ ILJ  FDS W

DVSHFWHOH FRQFUHWH

Q
a) JKT

Fig. 5.27. Conversiile n T

160

Capitolul 5

5.5.2. Conversia n SR
de conversie JK65 L 'SR.
3URFHGkQG VLPLODU RE LQHP WDE  FDUH SHUPLWH LPSOHPHQWDUHD FLUFXLWHORU

Tab. 5.11. Explicativ pentru realizarea conversiilor n RS

SnRn 00 00 01 01 10 10 11 11

Qn 0 1 0 1 0 1 0 1

JnKn 0x x0 0x x1 1x x0 xx xx

Dn 0 1 0 0 1 1 x x

Qn+1 0 1 0 0 1 1 0/0 1/0

Circuite log

' 1 % 0(& % 2 ' ) & ' '

161